WO2018184444A1 - 氮化物半导体元件及其制作方法 - Google Patents

氮化物半导体元件及其制作方法 Download PDF

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WO2018184444A1
WO2018184444A1 PCT/CN2018/078653 CN2018078653W WO2018184444A1 WO 2018184444 A1 WO2018184444 A1 WO 2018184444A1 CN 2018078653 W CN2018078653 W CN 2018078653W WO 2018184444 A1 WO2018184444 A1 WO 2018184444A1
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layer
pattern
substrate
semiconductor device
nitride semiconductor
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English (en)
French (fr)
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朱学亮
刘建明
卓昌正
陈秉扬
徐宸科
张中英
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厦门三安光电有限公司
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Publication of WO2018184444A1 publication Critical patent/WO2018184444A1/zh
Priority to US16/447,775 priority Critical patent/US10727054B2/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/025—Physical imperfections, e.g. particular concentration or distribution of impurities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02428—Structure
    • H01L21/0243—Surface structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02458—Nitrides
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02658—Pretreatments
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/12—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of group III and group V of the periodic system
    • H01L33/32—Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
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    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/22—Roughened surfaces, e.g. at the interface between epitaxial layers

Definitions

  • the present invention relates to a gallium nitride based semiconductor device for improving sidewall defects of a sapphire pattern and a method of fabricating the same
  • Gallium nitride-based LEDs have been widely used in various light sources such as backlight, illumination, and landscape due to their high luminous efficiency. From a technical point of view, further improvement of the luminous efficiency of LED chips is still the focus of current industry development.
  • the luminous efficiency is mainly determined by two efficiencies: the first is the radiation recombination efficiency of electron holes in the active region, that is, the internal quantum efficiency; the second is the extraction efficiency of light.
  • the mainstream technology of the existing mature blue LED materials is fabricated on a sapphire substrate, and the large lattice difference between the gallium nitride material and the sapphire substrate causes a large number of dislocation defects in the epitaxial material to form a non-radiative recombination center. This will reduce the internal quantum efficiency of the LED; the refractive index of the gallium nitride material is large, and the light emitted from the active region of the LED forms a full emission inside the device, and the light extraction efficiency is lowered.
  • the patterned sapphire substrate can effectively improve the above two difficulties.
  • the graphic interface can effectively scatter the light emitted by the active region, suppressing The total reflection effect inside the device.
  • a patterned sapphire substrate is usually formed by dry etching or wet etching, wherein the dry etching is formed by physical bombardment, and the sidewall of the pattern is damaged during the manufacturing process (as shown in FIG. 1 ), and the subsequent epitaxial material is The sidewall forms a defect center (as shown in Figures 2 and 3), which increases the defect density in the material and reduces the internal quantum efficiency.
  • the defect crystal at the sidewall has an absorption center that absorbs the light emitted by the device. , reduce the efficiency of light extraction.
  • A1N grown by physical vapor deposition (physical vapor deposition) is used as a buffer layer, and by controlling the process of the A1N layer, material quality can be further improved, and luminous efficiency can be improved.
  • physical vapor deposition physical vapor deposition
  • the present invention provides a nitride semiconductor device for improving sidewall defects of a sapphire pattern and a method for fabricating the same, which are formed by physical etching to form a patterned sapphire substrate, and then physically deposited on the surface of the sapphire substrate.
  • the Al x Ga (1 - X ) N layer is formed, and multiple etching processes are performed by plasma in the process of growing the physical vapor deposited Al x Ga (1 - X ) N layer, which effectively suppresses the epitaxial material at the sidewall of the pattern.
  • a nitride semiconductor device comprising: a sapphire pattern substrate, which is produced by a physical etching method, has a series of concave or convex patterns having sidewalls; a l x Ga (1 - X ) N layer formed on the surface of the pattern substrate by physical vapor deposition; a gallium nitride based semiconductor stack formed on the Al x Ga N layer by MOCVD; wherein the Al x The size of the crystal defects of the Ga N layer on the sidewall of the sapphire pattern substrate is less than 20 nm.
  • the Al x Ga (1 - X )N layer is plasma etched one or more times during formation to eliminate crystal defects in the sidewalls of the pattern.
  • the Al x Ga (1 - X ) N layer is located on a sidewall of a single pattern of the pattern substrate, and the number of crystal defect sizes greater than 10 nm is less than 10.
  • the Al x Ga M N layer has a thickness of 3 to 100 nm.
  • the gallium nitride-based semiconductor stack includes at least an n-type semiconductor layer, a light-emitting layer, and a p-type semiconductor layer.
  • a nitride semiconductor device comprising: a sapphire pattern substrate, produced by a physical etching method, having a series of concave or convex patterns having sidewalls; An Al x Ga (1 - X ) N layer formed on the surface of the pattern substrate by physical vapor deposition; a gallium nitride based semiconductor stack formed on the Al x Ga (1 - X ) N layer by MOCVD; Wherein the Al x Ga (1 - X ) N layer is located on a sidewall of a single pattern of the pattern substrate, and the number of crystal defect sizes greater than 10 nm is less than 10.
  • the Al x Ga M N layer has a thickness of 3 to 100 nm.
  • the gallium nitride-based semiconductor stack includes at least an n-type semiconductor layer, a light-emitting layer, and a p-type semiconductor layer.
  • the size of the crystal defect of the Al x Ga M N layer on the sidewall of the sapphire pattern substrate is less than 20 nm.
  • a method of fabricating a nitride semiconductor device includes the steps of: (1) providing a sapphire substrate, and forming a series of depressions on an upper surface of the substrate by a physical etching method; Or a raised pattern having sidewalls; (2) forming an Al x Ga (1 - X ) N layer on the surface of the patterned substrate by physical vapor deposition; (3) using MOCVD Depositing a gallium nitride-based semiconductor stack on the Al x Ga (1 - X ) N layer; wherein in the step (2), the liner is plasma etched before or during the formation of the Al x Ga M N layer The surface of the bottom is to improve defects of the sidewalls of the pattern, thereby reducing crystal defects of the Al x Ga (1 - X ) N layer on the sidewalls of the sapphire pattern substrate.
  • the sapphire substrate formed in the step (1) is placed in a physical vapor deposition device, firstly introduced with nitrogen or argon or both, and
  • the RF (radio frequency) power source in the device forms a plasma at the surface of the substrate, and nitrogen ions or argon ions in the plasma strike the surface of the substrate under the action of an electric field, eliminating defective portions at the sidewalls of the pattern.
  • the sapphire substrate formed in the step (1) is placed in a physical vapor deposition device, and then the following processing is performed: (a): smashing the DC pulse power supply, starting from Growth of Al x Ga (1 - X )N film, the first film thickness is grown from 1 nm to 5 nm ; (b): Turn off the DC power supply, smash the RF power supply, pass nitrogen or argon or both, plasma Nitrogen ions or argon ions in the body impinge on the surface of the substrate under the action of an electric field to eliminate the poor quality Al x Ga M N material grown at the sidewall of the pattern; (c): Repeat the above steps 5-25 times to obtain 3 ⁇ 100 nm Al x Ga (1 - X) N layer.
  • the size of the crystal defect of the Al x Ga M N layer formed in the step (2) on the sidewall of the sapphire pattern substrate is less than 20 nm.
  • the Al x Ga M N layer formed in the step (2) is located on the sidewall of the single pattern of the graphic substrate, and the number of crystal defects smaller than lOnm is less than 10.
  • the gallium nitride-based semiconductor stack formed in the step (3) includes an n-type semiconductor layer, a light-emitting layer, and a p-type semiconductor layer.
  • the foregoing fabrication method can effectively remove crystal defects at the sidewall of the pattern substrate, and can lack the sidewall of the pattern.
  • the number of traps is reduced from more than 15 to less than 10; the defect size is reduced from 20 to 100 nm to less than 20 nm.
  • the foregoing fabrication method is applied to a light-emitting diode, and the low defect density can significantly improve the luminous efficiency of the quantum well in the blue LED, and the same benefit from completely eliminating the defect crystal at the sidewall, greatly reducing the defect.
  • Light absorption phenomenon improves the light extraction efficiency of the LED chip.
  • the brightness of the LED chip can be increased by 2% or more.
  • 1 is a schematic view of a sapphire pattern substrate with defects caused by etching at the sidewalls.
  • FIG. 2 is a schematic view showing the epitaxial growth nitride epitaxial structure of the substrate shown in FIG. 1, in which epitaxial growth ⁇ forms a GaN defect region.
  • FIG. 3 is a TEM image of a epitaxially grown nitride epitaxial structure of the substrate shown in FIG. 1, with crystal defects at the sidewalls.
  • FIG. 4 is a flow chart of a method of fabricating a nitride semiconductor device in accordance with an embodiment of the present invention.
  • 5 to 8 are schematic views showing a process of fabricating a nitride semiconductor device in accordance with an embodiment of the present invention.
  • FIG. 9 is a TEM image of a nitride semiconductor epitaxial structure having no crystal defects at the sidewalls in accordance with an embodiment of the present invention.
  • 100 sapphire substrate; 110: pattern of sapphire substrate; 120: sidewall of sapphire substrate pattern; 13 0: defect of sidewall of sapphire substrate; 200: layer of A1N; 210: defect on layer of A1N 300: GaN-based epitaxial stack; 310, 320: defects on GaN-based epitaxial stacks.
  • FIG. 4 shows a method of fabricating a semiconductor device for improving epitaxial defects at the sidewalls of a sapphire pattern substrate, including steps S100 to S300, which will be described in detail below with reference to FIGS.
  • a sapphire substrate 100 is provided, and a series of recessed or raised patterns 110 are formed on the upper surface of the substrate by physical etching, the pattern having sidewalls 120, as shown in FIG.
  • the details are as follows: First, a layer of photoresist is coated on the flat sapphire substrate, and the thickness can be 0.5 ⁇ 3 micrometers; then, a yellow light process is used to fabricate a pattern composed of a series of columnar photoresists.
  • the pattern size diameter can be 0.1 U m ⁇ 6um, the gap between each pattern can be 0.1 ⁇ 6 microns; dry etching sapphire substrate
  • the first surface forms a series of raised patterns 110 on the first surface. During the dry etching process, the pattern is formed by physical bombardment, and thus the formed pattern sidewalls are damaged, forming a number of defects 130 formed in the sidewalls.
  • an A Ga ⁇ iN layer is formed on the surface of the aforementioned patterned substrate by physical vapor deposition, in which plasma is etched to improve the defects of the sidewall of the pattern.
  • the etched sapphire substrate 100 is placed in a physical vapor deposition apparatus, such as Endura II 300mm equipment of Applied Materials, Inc. or iTops A230 equipment of North China Microelectronics Corporation or other magnetron sputtering equipment.
  • a physical vapor deposition apparatus such as Endura II 300mm equipment of Applied Materials, Inc. or iTops A230 equipment of North China Microelectronics Corporation or other magnetron sputtering equipment.
  • the first film thickness is grown 1-5 nm, as shown in FIG. 6, the ⁇ Al x Ga (1 - X) N film has a plurality of defects 210 at the position of the pattern sidewall 120; ⁇ RF power supply, with nitrogen or argon or both, the nitrogen or argon ions in the plasma strike the surface of the substrate under the action of an electric field, and the surface of the Al x Ga (1 - X )N film is engraved. Corrosion, thereby eliminating the poor quality Al x Ga M N film material grown at the sidewall of the pattern; repeating the above steps 5-25 times, finally obtaining an Al x Ga M N layer of 3 to 100 nm, as shown in FIG.
  • the Al x Ga (1 - X ) N layer growth is treated by multiple plasma etching, and the defective Al x Ga (1 - X ) N at the sidewall is substantially removed.
  • the surface treatment of the substrate may be performed first, and then the Al x Ga (1 - X )N layer 200 is deposited.
  • the temperature of the deposition chamber of the physical vapor deposition apparatus is raised to between 300 and 800 ° C, and nitrogen or argon gas or both of them are introduced into the chamber, and the RF (radio frequency) power source in the apparatus is mounted on the sapphire substrate.
  • a plasma is formed at the surface of the 100.
  • the nitrogen ions or argon ions in the plasma strike the surface of the substrate under the action of an electric field, and have an etching effect on the surface, thereby eliminating the defect portion at the sidewall of the pattern, and the processing time can be controlled at 5 ⁇ 300 seconds.
  • the processing time can be controlled at 5 ⁇ 300 seconds.
  • the patterned sapphire substrate after growing the Al x Ga (1 _ X )N layer is placed in an MOCVD (Metal Organic Chemical Vapor Deposition) system, and the nitride semiconductor stack 300 is epitaxially grown, as shown in FIG. Show.
  • MOCVD Metal Organic Chemical Vapor Deposition
  • the temperature is raised to 500 ⁇ 1200 °C, and the surface is treated with a mixed gas of hydrogen, nitrogen and ammonia;
  • the temperature is adjusted to 500 ⁇ 1050 °C, ammonia gas and trimethylgallium are introduced, and a buffer layer of 20-50 nm is grown, then trimethylgallium is turned off; and the temperature is raised to 1000-1100.
  • C Annealing at this temperature for 1 to 5 minutes, then introducing trimethylgallium, growing non-tacky gallium nitride of 1 to 2 microns thickness; continuing to raise the temperature to 1050 ⁇ 1150 °C, growing 1 ⁇ 2 microns Thick non-difficult GaN; Cool down to 1030 ⁇ 1120 °C, grow 1.5 ⁇ 4 microns thick GaN, pass the monosilane to make it miscellaneous; Cool down to 770 ⁇ 870 °C, grow 15 ⁇ 30 cycles InGaN/GsN superlattice layer, InGaN has a thickness range of l ⁇ 3nm in each period, GaN thickness ranges from 2 to 10nm; temperature rises to 750 ⁇ 900°C, and 5 ⁇ 15
  • FIG. 9 shows a TEM photograph of an epitaxial structure of an LED formed by the above method, and compared with a TEM image of a conventional epitaxial structure shown in FIG. 3, the sidewall of the substrate pattern is processed by the fabrication method of the present invention. Starting, the sapphire pattern sidewall defects were effectively improved by repairing the defects of the pattern sidewalls.
  • the nitride epitaxial layer forms a defect center at the sidewall growth position at the sidewall of the sapphire substrate pattern, and the defect size is usually 20 to 100 nm.
  • the size of the sidewall of the single pattern 120 is lOnm or more and the number of defects is also 15 or more.
  • the LED epitaxial structure shown in FIG. 3 In the normally south side epitaxial structure shown in FIG. 3, the nitride epitaxial layer forms a defect center at the sidewall growth position at the sidewall of the sapphire substrate pattern, and the defect size is usually 20 to 100 nm.
  • the size of the sidewall of the single pattern 120 is lOnm or more and the number of defects is also 15 or more.
  • the defective Al x Ga (1 - X ) N at the sidewall of the sapphire substrate pattern has been substantially removed, so that the nitride epitaxial layer formed on the Al x Ga ( 1 - X ) N layer is substantially at the sidewall It does not produce a large-sized defect center, which can control the defect size of the sidewall piece to be more than 20 nm, or even less than 10 nm, and the number of defects can be reduced to 10 at the side wall of the single pattern 120 at a size of lOnm or more. the following.
  • the crystal defects at the sidewalls of the pattern substrate are effectively removed, and the luminous efficiency of the quantum well in the LED is significantly improved; the same is beneficial to completely eliminating the defect crystal at the sidewall, the pole The light absorption phenomenon at the defect is greatly reduced, and the light extraction efficiency of the LED chip is improved.
  • the brightness of the L ED chip can be increased by 3 to 5%.

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Abstract

一种氮化物半导体元件及其制作方法，采用物理蚀刻形成图形化蓝宝石衬底（100），然后在蓝宝石衬底的表面上采用物理气相沉积的方式形成Al xGa (1-x)N层，在生长物理气相沉积Al xGa (1-x)N层过程中采用等离子体进行多次刻蚀处理，有效的抑制了图形侧壁（120）处外延材料的晶体缺陷。

Description

说明书 发明名称：氮化物半导体元件及其制作方法 技术领域
[0001] 本发明涉及一种改善蓝宝石图形侧壁缺陷的氮化镓基半导体元件及其制作方法 背景技术
[0002] 氮化镓基 LED由于其高效的发光效率， 目前已经广泛的应用在背光、 照明、 景 观等各个光源领域。 从技术角度看， 进一步提高 LED芯片的发光效率仍然是当前 行业发展的重点。 发光效率主要有两个效率决定： 第一个是电子空穴在有源区 的辐射复合效率， 即通常说的内量子效率； 第二个是光的提取效率。
[0003] 现有成熟的蓝光 LED材料的主流技术是制作在蓝宝石衬底上， 氮化镓材料和蓝 宝石衬底的巨大的晶格差异导致外延材料中有大量位错缺陷， 形成非辐射复合 中心， 这会降低 LED的内量子效率； 氮化镓材料折射率较大， LED有源区发出的 光在器件内部形成全发射， 光的提取效率降低。 图案化蓝宝石衬底可以有效改 善上述两个难点， 一方面可以有效控制生长吋的成核岛密度， 提升氮化镓晶体 质量； 另一方面， 图形界面可以有效散射有源区发出的光， 抑制器件内部的全 反射效应。
[0004] 通常采用干蚀刻或湿蚀刻的方式形成图形化蓝宝石衬底， 其中干蚀刻是由物理 轰击形成图形， 制作过程中图形侧壁会受到损伤 （如图 1所示） ， 后续外延材料 在侧壁形成缺陷中心 （如图 2和 3所示） ， 其一方面会增加材料中的缺陷密度， 降低内量子效率； 另一方面， 侧壁处缺陷晶体存在吸收中心， 会吸收器件发出 的光， 降低光的提取效率。
[0005] 采用物理气相沉积 (物理气相沉积)生长的 A1N作为缓冲层， 通过控制 A1N层的工 艺， 可以进一步提升材料质量， 改善发光效率。 从已经报道的文献看， 如中国 专利文献 CN104246980A提到的方法， 采用物理气相沉积的 A1N作为缓冲层， 可 以大幅改善晶体质量。 但由于图形化图形侧壁处的晶体质量仍有待提升。 技术问题
问题的解决方案
技术解决方案
[0006] 本发明提供了一种改善蓝宝石图形侧壁缺陷的氮化物半导体元件及其制作方法 ， 采用物理蚀刻形成图形化蓝宝石衬底， 然后在蓝宝石衬底的表面上采用物理 所机沉积的方式形成 Al xGa (1— X)N层， 在生长物理气相沉积 Al xGa (1— X)N层过程中采 用等离子体进行多次刻蚀处理， 有效的抑制了图形侧壁处外延材料的晶体缺陷
[0007] 根据本发明的第一方面， 氮化物半导体元件， 包括： 蓝宝石图形衬底， 采用物 理刻蚀方法制作所得， 其具有一系列的凹陷或凸起的图形， 该图形具有侧壁； A l xGa (1— X)N层， 采用物理气相沉积法形成于图形衬底表面上； 氮化镓基半导体叠 层， 采用 MOCVD法形成于该 Al xGa N层上； 其中所述 Al xGa N层位于所述 蓝宝石图形衬底之侧壁的晶体缺陷的尺寸小于 20nm。
[0008] 优选地， 所述 Al xGa (1—X)N层在形成过程中一次或多次采用等离子体蚀刻以消除 图形侧壁的晶体缺陷。
[0009] 优选地， 所述 Al xGa (1—X)N层位于所述图形衬底之单个图形之侧壁的晶体缺陷尺 寸大于 10nm的个数小于 10。
[0010] 优选地， 所述 Al xGa MN层的厚度为 3~100nm。
[0011] 优选地， 所述氮化镓基半导体叠层至少包含 n型半导体层、 发光层和 p型半导体 层。
[0012] 根据本发明的第二个方面， 氮化物半导体元件， 包括： 蓝宝石图形衬底， 采用 物理刻蚀方法制作所得， 其具有一系列的凹陷或凸起的图形， 该图形具有侧壁 ； Al xGa (1— X)N层， 采用物理气相沉积法形成于图形衬底表面上； 氮化镓基半导体 叠层， 采用 MOCVD法形成于该 Al xGa (1— X)N层上； 其中所述 Al xGa (1— X)N层位于所 述图形衬底之单个图形之侧壁的晶体缺陷尺寸大于 10nm的个数小于 10。
[0013] 优选地， 所述 Al xGa MN层的厚度为 3~100nm。
[0014] 优选地， 所述氮化镓基半导体叠层至少包含 n型半导体层、 发光层和 p型半导体 层。 [0015] 优选地， 所述 Al xGa MN层位于所述蓝宝石图形衬底之侧壁的晶体缺陷的尺寸 小于 20nm。
[0016] 根据本发明的第三个方面， 氮化物半导体元件的制作方法， 包括步骤： （1) 提供一蓝宝石衬底， 采用物理刻蚀方法在所述衬底的上表面形成一系列的凹陷 或凸起的图形， 该图形具有侧壁； （2) 采用物理气相沉积法在前述图形化的衬 底上表面形成 Al xGa (1— X)N层； （3) 采用采用 MOCVD法在所述 Al xGa (1— X)N层上沉 积氮化镓基半导体叠层； 其中所述步骤 （2) 中， 在形成 Al xGa MN层前、 或者 过程中采用等离子体蚀刻所述衬底的表面以改善所述图形侧壁的缺陷， 从而减 低所述 Al xGa (1—X)N层位于所述蓝宝石图形衬底之侧壁的晶体缺陷。
[0017] 优选地， 所述步骤 （2) 中， 将所述步骤 （1) 形成的蓝宝石衬底放置于物理气 相沉积设备中， 先通入氮气或者氩气或者两者同吋通入， 打幵设备中的 RF (射频) 电源， 在衬底表面处形成等离子体， 等离子体中的氮离子或者氩离子在电场作 用下撞击衬底表面， 消除所述图形侧壁处的缺陷部分。
[0018] 优选地， 所述步骤 （2) 中将所述步骤 （1) 形成的蓝宝石衬底放置于物理气相 沉积设备中， 接着进行下面处理： （a): 打幵直流脉冲电源， 幵始生长 Al xGa (1— X)N 薄膜， 第一层膜厚生长 lnm~5nm; (b): 关闭直流电源， 打幵射频电源， 通入氮 气或者氩气或者两者同吋通入， 等离子体中的氮离子或者氩离子在电场作用下 撞击衬底表面， 消除图形侧壁处生长的质量较差的 Al xGa MN材料； (c): 重复以 上步骤 5-25次， 获得 3~100nm的 Al xGa (1— X)N层。
[0019] 优选地， 所述步骤 （2) 中形成的 Al xGa MN层位于所述蓝宝石图形衬底之侧 壁的晶体缺陷的尺寸小于 20nm。
[0020] 优选地， 所述步骤 （2) 中形成的 Al xGa MN层位于所述图形衬底之单个图形 之侧壁的晶体缺陷尺寸大于 lOnm的个数小于 10。
[0021] 优选地， 所述步骤 （3) 中形成的氮化镓基半导体叠层包含 n型半导体层、 发光 层和 p型半导体层。
发明的有益效果
有益效果
[0022] 前述制作方法可有效去除图形衬底侧壁处的晶体缺陷， 能够把图形侧壁处的缺 陷个数从大于 15个降低到 10个以下； 缺陷尺寸从 20~100nm的大小降低到 20nm以 下。
[0023] 前述制作方法应用于发光二极管吋， 低的缺陷密度可以显著提高了蓝光 LED中 量子阱的发光效率， 同吋得益于彻底消除侧壁处的缺陷晶体， 极大降低了缺陷 处的光吸收现象， 提高了 LED芯片的出光效率通过使用本结构， LED芯片亮度可 提升 2%或更高。
[0024] 本发明的其它特征和优点将在随后的说明书中阐述， 并且， 部分地从说明书中 变得显而易见， 或者通过实施本发明而了解。 本发明的目的和其他优点可通过 在说明书、 权利要求书以及附图中所特别指出的结构来实现和获得。
对附图的简要说明
附图说明
[0025] 附图用来提供对本发明的进一步理解， 并且构成说明书的一部分， 与本发明的 实施例一起用于解释本发明， 并不构成对本发明的限制。 此外， 附图数据是描 述概要， 不是按比例绘制。
[0026] 图 1为蓝宝石图形衬底示意图， 其侧壁处有刻蚀导致的缺陷。
[0027] 图 2为图示 1所示衬底外延生长氮化物外延结构示意图， 侧壁处外延生长吋形成 GaN缺陷区域。
[0028] 图 3为图示 1所示衬底外延生长氮化物外延结构的 TEM图片， 侧壁处有晶体缺陷
[0029] 图 4为根据本发明实施的一种氮化物半导体元件制作方法的流程图。
[0030] 图 5~8为根据本发明实施的一种氮化物半导体元件制作过程示意图。
[0031] 图 9为根据本发明实施的一种氮化物半导体外延结构的 TEM图片， 侧壁处没有 晶体缺陷。
[0032] 图中标号表示如下：
[0033] 100:蓝宝石衬底； 110: 蓝宝石衬底的图形； 120: 蓝宝石衬底图形的侧壁； 13 0： 蓝宝石衬底侧壁的缺陷； 200: A1N层； 210: A1N层上的缺陷； 300: GaN基 外延叠层； 310、 320： GaN基外延叠层上的缺陷。 本发明的实施方式
[0034] 下面结合示意图对本发明的薄膜芯片及其制作方法进行详细的描述， 在进一步 介绍本发明之前， 应当理解， 由于可以对特定的实施例进行改造， 因此， 本发 明并不限于下述的特定实施例。 还应当理解， 由于本发明的范围只由所附权利 要求限定， 因此所采用的实施例只是介绍性的， 而不是限制性的。
[0035] 图 4显示了一种改善蓝宝石图形衬底侧壁处的外延缺陷的半导体元件的制作方 法， 包括步骤 S 100~S300， 下面结合图 5~8进行详细说明。
[0036] 首先， 提供蓝宝石衬底 100， 采用物理刻蚀方法在所述衬底的上表面形成一系 列的凹陷或凸起的图形 110， 该图形具有侧壁 120， 如图 5所示。 具体如下： 首先 在平整的蓝宝石衬底上涂布一层光阻， 厚度可为 0.5〜3微米； 接下来运用黄光制 程制作出由一系列柱状光阻构成的图形， 此过程可采用步进式曝光机、 接触式 曝光机、 投影式曝光机或压印方式， 其图形尺寸直径可为 0.1Um〜6um， 各个图 形之间的间隙可为 0.1〜6微米； 干法蚀刻蓝宝石衬底的第一表面， 在第一表面上 形成一系列凸起图形 110。 在干法蚀刻过程中， 图形由物理轰击形成的， 因此形 成的图形侧壁会受到损伤， 形成在侧壁形成若干缺陷 130。
[0037] 接着， 采用物理气相沉积法在前述图形化的衬底上表面形成 A Ga ^iN层， 在 此过程中采用等离子体蚀刻所述衬底的表面以改善所述图形侧壁的缺陷。 具体 如下： 将前述经干法蚀刻处理的蓝宝石衬底 100放入物理气相沉积设备中， 例如 美国应用材料公司的 Endura II 300mm设备或者中国北方微电子公司的 iTops A230 设备或者其他磁控溅射设备中， 进行沉积 Al xGa (1— X)N层， 具体为： 通入氮气、 氩 气、 氧气， 打幵直流脉冲电源， 幵始生长 Al xGa M
N薄膜， 第一层膜厚生长 l~5nm， 如图 6所示， 此吋 Al xGa (1— X)N薄膜之位于图形侧 壁 120的位置具有若干缺陷 210; 接着关闭直流电源， 打幵射频电源， 通入氮气 或者氩气或者两者同吋通入， 等离子体中的氮离子或者氩离子在电场作用下撞 击衬底表面， 对 Al xGa (1— X)N薄膜表面具有刻蚀作用， 从而消除图形侧壁处生长的 质量较差的 Al xGa MN薄膜材料； 重复以上步骤 5-25次， 最终可以获得 3~100nm 的 Al xGa MN层， 如图 7所示， Al xGa (1— X)N层生长吋采用多次等离子体刻蚀处理 ， 侧壁处有缺陷的 Al xGa (1— X)N已基本被去除。 [0038] 较佳的， 将前述经干法蚀刻处理的蓝宝石衬底 100放入物理气相沉积设备后， 可先进行衬底表面处理， 再进行沉积 Al xGa (1— X)N层 200。 具体为： 将物理气相沉 积设备的沉积室内升温至 300~800°C之间， 通入氮气或者氩气或者两者同吋通入 ， 打幵设备中的 RF (射频)电源， 在蓝宝石衬底 100的表面处形成等离子体， 等离 子体中的氮离子或者氩离子在电场作用下撞击衬底表面， 对表面具有一刻蚀作 用， 从而消除图形侧壁处的缺陷部分， 处理吋间可以控制在 5~300秒。 通过在沉 积 Al xGa (1— X)N层前先对衬底表面做预处理， 可以预先去除衬底表面的缺陷， 获得 相当光滑的蓝宝石衬底表面。
[0039] 接下来， 将生长 Al xGa (1_X)N层后的图形蓝宝石衬底放入 MOCVD (金属有机物化 学气相沉积)系统中， 外延生长氮化物半导体叠层 300， 如图 8所示。 下面以发光 二极管为例进行详细说明。 首先升温至 500~1200°C， 通入氢气、 氮气、 氨气的 混合气体处理表面；
温度调整至 500~1050°C， 通入氨气和三甲基镓， 生长 20~50nm的缓冲层， 然后关 闭三甲基镓； 升温至 1000~1100。C， 在此温度下进行退火处理 1~5分钟， 然后通 入三甲基镓， 生长 1~2微米厚度的非惨杂氮化镓； 继续升温至 1050~1150°C， 生 长 1~2微米厚的非惨杂氮化镓； 降温至 1030~1120°C， 生长 1.5~4微米厚的氮化镓 ， 通入甲硅烷进行惨杂； 降温至 770~870°C， 生长 15~30个周期的 InGaN/GsN超晶 格层， 每个周期内 InGaN的厚度范围 l~3nm， GaN厚度范围 2~10nm; 升温至 750~ 900°C， 生长 5~15个周期的 InGaN/GaN多量子阱层； 然后降温至 730~800°C， 生长 低温 p型 AlInGaN空穴注入层， 厚度 20~80nm; 升温至 90~1000°C， 生长多层 AlGa N/GaN层， 通入二茂镁进行惨杂； 升温至 900~1000°C， 生长 GaN层， 通入二茂镁 进行惨杂， 构成氮化物发光二极管外延结构。
[0040] 图 9显示了采用上述方法形成的 LED外延结构的 TEM照片， 与图 3所示的常规外 延结构的 TEM图片对比， 采用本发明所述的制作方法， 从处理衬底图形的侧壁 出发， 通过修复图形侧壁的缺陷， 有效改善了蓝宝石图形侧壁缺陷。
[0041] 在图 3所示的常南侧外延结构中， 氮化物外延层在蓝宝石衬底图案侧壁处在侧 壁生长位置会形成缺陷中心， 其缺陷尺寸常通为 20~100nm， 而在单个图案 120的 侧壁处尺寸为 lOnm以上缺陷个数亦达 15以上。 在图 9所示的 LED外延结构中， 由 于蓝宝石衬底图形侧壁处有缺陷的 Al xGa (1— X)N已基本被去除， 因此形成于 Al xGa (1—X)N层之上的氮化物外延层在侧壁处基本不会产生大尺寸的缺陷中心， 其可将侧 壁片的缺陷尺寸控制在 20nm以上， 甚至 lOnm以下， 同吋在单个图案 120的侧壁 处尺寸为 lOnm以上缺陷个数也可降低到 10个以下。
[0042] 上述制作方法形成的 LED结构中， 有效去除图形衬底侧壁处的晶体缺陷， 显著 提高了 LED中量子阱的发光效率； 同吋得益于彻底消除侧壁处的缺陷晶体， 极大 降低了缺陷处的光吸收现象， 提高了 LED芯片的出光效率。 通过使用本结构， L ED芯片亮度可提升 3~5%。
[0043] 应当理解的是， 上述具体实施方案仅为本发明的优选实施例， 以上实施例还可 以进行各种组合、 变形。 本发明的范围不限于以上实施例， 凡依本发明所做的 任何变更， 皆属本发明的保护范围之内。

Claims

权利要求书
氮化物半导体元件， 包括：
蓝宝石图形衬底， 采用物理刻蚀方法制作所得， 其具有一系列的凹陷 或凸起的图形， 该图形具有侧壁；
Al xGa (1— X)N层， 采用物理气相沉积法形成于图形衬底表面上； 氮化镓基半导体叠层， 采用 MOCVD法形成于该 Al xGa (1— X)N层上； 其 特征在于：
所述 Al xGa (1—X)N层位于所述蓝宝石图形衬底之侧壁的晶体缺陷的尺寸 小于 20nm。
氮化物半导体元件， 包括：
蓝宝石图形衬底， 采用物理刻蚀方法制作所得， 其具有一系列的凹陷 或凸起的图形， 该图形具有侧壁；
Al xGa σ— X)N层， 采用物理气相沉积法形成于图形衬底表面上； 氮化镓基半导体叠层， 采用 MOCVD法形成于该 Al xGa (1— X)N层上； 其 特征在于：
所述 Al xGa (1—X)N层位于所述图形衬底之单个图形之侧壁的晶体缺陷尺 寸大于 10nm的个数小于 10。
根据权利要求 1或 2所述的氮化物半导体元件， 其特征在于： 所述 Al x Ga (1— X)N层的厚度为 3~100nm。
根据权利要求 1或 2所述的氮化物半导体元件， 其特征在于： 所述氮化 镓基半导体叠层至少包含 n型半导体层、 发光层和 p型半导体层。 根据权利要求 1或 2所述的氮化物半导体元件， 其特征在于： 所述 Al x Ga (1—X)N层在形成过程中一次或多次采用等离子体蚀刻以消除图形侧 壁的晶体缺陷。
根据权利要求 1所述的氮化物半导体元件， 其特征在于： 所述 Al xGa (1— X)N层位于所述图形衬底之单个图形之侧壁的晶体缺陷尺寸大于 10η m的个数小于 10。
根据权利要求 2所述的氮化物半导体元件， 其特征在于： 所述 Al xGa (1— X)N层位于所述蓝宝石图形衬底之侧壁的晶体缺陷的尺寸小于 20nm
[权利要求 8] 氮化物半导体元件的制作方法， 包括步骤：
(1) 提供一蓝宝石衬底， 采用物理刻蚀方法在所述衬底的上表面形 成一系列的凹陷或凸起的图形， 该图形具有侧壁；
(2) 采用物理气相沉积法在前述图形化的衬底上表面形成 Al xGa (1_x) Ν层；
(3) 采用 MOCVD法在所述 Al xGa (1— X)N层上沉积氮化镓基半导体叠层 其特征在于： 所述步骤 （2) 中， 在形成 Al xGa (1— X)N层前、 或者过程 中采用等离子体蚀刻所述衬底的表面以改善所述图形侧壁的缺陷， 从 而减低所述 Al xGa (1—X)N层位于所述蓝宝石图形衬底之侧壁的晶体缺陷
[权利要求 9] 根据权利要求 8所述氮化物半导体元件的制作方法， 其特征在于： 所 述步骤 （2) 中， 将所述步骤 （1) 形成的蓝宝石衬底放置于物理气相 沉积设备中， 先通入氮气或者氩气或者两者同吋通入， 打幵设备中的 RF (射频)电源， 在衬底表面处形成等离子体， 等离子体中的氮离子或 者氩离子在电场作用下撞击衬底表面， 消除所述图形侧壁处的缺陷部 分。
[权利要求 10] 根据权利要求 8或 9所述氮化物半导体元件的制作方法， 其特征在于： 所述步骤 （2) 中将所述步骤 （1) 形成的蓝宝石衬底放置于物理气相 沉积设备中， 接着进行下面处理：
(a) : 打幵直流脉冲电源， 幵始生长 Al xGa ^)
N薄膜， 第一层膜厚生长 l~5nm;
(b) : 关闭直流电源， 打幵射频电源， 通入氮气或者氩气或者两者同 吋通入， 等离子体中的氮离子或者氩离子在电场作用下撞击衬底表面 ， 消除图形侧壁处生长的质量较差的 Al xGa (1— X)N材料；
(c) : 重复以上步骤 5-25次， 获得 3~100nm的 Al xGa (1— X)N层。 [权利要求 11] 根据权利要求 9或 10或 11所述氮化物半导体元件的制作方法， 其特征 在于： 所述步骤 （2) 中形成的 Al xGa (1_x)N层位于所述蓝宝石图形衬 底之侧壁的晶体缺陷的尺寸小于 20nm。
[权利要求 12] 根据权利要求 9或 10或 11所述氮化物半导体元件的制作方法， 其特征 在于： 所述步骤 （2) 中形成的 Al xGa (1— X)N层位于所述图形衬底之单 个图形之侧壁的晶体缺陷尺寸大于 lOnm的个数小于 10。
[权利要求 13] 根据权利要求 9或 10或 11所述氮化物半导体元件的制作方法， 其特征 在于： 所述步骤 （3) 中形成的氮化镓基半导体叠层包含 n型半导体层
、 发光层和 p型半导体层。
[权利要求 14] 一种氮化物半导体元件， 其采用前述权利要求 8-13所述的任意一种制 作方法获得。
PCT/CN2018/078653 2017-04-05 2018-03-12 氮化物半导体元件及其制作方法 WO2018184444A1 (zh)

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