WO2024040958A1 - 基于氧化铝氧化硅复合衬底的led芯片及其制造方法 - Google Patents

基于氧化铝氧化硅复合衬底的led芯片及其制造方法 Download PDF

Info

Publication number
WO2024040958A1
WO2024040958A1 PCT/CN2023/083072 CN2023083072W WO2024040958A1 WO 2024040958 A1 WO2024040958 A1 WO 2024040958A1 CN 2023083072 W CN2023083072 W CN 2023083072W WO 2024040958 A1 WO2024040958 A1 WO 2024040958A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
aluminum
substrate
composite
silicon oxide
Prior art date
Application number
PCT/CN2023/083072
Other languages
English (en)
French (fr)
Inventor
江汉
程虎
徐洋洋
黎国昌
徐志军
王文君
Original Assignee
聚灿光电科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 聚灿光电科技股份有限公司 filed Critical 聚灿光电科技股份有限公司
Priority to DE112023000173.1T priority Critical patent/DE112023000173T5/de
Priority to KR1020247006838A priority patent/KR20240036106A/ko
Publication of WO2024040958A1 publication Critical patent/WO2024040958A1/zh

Links

Classifications

    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C28/00—Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D
    • C23C28/04—Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D only coatings of inorganic non-metallic material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/22—Roughened surfaces, e.g. at the interface between epitaxial layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes

Definitions

  • the present application relates to the technical field of LED chips, and in particular to an LED chip based on an alumina-silicon oxide composite substrate and a manufacturing method thereof.
  • LED Light Emitting Diode
  • MOCVD Metal-Organic Chemical Vapor Deposition
  • PSS substrate Powder Sapphire Substrate, patterned sapphire substrate
  • ICP inductively coupled plasma
  • the longitudinal epitaxy of the GaN material becomes lateral epitaxy.
  • it can effectively reduce the dislocation density of GaN epitaxial materials, thereby reducing non-radiative recombination in the active area, reducing reverse leakage current, and improving the life of the LED;
  • the light emitted by the active area passes through GaN and sapphire Multiple scattering at the substrate interface changes the exit angle of the total reflected light and increases the probability of the light from the flip-chip LED emerging from the sapphire substrate, thus improving the light extraction efficiency.
  • the LED market tends to be stable and conventionally manufactured, and the demand for high-end cutting-edge products is increasingly urgent, especially high-light-efficiency products.
  • it is increasingly difficult to improve internal quantum efficiency, which makes measures to improve external quantum efficiency and light extraction efficiency even more important.
  • alumina silicon oxide (Al 2 O 3 /SiO 2 ) composite PSS substrate with LED barrier crystal bottom layer that is, using Al 2 O 3 /SiO 2 composite PSS Substrate, epitaxially grow a layer of AlN (aluminum nitride) as a buffer layer on the Al 2 O 3 /SiO 2 composite PSS substrate pattern, and then epitaxially grow the LED structural layer on the buffer layer.
  • AlN aluminum nitride
  • This application provides an LED chip based on an alumina-silicon oxide composite substrate and a manufacturing method thereof to solve the problems of poor thickness uniformity and poor crystal lattice quality when using an AlN buffer layer.
  • this application provides an LED chip based on an alumina-silicon oxide composite substrate, including: an alumina-silicon oxide composite PSS substrate, a composite buffer layer and an LED structural layer, wherein the composite buffer layer is epitaxially grown on alumina oxygen On the silicon composite PSS substrate, the LED structural layer is epitaxially grown on the composite buffer layer;
  • the composite buffer layer includes: aluminum oxynitride/aluminum nitride layer and silicon oxynitride layer, aluminum oxide in the aluminum oxide silicon oxide composite PSS substrate is covered by an aluminum oxynitride/aluminum nitride layer, and the silicon oxide in the aluminum oxide silicon oxide composite PSS substrate is covered by an aluminum oxynitride/aluminum nitride layer and a silicon oxynitride layer at alternating intervals; aluminum oxynitride/aluminum nitride The aluminum nitride oxide in the layer is connected to the aluminum oxide silicon oxide composite PSS substrate,
  • the thickness of aluminum oxynitride in the aluminum oxynitride/aluminum nitride layer is 30%-60% of the overall thickness of the aluminum oxynitride/aluminum nitride layer.
  • the thickness of the aluminum oxynitride/aluminum nitride layer is 100-250A, and the thickness of the silicon oxynitride layer is 100-300A.
  • this application also provides an LED chip manufacturing method for manufacturing the LED chip based on the alumina-silicon oxide composite substrate of the first aspect.
  • the manufacturing method includes: placing the alumina-silicon oxide composite PSS substrate into a physical In the vapor deposition equipment, the aluminum oxynitride/aluminum nitride layer is epitaxially grown through physical vapor deposition to obtain the first substrate; the first substrate is placed in the metal organic compound chemical vapor deposition equipment, and the aluminum oxynitride/aluminum nitride layer is epitaxially grown through metal organic compound chemical vapor deposition.
  • a silicon oxynitride layer is grown to obtain a second substrate; an LED structural layer is epitaxially grown on the second substrate.
  • the aluminum oxide silicon oxide composite PSS substrate is placed into a physical vapor deposition device, and an aluminum oxynitride/aluminum nitride layer is epitaxially grown through physical vapor deposition.
  • the step of obtaining the first substrate includes: physical vapor deposition In the equipment cavity, in a nitrogen atmosphere, argon gas is used to bombard the aluminum target through magnetron sputtering on the surface of the alumina-silicon oxide composite PSS substrate. Oxygen is introduced, and the aluminum oxynitride film is epitaxially grown on the alumina-silicon oxide film through the reaction. On the composite PSS substrate; stop flowing in oxygen, and the aluminum nitride film obtained by the reaction is epitaxially grown on the aluminum nitride oxide layer to obtain the first substrate.
  • the physical vapor deposition equipment sputtering power setting range is 3000-4500W
  • the sputtering temperature setting range is 500-650°C
  • the flow rate of oxygen is 2 sccm-6 sccm
  • the time of introducing oxygen is physical Vapor deposition epitaxy accounts for 30%-60% of the overall growth time.
  • the first substrate is placed into a metal organic compound chemical vapor deposition equipment, and a silicon oxynitride layer is epitaxially grown through metal organic compound chemical vapor deposition.
  • the step of obtaining the second substrate includes: in metal organic compound chemistry In the vapor deposition equipment, the first substrate is heat treated in a hydrogen atmosphere at a first preset temperature, and the heat treatment lasts for a first preset time; the atmosphere is converted into a mixed atmosphere of nitrogen and ammonia, in which nitrogen is the carrier gas. , ammonia is used as a reaction gas to provide a nitrogen source, and a thermal displacement reaction is performed at a second preset temperature.
  • the reaction results in a silicon oxynitride layer epitaxially grown on the first substrate, and the second preset temperature is lower than the first preset temperature.
  • the heat replacement reaction lasts for the second preset time; the mixed atmosphere of nitrogen and ammonia is maintained, and the temperature is controlled to drop to the third preset temperature for annealing treatment.
  • the third preset temperature is lower than the second preset temperature, and the annealing treatment continues for the third preset time. Set time to obtain the second substrate.
  • the first preset temperature range is 1050°C-1150°C, and the first preset time range is 1-5 min; the second preset temperature range is 800°C-1000°C, and the second preset time range is 5min-20min; the third preset temperature range is 550°C-650°C, and the third preset time range is 20min-30min.
  • the thickness of the epitaxially grown aluminum oxynitride/aluminum nitride layer is 100-250A, and the thickness of the epitaxially grown silicon oxynitride layer is 100-300A.
  • the LED chip includes an alumina-silicon oxide composite PSS substrate, a composite buffer layer and an LED structural layer, wherein the composite buffer layer is epitaxially grown on the oxide layer.
  • the LED structural layer is epitaxially grown on the composite buffer layer.
  • the composite buffer layer includes: aluminum oxynitride/aluminum nitride layer and silicon oxynitride layer.
  • the aluminum oxide in the aluminum oxide silicon oxide composite PSS substrate is covered by the aluminum oxynitride/aluminum nitride layer.
  • the aluminum oxide silicon oxide composite PSS liner The silicon oxide in the bottom is composed of aluminum oxynitride/aluminum nitride layer and oxynitride Silicone layers are covered at staggered intervals; the aluminum oxynitride in the aluminum nitride oxide/aluminum nitride layer is connected to the aluminum oxide silicon oxide composite PSS substrate, and the aluminum nitride in the aluminum oxynitride/aluminum nitride layer is connected to the LED structural layer.
  • the composite buffer layer has better thickness uniformity on alumina and silicon oxide materials, and can better buffer the lattice mismatch and stress release caused by different materials from the alumina-silicon oxide composite PSS substrate to the bottom layer of the LED barrier crystal, reducing Defects in the connecting layer.
  • Figure 1 is a schematic structural diagram of an LED chip based on an alumina-silicon oxide composite substrate according to some embodiments of the present application;
  • Figure 2 is a schematic structural diagram of an Al 2 O 3 /SiO 2 composite PSS substrate
  • Figure 3 is a schematic structural diagram of an AlN buffer layer
  • Figure 4 is a schematic structural diagram of an LED chip with an AlN buffer layer
  • Figure 5 is a TEM image of an LED chip with an AlN buffer layer
  • Figure 6 is a TEM image 2 of an LED chip with an AlN buffer layer
  • Figure 7 is a TEM image of an LED chip based on an alumina-silicon oxide composite substrate according to some embodiments of the present application.
  • Figure 8 is a TEM image two of an LED chip based on an alumina-silicon oxide composite substrate according to some embodiments of the present application.
  • Figure 9 is a schematic flow chart of an LED chip manufacturing method based on an alumina-silicon oxide composite substrate according to some embodiments of the present application.
  • Figure 10 is a schematic process diagram of MOCVD epitaxial growth of a SiOxNy layer on a first substrate to obtain a second substrate according to some embodiments of the present application;
  • Figure 11 is a schematic structural diagram of the epitaxial growth of an AlOxNy layer on an Al 2 O 3 /SiO 2 composite PSS substrate according to some embodiments of the present application;
  • Figure 12 is a schematic structural diagram of epitaxially growing an AlN layer on an AlOxNy layer according to some embodiments of the present application.
  • Figure 13 is a schematic structural diagram of the AlOxNy/AlN layer after heat treatment according to some embodiments of the present application.
  • Figure 14 is a schematic structural diagram of a composite buffer layer provided according to some embodiments of the present application.
  • FIG. 15 is a partially enlarged structural schematic diagram of position A in FIG. 14 .
  • Epitaxial growth refers to the growth of a single crystal layer with certain requirements and the same crystal orientation as the substrate on a single crystal substrate (substrate), as if the original crystal has extended outward.
  • epitaxial layers There are many methods for growing epitaxial layers, such as: Liquid Phase Epitaxy (LPE), Physical Vapor Deposition (PVD), Metal-organic Chemical Vapor Deposition (MOCVD), Hydrogenation Vapor phase epitaxy (Hydride Vapor Phase Epitaxy, HVPE), molecular beam epitaxy (Molecular Beam Epitaxy, MBE), etc.
  • LPE Liquid Phase Epitaxy
  • PVD Physical Vapor Deposition
  • MOCVD Metal-organic Chemical Vapor Deposition
  • HVPE Hydrogenation Vapor phase epitaxy
  • MBE molecular beam epitaxy
  • the MOCVD epitaxy process is most commonly used in general industrial production.
  • MOCVD is a new vapor phase epitaxial growth technology developed on the basis of Vapor Phase Epitaxy VPE.
  • MOCVD uses organic compounds of Group III and Group II elements and hydrides of Group V and Group VI elements as crystals Growth source materials are used for vapor phase epitaxy on the substrate in a thermal decomposition reaction to grow thin-layer single crystal materials of various III-V main group, II-VI subgroup compound semiconductors and their multi-element solid solutions.
  • MOCVD has the ability to accurately It has the advantages of controlling crystal growth, good repeatability, large output, and suitable for industrial large-scale production.
  • PVD technology uses physical methods under vacuum conditions to vaporize the surface of the material source (solid or liquid) into gaseous atoms, molecules or partially ionized into ions, and deposits certain ions on the surface of the substrate through a low-pressure gas (or plasma) process.
  • a low-pressure gas or plasma
  • Figure 2 is an Al 2 O 3 /SiO 2 composite PSS substrate.
  • a layer of AlN (aluminum nitride) is epitaxially grown on the Al 2 O 3 /SiO 2 composite PSS substrate pattern as a buffer layer, see Figure 3.
  • the LED structural layer is then epitaxially grown on the AlN buffer layer, see Figure 4.
  • the thickness of the AlN buffer layer on the SiO 2 material in the pattern part of the Al 2 O 3 /SiO 2 composite PSS substrate is 49A and 74A, while on the Al 2 O 3 /SiO 2 composite PSS substrate
  • the thickness of the AlN buffer layer on the Al 2 O 3 material of the pattern part is 125A and 152A. It can be seen that the thickness of the two is nearly doubled, and the thickness uniformity is not good. From the arrow position in Figure 5, it can be clearly seen that there are problems such as oxygen vacancy defects in the SiO 2 pattern part of the Al 2 O 3 /SiO 2 composite PSS substrate.
  • this application provides an LED chip based on an alumina-silicon oxide composite substrate, see Figure 1, including: an alumina-silicon oxide (Al 2 O 3 /SiO 2 ) composite PSS substrate, a composite buffer layer and LED structural layer, wherein the composite buffer layer is epitaxially grown on the alumina-silicon oxide composite PSS substrate, and the LED structural layer is epitaxially grown on the composite buffer layer.
  • an alumina-silicon oxide (Al 2 O 3 /SiO 2 ) composite PSS substrate a composite buffer layer and LED structural layer, wherein the composite buffer layer is epitaxially grown on the alumina-silicon oxide composite PSS substrate, and the LED structural layer is epitaxially grown on the composite buffer layer.
  • the composite buffer layer is used to better buffer the lattice mismatch and stress release caused by different materials from the Al 2 O 3 /SiO 2 composite PSS substrate to the LED barrier crystal bottom layer, and reduce defects at the connecting layer.
  • the LED structural layer is the main working structural layer of the LED.
  • the LED structural layer may include: U-type GaN layer, N-type GaN layer, stress release layer, electron-rich layer, multi-quantum well layer and P layer.
  • the U-shaped GaN layer serves as the bottom layer of the LED barrier crystal to improve external quantum efficiency and light extraction efficiency.
  • the N-type GaN layer is used to form the N-type region of the LED.
  • the electrons provided by the N-type region recombine with holes in the quantum well to excite light, which is one of the main structures of the LED.
  • Stress relief layer used to release stress between crystal lattice.
  • the electron enrichment layer is used to generate an enrichment effect for electrons in the N-type region.
  • Multiple quantum well (MQW) refers to a system in which multiple quantum wells are combined. In terms of material structure and growth process, there is no substantial difference between multiple quantum wells and superlattice. The only difference is that the superlattice barrier layer is relatively thin and the coupling between potential wells is strong, forming microstrips. The barrier layer is thick, there is basically no tunneling coupling, and no microstrips are formed.
  • the multi-quantum well structure is mainly used for its optical properties and is one of the basic structural layers of LED epitaxial structures.
  • the P layer is used to form the P-type area of the LED and is one of the main structures of the LED.
  • the composite buffer layer includes: aluminum oxynitride/aluminum nitride layer (AlOxNy/AlN) and silicon oxynitride layer (SiOxNy).
  • AlOxNy/AlN aluminum oxynitride/aluminum nitride layer
  • SiOxNy silicon oxynitride layer
  • the aluminum oxide in the aluminum oxide silicon composite PSS substrate is covered by an aluminum oxynitride/aluminum nitride layer
  • the silicon oxide in the aluminum oxide silicon oxide composite PSS substrate is covered by an aluminum oxynitride/aluminum nitride layer and a silicon oxynitride layer. Staggered interval coverage.
  • the aluminum oxynitride (AlOxNy) in the aluminum oxynitride/aluminum nitride layer is connected to the aluminum oxide silicon oxide composite PSS substrate, and the aluminum nitride (AlN) in the aluminum oxynitride/aluminum nitride layer is connected to the LED structural layer.
  • the thickness of aluminum oxynitride in the aluminum oxynitride/aluminum nitride layer is 30%-60% of the overall thickness of the aluminum oxynitride/aluminum nitride layer. This setting is to reduce lattice defects. , making the crystal lattice denser.
  • the thickness of the aluminum oxynitride/aluminum nitride layer is 100-250A, and the thickness of the silicon oxynitride layer is 100-300A. This setting is to better buffer the lattice loss caused by different materials. Matching and stress relief, reducing defects at the connecting layer.
  • Figures 7 and 8 are respectively TEM images one and two of an LED chip based on an alumina-silicon oxide composite substrate according to some embodiments of the present application.
  • the thickness of the composite buffer layer on the SiO 2 material in the graphic part of the Al 2 O 3 /SiO 2 composite PSS substrate is 57A and 124A, while the thickness of the composite buffer layer on the Al 2 O 3 /SiO 2 composite PSS substrate
  • the thickness of the composite buffer layer on the Al 2 O 3 material of the graphic part is 88A and 117A. It can be seen that the thickness of the two is not much different. However, no obvious lattice defects can be seen in the SiO 2 pattern part of the Al 2 O 3 /SiO 2 composite PSS substrate in Figure 7, and its lattice is more dense.
  • the present application also provides an LED chip manufacturing method for preparing the LED chip based on the alumina-silicon oxide composite substrate in the above embodiments of the present application. See Figure 9.
  • the manufacturing method includes:
  • the PVD equipment sputtering power setting range is 3000-4500 watts W, and the sputtering temperature setting range is 500-650 degrees Celsius.
  • argon (Ar) is used to bombard aluminum.
  • the (Al) target is sputtered on the surface of the Al 2 O 3 /SiO 2 composite PSS substrate through magnetron sputtering.
  • Oxygen (O 2 ) is first introduced, and the flow rate of O 2 is 2 standard cubic centimeters/minute sccm-6 sccm , the reaction produces an AlOxNy film epitaxially grown on an Al 2 O 3 /SiO 2 composite PSS substrate. See Figure 11.
  • the time for introducing O 2 is 30%-60% of the entire PVD epitaxial growth time, that is, the thickness of AlOxNy is AlOxNy/ 30%-60% of the total thickness of the AlN layer.
  • AlN aluminum nitride
  • AlOxNy aluminum oxynitride
  • S200 Place the first substrate into a metal-organic compound chemical vapor deposition equipment, and epitaxially grow a silicon oxynitride layer through metal-organic compound chemical vapor deposition to obtain a second substrate. See Figure 10.
  • S200 is implemented by S210-S230.
  • the first substrate is transferred to a metal organic compound chemical vapor deposition (MOCVD) equipment.
  • MOCVD metal organic compound chemical vapor deposition
  • the first substrate is heat treated in a hydrogen (H 2 ) atmosphere at a first preset temperature.
  • the first preset temperature range is 1050°C-1150°C; the heat treatment lasts for the first preset time.
  • the first preset time range is 1-5 minutes.
  • S220 Perform a thermal displacement reaction at a second preset temperature to obtain a SiOxNy layer.
  • the atmosphere is converted into a mixed atmosphere of nitrogen (N2) and ammonia (NH 3 ), where N 2 is the carrier gas and NH 3 is the reaction gas to provide a nitrogen (N) source for heat replacement at the second preset temperature.
  • the second preset temperature is lower than the first preset temperature.
  • the second preset temperature range is 800°C-1000°C
  • the SiOxNy layer is epitaxially grown on the first substrate through the reaction.
  • the thermal displacement reaction continues for a second preset time.
  • the second preset time range is 5min-20min to control the thickness of the SiOxNy layer on the SiO2 surface layer and the concentration of the N replacement component.
  • the third preset temperature is smaller than the second preset temperature.
  • the third preset temperature range is 550°C-650°C, and the annealing process lasts for the third preset time.
  • the third preset time range is 20min-30min to remove a large amount of H impurities present in the surface layer of the SiOxNy film generated by the thermal replacement reaction in step S220.
  • a second substrate is obtained. See Figure 14.
  • the second substrate is an Al 2 O 3 /SiO 2 composite PSS substrate with a composite buffer layer.
  • the composite buffer layer includes: AlOxNy/AlN layer and SiOxNy layer, Al 2
  • AlOxNy/AlN layer is covered with an AlOxNy/AlN layer
  • the SiO 2 in the Al 2 O 3 /SiO 2 composite PSS substrate is covered with AlOxNy/AlN layers and SiOxNy layers at staggered intervals.
  • Figure 15 is a partially enlarged structural schematic diagram of position A in Figure 14.
  • the thickness of the epitaxially grown AlOxNy/AlN layer is 100-250A
  • the thickness of the epitaxially grown SiOxNy layer is 100-300A.
  • S300 Epitaxially grow the LED structural layer on the second substrate.
  • LED structural layers such as U-type GaN layer, N-type GaN layer, stress release layer, electron enrichment layer, multi-quantum well layer and P layer can be epitaxially grown on the second substrate in sequence.
  • the LED structural layer can be epitaxially grown. Any method is adopted and will not be described in detail in this application.
  • Figures 7 and 8 are TEM images of LED chips manufactured using the above manufacturing method.
  • the thickness of the composite buffer layer on the SiO 2 material in the graphic part of the Al 2 O 3 /SiO 2 composite PSS substrate is 57A and 124A, while the thickness of the composite buffer layer on the Al 2 O 3 /SiO 2 composite PSS substrate
  • the thickness of the composite buffer layer on the Al 2 O 3 material of the graphic part is 88A and 117A. It can be seen that the thickness of the two is not much different.
  • no obvious lattice defects can be seen in the SiO 2 pattern part of the Al 2 O 3 /SiO 2 composite PSS substrate, and its lattice is more dense.
  • the thickness uniformity of the composite buffer layer on the Al 2 O 3 material and SiO 2 material of the Al 2 O 3 /SiO 2 composite PSS substrate is greatly improved. Moreover, there are no obvious lattice defects in the SiO 2 pattern part, and its lattice quality has also been greatly improved.
  • the LED chip includes an alumina-silicon oxide composite PSS substrate, a composite buffer layer and an LED structural layer.
  • the composite buffer layer is epitaxially grown on the aluminum oxide silicon oxide composite PSS substrate, and the LED structural layer is epitaxially grown on the composite buffer layer.
  • the composite buffer layer includes: aluminum oxynitride/aluminum nitride layer and silicon oxynitride layer.
  • the aluminum oxide in the aluminum oxide silicon oxide composite PSS substrate is covered by the aluminum oxynitride/aluminum nitride layer.
  • the aluminum oxide silicon oxide composite PSS liner The silicon oxide in the bottom is covered by aluminum oxynitride/aluminum nitride layers and silicon oxynitride layers at alternating intervals.
  • the aluminum oxynitride in the aluminum oxynitride/aluminum nitride layer is connected to the aluminum oxide silicon oxide composite PSS substrate, and the aluminum nitride in the aluminum oxynitride/aluminum nitride layer is connected to the LED structural layer.
  • the composite buffer layer has better thickness uniformity on alumina and silicon oxide materials, and can better buffer the lattice mismatch and stress release caused by different materials from the alumina-silicon oxide composite PSS substrate to the bottom layer of the LED barrier crystal, reducing Defects at the connecting layer.

Abstract

本申请提供一种基于氧化铝氧化硅复合衬底的LED芯片及其制造方法，LED芯片包括氧化铝氧化硅复合PSS衬底、复合缓冲层和LED结构层，其中，复合缓冲层外延生长在氧化铝氧化硅复合PSS衬底上，LED结构层外延生长在复合缓冲层上。复合缓冲层包括：氮氧化铝/氮化铝层和氮氧化硅层，氧化铝氧化硅复合PSS衬底中的氧化铝上由氮氧化铝/氮化铝层覆盖，氧化铝氧化硅复合PSS衬底中的氧化硅上由氮氧化铝/氮化铝层和氮氧化硅层交错间隔覆盖。复合缓冲层在氧化铝和氧化硅材料上有更好厚度均匀性，并且可以更好缓冲氧化铝氧化硅复合PSS衬底到LED垒晶底层因材质不同引起的晶格失配和应力释放，减少衔接层处的缺陷。

Description

基于氧化铝氧化硅复合衬底的LED芯片及其制造方法
本申请要求于2022年8月24日提交到国家知识产权局、申请号为202211021069.3、发明名称为“一种基于氧化铝氧化硅复合衬底的LED芯片及其制造方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及LED芯片技术领域，尤其涉及一种基于氧化铝氧化硅复合衬底的LED芯片及其制造方法。
背景技术
LED(Light Emitting Diode，发光二极管)是一种常用的发光器件，通过电子与空穴复合释放能量发光，LED产品被广泛应用于各行各业，并在人们的日常生活及生产中起到重要作用。行业内主要采用MOCVD(Metal-Organic Chemical Vapour Deposition，金属有机化合物化学气相沉积)法来制备LED的外延片，一般使用PSS衬底(Patterned Sapphire Substrate，图形化蓝宝石衬底)。在PSS衬底材料上生长干法刻蚀用掩膜，并用标准的光刻工艺将掩膜刻出图形，再利用ICP(inductively coupled plasma，电感耦合等离子体)刻蚀技术刻蚀蓝宝石并去掉掩膜，在其上生长GaN(氮化镓)材料，使GaN材料的纵向外延变为横向外延。一方面可以有效减少GaN外延材料的位错密度，从而减小有源区的非辐射复合，减小反向漏电流，提高LED的寿命；另一方面有源区发出的光，经GaN和蓝宝石衬底界面的多次散射，改变了全反射光的出射角，增加了倒装LED的光从蓝宝石衬底出射的几率，从而提高了光的提取效率。
LED市场趋于平稳与常规制造化，针对高阶尖端产品的需求日益迫切，尤其是高光效型产品。但是目前内量子效率提升难度日趋增大，这就使得提升外量子效率以及光萃取效率的措施显得更加重要。行业内为了提升外量子效率以及光萃取效率，一般采用氧化铝氧化硅(Al2O3/SiO2)复合PSS衬底搭配LED垒晶底层的方式，即采用Al2O3/SiO2复合PSS衬底，在Al2O3/SiO2复合PSS衬底图形上外延生长一层AlN(氮化铝)作为缓冲层，之后在缓冲层上外延生长LED结构层。
但是一方面因AlN和GaN材料的生长率，在Al2O3/SiO2复合PSS衬底图形部分的Al2O3材料上和SiO2材料上相差比较大，使AlN缓冲层厚度均匀性不好。另一方面Al2O3/SiO2复合PSS衬底的SiO2图形部分，SiO2材料层晶格质量较差，其中存在浓度较高的氧空位缺陷等问题。
发明内容
本申请提供了一种基于氧化铝氧化硅复合衬底的LED芯片及其制造方法，以解决的使用AlN缓冲层厚度均匀性不好，及晶格质量较差的问题。
第一方面，本申请提供一种基于氧化铝氧化硅复合衬底的LED芯片，包括：氧化铝氧化硅复合PSS衬底、复合缓冲层和LED结构层，其中，复合缓冲层外延生长在氧化铝氧 化硅复合PSS衬底上，LED结构层外延生长在复合缓冲层上；复合缓冲层包括：氮氧化铝/氮化铝层和氮氧化硅层，氧化铝氧化硅复合PSS衬底中的氧化铝上由氮氧化铝/氮化铝层覆盖，氧化铝氧化硅复合PSS衬底中的氧化硅上由氮氧化铝/氮化铝层和氮氧化硅层交错间隔覆盖；氮氧化铝/氮化铝层中的氮氧化铝与氧化铝氧化硅复合PSS衬底连接，氮氧化铝/氮化铝层中的氮化铝与LED结构层连接。
在一些实施例中，氮氧化铝/氮化铝层中的氮氧化铝厚度为氮氧化铝/氮化铝层整体厚度的30％-60％。
在一些实施例中，氮氧化铝/氮化铝层厚度为100-250A，氮氧化硅层厚度为100-300A。
第二方面，本申请还提供一种LED芯片制造方法，用于制造第一方面的基于氧化铝氧化硅复合衬底的LED芯片，制造方法包括：将氧化铝氧化硅复合PSS衬底放入物理气相沉积设备中，通过物理气相沉积外延生长氮氧化铝/氮化铝层，得到第一衬底；将第一衬底放入金属有机化合物化学气相沉积设备中，通过金属有机化合物化学气相沉积外延生长氮氧化硅层，得到第二衬底；在第二衬底上外延生长LED结构层。
在一些实施例中，将氧化铝氧化硅复合PSS衬底放入物理气相沉积设备中，通过物理气相沉积外延生长氮氧化铝/氮化铝层，得到第一衬底的步骤包括：物理气相沉积设备腔中，在氮气氛围中，采用氩气轰击铝靶材通过磁控溅射在氧化铝氧化硅复合PSS衬底基板表面，通入氧气，反应得到氮氧化铝薄膜外延生长在氧化铝氧化硅复合PSS衬底上；停止通入氧气，反应得到氮化铝薄膜外延生长在氮氧化铝层上，得到第一衬底。
在一些实施例中，物理气相沉积设备溅射功率设定范围为3000-4500W，溅射温度设定范围为500-650℃；通入氧气的流量为2sccm-6sccm，通入氧气的时间为物理气相沉积外延生长整体时间的30％-60％。
在一些实施例中，将第一衬底放入金属有机化合物化学气相沉积设备中，通过金属有机化合物化学气相沉积外延生长氮氧化硅层，得到第二衬底的步骤包括：在金属有机化合物化学气相沉积设备中，对第一衬底采取在氢气氛围中，以第一预设温度进行热处理，热处理持续第一预设时间；气氛转化为氮气和氨气混合气氛的方式，其中氮气为载气，氨气为反应气体，用以提供氮源，以第二预设温度进行热置换反应，反应得到氮氧化硅层外延生长在第一衬底上，第二预设温度小于第一预设温度，热置换反应持续第二预设时间；维持氮气和氨气混合气氛，温度控制下降到第三预设温度进行退火处理，第三预设温度小于第二预设温度，退火处理持续第三预设时间，得到第二衬底。
在一些实施例中，第一预设温度范围为1050℃-1150℃，第一预设时间范围为1-5min；第二预设温度范围为800℃-1000℃，第二预设时间范围为5min-20min；第三预设温度范围为550℃-650℃，第三预设时间范围为20min-30min。
在一些实施例中，外延生长氮氧化铝/氮化铝层厚度为100-250A，外延生长氮氧化硅层厚度为100-300A。
本申请提供一种基于氧化铝氧化硅复合衬底的LED芯片及其制造方法，LED芯片包括氧化铝氧化硅复合PSS衬底、复合缓冲层和LED结构层，其中，复合缓冲层外延生长在氧化铝氧化硅复合PSS衬底上，LED结构层外延生长在复合缓冲层上。复合缓冲层包括：氮氧化铝/氮化铝层和氮氧化硅层，氧化铝氧化硅复合PSS衬底中的氧化铝上由氮氧化铝/氮化铝层覆盖，氧化铝氧化硅复合PSS衬底中的氧化硅上由氮氧化铝/氮化铝层和氮氧 化硅层交错间隔覆盖；氮氧化铝/氮化铝层中的氮氧化铝与氧化铝氧化硅复合PSS衬底连接，氮氧化铝/氮化铝层中的氮化铝与LED结构层连接。复合缓冲层在氧化铝和氧化硅材料上有更好厚度均匀性，并且可以更好缓冲氧化铝氧化硅复合PSS衬底到LED垒晶底层因材质不同引起的晶格失配和应力释放，减少衔接层处的缺陷。
附图说明
为了更清楚地说明本申请的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，对于本领域普通技术人员而言，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为根据本申请一些实施例提供的一种基于氧化铝氧化硅复合衬底的LED芯片的结构示意图；
图2为一种Al2O3/SiO2复合PSS衬底的结构示意图；
图3为一种AlN缓冲层的结构示意图；
图4为一种AlN缓冲层的LED芯片的结构示意图；
图5为一种AlN缓冲层的LED芯片的TEM图像一；
图6为一种AlN缓冲层的LED芯片的TEM图像二；
图7为根据本申请一些实施例提供的一种基于氧化铝氧化硅复合衬底的LED芯片的TEM图像一；
图8为根据本申请一些实施例提供的一种基于氧化铝氧化硅复合衬底的LED芯片的TEM图像二；
图9为根据本申请一些实施例提供的一种基于氧化铝氧化硅复合衬底的LED芯片制造方法的流程示意图；
图10为根据本申请一些实施例提供的第一衬底上MOCVD外延生长SiOxNy层得到第二衬底的流程示意图；
图11为根据本申请一些实施例提供的在Al2O3/SiO2复合PSS衬底上外延生长AlOxNy层的结构示意图；
图12为根据本申请一些实施例提供的在AlOxNy层上外延生长AlN层的结构示意图；
图13为根据本申请一些实施例提供的在AlOxNy/AlN层经过热处理后的结构示意图；
图14为根据本申请一些实施例提供的复合缓冲层的结构示意图；
图15为图14中A处的局部放大的结构示意图。
具体实施方式
下面将详细地对实施例进行说明，其示例表示在附图中。下面的描述涉及附图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下实施例中描述的实施方式并不代表与本申请相一致的所有实施方式。仅是与权利要求书中所详述的、本申请的一些方面相一致的系统和方法的示例。
外延生长是指在单晶衬底(基片)上生长一层具有一定要求的、与衬底晶向相同的单晶层，犹如原来的晶体向外延伸了一段。生长外延层有多种方法，例如：液相外延(Liquid Phase Epitaxy，LPE)、物理气相沉积(Physical Vapour Deposition，PVD)、金属有机化合物化学气相沉积(Metal-organic Chemical Vapor Deposition，MOCVD)、氢化物气相外延 (Hydride Vapor Phase Epitaxy，HVPE)、分子束外延(Molecular Beam Epitaxy，MBE)等，一般工业化生产采用最多的是MOCVD外延工艺。
MOCVD(是在气相外延生长(Vapor Phase Epitaxy VPE)的基础上发展的一种新型气相外延生长技术。MOCVD是以Ⅲ族、Ⅱ族元素的有机化合物和V、Ⅵ族元素的氢化物等作为晶体生长源材料，以热分解反应的方式在衬底上进行气相外延，生长各种Ⅲ-V主族、Ⅱ-Ⅵ副族化合物半导体以及它们的多元固溶体的薄层单晶材料。MOCVD具有可以精确控制晶体生长、重复性好、产量大、适合工业化大生产等优点。
PVD技术是在真空条件下，采用物理方法，将材料源(固体或液体)表面气化成气态原子、分子或部分电离成离子，并通过低压气体(或等离子体)过程，在基体表面沉积具有某种特殊功能的薄膜技术。
在一些实施例中，参见图2，为一种Al2O3/SiO2复合PSS衬底。在Al2O3/SiO2复合PSS衬底图形上外延生长一层AlN(氮化铝)作为缓冲层，参见图3。之后在AlN缓冲层上外延生长LED结构层，参见图4。
但是，一方面因AlN和GaN材料的生长率，在Al2O3/SiO2复合PSS衬底图形部分的Al2O3材料上和SiO2材料上相差比较大。另一方面Al2O3/SiO2复合PSS衬底的SiO2图形部分，SiO2材料层晶格质量较差，其中存在浓度较高的氧空位缺陷等问题。图5和图6为上述实施例中，使用透射电子显微镜(Transmission Electron Microscope，简称TEM)得到的微观图像。从图6中可以看出，在Al2O3/SiO2复合PSS衬底图形部分的SiO2材料上AlN缓冲层的厚度为49A和74A，而在Al2O3/SiO2复合PSS衬底图形部分的Al2O3材料上AlN缓冲层的厚度为125A和152A。可见，两者的厚度相差近一倍，厚度均匀性并不好。而从图5中的箭头位置可以很明显的看到Al2O3/SiO2复合PSS衬底的SiO2图形部分存在氧空位缺陷等问题。
为了解决上述问题，本申请提供一种基于氧化铝氧化硅复合衬底的LED芯片，参见图1，包括：氧化铝氧化硅(Al2O3/SiO2)复合PSS衬底、复合缓冲层和LED结构层，其中，复合缓冲层外延生长在氧化铝氧化硅复合PSS衬底上，LED结构层外延生长在复合缓冲层上。
复合缓冲层，用于更好缓冲Al2O3/SiO2复合PSS衬底到LED垒晶底层因材质不同引起的晶格失配和应力释放，减少衔接层处的缺陷。LED结构层为LED的主体工作结构层。示例的，LED结构层可以包括：U型GaN层、N型GaN层、应力释放层、电子富集层、多量子阱层和P层。其中，U型GaN层作为LED垒晶底层，用于提升外量子效率以及光萃取效率。N型GaN层，用于形成LED的N型区，N型区提供的电子在量子阱内与空穴复合激发出光，为LED的主要结构之一。应力释放层，用于释放晶格之间的应力。电子富集层，用于为N型区的电子产生富集效应。多量子阱层(multiple quantum well，MQW)，是指多个量子阱组合在一起的系统。就材料结构和生长过程而言，多量子阱和超晶格没有实质差别，仅在于超晶格势垒层比较薄，势阱之间的耦合较强，形成微带，而多量子阱之间的势垒层厚，基本无隧穿耦合，也不形成微带。多量子阱结构主要应用于其光学特性，为LED外延结构基本结构层之一。P层，用于形成LED的P型区，为LED的主要结构之一。
复合缓冲层包括：氮氧化铝/氮化铝层(AlOxNy/AlN)和氮氧化硅层(SiOxNy)，氧化 铝氧化硅复合PSS衬底中的氧化铝上由氮氧化铝/氮化铝层覆盖，氧化铝氧化硅复合PSS衬底中的氧化硅上由氮氧化铝/氮化铝层和氮氧化硅层交错间隔覆盖。氮氧化铝/氮化铝层中的氮氧化铝(AlOxNy)与氧化铝氧化硅复合PSS衬底连接，氮氧化铝/氮化铝层中的氮化铝(AlN)与LED结构层连接。
在一种示意性的实施方式中，氮氧化铝/氮化铝层中的氮氧化铝厚度为氮氧化铝/氮化铝层整体厚度的30％-60％，这样设置是为了减少晶格缺陷，使晶格更加致密。
在一种示意性的实施方式中，氮氧化铝/氮化铝层厚度为100-250A，氮氧化硅层厚度为100-300A，这样设置是为了更好的缓冲因材质不同引起的晶格失配和应力释放，减少衔接层处的缺陷。
图7和图8分别为根据本申请一些实施例提供的一种基于氧化铝氧化硅复合衬底的LED芯片的TEM图像一和图像二。从图8中可以看出，在Al2O3/SiO2复合PSS衬底图形部分的SiO2材料上复合缓冲层的厚度为57A和124A，而在Al2O3/SiO2复合PSS衬底图形部分的Al2O3材料上复合缓冲层的厚度为88A和117A，可见，两者的厚度相差不大。而从图7中Al2O3/SiO2复合PSS衬底的SiO2图形部分看不到有明显的晶格缺陷，其晶格更加致密。
基于上述实施例，本申请还提供一种LED芯片制造方法，用于制备上述本申请实施例中基于氧化铝氧化硅复合衬底的LED芯片，参见图9，制造方法包括：
S100：将Al2O3/SiO2复合PSS衬底放入物理气相沉积(PVD)设备中，通过物理气相沉积外延生长AlOxNy/AlN层，得到第一衬底。
PVD设备腔中，PVD设备溅射功率设定范围为3000-4500瓦特W，溅射温度设定范围为500-650摄氏度℃，在氮气(N2)氛围中，采用氩气(Ar)轰击铝(Al)靶材通过磁控溅射在Al2O3/SiO2复合PSS衬底基板表面，先通入氧气(O2)，通入O2的流量为2标准立方厘米/分钟sccm-6sccm，反应得到AlOxNy薄膜外延生长在Al2O3/SiO2复合PSS衬底上，参见图11，通入O2的时间为PVD外延生长整体时间的30％-60％，即AlOxNy厚度为AlOxNy/AlN层总厚度的30％-60％。之后停止通入氧气，反应得到氮化铝(AlN)薄膜外延生长在氮氧化铝(AlOxNy)层上，参见图12，得到第一衬底，第一衬底是带有PVD沉积AlOxNy/AlN层的Al2O3/SiO2复合PSS衬底。
S200：将第一衬底放入金属有机化合物化学气相沉积设备中，通过金属有机化合物化学气相沉积外延生长氮氧化硅层，得到第二衬底，参见图10，S200由S210-S230实现。
S210：在MOCVD设备中，对第一衬底以第一预设温度进行热处理。
将第一衬底转移到金属有机化合物化学气相沉积(MOCVD)设备中，在MOCVD设备中，对第一衬底采取在氢气(H2)氛围中，以第一预设温度进行热处理。示例的，第一预设温度范围为1050℃-1150℃；热处理持续第一预设时间。示例的，第一预设时间范围为1-5min。
参见图13，SiO2图形表层处AlOxNy/AlN层沉积生长难度较大，SEM扫描显示其生长形貌为非薄膜式的不规则间断分布。因此，需要进行热处理以去除衬底表层水氧等杂质，且在高温过程中，可使得沉积在SiO2表层部分的AlOxNy/AlN层复合物质产生团聚效应形成间隔较大的颗粒状，从而裸露出更大面积的SiO2表层。
S220：以第二预设温度进行热置换反应，得到SiOxNy层。
气氛转化为氮气(N2)和氨气(NH3)混合气氛的方式，其中N2为载气，NH3为反应气体，用以提供氮(N)源，以第二预设温度进行热置换反应，第二预设温度小于第一预设温度。示例的，第二预设温度范围为800℃-1000℃，反应得到SiOxNy层外延生长在第一衬底上。参见图14，热置换反应持续第二预设时间。示例的，第二预设时间范围为5min-20min，以控制SiO2表层SiOxNy层的厚度和N置换组分浓度。
S230：温度下降到第三预设温度进行退火处理，得到第二衬底。
继续维持N2和NH3混合气氛，将温度控制下降到第三预设温度进行退火处理，第三预设温度小于第二预设温度。示例的，第三预设温度范围为550℃-650℃，退火处理持续第三预设时间。示例的，第三预设时间范围为20min-30min，以去除S220步骤中热置换反应生成的SiOxNy薄膜表层存在的大量H杂质。退火后得到第二衬底，参见图14，第二衬底为带有复合缓冲层的Al2O3/SiO2复合PSS衬底，复合缓冲层包括：AlOxNy/AlN层和SiOxNy层，Al2O3/SiO2复合PSS衬底中的Al2O3上由AlOxNy/AlN层覆盖，Al2O3/SiO2复合PSS衬底中的SiO2上由AlOxNy/AlN层和SiOxNy层交错间隔覆盖，参见图15，图15为图14中A处的局部放大的结构示意图。示例的，外延生长AlOxNy/AlN层厚度为100-250A，外延生长SiOxNy层厚度为100-300A。
S300：在第二衬底上外延生长LED结构层。
示例的，可以在第二衬底上依次外延生长U型GaN层、N型GaN层、应力释放层、电子富集层、多量子阱层和P层等LED结构层，外延生长LED结构层可以采用任意方法，本申请不再赘述。
图7和图8为使用上述制造方法制造的LED芯片的TEM图像。从图8中可以看出，在Al2O3/SiO2复合PSS衬底图形部分的SiO2材料上复合缓冲层的厚度为57A和124A，而在Al2O3/SiO2复合PSS衬底图形部分的Al2O3材料上复合缓冲层的厚度为88A和117A，可见，两者的厚度相差不大。而从图7中可以看出，Al2O3/SiO2复合PSS衬底的SiO2图形部分看不到有明显的晶格缺陷，其晶格更加致密。相比于图5和图6中的LED芯片，复合缓冲层在Al2O3/SiO2复合PSS衬底的Al2O3材料上和SiO2材料上的厚度均匀性有很大的提高，而且在SiO2图形部分没有明显的晶格缺陷，其晶格质量也有很大的提高。
本申请提供一种基于氧化铝氧化硅复合衬底的LED芯片及其制造方法，LED芯片包括氧化铝氧化硅复合PSS衬底、复合缓冲层和LED结构层。其中，复合缓冲层外延生长在氧化铝氧化硅复合PSS衬底上，LED结构层外延生长在复合缓冲层上。复合缓冲层包括：氮氧化铝/氮化铝层和氮氧化硅层，氧化铝氧化硅复合PSS衬底中的氧化铝上由氮氧化铝/氮化铝层覆盖，氧化铝氧化硅复合PSS衬底中的氧化硅上由氮氧化铝/氮化铝层和氮氧化硅层交错间隔覆盖。氮氧化铝/氮化铝层中的氮氧化铝与氧化铝氧化硅复合PSS衬底连接，氮氧化铝/氮化铝层中的氮化铝与LED结构层连接。复合缓冲层在氧化铝和氧化硅材料上有更好厚度均匀性，并且可以更好缓冲氧化铝氧化硅复合PSS衬底到LED垒晶底层因材质不同引起的晶格失配和应力释放，减少衔接层处的缺陷。
本申请提供的实施例之间的相似部分相互参见即可，以上提供的具体实施方式只是本申请总的构思下的几个示例，并不构成本申请保护范围的限定。对于本领域的技术人员而言，在不付出创造性劳动的前提下依据本申请方案所扩展出的任何其他实施方式都属于本申请的保护范围。

Claims (9)

  1. 一种基于氧化铝氧化硅复合衬底的LED芯片，其特征在于，包括：氧化铝氧化硅复合PSS衬底、复合缓冲层和LED结构层，其中，所述复合缓冲层外延生长在所述氧化铝氧化硅复合PSS衬底上，所述LED结构层外延生长在所述复合缓冲层上；
    所述复合缓冲层包括：氮氧化铝/氮化铝层和氮氧化硅层；
    所述氧化铝氧化硅复合PSS衬底中的氧化铝上由所述氮氧化铝/氮化铝层覆盖，所述氧化铝氧化硅复合PSS衬底中的氧化硅上由所述氮氧化铝/氮化铝层和所述氮氧化硅层交错间隔覆盖；
    所述氮氧化铝/氮化铝层中的氮氧化铝与所述氧化铝氧化硅复合PSS衬底连接，所述氮氧化铝/氮化铝层中的氮化铝与所述LED结构层连接。
  2. 根据权利要求1所述的基于氧化铝氧化硅复合衬底的LED芯片，其特征在于，所述氮氧化铝/氮化铝层中的氮氧化铝厚度为所述氮氧化铝/氮化铝层整体厚度的30％-60％。
  3. 根据权利要求1所述的基于氧化铝氧化硅复合衬底的LED芯片，其特征在于，所述氮氧化铝/氮化铝层厚度为100-250A，所述氮氧化硅层厚度为100-300A。
  4. 一种LED芯片制造方法，用于制造权利要求1-3任一项所述的基于氧化铝氧化硅复合衬底的LED芯片，其特征在于，所述制造方法包括：
    将氧化铝氧化硅复合PSS衬底放入物理气相沉积设备中，通过物理气相沉积外延生长氮氧化铝/氮化铝层，得到第一衬底；
    将所述第一衬底放入金属有机化合物化学气相沉积设备中，通过金属有机化合物化学气相沉积外延生长氮氧化硅层，得到第二衬底；
    在所述第二衬底上外延生长LED结构层。
  5. 根据权利要求4所述的LED芯片制造方法，其特征在于，所述将氧化铝氧化硅复合PSS衬底放入物理气相沉积设备中，通过物理气相沉积外延生长氮氧化铝/氮化铝层，得到第一衬底的步骤包括：
    物理气相沉积设备腔中，在氮气氛围中，采用氩气轰击铝靶材通过磁控溅射在所述氧化铝氧化硅复合PSS衬底基板表面，通入氧气，反应得到氮氧化铝薄膜外延生长在所述氧化铝氧化硅复合PSS衬底上；
    停止通入氧气，反应得到氮化铝薄膜外延生长在氮氧化铝层上，得到所述第一衬底。
  6. 根据权利要求5所述的LED芯片制造方法，其特征在于，物理气相沉积设备溅射功率设定范围为3000-4500W，溅射温度设定范围为500-650℃；通入氧气的流量为2sccm-6sccm，通入氧气的时间为物理气相沉积外延生长整体时间的30％-60％。
  7. 根据权利要求4所述的LED芯片制造方法，其特征在于，所述将所述第一衬底放入金属有机化合物化学气相沉积设备中，通过金属有机化合物化学气相沉积外延生长氮氧化硅层，得到第二衬底的步骤包括：
    在金属有机化合物化学气相沉积设备中，对所述第一衬底采取在氢气氛围中，以第一预设温度进行热处理，热处理持续第一预设时间；
    气氛转化为氮气和氨气混合气氛的方式，其中氮气为载气，氨气为反应气体，用 以提供氮源，以第二预设温度进行热置换反应，反应得到氮氧化硅层外延生长在所述第一衬底上，所述第二预设温度小于所述第一预设温度，热置换反应持续第二预设时间；
    维持氮气和氨气混合气氛，温度控制下降到第三预设温度进行退火处理，所述第三预设温度小于所述第二预设温度，退火处理持续第三预设时间，得到所述第二衬底。
  8. 根据权利要求7所述的LED芯片制造方法，其特征在于，所述第一预设温度范围为1050℃-1150℃，所述第一预设时间范围为1-5min；所述第二预设温度范围为800℃-1000℃，所述第二预设时间范围为5min-20min；所述第三预设温度范围为550℃-650℃，所述第三预设时间范围为20min-30min。
  9. 根据权利要求4所述的LED芯片制造方法，其特征在于，外延生长所述氮氧化铝/氮化铝层厚度为100-250A，外延生长所述氮氧化硅层厚度为100-300A。
PCT/CN2023/083072 2022-08-24 2023-03-22 基于氧化铝氧化硅复合衬底的led芯片及其制造方法 WO2024040958A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
DE112023000173.1T DE112023000173T5 (de) 2022-08-24 2023-03-22 LED Chip auf Basis eines Aluminiumoxid Siliziumdioxid Verbundsubstrats und ein Herstellungsverfahren dafür
KR1020247006838A KR20240036106A (ko) 2022-08-24 2023-03-22 산화알루미늄-산화규소 복합기판을 기반으로 하는 led 칩 및 그 제조방법

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202211021069.3A CN115692570A (zh) 2022-08-24 2022-08-24 一种基于氧化铝氧化硅复合衬底的led芯片及其制造方法
CN202211021069.3 2022-08-24

Publications (1)

Publication Number Publication Date
WO2024040958A1 true WO2024040958A1 (zh) 2024-02-29

Family

ID=85060752

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2023/083072 WO2024040958A1 (zh) 2022-08-24 2023-03-22 基于氧化铝氧化硅复合衬底的led芯片及其制造方法

Country Status (4)

Country Link
KR (1) KR20240036106A (zh)
CN (1) CN115692570A (zh)
DE (1) DE112023000173T5 (zh)
WO (1) WO2024040958A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115692570A (zh) * 2022-08-24 2023-02-03 聚灿光电科技股份有限公司 一种基于氧化铝氧化硅复合衬底的led芯片及其制造方法
CN116759505B (zh) * 2023-08-23 2023-11-17 江西兆驰半导体有限公司 基于硅衬底的led外延片及其制备方法、led

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102576663A (zh) * 2009-07-17 2012-07-11 应用材料公司 在图案化基材上藉由氢化物气相外延法(hvpe)形成三族氮化物结晶膜的方法
CN109786524A (zh) * 2019-02-22 2019-05-21 湘能华磊光电股份有限公司 一种具有新型pss结构的led外延层及其制备方法
CN114284415A (zh) * 2022-03-08 2022-04-05 江西兆驰半导体有限公司 一种倒装led外延结构及其制备方法
US20220199860A1 (en) * 2020-12-18 2022-06-23 Sky Tech Inc. Semiconductor component with oxidized aluminum nitride film and manufacturing method thereof
CN115692570A (zh) * 2022-08-24 2023-02-03 聚灿光电科技股份有限公司 一种基于氧化铝氧化硅复合衬底的led芯片及其制造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102576663A (zh) * 2009-07-17 2012-07-11 应用材料公司 在图案化基材上藉由氢化物气相外延法(hvpe)形成三族氮化物结晶膜的方法
CN109786524A (zh) * 2019-02-22 2019-05-21 湘能华磊光电股份有限公司 一种具有新型pss结构的led外延层及其制备方法
US20220199860A1 (en) * 2020-12-18 2022-06-23 Sky Tech Inc. Semiconductor component with oxidized aluminum nitride film and manufacturing method thereof
CN114284415A (zh) * 2022-03-08 2022-04-05 江西兆驰半导体有限公司 一种倒装led外延结构及其制备方法
CN115692570A (zh) * 2022-08-24 2023-02-03 聚灿光电科技股份有限公司 一种基于氧化铝氧化硅复合衬底的led芯片及其制造方法

Also Published As

Publication number Publication date
CN115692570A (zh) 2023-02-03
KR20240036106A (ko) 2024-03-19
DE112023000173T5 (de) 2024-04-25

Similar Documents

Publication Publication Date Title
WO2024040958A1 (zh) 基于氧化铝氧化硅复合衬底的led芯片及其制造方法
US7208393B2 (en) Growth of planar reduced dislocation density m-plane gallium nitride by hydride vapor phase epitaxy
US7956360B2 (en) Growth of planar reduced dislocation density M-plane gallium nitride by hydride vapor phase epitaxy
US8882910B2 (en) AlGaN substrate and production method thereof
KR102342796B1 (ko) Gan-기반 광전자 및 전자 장치를 위한 산소 제어된 pvd aln 버퍼
US20080152903A1 (en) System and Process for High-Density, Low-Energy Plasma Enhanced Vapor Phase Epitaxy
US20020155712A1 (en) Method of fabricating group-III nitride semiconductor crystal, method of fabricating gallium nitride-based compound semiconductor, gallium nitride-based compound semiconductor, gallium nitride-based compound semiconductor light-emitting device, and light source using the semiconductor light-emitting device
US8853086B2 (en) Methods for pretreatment of group III-nitride depositions
US9196795B2 (en) Formation of group III-V material layers on patterned substrates
US8138069B2 (en) Substrate pretreatment for subsequent high temperature group III depositions
JPH0864791A (ja) エピタキシャル成長方法
WO2005122267A2 (en) Growth of planar reduced dislocation density m-plane gallium nitride by hydride vapor phase epitaxy
WO2005112079A1 (ja) 酸化ガリウム単結晶複合体及びその製造方法並びに酸化ガリウム単結晶複合体を用いた窒化物半導体膜の製造方法
CN109103303A (zh) 一种发光二极管外延片的制备方法及发光二极管外延片
US20120235115A1 (en) Growth of iii-v led stacks using nano masks
JP2009155141A (ja) 半導体基板の作成方法ならびに半導体基板およびそれを用いる化合物半導体発光素子
WO2018184444A1 (zh) 氮化物半导体元件及其制作方法
CN114759126B (zh) 基于氮化物单晶衬底的半导体器件结构及其制备方法
JP2008297138A (ja) Ｉｉｉ族窒化物系化合物半導体製造用基板とその製造方法
JPH09295890A (ja) 半導体製造装置および半導体製造方法
CN112133802B (zh) 一种GaN薄膜及其制备方法
CN115763658A (zh) 一种基于新型图形化衬底的led芯片及其制造方法
CN112575378A (zh) 一种在hpve生长中实现一次或多次空洞掩埋插入层的方法
CN109860340A (zh) 一种发光二极管外延片的生长方法
JP3743013B2 (ja) エピタキシャルウェハの製造方法

Legal Events

Date Code Title Description
ENP Entry into the national phase

Ref document number: 20247006838

Country of ref document: KR

Kind code of ref document: A

WWE Wipo information: entry into national phase

Ref document number: 112023000173

Country of ref document: DE

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 23856054

Country of ref document: EP

Kind code of ref document: A1