WO2018176181A1 - Carte adaptatrice flexible pci-e à broches réadaptées - Google Patents

Carte adaptatrice flexible pci-e à broches réadaptées Download PDF

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Publication number
WO2018176181A1
WO2018176181A1 PCT/CN2017/000447 CN2017000447W WO2018176181A1 WO 2018176181 A1 WO2018176181 A1 WO 2018176181A1 CN 2017000447 W CN2017000447 W CN 2017000447W WO 2018176181 A1 WO2018176181 A1 WO 2018176181A1
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WIPO (PCT)
Prior art keywords
pin
wiring
pins
group
pci
Prior art date
Application number
PCT/CN2017/000447
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English (en)
Chinese (zh)
Inventor
陈亮合
陈彦为
Original Assignee
陈亮合
陈彦为
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Filing date
Publication date
Application filed by 陈亮合, 陈彦为 filed Critical 陈亮合
Publication of WO2018176181A1 publication Critical patent/WO2018176181A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R31/00—Coupling parts supported only by co-operation with counterpart
    • H01R31/06—Intermediate parts for linking two coupling parts, e.g. adapter
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure

Definitions

  • the present invention relates to a PCI-E flexible riser card for re-matching a pin, especially a pin having a PCIe interface defined and sorted pin, and each pin is matched by a high-speed differential signal.
  • Pins are designed to match the flexible materials of equidistant gauges, side-by-side cables and flexible boards, physically eliminating the interference of differential signals to improve signal integrity and size. Improve the applicability of the finished product.
  • PCI Express the Intel third-generation I/O technology announced by Intel on the Intel Developer Forum (IDF) in 2001.
  • the bus was developed by the AWG (Arapahoe Work Group) supported by Intel.
  • PCI-SIG PCI Special Interest Group
  • PCIe PCI Express
  • FIG. 1A and FIG. 1B the pins of the PCIe interface are defined and sorted.
  • FIG. 2A, FIG. 2B, FIG. 2C, FIG. 2D, and FIG. 2E the connector 10 having a PCIe interface is formed according to FIG. 1A and FIG.
  • the first and second pads 21 and 22 can be fabricated by using the PCIe interface characteristics of the connector 10, as shown in FIGS. 3A, 3B, 3C, 3D, 3E, and 3F.
  • the A side 211 on the front side of the pad 21 and the B side 212 on the opposite side are respectively provided with a group A pin position (A) and a B group pin position (B), and an A' having the second pad 22 front side.
  • the face 221 and the opposite side B' face 222 are respectively provided with a group A insertion pin and a group B insertion pin, and are further formed into a PCI-E cable riser card 20, as shown in FIG. 4A and FIG. 4B. They are respectively adjusted to have at least A 1 wiring pin ⁇ A 82 wiring pin (A 1 ⁇ A 82 ) a total of 82 pins, B 1 wiring pin ⁇ B 82 wiring pin (B 1 ⁇ B 82 ) a total of 82 Pins, A 1 plug
  • the input pin ⁇ A 82 insertion pin (A' 1 ⁇ A' 82 ) has 82 pins and B 1 insertion pin ⁇ B 82 insertion pin (B' 1 ⁇ B' 82 ) has 82 pins.
  • a 1 insertion pin - A 82 insertion pin (A' 1 - A' 82 ) and the B 1 insertion pin - B 82 insertion pin (B' 1 - B' 82 ) are respectively electrically connected to the A 1 wiring pin ⁇ A 82 wiring pin (A 1 ⁇ A 82 ) and B 1 wiring pin ⁇ B 82 wiring pin (B 1 ⁇ B 82 ), and the A 1 wiring pin ⁇ A 32 wiring
  • the legs (A 1 to A 32 ) and the B 1 wiring pins to the B 32 wiring pins (B 1 to B 32 ) correspond to the numbers (1 to 32) shown in Figs. 1A and 1B, respectively.
  • the width of the cable connecting the PCI-E cable riser card 20 is subject to Each of the wiring pins has a pitch of 1.0 mm and is too wide.
  • the PCIe interface is a two-way, high-speed differential signal that is connected in series by multiple pairs, and the difference in each pair is based on the transmission principle of the high-frequency signal. The number or spacing of ground lines between signals must be matched in a certain ratio to prevent EMI diffusion and interference, and each pair of I/O signals can use their respective couplings to maintain signal stability and Integrity.
  • the inventor further infers that the two pairs of different rates are adjacent differential signal pairs, and the number or spacing of the ground wires sandwiched between them should be required with a higher rate of matching, especially the characteristic impedance cannot be expected.
  • the PCI-E cable riser card 20 is actually fabricated according to the pins of FIG. 1A and FIG. 1B, and the wiring of the A-side line is on the lower layer and the B-side.
  • the wiring is on the upper layer, they are overlapping, after the completion is the front and back, for example: A 16 wiring pin in the A side of the line, A 17 wiring pin is a differential signal pair, and the spacing needs to be 1.0mm, And each pair of high-speed differential signal pairs must be a pair of ground pins, for example: A 25 wiring pins, A 26 wiring pins for differential signal pairs and A 29 wiring pins, A 30 wiring pins for differential signals There is an A 27 wiring pin and an A 28 wiring pin between the pair, and the A 27 wiring pin and the A 28 wiring pin are a pair of ground pins. As a result, as shown in FIG. 4A, A 13 on the A side.
  • a 14 wiring pin is also the reference clock for the differential signal (marked in Figure 1A), with A 16 wiring pins, A 17 wiring pins have A 15 wiring pins, and A 15 wiring pins are a grounding pin. Therefore, only one grounding pin is configured, and high-speed differential signals are violated.
  • the matching logic as shown in FIG.
  • a 4A has the A 1 insertion pin ⁇ A 18 insertion pin (A' 1 - A' 18 ) electrically connected to the A 1 wiring pin to the A 18 wiring pin ( The wiring in A 1 to A 18 ), due to the size limitation of the first and second pads 21, 22, the routing path that cannot be arbitrarily traversed, so that the reference clock and the adjacent high-speed differential signal, the ground line The number, or the matching of the pitch, cannot achieve a complete isolation effect, so the two pairs of signals that should not be coupled are mixed together before the cable is not connected, such as the first and second pads 21, 22 is not a multi-layer PCB board without a ground plane.
  • the reference clock of the A 14 wiring pin of the A side 211 is also completely isolated, and the B 14 wiring pin of the B side 212 is also a high-speed differential signal. pin, constituting the upper and lower overlapping, so there is confusion differential signal terminal pins a 13 and a 14-pin wiring, a 16 then A 17 pin connection pin, A 14 and B three terminal pins 14 of the differential signal connection pin, I wonder pin PCIe interface in accordance with the fabrication of the PCI-E riser cable 20, vary with As the length increases, it becomes more unstable.
  • the flexible adapter cable 30A of the high-frequency signal double-layer cable riser card developed by me is used for the wire and the wire diameter specification industry number UL2651, UL2678, etc.
  • the cable is either made up of a single insulated conductor wire and is made of other numbered parallel wires.
  • the insulation layer is made of PVC or Teflon material, but it cannot solve the problem of differential signal confusion; 3M Company R&D
  • the main technical problem to be solved by the present invention is to overcome the above-mentioned drawbacks of the prior art, and to provide a PCI-E flexible riser card that re-matches the pin, which extends the signal transmission without distortion, and A PCI-E flexible adapter card that achieves the effect of bending and reduces the cost, thereby solving the development of the PCIe interface to the specification, because it has not considered the application of flexible switching including cable, but at the foot A mismatch in the matching of the pins of the bit.
  • Another object of the present invention is to provide a PCI-E flexible riser card with a re-matching pin.
  • the bandwidth of the transmission line the better the flexibility.
  • the acceptance of the market will also be higher; since the present invention has made all differential signal pairs equidistantly matched, thereby improving the signal transmission quality.
  • a PCI-E flexible riser card that re-matches the pin including:
  • An electrical cable connector providing a PCI-E interface, comprising: a first end and a second end; the first end is provided with a first pad for wire bonding; the second end is parallel corresponding
  • the first pad is further provided with a second pad for the socket, and the A side of the front surface of the first pad and the B side of the opposite side are respectively provided with a group A pin position and a B group pin position.
  • the A group wiring pin and the B group wiring pin are respectively transmitted at least twice the rate according to the electrical cable connector of the PCI-E interface, and are adjusted to have at least an A 1 wiring pin to an A 18 wiring lead.
  • the corresponding A and B faces of the second pad are respectively provided with a set of A pins and B.
  • the group insertion pin, the A group insertion pin and the B group insertion pin are respectively arranged according to the PCI-E interface electrical cable connector, the PCI-E transmission channel is set to at least x1 channel, and is adjusted to At least A 1 insertion pin ⁇ A 18 insertion pin has 18 pins and at least B 1 insertion pin ⁇ B 18 insertion pin has 18 pins, and the A 1 insertion lead Pins ⁇ A 18 are inserted into the pins and B 1 is inserted into the pins - B 18 is inserted into the pins to electrically connect the A 1 wiring pins to the A 18 wiring pins and the B 1 wiring pins to the B 18 wiring pins;
  • the feature is that the B 13 wiring pin is set to a first ground line pin and the A 15 wiring pin is set to a second ground line pin, and the B 13 wiring pin and the A 15 wiring lead are used.
  • the pin is a reference, and a third ground pin and a fourth ground pin are respectively added, so that the third ground pin and the fourth ground pin can be inserted into the original B 14 wiring pin and the A 16 wiring.
  • the position of the pin is such that the first ground pin and the third ground pin are re-matched corresponding to the positive reference clock set by the A 13 wiring pin and the negative set by the A 14 wiring pin.
  • the reference clock is re-matched with the second ground pin and the fourth ground pin corresponding to the channel 0 transmission data set by the B 15 wiring pin and the B 16 wiring pin is set.
  • the channel 0 transmission data is turned off, forming a reference clock differential pair with ground line rematch and channel 0 transmission data.
  • the A group wiring pin, the B group pin position, the A group insertion pin and the B group insertion pin are respectively PCI-E transmitted according to the electrical cable connector of the PCI-E interface.
  • the transmission channel is set to x4 channels, and is adjusted to 32 pins respectively.
  • the 32 pins are connected by A 1 wiring pin to A 32 wiring pin, B 1 wiring pin to B 32 wiring pin, A 1 Insert pin ⁇ A 32 insert pin and B 1 insert pin ⁇ B 32 insert pin, and cooperate with the third ground pin and the fourth ground pin.
  • the reserved pins of the A 32 wiring pin and the B 30 wiring pin are deleted.
  • the A group wiring pin, the B group pin position, the A group insertion pin and the B group insertion pin are respectively PCI-E transmitted according to the electrical cable connector of the PCI-E interface.
  • the transmission channel is set to x8 channel or x16 channel, and is respectively adjusted to include 49 pins or 82 pins of the 32 pins, and is matched with the third ground pin and the fourth ground pin, and deleted.
  • the electrical cable connector of the PCI-E interface is a flexible circuit board, and the A 1 insertion pin - A 32 insertion pin, the B 1 insertion pin - the B 32 insertion pin form a Provides a nip for the combination of rigid boards.
  • the group A wiring pin and the B group pin are re-matched by the ground wire, and the transmission of the differential signal pair can be stabilized, so that the wire diameter of each wiring pin can be reduced to form each wire.
  • the line spacing of the pins is reduced from the original 1.0mm to 0.5mm to 0.635mm, so that the width of the original group A and the group B pins form a bandwidth of 50% to 63.5%.
  • the pins of the PCIe interface in the existing FIG. 1A and FIG. 1B are simultaneously formed on the B 13 wiring pins on the B side and the A 15 wiring pins on the A side, each of which is formed by adding one wiring pin.
  • the first ground pin and the second ground pin are rearranged as shown in Figures 7A and 7B, which overcome the confusion of the differential signal pair and can be used for flexible connection in the group A.
  • the PCI-E flexible riser card is improved and completed when the pitch and order of the insertion pin and the B insertion pin remain unchanged, so that not only the A 13 wiring pin and the A 14 of the A side can be satisfied.
  • the wiring pin is the reference clock differential signal pair, and the A 17 wiring pin and the A 18 wiring pin on the adjacent A side are the grounding and isolation required for the I/O differential signal pair, even the cable electrically to the PCB connectors, the a side of the PCB 14 a pin junction surface B 14 B wiring path connection pin will be shifted, thus together vertically overlap problem resolved
  • the transmitted PCI-E transmission channel is set to x1, x4, x8 to x16 channels, or even x32 channel pins, each pair of A and B faces The signal pair line also retains the original symmetry and ordering.
  • the A 32 wiring pin of the A side can be deleted together with the spare pin of the B 32 wiring pin of the B side to maintain the original
  • the invention has the beneficial effects that the PCI-E flexible adapter card can extend the signal transmission without distortion, and realize the bendable effect and reduce the cost benefit, thereby solving the development of the PCIe interface.
  • the specification was issued, because the application of flexible transfer including cable is not considered. And the missing pin on the pin matches.
  • the electrical cable connector of the PCI-E interface the smaller the bandwidth of the transmission line, the better the flexibility, and the higher the market acceptance; since the invention has already made all the differential signals to the line The equidistant matching improves the signal transmission quality.
  • FIG. 1A is a 1 to 18 pin description of a conventional PCIe 3.0.
  • FIG. 1B is a 19-32 pin description of the existing PCIe 3.0.
  • 2A is a perspective view of a connector of a conventional PCIe 3.0.
  • 2B is a top view of a connector of the conventional PCIe 3.0.
  • 2C is a front view of a connector of the prior PCIe 3.0.
  • 2D is a bottom view of the connector of the existing PCIe 3.0.
  • 2E is a rear view of the connector of the existing PCIe 3.0.
  • 3A is a first pad end view of a conventional high frequency signal double layer cable riser card.
  • 3B is a front elevational view of a first pad of a conventional high frequency signal double layer cable riser card.
  • 3C is a reverse view of the first pad of the conventional high-frequency signal double-layer cable riser card.
  • 3D is a second pad end view of a conventional high frequency signal double layer cable riser card.
  • 3E is a front elevational view of a second pad of a conventional high frequency signal double layer cable riser card.
  • 3F is a reverse view of a second pad of a conventional high frequency signal double layer cable riser card.
  • 4A is a schematic diagram of the A 1 -A 82 wiring pins and A 1 -A 82 insertion pins of the conventional high-frequency signal double-layer cable riser card.
  • 4B is a schematic diagram of the B 1 to B 82 wiring pins and B 1 to B 82 insertion pins of the conventional high-frequency signal double-layer cable riser card.
  • FIG. 5A is a schematic structural view of a conventional flexible adapter cable.
  • FIG. 5B is a schematic structural view of a conventional shielded cable.
  • FIG. 5C is a schematic structural view of another conventional shielded cable.
  • Figure 6A is a 1 to 19 pin description of the rematching PCIe 3.0 of the present invention.
  • Figure 6B is a 20-32 pin description of the rematch PCIe 3.0 of the present invention.
  • FIG. 7A is a schematic diagram of the re-matched A 1 -A 82 wiring pins and A 1 -A 82 insertion pins of the present invention.
  • FIG. 7B is a schematic diagram of the B 1 to B 82 wiring pins and B 1 to B 82 insertion pins of the rematching of the present invention.
  • Fig. 7C is an enlarged view of 7C in Fig. 7A.
  • Fig. 7D is an enlarged view of 7D in Fig. 7B.
  • Fig. 7E is a wiring diagram of the width reduction circuit of the A wiring pin of the present invention.
  • Fig. 7F is a wiring diagram of the width reduction circuit of the B terminal of the present invention.
  • Fig. 7G is an enlarged view of 7G in Fig. 7E.
  • Fig. 7H is an enlarged view of 7H in Fig. 7F.
  • the preferred embodiment of the PCI-E flexible riser card 40 of the re-matching pin of the present invention comprises: an electrical cable connector 41 for providing a PCI-E interface,
  • the first end 42 is provided with a first pad 421 for wire bonding;
  • the second end 43 is parallel to the first pad 421, on which A second pad 431 for a socket is further provided, and the A surface 4211 on the front surface of the first pad 421 and the B surface 4212 on the opposite side are respectively provided with a group A pin position (A) and a group B pin position.
  • the PCI-E transmission channel is at least set to X1 channel, adjusted to have at least A 1 wiring pin ⁇ A 18 wiring pin (A 1 ⁇ A 18 ) has 18 pins and at least B 1 wiring pin ⁇ B 18 wiring pin (B 1 ⁇ B 18 ) A total of 18 pins, and corresponding to the A' surface 4311 and the B' surface 4312 of the second pad 431 are respectively provided with a group A insertion pin (A') and a group B insertion pin (B').
  • the A group insertion pin (A') and the B group insertion pin position (B') are respectively according to the P CI-E is electrically connected to cable interface 41 of at least twice the transmission rate (1X), and adjusted to have at least A 1 ⁇ A 18 pin inserted insert pin (A '1 ⁇ A' 18 ) Total 18
  • the A 1 insertion pin ⁇ A 18 insertion pin (A' 1 ⁇ A ' 18 ) and B 1 insertion pins ⁇ B 18 insertion pins (B' 1 ⁇ B' 18 ) are electrically connected to the A 1 wiring pins ⁇ A 18 wiring pins (A 1 ⁇ A 18 ) and B 1 Wiring pin ⁇ B 18 wiring pin (B 1 ⁇ B 18 ).
  • the above configuration is a prior art, and is not a patent of the present invention, and is not described herein.
  • FIGS. 6A and 6B the rematched A 1 to A 82 wiring pins (A 1 ) as shown in FIGS. 7A, 7B, 7C, and 7D are fabricated.
  • the main feature of the present invention is that the B 13 wiring pin (B 13 ) is set to a first ground pin (G 1 ) and the A 15 wiring pin (A 15 ) It is set as a second ground pin (G 2 ), and a third ground pin is added based on the B 13 wiring pin (B 13 ) and the A 15 wiring pin (A 15 ).
  • the group A wiring pins (A), B The group wiring pin (B), the A group insertion pin (A'), and the B group insertion pin (B') are PCI-E transmissions respectively transmitted according to the electrical cable connector 41 of the PCI-E interface.
  • the channel is set to x4 channels and is adjusted to 32 pins respectively.
  • the 32 pins are connected by A 1 to A 32 wiring pins (A 1 to A 32 ) and B 1 wiring pins to B 32 Wiring pins (B 1 to B 32 ), A 1 insertion pins ⁇ A 32 insertion pins (A' 1 to A' 32 ) and B 1 insertion pins ⁇ B 32 insertion pins (B' 1 - B' 32 ), and cooperate with the third ground pin (G 3 ) and the fourth ground pin (G 4 ), delete the A 32 wiring pin (A 32 ) and the B 30 wiring pin (B 30 After the retention of the foot, and corresponding to the serial number (1 ⁇ 32) shown in Figure 6A, Figure 6B, in other words, the existing A, B face 32 shown in Figure 4, Figure 4B
  • the wiring pins, through the 33 matching pins of the A and B faces 4211 and 4212 after re-matching according to the present invention, may also delete one reserved pin on the A and B faces 4211 and 4212 to maintain 32 wiring pins. .
  • the A 16 wiring pin (A 16 ), the A 16 insertion pin (A' 16 ), the A 17 wiring pin (A 17 ), and the A 17 insertion pin (A' 17 ) It is provided with a second pair of differential signal lines (S 2); the terminal pins a 21 (a 21), a 21 is inserted into the pin (a '21), a 22 pin connection (a 22) and a 22 is inserted primer
  • the pin (A' 22 ) is provided with a third differential signal pair (S 3 ); the A 25 wiring pin (A 25 ), the A 25 insertion pin (A' 25 ), and the A 26 wiring pin (A 26)
  • the A 26 insertion pin (A' 26 ) is provided with a fourth differential signal pair (S 4 ); the A 29 wiring pin (A 29 ), the A 29 insertion pin (A' 29 ), A 30 terminal pin (a 30) and a 30 is inserted pins (a '30) is provided with a fifth differential pair of signal lines (S 5), therefore,
  • the electrical cable connector 41 of the PCI-E interface is a flexible circuit board (FPC), and the A 1 insertion pin - A 32 insertion pin (A' 1 - A' 32 ) , B 1 insertion pin ⁇ B 32 insertion pin (B′ 1 ⁇ B′ 32 ) forms a nip area for providing a rigid circuit board combination, and the electrical cable connector 41 matching the PCI-E interface is
  • the second end further extends a third end, wherein the third end is a third pad for providing a slot; the third end is parallel to the third pad, and the third pad is front A
  • the B side of the face and the opposite side are respectively provided with another A 1 insertion pin - A 32 insertion pin (A' 1 - A' 32 ), B 1 insertion pin ⁇ B 32 insertion pin (B' 1 ⁇ B' 32 ) forming another nip region for providing a rigid circuit board combination, so that the flexible circuit board (FPC) is centered on the differential signal re-matched at each of the
  • the line spacing (E) of each of the insertion pins (A', B') is 1.0 mm, forming each of the differential signal pairs (S
  • the distance between the first and second spacings (a, b) and the third and fourth spacings (c, d) is also more than twice the spacing, without interfering with each other, so that the original group A wiring pins (
  • the width of the A- and B-group wiring pins (B) forms a bandwidth (D) for providing the transmission line to be reduced to 50% to 63.5%, in other words, the electrical cable connector 41 for the PCI-E interface.
  • the bandwidth (D) of the transmission line the better the flexibility, the higher the market acceptance, and the improved signal is improved by the fact that all differential signals are equidistantly matched.
  • the transmission quality so it can be made with a wire with a smaller wire diameter, reducing the original 1.0mm pitch to 0.635mm or even 0.5mm, and reducing the bandwidth (D) of the original transmission line to 63.5%, even Up to 50%.
  • the technology disclosed in the present invention replaces the first substrate and the second substrate disclosed in US Pat. No. 9,215,834 with two PCI-E flexible riser cards 40, and the transmission lines formed by symmetrical lines.
  • the electrical connection can not only solve the design of the PCIe interface, but also according to the ratio, the wiring pins (A and B) which are originally spaced apart by 1.0 mm can be changed to the wires with smaller specifications. The width and thickness of the cable are minimized to increase the value of the finished product.

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Coupling Device And Connection With Printed Circuit (AREA)

Abstract

L'invention concerne une carte adaptatrice flexible PCI-E à broches réadaptées, pourvue de broches dont les positions sont définies et ordonnées par une interface PCIe ; les broches sont réadaptées selon le principe d'adaptation d'un signal différentiel à haut débit, et les broches peuvent être adaptées à un matériau flexible tel qu'un agencement de fils, qu'un agencement de fils côte à côte, et qu'une carte de circuit imprimé flexible ; d'un point de vue physique, cela permet de résoudre de nombreux problèmes, comme une obstruction de la transmission de cartes adaptatrices flexibles PCI-E provoquée par l'absence restante d'une interface PCIe, ou comme le fait qu'un signal soit incomplet.
PCT/CN2017/000447 2017-03-30 2017-07-17 Carte adaptatrice flexible pci-e à broches réadaptées WO2018176181A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201710200939.6A CN108666836A (zh) 2017-03-30 2017-03-30 重新匹配脚位的pci-e柔性转接卡
CN201710200939.6 2017-03-30

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Publication Number Publication Date
WO2018176181A1 true WO2018176181A1 (fr) 2018-10-04

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP4180980A1 (fr) * 2021-11-11 2023-05-17 INTEL Corporation Connecteur de dispositif d'entrée/sortie avec connexions de câble internes

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115169276B (zh) * 2022-07-22 2023-04-07 北京云枢创新软件技术有限公司 一种基于叠放模块的引脚区域匹配方法

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TW200534758A (en) * 2004-04-09 2005-10-16 Asrock Inc A computer system with PCI express interface
US20090061662A1 (en) * 2007-09-03 2009-03-05 Asustek Computer Inc. Connector
CN102650978A (zh) * 2012-03-27 2012-08-29 北京航空航天大学 一种用于PCI Express X16至CPCI Express X16的转接卡
CN103579857A (zh) * 2012-07-23 2014-02-12 陳亮合 高频信号双层排线转接卡
CN203574938U (zh) * 2013-10-24 2014-04-30 安费诺电子装配（厦门）有限公司 一种带金手指的pcb板及传输线用连接器
CN105470675A (zh) * 2014-09-03 2016-04-06 联想(北京)有限公司 电连接器

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200534758A (en) * 2004-04-09 2005-10-16 Asrock Inc A computer system with PCI express interface
US20090061662A1 (en) * 2007-09-03 2009-03-05 Asustek Computer Inc. Connector
CN102650978A (zh) * 2012-03-27 2012-08-29 北京航空航天大学 一种用于PCI Express X16至CPCI Express X16的转接卡
CN103579857A (zh) * 2012-07-23 2014-02-12 陳亮合 高频信号双层排线转接卡
CN203574938U (zh) * 2013-10-24 2014-04-30 安费诺电子装配（厦门）有限公司 一种带金手指的pcb板及传输线用连接器
CN105470675A (zh) * 2014-09-03 2016-04-06 联想(北京)有限公司 电连接器

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP4180980A1 (fr) * 2021-11-11 2023-05-17 INTEL Corporation Connecteur de dispositif d'entrée/sortie avec connexions de câble internes

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