WO2018176181A1

WO2018176181A1 - Pin-rematched pci-e flexible riser card

Info

Publication number: WO2018176181A1
Application number: PCT/CN2017/000447
Authority: WO
Inventors: 陈亮合; 陈彦为
Original assignee: 陈亮合; 陈彦为
Priority date: 2017-03-30
Filing date: 2017-07-17
Publication date: 2018-10-04
Also published as: CN108666836A

Abstract

Provided is a pin-rematched PCI-E flexible riser card, provided with pins whose positions are defined and ordered by a PCIe interface; the pins are re-matched according to the matching principle of a high-speed differential signal, and the pins may be matched with such flexible material as a wire arrangement, a side-by-side wire arrangement, and a flexible circuit board; thus in physical terms, many problems such as PCI-E flexible riser card transmission obstruction caused by the absence remaining from a PCIe interface, or a signal being incomplete, are resolved.

Description

Re-match the PCI-E flexible riser card

Technical field

The present invention relates to a PCI-E flexible riser card for re-matching a pin, especially a pin having a PCIe interface defined and sorted pin, and each pin is matched by a high-speed differential signal. Pins are designed to match the flexible materials of equidistant gauges, side-by-side cables and flexible boards, physically eliminating the interference of differential signals to improve signal integrity and size. Improve the applicability of the finished product.

Background technique

According to the "PCI Express" interface, the Intel third-generation I/O technology announced by Intel on the Intel Developer Forum (IDF) in 2001. The bus was developed by the AWG (Arapahoe Work Group) supported by Intel. In 2002, it was transferred to the PCI Special Interest Group (PCI-SIG), which was announced after auditing and was renamed "PCI Express" (PCIe for short). As shown in FIG. 1A and FIG. 1B, the pins of the PCIe interface are defined and sorted. As shown in FIG. 2A, FIG. 2B, FIG. 2C, FIG. 2D, and FIG. 2E, the connector 10 having a PCIe interface is formed according to FIG. 1A and FIG. 1B, and includes: a sley 11 and a golden finger 12 Since this is a shared standard in the industry, I have not hesitated to invent a high-frequency signal double-layer cable riser card as shown in FIG. 1A and FIG. 1B, and disclosed in US Patent No. 9,215,834. The first and

second pads

21 and 22 can be fabricated by using the PCIe interface characteristics of the connector 10, as shown in FIGS. 3A, 3B, 3C, 3D, 3E, and 3F. The A side 211 on the front side of the pad 21 and the B side 212 on the opposite side are respectively provided with a group A pin position (A) and a B group pin position (B), and an A' having the second pad 22 front side. The face 221 and the opposite side B' face 222 are respectively provided with a group A insertion pin and a group B insertion pin, and are further formed into a PCI-E cable riser card 20, as shown in FIG. 4A and FIG. 4B. They are respectively adjusted to have at least A ₁ wiring pin ~ A ₈₂ wiring pin (A ₁ ~ A ₈₂ ) a total of 82 pins, B ₁ wiring pin ~ B ₈₂ wiring pin (B ₁ ~ B ₈₂ ) a total of 82 Pins, A ₁ plug The input pin ~A ₈₂ insertion pin (A' ₁ ~ A' ₈₂ ) has 82 pins and B ₁ insertion pin ~ B ₈₂ insertion pin (B' ₁ ~ B' ₈₂ ) has 82 pins. And the A ₁ insertion pin - A ₈₂ insertion pin (A' ₁ - A' ₈₂ ) and the B ₁ insertion pin - B ₈₂ insertion pin (B' ₁ - B' ₈₂ ) are respectively electrically connected to the A ₁ wiring pin ~ A ₈₂ wiring pin (A ₁ ~ A ₈₂ ) and B ₁ wiring pin ~ B ₈₂ wiring pin (B ₁ ~ B ₈₂ ), and the A ₁ wiring pin ~ A ₃₂ wiring The legs (A ₁ to A ₃₂ ) and the B ₁ wiring pins to the B ₃₂ wiring pins (B ₁ to B ₃₂ ) correspond to the numbers (1 to 32) shown in Figs. 1A and 1B, respectively.

According to the configuration of the pins defined by the PCIe interface and the pitch of the pins and the pitch of each pin is 1.0 mm, the width of the cable connecting the PCI-E cable riser card 20 is subject to Each of the wiring pins has a pitch of 1.0 mm and is too wide. Further, the PCIe interface is a two-way, high-speed differential signal that is connected in series by multiple pairs, and the difference in each pair is based on the transmission principle of the high-frequency signal. The number or spacing of ground lines between signals must be matched in a certain ratio to prevent EMI diffusion and interference, and each pair of I/O signals can use their respective couplings to maintain signal stability and Integrity. Therefore, the inventor further infers that the two pairs of different rates are adjacent differential signal pairs, and the number or spacing of the ground wires sandwiched between them should be required with a higher rate of matching, especially the characteristic impedance cannot be expected. As shown in FIG. 4A and FIG. 4B, the PCI-E cable riser card 20 is actually fabricated according to the pins of FIG. 1A and FIG. 1B, and the wiring of the A-side line is on the lower layer and the B-side. The wiring is on the upper layer, they are overlapping, after the completion is the front and back, for example: A ₁₆ wiring pin in the A side of the line, A ₁₇ wiring pin is a differential signal pair, and the spacing needs to be 1.0mm, And each pair of high-speed differential signal pairs must be a pair of ground pins, for example: A ₂₅ wiring pins, A ₂₆ wiring pins for differential signal pairs and A ₂₉ wiring pins, A ₃₀ wiring pins for differential signals There is an A ₂₇ wiring pin and an A ₂₈ wiring pin between the pair, and the A ₂₇ wiring pin and the A ₂₈ wiring pin are a pair of ground pins. As a result, as shown in FIG. 4A, A ₁₃ on the A side. Wiring pin, A ₁₄ wiring pin is also the reference clock for the differential signal (marked in Figure 1A), with A ₁₆ wiring pins, A ₁₇ wiring pins have A ₁₅ wiring pins, and A ₁₅ wiring pins are a grounding pin. Therefore, only one grounding pin is configured, and high-speed differential signals are violated. The matching logic, as shown in FIG. 4A, has the A ₁ insertion pin ~ A ₁₈ insertion pin (A' ₁ - A' ₁₈ ) electrically connected to the A ₁ wiring pin to the A ₁₈ wiring pin ( The wiring in A ₁ to A ₁₈ ), due to the size limitation of the first and

second pads

21, 22, the routing path that cannot be arbitrarily traversed, so that the reference clock and the adjacent high-speed differential signal, the ground line The number, or the matching of the pitch, cannot achieve a complete isolation effect, so the two pairs of signals that should not be coupled are mixed together before the cable is not connected, such as the first and

second pads

21, 22 is not a multi-layer PCB board without a ground plane. The reference clock of the A ₁₄ wiring pin of the A side 211 is also completely isolated, and the B ₁₄ wiring pin of the B side 212 is also a high-speed differential signal. pin, constituting the upper and lower overlapping, so there is confusion differential signal terminal pins a ₁₃ and a _14-pin wiring, a ₁₆ then A ₁₇ pin connection pin, A ₁₄ and B three terminal pins ₁₄ of the differential signal connection pin, I wonder pin PCIe interface in accordance with the fabrication of the PCI-E riser cable 20, vary with As the length increases, it becomes more unstable.

After pressing, the flexible adapter cable 30A of the high-frequency signal double-layer cable riser card developed by me, as shown in Fig. 5A, is used for the wire and the wire diameter specification industry number UL2651, UL2678, etc. The cable is either made up of a single insulated conductor wire and is made of other numbered parallel wires. The insulation layer is made of PVC or Teflon material, but it cannot solve the problem of differential signal confusion; 3M Company R&D A shielded cable 30B, as shown in FIG. 5B, needs to be pre-designed with two wires as a group, each group having a certain interval arrangement, and a bare copper or silver-plated copper wire covered with a shielding layer such as aluminum foil. It is made by special process; another type of shielded cable 30C is developed by other manufacturers, as shown in Fig. 5C, the bare copper or silver-plated copper wire covered by aluminum foil, etc. The

cables

30B, 30C completely separate the pair of signal pairs by shielding, which can reduce the confusion of the differential signal pair, but the process is relatively expensive.

Therefore, the inventors have considered the various obstacles arising from the loss of the PCIe interface, and after the application of the previous patent, the methods and main problems are considered.

Summary of the invention

The main technical problem to be solved by the present invention is to overcome the above-mentioned drawbacks of the prior art, and to provide a PCI-E flexible riser card that re-matches the pin, which extends the signal transmission without distortion, and A PCI-E flexible adapter card that achieves the effect of bending and reduces the cost, thereby solving the development of the PCIe interface to the specification, because it has not considered the application of flexible switching including cable, but at the foot A mismatch in the matching of the pins of the bit.

Another object of the present invention is to provide a PCI-E flexible riser card with a re-matching pin. For an electrical cable connector of the PCI-E interface, the smaller the bandwidth of the transmission line, the better the flexibility. The acceptance of the market will also be higher; since the present invention has made all differential signal pairs equidistantly matched, thereby improving the signal transmission quality.

The technical solution adopted by the present invention to solve the technical problem thereof is:

A PCI-E flexible riser card that re-matches the pin, including:

An electrical cable connector providing a PCI-E interface, comprising: a first end and a second end; the first end is provided with a first pad for wire bonding; the second end is parallel corresponding The first pad is further provided with a second pad for the socket, and the A side of the front surface of the first pad and the B side of the opposite side are respectively provided with a group A pin position and a B group pin position. The A group wiring pin and the B group wiring pin are respectively transmitted at least twice the rate according to the electrical cable connector of the PCI-E interface, and are adjusted to have at least an A ₁ wiring pin to an A ₁₈ wiring lead. There are 18 pins in the pin and at least 18 pins in the B ₁ pin to the B ₁₈ pin. The corresponding A and B faces of the second pad are respectively provided with a set of A pins and B. The group insertion pin, the A group insertion pin and the B group insertion pin are respectively arranged according to the PCI-E interface electrical cable connector, the PCI-E transmission channel is set to at least x1 channel, and is adjusted to At least A ₁ insertion pin ~ A ₁₈ insertion pin has 18 pins and at least B ₁ insertion pin ~ B ₁₈ insertion pin has 18 pins, and the A ₁ insertion lead Pins ~A _{18 are} inserted into the pins and B _{1 is} inserted into the pins - B _{18 is} inserted into the pins to electrically connect the A ₁ wiring pins to the A ₁₈ wiring pins and the B ₁ wiring pins to the B ₁₈ wiring pins; The feature is that the B ₁₃ wiring pin is set to a first ground line pin and the A ₁₅ wiring pin is set to a second ground line pin, and the B ₁₃ wiring pin and the A ₁₅ wiring lead are used. The pin is a reference, and a third ground pin and a fourth ground pin are respectively added, so that the third ground pin and the fourth ground pin can be inserted into the original B ₁₄ wiring pin and the A ₁₆ wiring. The position of the pin is such that the first ground pin and the third ground pin are re-matched corresponding to the positive reference clock set by the A ₁₃ wiring pin and the negative set by the A ₁₄ wiring pin. The reference clock is re-matched with the second ground pin and the fourth ground pin corresponding to the channel 0 transmission data set by the B ₁₅ wiring pin and the B ₁₆ wiring pin is set. The channel 0 transmission data is turned off, forming a reference clock differential pair with ground line rematch and channel 0 transmission data.

According to the foregoing feature, the A group wiring pin, the B group pin position, the A group insertion pin and the B group insertion pin are respectively PCI-E transmitted according to the electrical cable connector of the PCI-E interface. The transmission channel is set to x4 channels, and is adjusted to 32 pins respectively. The 32 pins are connected by A ₁ wiring pin to A ₃₂ wiring pin, B ₁ wiring pin to B ₃₂ wiring pin, A ₁ Insert pin ~ A ₃₂ insert pin and B ₁ insert pin ~ B ₃₂ insert pin, and cooperate with the third ground pin and the fourth ground pin.

According to the predecessor feature, the reserved pins of the A ₃₂ wiring pin and the B ₃₀ wiring pin are deleted.

According to the foregoing feature, the A group wiring pin, the B group pin position, the A group insertion pin and the B group insertion pin are respectively PCI-E transmitted according to the electrical cable connector of the PCI-E interface. The transmission channel is set to x8 channel or x16 channel, and is respectively adjusted to include 49 pins or 82 pins of the 32 pins, and is matched with the third ground pin and the fourth ground pin, and deleted. A ₃₂ wiring pin and a retention pin for the B ₃₀ wiring pin.

According to the foregoing feature, the electrical cable connector of the PCI-E interface is a flexible circuit board, and the A ₁ insertion pin - A ₃₂ insertion pin, the B ₁ insertion pin - the B ₃₂ insertion pin form a Provides a nip for the combination of rigid boards.

According to the pre-existing feature, the group A wiring pin and the B group pin are re-matched by the ground wire, and the transmission of the differential signal pair can be stabilized, so that the wire diameter of each wiring pin can be reduced to form each wire. The line spacing of the pins is reduced from the original 1.0mm to 0.5mm to 0.635mm, so that the width of the original group A and the group B pins form a bandwidth of 50% to 63.5%.

By means of the above-mentioned technical means, the pins of the PCIe interface in the existing FIG. 1A and FIG. 1B are simultaneously formed on the B ₁₃ wiring pins on the B side and the A ₁₅ wiring pins on the A side, each of which is formed by adding one wiring pin. The first ground pin and the second ground pin are rearranged as shown in Figures 7A and 7B, which overcome the confusion of the differential signal pair and can be used for flexible connection in the group A. The PCI-E flexible riser card is improved and completed when the pitch and order of the insertion pin and the B insertion pin remain unchanged, so that not only the A ₁₃ wiring pin and the A _{14 of the} A side can be satisfied. The wiring pin is the reference clock differential signal pair, and the A ₁₇ wiring pin and the A ₁₈ wiring pin on the adjacent A side are the grounding and isolation required for the I/O differential signal pair, even the cable electrically to the PCB connectors, the a side of the PCB ₁₄ a pin junction surface B ₁₄ B wiring path connection pin will be shifted, thus together vertically overlap problem resolved And the transmitted PCI-E transmission channel is set to x1, x4, x8 to x16 channels, or even x32 channel pins, each pair of A and B faces The signal pair line also retains the original symmetry and ordering. Of course, if necessary, the A ₃₂ wiring pin of the A side can be deleted together with the spare pin of the B ₃₂ wiring pin of the B side to maintain the original The total number of pins, so the update of this ground pin, for the high-speed differential signal line pin matching, is more perfect than the standard interface originally only for the PCB wiring rules.

The invention has the beneficial effects that the PCI-E flexible adapter card can extend the signal transmission without distortion, and realize the bendable effect and reduce the cost benefit, thereby solving the development of the PCIe interface. The specification was issued, because the application of flexible transfer including cable is not considered. And the missing pin on the pin matches. For the electrical cable connector of the PCI-E interface, the smaller the bandwidth of the transmission line, the better the flexibility, and the higher the market acceptance; since the invention has already made all the differential signals to the line The equidistant matching improves the signal transmission quality.

DRAWINGS

The invention will now be further described with reference to the drawings and embodiments.

FIG. 1A is a 1 to 18 pin description of a conventional PCIe 3.0.

FIG. 1B is a 19-32 pin description of the existing PCIe 3.0.

2A is a perspective view of a connector of a conventional PCIe 3.0.

2B is a top view of a connector of the conventional PCIe 3.0.

2C is a front view of a connector of the prior PCIe 3.0.

2D is a bottom view of the connector of the existing PCIe 3.0.

2E is a rear view of the connector of the existing PCIe 3.0.

3A is a first pad end view of a conventional high frequency signal double layer cable riser card.

3B is a front elevational view of a first pad of a conventional high frequency signal double layer cable riser card.

3C is a reverse view of the first pad of the conventional high-frequency signal double-layer cable riser card.

3D is a second pad end view of a conventional high frequency signal double layer cable riser card.

3E is a front elevational view of a second pad of a conventional high frequency signal double layer cable riser card.

3F is a reverse view of a second pad of a conventional high frequency signal double layer cable riser card.

4A is a schematic diagram of the A ₁ -A ₈₂ wiring pins and A ₁ -A ₈₂ insertion pins of the conventional high-frequency signal double-layer cable riser card.

4B is a schematic diagram of the B ₁ to B ₈₂ wiring pins and B ₁ to B ₈₂ insertion pins of the conventional high-frequency signal double-layer cable riser card.

FIG. 5A is a schematic structural view of a conventional flexible adapter cable.

FIG. 5B is a schematic structural view of a conventional shielded cable.

FIG. 5C is a schematic structural view of another conventional shielded cable.

Figure 6A is a 1 to 19 pin description of the rematching PCIe 3.0 of the present invention.

Figure 6B is a 20-32 pin description of the rematch PCIe 3.0 of the present invention.

FIG. 7A is a schematic diagram of the re-matched A ₁ -A ₈₂ wiring pins and A ₁ -A ₈₂ insertion pins of the present invention.

FIG. 7B is a schematic diagram of the B ₁ to B ₈₂ wiring pins and B ₁ to B ₈₂ insertion pins of the rematching of the present invention.

Fig. 7C is an enlarged view of 7C in Fig. 7A.

Fig. 7D is an enlarged view of 7D in Fig. 7B.

Fig. 7E is a wiring diagram of the width reduction circuit of the A wiring pin of the present invention.

Fig. 7F is a wiring diagram of the width reduction circuit of the B terminal of the present invention.

Fig. 7G is an enlarged view of 7G in Fig. 7E.

Fig. 7H is an enlarged view of 7H in Fig. 7F.

The label in the figure shows:

40 PCI-E Flexible Riser

41 Electrical cable connector

42 first end

421 first pad

4211 A side

4212 B side

43 second end

431 second pad

4311 A' face

4312 B' face

A group A wiring pin

A ₁ ~ A ₈₂ A ₁ wiring pin ~ A ₈₂ wiring pin

B group B wiring pin

B ₁ to B ₈₂ B ₁ wiring pin ~ B ₈₂ wiring pin

A’A group insertion pin

A' ₁ ~ A' ₈₂ A ₁ insertion pin ~ A ₈₂ insertion pin

B'B group inserted into the foot

B' ₁ to B' ₈₂ B ₁ insertion pin ~ B ₈₂ insertion pin

C clock lead

D bandwidth

E Insert the line spacing of the pins

E' differential signal to line wide line spacing

G ₁ first ground pin

G ₂ second ground pin

G ₃ third ground pin

G ₄ fourth ground pin

S ₁ to S ₉ first differential signal pair line to ninth difference signal pair line

a first spacing

b second spacing

c third spacing

d fourth spacing

e Line spacing of wiring pins

e' differential signal to line narrow line spacing

detailed description

First, referring to FIG. 6A to FIG. 7H, the preferred embodiment of the PCI-E flexible riser card 40 of the re-matching pin of the present invention comprises: an electrical cable connector 41 for providing a PCI-E interface, The first end 42 is provided with a first pad 421 for wire bonding; the second end 43 is parallel to the first pad 421, on which A second pad 431 for a socket is further provided, and the A surface 4211 on the front surface of the first pad 421 and the B surface 4212 on the opposite side are respectively provided with a group A pin position (A) and a group B pin position. (B), the A group wiring pin (A) and the B group wiring pin (B) are respectively arranged according to the PCI-E interface, the PCI-E transmission channel is at least set to X1 channel, adjusted to have at least A ₁ wiring pin ~ A ₁₈ wiring pin (A ₁ ~ A ₁₈ ) has 18 pins and at least B ₁ wiring pin ~ B ₁₈ wiring pin (B ₁ ~ B ₁₈ ) A total of 18 pins, and corresponding to the A' surface 4311 and the B' surface 4312 of the second pad 431 are respectively provided with a group A insertion pin (A') and a group B insertion pin (B'). The A group insertion pin (A') and the B group insertion pin position (B') are respectively according to the P CI-E is electrically connected to cable interface 41 of at least twice the transmission rate (1X), and adjusted to have at least A ₁ ~ A ₁₈ pin inserted insert pin _{_{(A '1 ~ A' 18}} ) Total 18 There are 18 pins on the pin and at least B ₁ insertion pin ~ B ₁₈ insertion pin (B' ₁ ~ B' ₁₈ ), and the A ₁ insertion pin ~ A ₁₈ insertion pin (A' ₁ ~ A ' ₁₈ ) and B ₁ insertion pins ~ B ₁₈ insertion pins (B' ₁ ~ B' ₁₈ ) are electrically connected to the A ₁ wiring pins ~ A ₁₈ wiring pins (A ₁ ~ A ₁₈ ) and B ₁ Wiring pin ~ B ₁₈ wiring pin (B ₁ ~ B ₁₈ ). The above configuration is a prior art, and is not a patent of the present invention, and is not described herein.

Referring to the rematching PCIe3.0 pin description shown in FIGS. 6A and 6B, the rematched A ₁ to A ₈₂ wiring pins (A _{1 )} as shown in FIGS. 7A, 7B, 7C, and 7D are fabricated. ~A ₈₂ ), A ₁ to A ₈₂ insertion pins (A' ₁ to A' ₈₂ ), B ₁ to B ₈₂ wiring pins (B ₁ to B ₈₂ ) and B ₁ to B ₈₂ insertion pins (B' ₁ to B' ₈₂ ), and the main feature of the present invention is that the B ₁₃ wiring pin (B ₁₃ ) is set to a first ground pin (G ₁ ) and the A ₁₅ wiring pin (A ₁₅ ) It is set as a second ground pin (G ₂ ), and a third ground pin is added based on the B ₁₃ wiring pin (B ₁₃ ) and the A ₁₅ wiring pin (A ₁₅ ). (G ₃ ) and the fourth ground pin (G ₄ ), so that the third ground pin (G ₃ ) and the fourth ground pin (G ₄ ) can be inserted into the original B ₁₄ wiring pin (B ₁₄ ) and the position of the A ₁₆ wiring pin (A ₁₆ ), so that the first ground pin (G ₁ ) and the third ground pin (G ₃ ) are re-matched to correspond to the A ₁₃ wiring pin. (A ₁₃ ) Set the positive reference clock (REFCLK+) and the negative reference clock (REFCLK-) set by the A ₁₄ wiring pin (A ₁₄ ), and the second ground pin (G ₂ ) and Four ground lines The pin (G ₄ ) rematch is set corresponding to the 0 channel transmission data open (HSOp(0)) and B ₁₆ wiring pin (B ₁₆ ) set by the B ₁₅ wiring pin (B ₁₅ ). The fixed channel 0 transmission data is off (HSOn(0)), forming a reference clock differential pair with ground rematch and channel 0 transmission data. In this embodiment, the group A wiring pins (A), B The group wiring pin (B), the A group insertion pin (A'), and the B group insertion pin (B') are PCI-E transmissions respectively transmitted according to the electrical cable connector 41 of the PCI-E interface. The channel is set to x4 channels and is adjusted to 32 pins respectively. The 32 pins are connected by A ₁ to A ₃₂ wiring pins (A ₁ to A ₃₂ ) and B ₁ wiring pins to B ₃₂ Wiring pins (B ₁ to B ₃₂ ), A ₁ insertion pins ~ A ₃₂ insertion pins (A' ₁ to A' ₃₂ ) and B ₁ insertion pins ~ B ₃₂ insertion pins (B' ₁ - B' ₃₂ ), and cooperate with the third ground pin (G ₃ ) and the fourth ground pin (G ₄ ), delete the A ₃₂ wiring pin (A ₃₂ ) and the B ₃₀ wiring pin (B ₃₀ After the retention of the foot, and corresponding to the serial number (1 ~ 32) shown in Figure 6A, Figure 6B, in other words, the existing A, B face 32 shown in Figure 4, Figure 4B The wiring pins, through the 33 matching pins of the A and B faces 4211 and 4212 after re-matching according to the present invention, may also delete one reserved pin on the A and B faces 4211 and 4212 to maintain 32 wiring pins. .

In the above, the A group wiring pin position (A), the B group wiring pin position (B), the A group insertion pin position (A'), and the B group insertion pin position (B') are respectively according to the PCI-E interface. The PCI-E transmission channel transmitted by the electrical cable connector 41 is set to x8 channel or x16 channel, and is respectively adjusted to include 49 pins or 82 pins of the 32 pins, and cooperate with the third The ground pin (G ₃ ) and the fourth ground pin (G ₄ ), the A ₃₂ wire pin (A ₃₂ ) and the B ₃₀ wire pin (B ₃₀ ) are reserved, so that the present invention The first pad 421 of the PCI-E flexible riser card 40 is also a gold finger pad, and the A group pin position (A) and the B group pin position (B) of the first pad 421 are The inventor rearranged the configuration of the foot.

According to the inventor's rearranged pin configuration, the first pad 421 of the PCI-E flexible riser card 40 must be the wire of the wire, and the A ₁₅ wire pin of the A face 4211 of the gold finger end (A ₁₅ ) and on the A ₁₃ wiring pin (A ₁₃ ) of the B side 4212, add a lead to the soldering pin at the same time, so that the differential signal of the reference clock is aligned with the adjacent and adjacent lines. The two pairs of differential signal pairs can also be matched to other I/O differential signal pairs, with enough matching to isolate them one pair, and can be individually coupled to improve signal integrity. .

Further, starting from the self-propelled line, the spacing between the original one pin is increased to two pins apart, and the differential signal pair alignment can be obtained, and the same isolation matching is obtained, for example, on the A side 4211. Said that the A ₁₃ wiring pin (A ₁₃ ), the A ₁₃ insertion pin (A' ₁₃ ), the A ₁₅ wiring pin (A ₁₅ ), and the A ₁₅ insertion pin (A' ₁₅ ) are provided with a first difference. Signal to line (S ₁ ); the A ₁₆ wiring pin (A ₁₆ ), the A ₁₆ insertion pin (A' ₁₆ ), the A ₁₇ wiring pin (A ₁₇ ), and the A ₁₇ insertion pin (A' ₁₇ ) It is provided with a second pair of differential signal lines (S _2); the terminal pins a ₂₁ (a _21), a ₂₁ is inserted into the pin (a _'21), a ₂₂ pin connection (a ₂₂₎ and a ₂₂ is inserted primer The pin (A' ₂₂ ) is provided with a third differential signal pair (S ₃ ); the A ₂₅ wiring pin (A ₂₅ ), the A ₂₅ insertion pin (A' ₂₅ ), and the A ₂₆ wiring pin (A ₂₆₎ And the A ₂₆ insertion pin (A' ₂₆ ) is provided with a fourth differential signal pair (S ₄ ); the A ₂₉ wiring pin (A ₂₉ ), the A ₂₉ insertion pin (A' ₂₉ ), A ₃₀ terminal pin (a ₃₀₎ and a ₃₀ is inserted pins (a _'30) is provided with a fifth differential pair of signal lines (S _5), therefore, the first pair of differential signal lines (S ₁₎ and The second differential signal line pair of the re-match between the pin (S _2), as the third differential pair signal lines (S ₃₎ and the fourth differential pair signal lines (S _4), the fourth differential signal pair Forming a first pitch (a) of two pins between the line (S ₄ ) and the fifth differential signal pair line (S ₅ ), and the second differential signal pair line (S ₂ ) and the third differential signal A third pitch (c) of three pins is formed between the lines (S ₃ ). In the case of the B side 4212, the B ₁₂ wiring pin (B ₁₂ ), the B ₁₂ insertion pin (B' ₁₂ ) are provided with a clock lead (C); the B ₁₄ wiring pin (B ₁₄ ), B _{14 is} inserted. The pin (A' ₁₄ ) and the B ₁₅ pin (B ₁₅ ) and the B ₁₅ pin (B' ₁₅ ) are provided with a sixth differential signal pair (S ₆ ); the B ₁₉ pin (B) ₁₉ ), B ₁₉ insertion pin (B' ₁₉ ), B ₂₀ wiring pin (B ₂₀ ) and B ₂₀ insertion pin (B' ₂₀ ) are provided with a seventh differential signal pair line (S ₇ ); ₂₃ wiring pins (B ₂₃ ), B ₂₃ insertion pins (B' ₂₃ ), B ₂₄ wiring pins (B ₂₄ ), B ₂₄ insertion pins (B' ₂₄ ) are provided with an eighth differential signal pair ( S ₈ ); the B ₂₇ wiring pin (B ₂₇ ), the B ₂₇ insertion pin (B' ₂₇ ), the B ₂₈ wiring pin (B ₂₈ ), and the B ₂₈ insertion pin (B' ₂₈ ) are provided with a first The nine differential signals are paired with the line (S ₉ ), and therefore, after the clock pin (C) and the sixth differential signal pair (S ₆ ) are re-matched, the seventh differential signal is aligned (S _{7 )} Forming a second pitch of two pins between the eighth differential signal pair (S ₈ ), the eighth differential signal pair (S ₈ ), and the ninth differential signal pair (S ₉ ) ) and Six differential pair signal lines (S ₆₎ is formed of three fourth pin spacing (d) between the seventh pair of differential signal lines (S _7).

In another embodiment, the electrical cable connector 41 of the PCI-E interface is a flexible circuit board (FPC), and the A ₁ insertion pin - A ₃₂ insertion pin (A' ₁ - A' ₃₂ ) , B ₁ insertion pin ～B ₃₂ insertion pin (B′ ₁ ～B′ ₃₂ ) forms a nip area for providing a rigid circuit board combination, and the electrical cable connector 41 matching the PCI-E interface is The second end further extends a third end, wherein the third end is a third pad for providing a slot; the third end is parallel to the third pad, and the third pad is front A The B side of the face and the opposite side are respectively provided with another A ₁ insertion pin - A ₃₂ insertion pin (A' ₁ - A' ₃₂ ), B ₁ insertion pin ~ B ₃₂ insertion pin (B' ₁ ~ B' ₃₂ ) forming another nip region for providing a rigid circuit board combination, so that the flexible circuit board (FPC) is centered on the differential signal re-matched at each of the pitches, and two of the upper and lower extensions are extended. Instead of soldering, the nip area replaces the hard and soft board of the cable with a flexible circuit board (FPC).

Moreover, as shown in FIG. 7E, FIG. 7F, FIG. 7G and FIG. 7H, the difference between each pair is obtained after the A group wiring pin (A) and the B group wiring pin (B) are re-matched by the ground. The signal can be coupled with each other across a distance ratio of two wires, and can stabilize the transmission of the differential signal pair, such as: the first differential signal pair to the ninth differential signal pair (S ₁ - S ₉ ) The differential signal is transmitted at a high speed and stably at a distance ratio between the first and second pitches (a, b) and the third and fourth pitches (c, d), so that each of the wiring pins (A, B) The wire diameter can also be reduced, so that the line spacing (e) of each of the wiring pins (A, B) is reduced from the original 1.0 mm to 0.5 mm to 0.635 mm, and the differential signal pair lines (S ₁ to S ₉ ) are formed. The narrow line spacing (e') is at least e'=2e relationship, and the line spacing (E) of each of the insertion pins (A', B') is 1.0 mm, forming each of the differential signal pairs (S The wide line spacing (E') of ₁ to S ₉ ) is at least E'=2E, and the correspondence between the narrow line spacing (e') and the wide line spacing (E') has a spacing of more than 2 times. , remains between each of the differential signal lines (S ₁ ~ S ₉₎ held in the The distance between the first and second spacings (a, b) and the third and fourth spacings (c, d) is also more than twice the spacing, without interfering with each other, so that the original group A wiring pins ( The width of the A- and B-group wiring pins (B) forms a bandwidth (D) for providing the transmission line to be reduced to 50% to 63.5%, in other words, the electrical cable connector 41 for the PCI-E interface. In terms of the bandwidth (D) of the transmission line, the better the flexibility, the higher the market acceptance, and the improved signal is improved by the fact that all differential signals are equidistantly matched. The transmission quality, so it can be made with a wire with a smaller wire diameter, reducing the original 1.0mm pitch to 0.635mm or even 0.5mm, and reducing the bandwidth (D) of the original transmission line to 63.5%, even Up to 50%.

In summary, the technology disclosed in the present invention replaces the first substrate and the second substrate disclosed in US Pat. No. 9,215,834 with two PCI-E flexible riser cards 40, and the transmission lines formed by symmetrical lines. The electrical connection can not only solve the design of the PCIe interface, but also according to the ratio, the wiring pins (A and B) which are originally spaced apart by 1.0 mm can be changed to the wires with smaller specifications. The width and thickness of the cable are minimized to increase the value of the finished product.

The above is only a preferred embodiment of the present invention, and is not intended to limit the present invention in any way. Any simple modifications, equivalent changes and modifications made to the above embodiments in accordance with the technical spirit of the present invention are still Within the scope of the technical solution of the present invention.

In summary, the present invention fully meets the needs of industrial development in terms of structural design, practicality and cost-effectiveness, and the disclosed structure is also an unprecedented innovative structure, novel, creative, practical, and relevant. The provisions of the invention patent requirements, so file an application in accordance with the law.

Claims

A PCI-E flexible riser card that re-matches the pin, including:

An electrical cable connector providing a PCI-E interface, comprising: a first end and a second end; the first end is provided with a first pad for wire bonding; the second end is parallel corresponding The first pad is further provided with a second pad for the socket, and the A side of the front surface of the first pad and the B side of the opposite side are respectively provided with a group A pin position and a B group pin position. the group a terminal pin and group B terminal pin respectively depending transmitted to the PCI-E electrical cable connector interface PCI-E transmission channels is at least set to x1 lane, and adjusted to have at least a 1 Wiring pin ~ A 18 wiring pin has 18 pins and at least B 1 wiring pin ~ B 18 wiring pin has 18 pins, and the corresponding A side and B side of the second pad are separately set. There is a group A insertion pin and a B group insertion pin. The A group insertion pin and the B group insertion pin are respectively adjusted according to the rate of the electrical cable connector of the PCI-E interface, and are adjusted to at least one rate. At least A 1 insertion pin ~ A 18 insertion pin has 18 pins and at least B 1 insertion pin ~ B 18 insertion pin has 18 pins, and the A 1 insertion lead Pin ~ A 18 insertion pin and B 1 insertion pin ~ B 18 insertion pin is electrically connected to the A 1 wiring pin ~ A 18 wiring pin and B 1 wiring pin ~ B 18 wiring pin;

It is characterized by:

The B 13 wiring pin is set to a first ground line pin and the A 15 wiring pin is set to a second ground line pin, and is based on the B 13 wiring pin and the A 15 wiring pin. And adding a third ground pin and a fourth ground pin respectively, so that the third ground pin and the fourth ground pin can be inserted into the original B 14 wiring pin and the A 16 wiring pin. Position, the first ground pin and the third ground pin are re-matched corresponding to the positive reference clock set by the A 13 wiring pin and the negative reference clock set by the A 14 wiring pin. The rematching with the second ground pin and the fourth ground pin is corresponding to the 0 channel transmission data set by the B 15 wiring pin and the 0 channel set by the B 16 wiring pin. The transmission data is turned off to form a reference clock differential pair that is re-matched by the ground and a channel 0 to transmit data.
The PCI-E flexible riser card of the re-matching pin according to claim 1, wherein the group A pin position, the B group pin position, the A group insertion pin position, and the B group insertion pin position are The PCI-E transmission channel transmitted by the electrical cable connector of the PCI-E interface is set to x4 channel, and is respectively adjusted to 32 pins, and the 32 pins are connected by the A 1 wiring pin. A 32 wiring pin, B 1 wiring pin ~ B 32 wiring pin, A 1 insertion pin ~ A 32 insertion pin and B 1 insertion pin ~ B 32 insertion pin, and cooperate with the third ground Line pin and fourth ground pin.
The PCI-E flexible riser card of the re-matching pin according to claim 2, wherein the retaining pins of the A 32 wiring pin and the B 30 wiring pin are deleted.
The PCI-E flexible adapter card of the re-matching pin according to claim 3, wherein the group A pin position, the B group pin position, the A group insertion pin position, and the B group insertion pin position are The PCI-E transmission channels respectively transmitted by the electrical cable connectors of the PCI-E interface are set to x8 channels or x16 channels, and are respectively adjusted to include 49 pins or 82 leads of the 32 pins. The pin is matched with the third ground pin and the fourth ground pin, and the reserved pin of the A 32 wiring pin and the B 30 wiring pin is deleted.
The PCI-E flexible riser card of the re-matching pin according to claim 2, wherein the electrical cable connector of the PCI-E interface is a flexible circuit board, and the A 1 insertion pin ~A 32 insertion pins, B 1 insertion pins ~ B 32 insertion pins form a nip for hard circuit board bonding.
The PCI-E flexible riser card of the re-matching pin according to claim 2, wherein the group A pin position and the B group pin position are re-matched by the ground line to stabilize the differential signal. For the transmission, the wire diameter of each of the wiring pins can be reduced, and the line spacing of each of the wiring pins is reduced from the original 1.0 mm to 0.5 mm to 0.635 mm, so that the original A group wiring pin and the B group wiring are made. The width of the pin forms a bandwidth for the transmission line to be reduced by 50% to 63.5%.