WO2017166657A1

WO2017166657A1 - Peripheral component interconnect bus

Info

Publication number: WO2017166657A1
Application number: PCT/CN2016/097022
Authority: WO
Inventors: 常琪
Original assignee: 乐视控股（北京）有限公司; 乐视致新电子科技（天津）有限公司
Priority date: 2016-03-31
Filing date: 2016-08-26
Publication date: 2017-10-05
Also published as: CN105843338A

Abstract

The present invention belongs to the technical field of communications. A peripheral component interconnect bus is disclosed, comprising: a surface layer of a printed circuit board for communicating with a first peripheral interface circuit, and a bottom layer of the printed circuit board for communicating with a second peripheral interface circuit, wherein the surface layer of the printed circuit board comprises surface layer contact wires arranged to match a differential impedance of the first peripheral interface circuit, and the bottom layer of the printed circuit board comprises bottom layer contact wires arranged to match a differential impedance of the second peripheral interface circuit.

Description

Peripheral component interconnect bus

The present application claims the priority of the Chinese Patent Application, which is filed on March 31, 2016, the application of which is hereby incorporated by reference. .

Technical field

The present application relates to the field of communication technologies, for example, to a peripheral component interconnection bus.

Background technique

Peripheral Component Interconnect (PCI) and PCI-E (PCI Express) are bus structures that combine high-speed peripheral devices with processors to meet the increasing data rate requirements of users. A device with a PCI bus structure can achieve a theoretical data rate of 132 Mbytes/s. One of the outstanding advantages of using the PCI bus is that the central processing unit (CPU) has a very low occupancy rate. The interaction between the CPU and the memory is basically through direct memory access (DMA), so high data is required. PCI bus devices can be used for both rate and low power consumption.

The PCI bus typically includes a PCI interface chip and a configuration chip. In the process of implementing the present application, the inventors have found that at least the following problems exist in the related art: at present, the design of the smart TV tends to be flat, which seriously compresses the space of the PCI bus, if the circuits of different peripheral interface circuit communication are combined On a printed circuit board, the differential impedance required by different peripheral interface circuits is inconsistent, which affects signal integrity and time delay, thereby reducing communication quality.

Summary of the invention

The embodiment of the present application provides a peripheral component interconnection bus and a smart TV, which implements PCI bus multiplexing.

In a first aspect, an embodiment of the present application provides a peripheral component interconnection bus, including: a printed circuit board surface layer for communicating with a first peripheral interface circuit and a printed circuit board for communicating with a second peripheral interface circuit a bottom layer, wherein the printed circuit board surface layer includes a surface contact line that is matched to meet a differential impedance of the first peripheral interface circuit, and the printed circuit board bottom layer includes a differential impedance that is matched to the second peripheral interface circuit The bottom layer of the contact line.

Optionally, the bus further includes a connector slot that mates with the printed circuit board.

Optionally, the surface contact line includes: a first predetermined length of contact line, wherein the first preset length is determined according to a differential impedance of the first peripheral interface circuit;

The bottom layer contact line includes: a second predetermined length of contact line, the second set length being determined according to a differential impedance of the second peripheral interface circuit.

Optionally, the surface contact line includes: a plurality of contact lines disposed at equal intervals, and the spacing is determined according to a differential impedance of the first peripheral interface circuit;

The bottom layer contact line includes: a plurality of contact lines disposed at equal intervals, the spacing being determined according to a differential impedance of the second peripheral interface circuit.

Optionally, the surface contact line is bent and arranged on the surface of the printed circuit board according to the first preset length; and/or the bottom contact line is bent and arranged on the surface of the printed circuit board according to the second preset length.

Optionally, the printed circuit board surface layer includes: a first material filled between the surface contact lines, the first material being determined according to a differential impedance of the first peripheral interface circuit;

The printed circuit board bottom layer includes a second material filled between the bottom layer contact lines, the second material being determined according to a second peripheral interface circuit differential impedance, the second material being different from the first material.

Optionally, the first material is a plastic and the second material is a resin.

Optionally, the first peripheral interface circuit is a universal serial bus USB interface circuit.

More optionally, the second peripheral interface circuit is a high definition multimedia interface circuit or a universal asynchronous transceiver transmitter UART interface circuit.

The peripheral component interconnection bus provided by the embodiment of the present application can achieve dual interface multiplexing by connecting the surface layer and the bottom layer of the PCI bus to different peripheral interfaces respectively. In addition, by matching the surface contact line and the bottom contact line to meet the corresponding interface circuit differential impedance, the problem of different differential impedances of different interface circuits can be solved, and the communication quality is improved.

DRAWINGS

The one or more embodiments are exemplified by the accompanying drawings in the accompanying drawings, and FIG. The figures in the drawings do not constitute a scale limitation unless otherwise stated.

1 is a schematic diagram of a peripheral component interconnection bus provided by Embodiment 1 of the present application;

1a is a schematic structural diagram of a printed circuit board surface layer of a peripheral component interconnection bus according to Embodiment 1 of the present application;

1b is a schematic structural diagram of a bottom layer of a printed circuit board of a peripheral component interconnection bus according to Embodiment 1 of the present application;

2 is a schematic diagram showing a microscopic shape of a surface contact line in a peripheral component interconnect bus provided by Embodiment 2 of the present application;

3 is a schematic diagram showing the microscopic shape of an underlying contact line in a peripheral component interconnect bus provided by Embodiment 2 of the present application;

4 is a schematic diagram of a surface layer of a printed circuit board in a peripheral component interconnect bus provided by Embodiment 3 of the present application;

FIG. 5 is a schematic diagram of a bottom layer of a printed circuit board in a peripheral component interconnect bus provided by Embodiment 3 of the present application.

The technical features indicated by the reference numerals in the figures are:

1. Printed circuit board; 2. Connector slot; 3. Surface contact line; 4. Bottom contact line; 5. Contact line.

detailed description

The present application will be described in detail below with reference to the accompanying drawings and embodiments. It is to be understood that the embodiments described herein are merely illustrative of the application and are not intended to be limiting. It should also be noted that, for the convenience of description, only some, but not all, of the contents related to the present application are shown in the drawings. The features in the embodiments of the present application may be arbitrarily combined without conflict.

In the embodiments of the present application, the orientation words used are as follows: "upper, lower, The top and bottom" are generally used in terms of the directions shown in the drawings or are used to describe the positional relationship of the components in terms of vertical, vertical or gravity directions.

Embodiment 1

Embodiment 1 of the present application provides a peripheral component interconnection bus. FIG. 1 is a schematic diagram of a peripheral component interconnection bus provided by Embodiment 1 of the present application. As shown in FIG. 1, the peripheral component interconnect bus includes a printed circuit board surface for communicating with the first peripheral interface circuit and a printed circuit board bottom layer for communicating with the second peripheral interface circuit. Wherein the printed circuit board surface layer includes a surface contact line that is matched to meet a differential impedance of the first peripheral interface circuit, and the printed circuit board bottom layer includes a bottom layer that is matched to conform to a differential impedance of the second peripheral interface circuit Contact line. The interface multiplexed peripheral component interconnect bus PCI bus can be divided into a printed circuit board surface layer and a printed circuit board bottom layer.

As shown in FIG. 1, the peripheral component interconnection bus includes: a printed circuit board 1 and a connector slot 2, and a contact line 5 is provided on the printed circuit board, and the printed circuit board 1 is matched with the connector slot 2 through the contact line 5 connection.

FIG. 1 is a schematic structural diagram of a printed circuit board surface layer of a peripheral component interconnection bus according to Embodiment 1 of the present application; FIG. 1B is a schematic structural diagram of a printed circuit board bottom layer of a peripheral component interconnection bus according to Embodiment 1 of the present application. The printed circuit board surface layer and the printed circuit board bottom layer may respectively include an insulating substrate, a conductive pattern layer on the insulating substrate, and various integrated chips, wherein the conductive pattern layer and the integrated chip on the surface of the printed circuit board and on the bottom layer of the printed circuit board are respectively used Receive signals transmitted by different peripheral interfaces. Below the surface layer of the printed circuit board, a contact line 5 is provided, which is composed of a plurality of conductive contacts. The signal is transmitted through the contact line. Since the printed circuit board surface layer and the printed circuit board bottom layer respectively communicate with different peripheral interfaces, when the signal propagates through the transmission channel, the electromagnetic coupling affects the adjacent transmission line. In order to avoid the influence of crosstalk and ensure the integrity of the signal, it is necessary to ensure the matching and continuity of the differential impedance. Since the differential impedance required by different peripheral interfaces is different, it is necessary to match the surface contact line 3 and the bottom contact line 4 to the differential impedance of the peripheral interface corresponding to the corresponding connection. Correspondingly, the printed circuit board surface layer includes a surface contact line 3 matched to meet a differential impedance of the first peripheral interface circuit, and the printed circuit board bottom layer includes a differential impedance matched to the second peripheral interface circuit. The bottom contact line 4. In addition, the peripheral component interconnect bus also includes a connector slot 2 that is mated to the printed circuit board. The signal is transmitted to the corresponding channel through the pins of the connector slot 2.

In an optional implementation manner of this embodiment, the printed circuit board surface layer is used for interfacing with a universal serial bus (USB), and further, the printed circuit board bottom layer is used for Connected to the High Definition Multimedia Interface (HDMI). The USB interface and the HDMI interface are more commonly used interfaces in smart TVs. Through the peripheral component interconnection bus, the PCI bus can realize the purpose of transmitting USB interface data or HDMI interface data. In addition, the second peripheral interface circuit can also be a Universal Asynchronous Receiver/Transmitter (UART) interface circuit. The interface circuit can be adjusted according to the design requirements.

Embodiment 2

2 is a schematic diagram showing a microscopic shape of a surface contact line of a peripheral component interconnection bus provided in Embodiment 2 of the present application; FIG. 3 is a schematic diagram showing a microscopic shape of an underlying contact line in a peripheral component interconnection bus provided in Embodiment 2 of the present application. The embodiment is based on the above embodiment, the surface contact line 3 can be set as a contact line of a first preset length, and the first preset length is determined according to the differential impedance of the first peripheral interface circuit; A contact line of a second preset length may be set, the second preset length being determined according to a differential impedance of the second peripheral interface circuit. Since the length of the contact line can affect the differential impedance, the length of the contact line can be experimentally determined according to the differential impedance value of the peripheral interface. Since the differential impedance of the first peripheral interface circuit is different from the differential impedance of the first peripheral interface circuit, the length of the surface contact line 3 is different from the length of the bottom contact line 4. As can be seen from FIG. 2, the microscopic shape of the surface contact line 3 is approximately "F" shaped, since the length of the region where the contact line is referred to on the circuit board is fixed, and in order to satisfy the length requirement of the surface contact line 3, The surface contact line 3 may be formed by bending the contact line regions in the surface layer of the printed circuit board in accordance with the first predetermined length. Similarly, as can be seen from FIG. 3, the bottom contact line 4 is set to a second predetermined length, and its microscopic shape is approximately "bow" shaped. The length of the surface contact line 3 is smaller than the length of the underlying contact line 4. This is because the surface is connected to the USB interface and the bottom layer is connected to the HDMI interface. The differential impedance of the USB interface is 90Ω, and the differential impedance of the HDMI interface is 100Ω. The length of the contact line is proportional to the differential impedance, and the length of the contact line on the printed circuit board 1 can be determined experimentally based on the differential impedance value of the interface. When there is a limit to the length of the contact line on the printed circuit board, the surface contact line 3 may be bent and arranged on the surface of the printed circuit board according to the first predetermined length; and/or the bottom contact line 4 may be according to the second pre- Set the length to be curved on the surface of the printed circuit board.

Embodiment 3

4 is a schematic diagram of a printed circuit board surface layer in a peripheral component interconnection bus according to Embodiment 3 of the present application; FIG. 5 is a schematic diagram of a printed circuit board bottom layer in a peripheral component interconnection bus according to Embodiment 3 of the present application; Figure. The embodiment is based on the above embodiment, the surface contact line 3 includes: a plurality of contact lines disposed at equal intervals, the spacing is determined according to a differential impedance of the first peripheral interface circuit; and the bottom contact line 4 includes: A plurality of contact lines disposed at a pitch, the spacing being determined according to a differential impedance of the second peripheral interface circuit. Since the spacing between the contact lines can affect the differential impedance, the spacing between the contact lines can be experimentally determined based on the differential impedance values of the peripheral interfaces. Since the differential impedance of the first peripheral interface circuit is different from that of the first peripheral interface circuit, the pitch of the surface contact line 3 is different from the pitch of the bottom contact line 4. As can be seen from Figures 2 and 3, the pitch of the surface contact lines 3 is greater than the pitch of the bottom contact lines 4. Because the surface is connected to the USB interface, the bottom layer is connected to the HDMI interface. The differential impedance of the USB interface is 90Ω, and the differential impedance of the HDMI interface is 100Ω. The size of the pitch is inversely proportional to the differential impedance, and the spacing between the contact lines on the printed circuit board 1 can be determined experimentally based on the differential impedance values of the interface.

In addition, the differential impedance can also be adjusted by filling different materials between the contact lines. a first material that may be filled between the surface contact lines 3, the first material being determined according to a differential impedance of the first peripheral interface circuit; the printed circuit board underlayer comprising: filling between the underlying contact lines 4 a second material, the second material being determined according to a differential impedance of the second peripheral interface circuit, the second material being different from the first material. Wherein the first material is a plastic and the second material is a resin. Since different materials have different absorption coefficients for the propagation of electromagnetic waves, thereby affecting the electromagnetic coupling between the contact lines, thereby affecting the differential impedance, the electromagnetic absorption characteristics of the materials can also be used to modulate the differential impedance, for example, The test determines the effect of different materials on the differential printed circuit on the same printed circuit board 1, and optionally fills the material between the contact lines.

In addition, the ratio of the differential impedance can be achieved by any combination of the above three methods, such as adjusting the length of the contact line, adjusting the spacing between the contact lines, and simultaneously filling the material between the contact lines. The combination method will not be described here.

Note that the above are only the preferred embodiments of the present application and the technical principles applied thereto. A person skilled in the art will understand that the present application is not limited to the specific embodiments described herein, and that various changes, modifications and substitutions can be made by those skilled in the art without departing from the scope of the invention. Therefore, although the present application has been described in detail by the above embodiments, the present application is not limited to the above embodiments, and other equivalent embodiments may be included without departing from the concept of the present application. The scope is determined by the scope of the appended claims.

Industrial applicability

The peripheral component interconnection bus provided by the embodiment of the present application improves the communication quality.

Claims

A peripheral component interconnect bus comprising: a printed circuit board surface for communicating with a first peripheral interface circuit and a printed circuit board bottom layer for communicating with a second peripheral interface circuit, wherein the printed circuit board surface A surface contact line that is matched to meet a differential impedance of the first peripheral interface circuit is included, and the printed circuit board bottom layer includes an underlying contact line that is matched to a differential impedance of the second peripheral interface circuit.
The bus of claim 1 further comprising a connector slot that mates with the printed circuit board.
The bus of claim 1, wherein the surface contact line comprises: a first predetermined length of contact line, the first predetermined length being determined according to a differential impedance of the first peripheral interface circuit;

The bottom layer contact line includes: a second preset length of contact line, and the second preset length is determined according to a second peripheral interface circuit differential impedance.
The bus of claim 3, wherein the surface contact line is curved in a surface of the printed circuit board according to the first predetermined length; and/or

The underlying contact lines are curvedly arranged on the surface of the printed circuit board according to the second predetermined length.
The bus of claim 1, wherein the surface contact line comprises: a plurality of contact lines arranged at equal intervals, the spacing being determined according to a differential impedance of the first peripheral interface circuit;

The bottom layer contact line includes: a plurality of contact lines disposed at equal intervals, the spacing being determined according to a differential impedance of the second peripheral interface circuit.
The bus of claim 1 wherein said printed circuit board skin layer comprises: a first material filled between said skin contact lines, said first material being determined in accordance with a differential impedance of said first peripheral interface circuit;

The printed circuit board bottom layer includes a second material filled between the bottom layer contact lines, the second material being determined according to a second peripheral interface circuit differential impedance, the second material being different from the first material.
The bus of claim 6 wherein said first material is plastic and said second material is a resin.
A bus according to any of claims 1-7, wherein said first peripheral interface circuit is a universal serial bus USB interface circuit.
The bus of any of claims 1-7, wherein the second peripheral interface circuit is a high definition multimedia interface circuit or a universal asynchronous transceiver UART interface circuit.