WO2018173718A1 - Couche d'arrêt de gravure et procédé de fabrication de dispositif à semiconducteur - Google Patents

Couche d'arrêt de gravure et procédé de fabrication de dispositif à semiconducteur Download PDF

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Publication number
WO2018173718A1
WO2018173718A1 PCT/JP2018/008299 JP2018008299W WO2018173718A1 WO 2018173718 A1 WO2018173718 A1 WO 2018173718A1 JP 2018008299 W JP2018008299 W JP 2018008299W WO 2018173718 A1 WO2018173718 A1 WO 2018173718A1
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WIPO (PCT)
Prior art keywords
etching
stop layer
layer
etching stop
etched
Prior art date
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PCT/JP2018/008299
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English (en)
Japanese (ja)
Inventor
中村　真也
充則 逸見
藤井　佳詞
佳広 池田
Original Assignee
株式会社アルバック
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Publication date
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Priority to JP2019507505A priority Critical patent/JP6603436B2/ja
Priority to KR1020197016732A priority patent/KR102228330B1/ko
Priority to CN201880003102.5A priority patent/CN109643651B/zh
Publication of WO2018173718A1 publication Critical patent/WO2018173718A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76813—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

Definitions

  • the present invention relates to an etching stop layer and a method for manufacturing a semiconductor device having a stacked structure of the etching stop layer and a layer to be etched.
  • Patent Document 1 discloses a 3D (three-dimensional) -NAND flash memory in which memory cells are stacked in the vertical direction.
  • the manufacturing process of this 3D-NAND flash memory includes a step of forming an etching stop layer, a step of laminating a polysilicon layer, a silicon oxide layer, etc. constituting a memory cell on the etching stop layer, and laminating these layers.
  • An aluminum oxide film is generally used as such an etching stop layer.
  • the etching stop layer is wet-etched using an etchant such as hydrofluoric acid.
  • an etchant such as hydrofluoric acid.
  • the wet etching rate of the aluminum oxide film is relatively high at about 70 ⁇ / min, and it is difficult to finish the wet etching at an appropriate timing. If the end timing of the wet etching is delayed, the wet etching proceeds isotropically, resulting in a problem that the etching stop layer is excessively etched in the lateral direction. This defect becomes more prominent when the aluminum oxide film is thin.
  • the etching stop layer formed of the aluminum oxide film does not have good controllability with respect to wet etching.
  • an object of the present invention is to provide an etching stop layer having excellent controllability when wet etching and a method for manufacturing a semiconductor device.
  • the etching stop layer of the present invention laminated on the front side in the etching progress direction of the etching target layer when etching the etching target layer in one direction by dry etching contains 20 to 50% by weight of boron. It is characterized by comprising an aluminum oxide film.
  • the wet etching rate of the etching stop layer can be suppressed low. According to an experiment described later, it was confirmed that when wet etching was performed using hydrofluoric acid as an etching solution, the wet etching rate could be suppressed to a range of 10 to 50 mm / min. Therefore, it is possible to obtain an etching stop layer having excellent controllability when wet etching is performed.
  • the present invention is preferably applied to the case where the layer to be etched is composed of a laminated film in which 32 layers or more of a polysilicon layer and an insulating layer containing silicon are laminated by dry etching using oxygen gas. Can do.
  • the method for manufacturing a semiconductor device of the present invention for manufacturing a semiconductor device having a laminated structure of the etching stop layer and the layer to be etched is one selected from hydrofluoric acid after dry etching the layer to be etched.
  • the method includes the step of wet etching the etching stop layer using an etchant, wherein the wet etching rate of the etching stop layer is set in a range of 10 to 50 mm / min.
  • FIG. 1 The schematic cross section of the semiconductor device to which the etching stop layer of the embodiment of the present invention is applied.
  • (A)-(d) is a schematic cross section explaining the manufacturing method of a semiconductor device. The figure which illustrates typically the sputtering device which can form the etching stop layer of embodiment of this invention. The graph which shows the experimental result which confirms the effect of this invention.
  • the semiconductor device SD includes a substrate S, an etching stop layer Ls formed on the substrate S, and an etching target layer Le formed on the etching stop layer Ls.
  • the substrate S can be appropriately selected from a silicon substrate, a GaAs substrate, a GaP substrate, an InP substrate, or the like according to the type of the semiconductor device SD.
  • the substrate S includes a substrate in which a semiconductor element such as a transistor is formed on the surface of the substrate S.
  • the etching stop layer Ls is laminated on the etching progress front side (lower side) of the etching target layer Le when the etching target layer Le is etched in one direction (downward) by dry etching.
  • the etching stop layer Ls is composed of an aluminum oxide film (BAlOx film) containing 20 to 50% by weight of boron.
  • BAlOx film aluminum oxide film
  • the wet etching rate of the etching stop layer Ls may not be sufficiently suppressed.
  • the dry etching resistance decreases. There is.
  • the to-be-etched layer Le is formed, for example, by laminating a large number (for example, 32 layers or more) of polysilicon layers or insulating layers containing silicon.
  • a large number for example, 32 layers or more
  • the insulating layer containing silicon a silicon oxide film, a silicon nitride film, or a silicon oxynitride film can be used.
  • a method for manufacturing the semiconductor device SD will be described with reference to FIG.
  • an etching stop layer Ls is formed on the substrate S as shown in FIG.
  • the etching stop layer Ls can be formed using the sputtering apparatus SM shown in FIG.
  • the sputtering apparatus SM includes a vacuum chamber 1 that defines a processing chamber 10.
  • a gas pipe 11 for introducing a sputtering gas into the processing chamber 10 is connected to the side wall of the vacuum chamber 1.
  • a mass flow controller 12 is interposed in the gas pipe 11 and communicates with a gas source 13 of the sputtering gas.
  • the sputtering gas includes a reactive gas such as oxygen gas or water vapor gas when reactive sputtering is performed.
  • an exhaust pipe 14 communicating with a vacuum exhaust means P such as a rotary pump or a turbo molecular pump.
  • the substrate stage 2 includes a metal base 21 having an upper surface shape corresponding to the outline of the substrate S, for example, and a chuck plate 22 mounted on the upper surface of the base 21.
  • a known electrode (not shown) is embedded in the chuck plate 22, and a chuck voltage is applied to the electrode from a chuck power source so that the substrate S can be sucked and held on the upper surface of the chuck plate 22 with its film-forming surface facing up. It has become.
  • a rotating shaft 24 supported by a bearing 23 inserted through an opening provided on the bottom surface of the vacuum chamber 1 is connected to the center of the lower surface of the base 21.
  • the rotating shaft 24 is connected to a driving unit (not shown) outside the vacuum chamber 1. )
  • the base 21 may be provided with a passage for circulating the refrigerant and a heater so that the substrate S can be controlled to a predetermined temperature during film formation by sputtering.
  • Two targets 3a and 3b are inclinedly arranged at an interval of 180 ° in the circumferential direction so that the sputtering surfaces 31a and 31b respectively face the substrate S on the ceiling portion of the vacuum chamber 1.
  • the target 3a can be made of aluminum oxide, and the target 3b can be made of boron.
  • a copper backing plate for cooling the targets 3a and 3b during the film formation by sputtering is heated by heat such as indium and tin. Bonding is performed via a bonding material made of a material having high conductivity.
  • a known magnet unit is disposed above each of the targets 3a and 3b, and a magnetic field (known closed magnetic field or cusp magnetic field) is generated in the space below the sputtering surfaces 31a and 31b of the targets 3a and 3b.
  • You may comprise so that the ion etc. ionized below the surfaces 31a and 31b may be captured, and the sputtered particles scattered from the targets 3a and 3b may be efficiently ionized.
  • the targets 3a and 3b are connected to high-frequency power sources E1 and E2 as sputtering power sources, respectively, and high-frequency power of a predetermined frequency (for example, 13.56 MHz) is supplied between the target 3a and 3b and the ground.
  • the sputtering apparatus SM has known control means including a microcomputer, a sequencer, etc., and controls the operation of the mass flow controller 12, the operation of the evacuation means P, the operation of the sputtering power sources E1, E2, and the like. I have to.
  • the inside of the vacuum chamber 1 (processing chamber 10) reaches a predetermined degree of vacuum (for example, 1 ⁇ 10 ⁇ 5 Pa).
  • the substrate S is transported into the vacuum chamber 1 by a transport robot (not shown), and the substrate S is positioned and held on the substrate stage 2.
  • the mass flow controller 12 is controlled to introduce argon gas at a predetermined flow rate (at this time, the pressure in the processing chamber 10 is 0.1 to 0.2 Pa).
  • high frequency power of 13.56 MHz is input from 100 W to 500 W
  • high frequency power of 13.56 MHz is input from the high frequency power source E2 to the target 3b, for example, from 100 W to 500 W.
  • plasma is formed in the vacuum chamber 1 and the target 31 is sputtered.
  • an aluminum oxide film (BAlOx film) containing boron is formed on the surface of the substrate S.
  • the boron content in the aluminum oxide film can be controlled by changing the ratio of the input power to the target 3a and the input power to the target 3b.
  • a multilayer of a polysilicon film, a silicon oxide film, etc. is formed as an etched layer Le on the etching stop layer Ls. Since the polysilicon film and the silicon oxide film can be formed using a known method such as a sputtering method or a CVD method, detailed description thereof is omitted here. In the case where a known sputtering apparatus is used, a silicon target may be used as a target in the treatment chamber. When a resist pattern which is the mask layer Lm is formed on the layer to be etched Le using a known method, the structure shown in FIG. 2A is obtained.
  • the etching target layer Le is dry-etched in the vertical direction to form wiring holes h in the etching target layer Le.
  • a well-known RIE condition using a fluorine-containing gas such as CHF 3 , C 2 F 6 , or CF 4 as an etching gas can be used. .
  • the etching stop layer Ls is wet etched as shown in FIG.
  • an etchant used for wet etching for example, a known one selected from hydrofluoric acid or the like can be used.
  • the etching stop layer Ls of this embodiment is composed of an aluminum oxide film containing 20 to 50% by weight of boron, the wet etching rate of the etching stop layer Ls can be suppressed low. For this reason, wet etching can be terminated at an appropriate timing, and the etching stop layer Ls can be prevented from excessively proceeding in the lateral direction. Therefore, it can be said that the etching stop layer Ls of this embodiment has excellent controllability with respect to wet etching.
  • the semiconductor device SD shown in FIG. 2D is obtained. If necessary, a conductive film is formed in the hole h.
  • ashing conditions known ones can be used, and thus detailed description thereof is omitted here.
  • the following experiment was performed using the sputtering apparatus SM.
  • a ⁇ 300 mm silicon substrate was used as the substrate S, and this substrate S was set on the substrate stage 2 in the vacuum chamber 1, and then argon gas was introduced into the processing chamber 10 at a flow rate of 300 sccm (the processing chamber at this time).
  • the pressure inside 10 is about 1.35 Pa), and 227 W of high frequency power of 13.56 MHz was supplied from the power source E1 to the aluminum oxide target 3a and 300 W of high frequency power of 13.56 MHz was supplied from the power source E2 to the boron target 3b ( At this time, the input power ratio to the targets 3a and 3b is 1: 1.32).
  • the targets 3a and 3b were sputtered to form an aluminum oxide film (BAlOx film) containing 20% by weight (wt%) of boron on the surface of the substrate S.
  • the aluminum oxide containing 20% by weight of boron was wet etched, and the etching rate was measured to be 45 ⁇ / min.
  • the input power ratios to the targets 3a and 3b are 1: 0, 1: 0.7, 1: 1, 1: 1.3, 1: 1.5, 1: 1.8, and 1: 2.6.
  • the wet etching rate of the aluminum oxide film can be suppressed to a range of 10 to 25% / min by setting the boron content in the aluminum oxide film to a range of 25 to 50% by weight. . It was confirmed that when the boron content exceeded 50% by weight, the wet etching rate did not change and there were many particles.
  • an aluminum oxide target is used as the target 3a.
  • an aluminum target may be used as the target 3a, and the aluminum target may be reactively sputtered.
  • the target made from aluminum oxide (for example, 30 weight%) containing a predetermined concentration of boron (The etching stop layer Ls can be formed using one BAlOx target.
  • the formation method of the etching stop layer Ls is not limited to this,
  • well-known film-forming methods such as CVD method, are used. Can be used.
  • the boron content can be controlled by controlling the flow rate ratio between the boron-containing source gas and the aluminum-containing source gas.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Weting (AREA)

Abstract

L'invention concerne une couche d'arrêt de gravure ayant une excellente performance de commande lorsqu'une gravure humide est réalisée, et un procédé de fabrication d'un dispositif à semiconducteur. Cette couche d'arrêt de gravure Ls, qui est stratifiée sur Le côté avant, par rapport à la direction d'avancement de gravure, d'une couche gravée Le lorsque la couche en cours de gravure Le est gravée à sec dans une direction, est constituée d'un film d'oxyde d'aluminium (film de BAlOx, film de YAlOx) contenant 20 à 50 % en poids de bore ou d'yttrium.
PCT/JP2018/008299 2017-03-24 2018-03-05 Couche d'arrêt de gravure et procédé de fabrication de dispositif à semiconducteur WO2018173718A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2019507505A JP6603436B2 (ja) 2017-03-24 2018-03-05 エッチングストップ層及び半導体デバイスの製造方法
KR1020197016732A KR102228330B1 (ko) 2017-03-24 2018-03-05 에칭 스톱층 및 반도체 디바이스의 제조 방법
CN201880003102.5A CN109643651B (zh) 2017-03-24 2018-03-05 蚀刻停止层及半导体器件的制造方法

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JP2017-058670 2017-03-24
JP2017058670 2017-03-24

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KR (1) KR102228330B1 (fr)
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WO (1) WO2018173718A1 (fr)

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US11488859B2 (en) * 2019-12-27 2022-11-01 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
CN112289803A (zh) * 2020-10-22 2021-01-29 长江存储科技有限责任公司 3d存储器件及其制造方法

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US20130084441A1 (en) * 2011-09-29 2013-04-04 Seagate Technology Llc Optical articles and methods of making same
JP2015056444A (ja) * 2013-09-10 2015-03-23 株式会社東芝 不揮発性記憶装置およびその製造方法
JP2015191922A (ja) * 2014-03-27 2015-11-02 株式会社東芝 半導体装置の製造方法

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US4767724A (en) * 1986-03-27 1988-08-30 General Electric Company Unframed via interconnection with dielectric etch stop
KR100655774B1 (ko) * 2004-10-14 2006-12-11 삼성전자주식회사 식각 저지 구조물, 이의 제조 방법, 이를 포함하는 반도체장치 및 그 제조 방법
CN104051256B (zh) * 2013-03-14 2018-04-17 台湾积体电路制造股份有限公司 半导体器件及其制造方法
US9437606B2 (en) 2013-07-02 2016-09-06 Sandisk Technologies Llc Method of making a three-dimensional memory array with etch stop
US9960280B2 (en) * 2013-12-26 2018-05-01 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
JP6290022B2 (ja) 2014-07-17 2018-03-07 東芝メモリ株式会社 半導体装置の製造方法

Patent Citations (3)

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Publication number Priority date Publication date Assignee Title
US20130084441A1 (en) * 2011-09-29 2013-04-04 Seagate Technology Llc Optical articles and methods of making same
JP2015056444A (ja) * 2013-09-10 2015-03-23 株式会社東芝 不揮発性記憶装置およびその製造方法
JP2015191922A (ja) * 2014-03-27 2015-11-02 株式会社東芝 半導体装置の製造方法

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CN109643651B (zh) 2023-04-28
JP6603436B2 (ja) 2019-11-06
KR20190071829A (ko) 2019-06-24
CN109643651A (zh) 2019-04-16
KR102228330B1 (ko) 2021-03-16
JPWO2018173718A1 (ja) 2019-06-27

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