WO2018170688A1 - 电阻电容rc振荡器 - Google Patents

电阻电容rc振荡器 Download PDF

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Publication number
WO2018170688A1
WO2018170688A1 PCT/CN2017/077344 CN2017077344W WO2018170688A1 WO 2018170688 A1 WO2018170688 A1 WO 2018170688A1 CN 2017077344 W CN2017077344 W CN 2017077344W WO 2018170688 A1 WO2018170688 A1 WO 2018170688A1
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Prior art keywords
signal
output
switch
voltage
oscillator
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PCT/CN2017/077344
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English (en)
French (fr)
Inventor
王程左
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深圳市汇顶科技股份有限公司
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Priority to CN201780000234.8A priority Critical patent/CN107112947A/zh
Priority to PCT/CN2017/077344 priority patent/WO2018170688A1/zh
Publication of WO2018170688A1 publication Critical patent/WO2018170688A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/02—Details
    • H03B5/04—Modifications of generator to compensate for variations in physical values, e.g. power supply, load, temperature
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/20—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising resistance and either capacitance or inductance, e.g. phase-shift oscillator
    • H03B5/24—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising resistance and either capacitance or inductance, e.g. phase-shift oscillator active element in amplifier being semiconductor device

Definitions

  • the present application relates to the field of electronic technology and, more particularly, to a resistive capacitor (RC) oscillator.
  • RC resistive capacitor
  • the circuit structure of the conventional RC oscillator includes a voltage to current unit, a bandgap reference unit, an active filter unit, and a symmetric voltage controlled relaxation oscillation unit.
  • the voltage-to-current unit is used for inputting current for a symmetrical voltage-controlled relaxation oscillating unit;
  • the symmetrical voltage-controlled relaxation oscillating unit is generally two symmetrical charging and discharging circuits including a voltage source, and the output voltages are respectively V1 and V2;
  • a bandgap reference unit is used to generate a reference voltage;
  • the active filter unit forms a negative feedback loop by using a superimposed signal of V1 and V2 and a reference voltage as a positive and negative input and an output of the active filter unit, thereby output frequency precision High signal, but the structure of the circuit structure of the conventional RC oscillator is relatively complicated.
  • the embodiment of the present application provides a resistor-capacitor RC oscillator, which can reduce the structural complexity of the RC oscillator on the basis of ensuring the frequency precision of the output signal.
  • an RC oscillator in a first aspect, includes: a reference voltage generating unit 210, a voltage controlled relaxation oscillating unit 220, an active filter unit 230, a voltage control unit 240, and a reference voltage generating unit 210 for generating a reference voltage; the voltage controlling the relaxation oscillating unit
  • the 220 includes a first constant current source, a first charging and discharging circuit, and a second charging and discharging circuit, wherein the first constant current source is configured to alternately charge the first charging and discharging circuit and the second charging and discharging respectively to generate a first oscillating signal Or a second oscillating signal, the first oscillating signal and the second oscillating signal are superimposed to obtain a third oscillating signal, wherein a structure of the first charging and discharging circuit is symmetric with a structure of the second charging and discharging circuit; the active filter
  • the unit 230 is configured to integrate the reference voltage and the third oscillating signal to obtain a fourth signal.
  • the symmetric voltage-controlled relaxation oscillation unit 220 includes a first constant current source and a structurally symmetric charge and discharge circuit, and the first constant current source can alternately charge the charging circuit in the structurally symmetric charge and discharge circuit and generate the first The oscillation signal V1 and the second oscillation signal V2.
  • the embodiment of the present application generates V1 and V2 through a constant current source, and generates V1 and V2 by voltage source and voltage to current unit generation in the conventional scheme, which reduces the complexity of the RC oscillator structure.
  • the reference voltage generating unit 210 includes: a second constant current source and a first resistor.
  • the use of the reference voltage unit 210 to generate the reference voltage by the RC oscillator can avoid the temperature error caused by the bandgap reference unit, thereby improving the frequency accuracy of the RC oscillator output signal.
  • the reference voltage generating unit of the embodiment of the present application has a bandgap reference. The unit reduces the power consumption and chip area of the RC oscillator.
  • the first constant current source and the second constant current source are provided by the same current source system.
  • the RC oscillator saves the area of the RC oscillator by using the same current source system, and the output current is a positive temperature coefficient, which can reduce the performance degradation of the op amp at high temperatures.
  • the first resistor is a resistor having a temperature coefficient less than a predetermined coefficient threshold.
  • the temperature coefficient of the first resistor may be composed of a polycrystalline resistor of a negative temperature coefficient and a diffusion resistor of a positive temperature coefficient, and the ratio of the ratio between them may be such that the temperature coefficient is less than a preset coefficient threshold, and the preset coefficient threshold may be exhausted It is possible to be close to zero, which further improves the frequency accuracy of the output signal by improving the first resistance.
  • the first resistor can be an off-chip precision resistor.
  • the comparator consists of a two-stage amplifier, a Schmitt inverter, and an inverting buffer.
  • the signal output frequency of the RC oscillator is further improved by the first stage differential amplifier and the second stage common source amplifier, and the Schmitt inverter INV1 and the buffered INV2 inverter.
  • the voltage control unit 240 includes a comparator including a first positive input terminal, a first negative input terminal, and a first output terminal, and the first positive input terminal is configured to alternately input the a fourth signal and the second oscillating signal, the first negative input terminal is for alternately inputting the fourth signal and the first oscillating signal, and the first positive input terminal and the first negative input terminal are present at the same time Any one of the terminals is for inputting the fourth signal, and the first output is for outputting the fifth signal or the sixth signal.
  • the voltage control unit of the embodiment of the present application can input only one comparator by alternately inputting the output signal of the symmetric voltage-controlled relaxation oscillation unit to the comparator, which saves the power consumption of the RC oscillator and the area of the chip.
  • the RC oscillator further includes: a logic control unit 250, configured to perform logic processing on the fifth signal or the sixth signal to generate a first control signal and a second control signal, the first control The signal and the second control signal are opposite phase signals, and the first control signal and the second control signal are used to control the first constant current source to alternately charge the symmetric charging and discharging circuit.
  • a logic control unit 250 configured to perform logic processing on the fifth signal or the sixth signal to generate a first control signal and a second control signal, the first control The signal and the second control signal are opposite phase signals, and the first control signal and the second control signal are used to control the first constant current source to alternately charge the symmetric charging and discharging circuit.
  • the first constant current source is automatically controlled by the logic control unit to alternately charge the structurally symmetric charging and discharging circuit, thereby avoiding setting a special alternating control device and saving the power consumption of the RC oscillator.
  • the voltage controlled relaxation oscillating unit further includes a second output end and a third output end
  • the first charging and discharging circuit includes a first charging circuit and a first discharging circuit
  • the second charging and discharging circuit includes a second charging circuit and a second discharging circuit
  • the first charging circuit is composed of a first switching tube and a first capacitor
  • the first discharging circuit is composed of the first capacitor and the third switching tube
  • the second charging circuit is composed of a second switch tube and a second capacitor
  • the second discharge circuit is composed of the second capacitor and the fourth switch tube
  • the switch states of the third switch tube and the second switch tube are controlled by the first control signal
  • the first A switching state of a switching transistor and the fourth switching transistor is controlled by the second control signal
  • the second output terminal is configured to output the first oscillation signal
  • the third output terminal is configured to output the second oscillation signal.
  • a first switch and a second switch are sequentially disposed between the second output end and the third output end, and a switch state of the first switch is controlled by the first control signal, the second The switching state of the switch is controlled by the second control signal;
  • the symmetrical voltage-controlled relaxation oscillating unit 220 further includes a fourth output end, the fourth output end is disposed between the first switch and the second switch, and the The four outputs are used to output the third oscillating signal.
  • the active filter unit 230 includes an operational amplifier, a second resistor and a third capacitor
  • the operational amplifier includes a second positive input terminal, a second negative input terminal, and a fifth output terminal, wherein the second negative input terminal is respectively connected to one end of the second resistor and one end of the third capacitor
  • the other end of the second resistor is connected to the output end of the third oscillating signal
  • the other end of the third capacitor is connected to the fifth output end
  • the second positive input terminal is used for inputting the reference voltage
  • the fifth The output is used to output the fourth signal.
  • the fourth signal is maintained at a fixed DC voltage value, and the stability of the frequency of the output signal is improved.
  • the voltage average feedback loop can eliminate the hysteresis time of the comparator and further improve The frequency accuracy of the output signal.
  • the voltage control unit 240 further includes a third switch, a fourth switch, a fifth switch, and a sixth switch, where the third switch is disposed at the fifth output end and the first positive input end
  • the fourth switch is disposed between the third output end and the first positive input end
  • the fifth switch is disposed between the second output end and the first negative input end
  • the sixth switch is disposed at The fifth output end and the first negative input end
  • the switch states of the third switch and the fifth switch are controlled by the first control signal
  • the switch states of the fourth switch and the sixth switch pass the The second control signal is controlled.
  • the two comparators are avoided, the number of comparators is reduced, thereby saving the power consumption of the RC oscillator and the chip. area.
  • the operational amplifier is a two-stage operational amplifier with Miller compensation.
  • the transistor area in the op amp can be designed to increase the noise performance of the op amp, thereby increasing the frequency accuracy of the output signal.
  • the logic control unit includes a first inverter, a second inverter, a third inverter, a first NAND gate, and a second NAND gate, where the first inverter includes a third input end and a sixth output end, the first NAND gate includes the third input end, the fourth input end, and the seventh output end, the second NAND gate includes a fifth input end, a sixth input end, and An eighth output terminal, the second inverter includes a seventh input end and a ninth output end, the third inverter includes an eighth input end and a tenth output end, the fourth input end and the eighth output end Connecting, the fifth input end is connected to the seventh output end, the sixth output end is connected to the sixth input end, the seventh output end is connected to the seventh input end, the eighth output end is connected to the eighth An input terminal, the third input terminal is configured to input the fifth signal or the sixth signal, the ninth output terminal is configured to output the first control signal, and the tenth output terminal is configured to output the first Two control signals
  • the first constant current source is automatically controlled by the logic control unit to alternately charge the structurally symmetric charging and discharging circuit, thereby avoiding setting a special alternating control device and saving the power consumption of the RC oscillator.
  • the fifth signal and the sixth signal are opposite in phase.
  • the voltage control unit outputs the fifth signal and the sixth signal as a clock signal.
  • the present application provides a method of signal processing, which is performed by the unit of the RC oscillator described in the above first aspect or any of the possible implementations of the first aspect above.
  • a timing chip comprising the RC oscillator and the memory of any one of the first aspect or the first aspect, wherein the memory storage program is used as the RC oscillator
  • the system clock that executes the program in memory.
  • the reference voltage generating unit generates a reference voltage
  • the symmetric voltage-controlled relaxation oscillating unit is configured to alternately charge the symmetrical charging and discharging circuit to generate a first oscillating signal or a second An oscillating signal
  • the active filter unit integrates the reference voltage and the third oscillating signal obtained by superimposing the first oscillating signal and the second oscillating signal to obtain a fourth signal
  • the voltage control unit is configured to the fourth signal and the first oscillating The signal is compared to generate a fifth signal or the fourth signal and the second oscillating signal are compared to generate a sixth signal, such that V1 and V2 are generated by the first constant current source, and the voltage source and the voltage are converted to current according to the conventional scheme.
  • Cell generation for charging generates V1 and V2, reducing the complexity of the RC oscillator structure.
  • FIG. 1 is a schematic diagram of a circuit configuration of a conventional RC oscillator
  • FIG. 2 is a schematic diagram of signal transmission in an RC oscillator of the present application.
  • FIG. 3 is a schematic structural view of an RC oscillator of the present application.
  • FIG. 4 is a schematic diagram of waveforms of signals transmitted between different units in an RC oscillator according to an embodiment of the present application
  • FIG. 5 is a schematic structural diagram of an operational amplifier according to an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of a comparator according to an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of a current source according to an embodiment of the present application.
  • FIG. 1 shows a schematic diagram of a circuit configuration of a conventional RC oscillator.
  • the circuit structure of the conventional RC oscillator is composed of a voltage-to-current unit 110, a bandgap reference unit 120, an active filter unit 130, and a symmetry.
  • the voltage control relaxation oscillation unit 140 is composed of.
  • the voltage-to-current unit 110 causes the input voltage to be linearly converted into a current through a feedback loop controlled by the amplifier, and the current is input to the symmetric voltage-controlled relaxation oscillation unit 140, and the symmetric voltage-controlled relaxation oscillation unit 140 outputs the first a signal V1 and a second signal V2, and a continuous oscillating signal Vosc obtained by superimposing V1 and V2; the bandgap reference unit 120 generates a zero temperature reference voltage VREF1; the active filter unit 130 passes the rail-to-rail input forming a feedback loop
  • the operational amplifier (Rail to RaiInput Amplifier amplifier, RtR Input AMP) integrates Vosc and VREF1 to generate Vc; Vc and V1 are input to the first comparator (Rail to Rai Input comparator, RtR InputCMP1) to obtain the first CLK signal, Vc and V2.
  • the operational amplifier RtR Input AMP, the first comparator RtRInput CMP1 and the second comparator RtR Input CMP2 are rail-to-rail input type.
  • the rail-to-rail input refers to the common-mode input range of the op amp or comparator that is the range between the power rail (eg, VSS or GND) to the power rail (eg, VDD).
  • the circuit configuration of the conventional RC oscillator is such that the frequency accuracy of the output signal of the oscillator is improved by the negative feedback adjustment characteristic peculiar to the voltage average feedback technique of the active filter unit 130.
  • the symmetrical voltage-controlled relaxation oscillating unit 140 in the conventional circuit structure needs to generate the first signal V1 and the second signal V2 through the voltage source and the current output by the voltage-to-current unit 110, thereby showing the circuit structure of the conventional RC oscillator. quite complicated.
  • the factors affecting the frequency accuracy of the RC oscillator output signal mainly include temperature, flicker noise of the current source, and delay.
  • FIG. 2 is a schematic structural diagram of an RC oscillator according to an embodiment of the present application.
  • the RC oscillator includes a reference voltage generating unit 210, a voltage controlled relaxation oscillating unit 220, an active filter unit 230, and a voltage control unit 240.
  • the reference voltage generating unit 210 is configured to generate a reference voltage;
  • the voltage controlled relaxation oscillation unit 220 includes a first constant current source and a structurally symmetric charge and discharge circuit, that is, the voltage controlled relaxation oscillation unit 220 has a symmetrical circuit structure or is a symmetric voltage controlled relaxation oscillation unit, the symmetrical
  • the circuit structure may be a first charging and discharging circuit and a second charging and discharging circuit, respectively, the first constant current source is used for alternately charging the first charging and discharging circuit and the second charging and discharging circuit. And charging a road to generate a first oscillating signal or a second oscillating signal, wherein the first oscillating signal and the second oscillating signal are superimposed to obtain a third oscillating signal;
  • the active filter unit 230 is configured to integrate the reference voltage and the third oscillating signal to obtain a fourth signal
  • the voltage control unit 240 is configured to compare the fourth signal and the first oscillating signal to generate a fifth signal, or compare the fourth signal and the second oscillating signal to generate a sixth signal.
  • the symmetrical voltage-controlled relaxation oscillating unit 220 includes a first constant current source and a structurally symmetric charging and discharging circuit, and the first constant current source can alternately charge the charging circuit in the structurally symmetric charging and discharging circuit. And generating a first oscillating signal V1 and a second oscillating signal V2.
  • the first oscillating signal V1 and the second oscillating signal V2 are generated by the constant current source, and the first oscillating signal V1 and the second oscillating signal V2 are generated by charging by the voltage source and the voltage converting current unit according to the conventional solution.
  • the complexity of the RC oscillator structure is reduced.
  • the fifth signal and the sixth signal have high-precision timing functions, and can be applied to systems such as biological information detecting chips and low-power standard wireless transmission chips.
  • the symmetrical voltage-controlled relaxation oscillating unit 220 may be configured to form a first charging circuit through the first constant current source I1 and the capacitor C1, and form a first charging circuit through the first constant current source and the capacitor C2.
  • switch SW1 or SW2 may be a transistor or a switch tube, etc., which is not limited in this application.
  • the reference voltage generating unit in the embodiment of the present application may be the bandgap reference unit 130 in FIG. 1, or may be another unit capable of generating a reference voltage; the voltage control unit 240 may be respectively paired by two comparators.
  • the fourth signal is compared with the first oscillating signal V1, the fourth signal, and the second oscillating signal V2 to obtain a fifth signal and a sixth signal.
  • the fifth signal and the sixth signal are signals having opposite phases, which is not limited in this application.
  • the RC oscillator further includes an inverter, as shown in FIG. 3, for buffering the fifth signal or the sixth signal, so that the buffered signal has a higher driving capability.
  • the fifth signal or the sixth signal may also be outputted by means of a two-way frequency for buffering the fifth signal or the sixth signal, or may buffer the fifth signal or the sixth signal through other buffers.
  • the application does not limit this.
  • the reference voltage generating unit 210 in the embodiment of the present application may include a second constant current source. I2 and the first resistor R1. As shown in FIG. 3, the reference voltage generating unit 210 can be obtained by the I2 bias at R1. Since the zero temperature reference voltage provided by the bandgap reference unit is a non-ideal temperature coefficient in practice, the reference voltage provided by the bandgap reference unit will be The temperature error is caused by the embodiment of the present application, and the frequency accuracy of the RC oscillator output signal can be improved, and the reference voltage generating unit (such as the reference voltage generating unit 210 in FIG. 3) of the embodiment of the present application is compared. The bandgap reference cell reduces the power consumption and chip area of the RC oscillator.
  • the voltage control unit 240 in the embodiment of the present application may include a comparator CMP including a positive input terminal, a negative input terminal, and an output terminal.
  • the comparator CMP included in the voltage control unit 240 can be described as including a first positive input terminal, a first negative input terminal, and a first output terminal for alternately inputting the fourth signal and the second An oscillating signal, the first negative input terminal is for alternately inputting the fourth signal and the first oscillating signal, and at the same time, one of the first positive input terminal and the first negative input terminal is used for inputting the first a fourth signal, the first output is used to output the fifth signal or the sixth signal.
  • one of the first positive input terminal and the first negative input terminal is used to input the fourth signal at the same time, that is, the comparator can compare the fourth signal with the first oscillating signal.
  • the fifth signal may also compare the fourth signal and the second oscillating signal to obtain a sixth signal, and output the fifth signal or the sixth signal through the first output end.
  • the voltage control unit of the embodiment of the present application can only require one comparator, which saves the power consumption of the RC oscillator and the area of the chip.
  • the voltage control unit may be simply referred to as a "voltage control unit of a cross-input structure.”
  • the active filter unit 230 may be the active filter unit 130 of FIG. 1, and the active filter unit 230 includes an operational amplifier AMP, a second resistor R2, and a third capacitor C3, and AMP, R2, and C3 are formed.
  • An integrator Specifically, the second negative input terminal of the AMP is connected to one end of R2 and C3, the other end of R2 is connected to the output end of the output third signal, the other end of C3 is connected to the fifth output end of the AMP, and the second end of the AMP
  • the positive input is used to input the reference voltage, and the fifth output is used to output the fourth signal, so that the input is improved by the negative feedback structure of the operational amplifier AMP.
  • the noise characteristic of the outgoing signal that is, the frequency accuracy of the output signal is improved.
  • the reference voltage generated by the reference voltage generating unit 210 is less than a voltage threshold, and the voltage threshold is a maximum voltage value that the second constant current source can generate.
  • the comparators in the operational amplifier unit 230 and the comparators in the voltage control unit 240 do not require a rail-to-rail input configuration, thereby reducing the power consumption and chip area of the RC oscillator.
  • the RC oscillator may further include a logic control unit 250, and the logic control unit 250 may perform logic processing on the fifth signal or the sixth signal to generate the first control signal and the second control signal, the first control signal and the second
  • the control signal is a signal with an opposite phase, that is, when the first control signal is at a high level 1, the second control signal is at a low level of zero.
  • the first control signal and the second control signal may be used to control the startup or shutdown of the RC oscillator, or the activation or deactivation of a certain unit in the RC oscillator, which is not limited in this embodiment of the present application.
  • the structurally symmetric charging and discharging circuit may specifically include a first charging circuit, a first discharging circuit, a second charging circuit, a second discharging circuit, a second output end, and a third output end.
  • the first charging circuit is composed of a first switching transistor M1 and a first capacitor C1.
  • the first discharging circuit is composed of C1 and a third switching transistor M3, and the drain of M3 is connected to one end of C1.
  • the second charging circuit is composed of a second switching tube M2 and a second capacitor C2.
  • the second discharging circuit is composed of C2 and a fourth switching tube M4, and the drain of M4 is connected to one end of C2.
  • the switching states of the second switching transistor and the third switching transistor may be controlled by a first control signal, and the switching states of the first switching transistor and the fourth switching transistor may pass the second control signal.
  • M1 and M3 may be controlled by the same control signal, for example, the first control signal.
  • M1 and M3 may be respectively set to be P-type or N-type, so that when the first control signal is When the level is high 1, M1 turns off and M3 turns on.
  • M2 and M4 can also be set to be similar to M1 and M3. To avoid repetition, details are not described herein.
  • symmetric voltage controlled relaxation oscillation unit 220 includes a structurally symmetric charge and discharge circuit, M1 and M2, M3 and M4, and C1 and C2 should be the same device, respectively.
  • a first switch and a second switch may be sequentially disposed between the second output end and the third output end, and the switch state of the first switch is controlled by the first control signal, and the second switch The switching state is controlled by a second control signal.
  • the symmetrical voltage-controlled relaxation oscillating unit 220 can also be provided with a fourth output terminal, the fourth output terminal can be disposed between the first switch and the second switch, and the fourth output terminal is configured to output the oscillating signal Vosc obtained by superimposing V1 and V2.
  • the voltage control unit 240 may further include a third switch, a fourth switch, and a fifth switch.
  • a sixth switch specifically, a third switch is disposed between the fourth signal output end and the first positive input end, and the fourth switch is disposed at the second oscillating signal output end and the first positive input end
  • the fifth switch is disposed between the first oscillating signal output end and the first negative input end
  • the sixth switch is disposed between the fourth signal output end and the first negative input end.
  • the switching states of the third switch and the fifth switch are controlled by the first control signal
  • the switching states of the fourth switch and the sixth switch are controlled by the second control signal, so that the fourth signal and the first oscillating signal can be compared.
  • a fifth signal is generated, and the fourth signal and the second oscillating signal are compared to generate a sixth signal. That is to say, the voltage control unit 240 alternately inputs different signals of the comparators through the switching states of the different switches, so that the connected state of the voltage control unit 240 can be uniformly controlled by the logic control unit, thereby saving time delay.
  • the logic control unit 250 may be specifically configured as shown in FIG. 3, where the logic control unit includes a first inverter, a second inverter, a third inverter, a first NAND gate, and a second AND a first inverter comprising a third input terminal and a sixth output terminal, the first NAND gate including the third input terminal, the fourth input terminal and the seventh output terminal a fifth input terminal, a sixth input end, and an eighth output end, the second inverter includes a seventh input end and a ninth output end, the third inverter includes an eighth input end and a tenth output end, the first a fourth input end is connected to the eighth output end, the fifth input end is connected to the seventh output end, the sixth output end is connected to the sixth input end, and the seventh output end is connected to the seventh input end, The eighth output end is connected to the eighth input end, the third input end is configured to input the fifth signal or the sixth signal, and the ninth output end is configured to output the first control signal, the tenth output end For outputting
  • I2 continues to charge C3.
  • the relaxation oscillation circuit operates while the left relaxation oscillation circuit is in a reset state;
  • FIG. 4 is a schematic diagram showing waveforms of signals transmitted between different units in the RC oscillator of the embodiment of the present application.
  • the first constant current source alternately charges the structurally symmetric charging and discharging circuit to generate oscillating signals V1 and V2, and superimposes V1 and V2 through switches SW1 and SW2 to obtain a continuous sawtooth oscillating signal Vosc, and then Vosc is sent to the active filter to integrate with the reference voltage VREF to obtain an oscillating voltage control signal Vc of the symmetric voltage controlled relaxation oscillator circuit, thereby forming a negative feedback control loop.
  • the active filter Based on the voltage average feedback control mechanism, the active filter always wants to maintain the oscillating voltage control signal Vc at a fixed DC voltage value to maintain the stability of the output frequency, that is, the output frequency has good voltage, temperature and noise characteristics.
  • the oscillating signals V1 and V2 can be expressed as:
  • the voltage average feedback loop always maintains the equivalent DC value of the sawtooth oscillating signal Vosc equal to the reference voltage VREF, ie:
  • T is the oscillation period of the output oscillating signal, and according to known conditions:
  • the output frequency of the voltage-average feedback RC oscillator of the present application is determined only by the RC and the current ratio coefficient a, that is, the output frequency is a linear function of RC.
  • the oscillator noise of the present invention can be divided into two parts according to a voltage average feedback loop:
  • the first part is the noise equivalent of the reference voltage generating unit and the active filter on the oscillating voltage control signal Vc, which is called voltage average feedback noise;
  • the second part is the symmetric voltage controlled relaxation oscillating unit and its voltage control unit (including The phase noise of the oscillating signal Vosc is referred to as the phase noise of the voltage controlled oscillating circuit.
  • the flicker noise and the hot dry noise of the comparator and the constant current source I2 are attenuated by the high-pass characteristic of the voltage average feedback loop, and the heat of the reference voltage generating unit and the active filter are simultaneously.
  • the noise is attenuated by the low-pass characteristic of the voltage-average feedback loop, so the noise of the oscillator of the present invention is mainly contributed by the flicker noise of the operational amplifier.
  • the flicker noise of the operational amplifier can be reduced by designing a sufficiently large transistor area, and the parasitic capacitance caused by the increased area does not affect the output frequency on the voltage average feedback loop. Therefore, the embodiment of the present application can make the RC oscillator Keep the power consumption low.
  • the operational amplifier in the active filter unit 330 may be a two-stage operational amplifier using Miller compensation.
  • the switch tubes M6, M8-M11 form a first-stage differential amplifier
  • M7 and M12 are second-stage common-source amplifiers
  • Cc is a Miller compensation capacitor for ensuring sufficient phase margin of the operational amplifier. degree.
  • M5 is the bias current input of the operational amplifier
  • the bias current I3 is input from the drain of M5.
  • the P-channel Metal Oxide Semiconductor (PMOS) PMOS input ensures that the op amp can operate at very low common-mode voltages.
  • the operational amplifier of the embodiment of the present application may also be other operational amplifiers that can operate at a low common mode voltage, which is not limited in this application.
  • the first resistor of the embodiment of the present application is a resistor whose temperature coefficient is less than a preset coefficient threshold.
  • the change of the output frequency and the power supply voltage is not The relationship, and the general oscillator is operated under the voltage provided by the linear regulator.
  • the linear regulator has good output voltage accuracy, so the change of the power supply voltage has less influence on the output frequency. It can be seen from equation (5) that the output frequency is determined only by the resistor R and the capacitor C. Therefore, the temperature coefficient of the output frequency is also determined by the temperature coefficient of the RC, and the metal in the complementary metal oxide semiconductor (CMOS) process.
  • CMOS complementary metal oxide semiconductor
  • the temperature coefficient of the Metal Insulator Metal (MIM) capacitor is very negligible, and the temperature coefficient of the first resistor can be determined by the negative temperature coefficient of the polycrystalline resistor and the positive temperature system.
  • the number of diffusion resistors is constructed, and by reasonably designing the ratio between them, the temperature coefficient can be made smaller than the preset coefficient threshold, and the preset coefficient threshold can be as close as possible to zero, which further improves the improvement of the first resistance.
  • the frequency accuracy of the output signal is very negligible, and the temperature coefficient of the first resistor can be determined by the negative temperature coefficient of the polycrystalline resistor and the positive temperature system.
  • the number of diffusion resistors is constructed, and by reasonably designing the ratio between them, the temperature coefficient can be made smaller than the preset coefficient threshold, and the preset coefficient threshold can be as close as possible to zero, which further improves the improvement of the first resistance.
  • the frequency accuracy of the output signal is very negligible, and the temperature coefficient of the first resistor can be determined by the negative temperature coefficient of the polycrystalline resistor and
  • one of the voltage control units 240 may specifically be composed of a two-stage amplifier, a Schmitt inverter, and an inverting buffer.
  • M13 to M20 constitute a two-stage amplifier
  • M14 to M18 are first-stage differential amplifiers
  • M19 and M20 are second-stage common-source amplifiers
  • M13 is a bias current of the comparator.
  • the bias current I4 is input from the drain of M13.
  • the PMOS input ensures that the comparator can operate at very low common-mode voltages.
  • INV1 is a Schmitt inverter that prevents noise from causing signal jitter and causes the comparator to flip.
  • the INV2 is a buffered inverter. Such a comparator further increases the frequency accuracy of the output signal of the RC oscillator.
  • comparator of the embodiment of the present application may also be other comparators that can operate under a low common mode voltage, which is not limited in this application.
  • the first constant current source and the second constant current source are provided by the same current source system.
  • the RC oscillator can uniformly supply current through the current source system shown in FIG.
  • N, J, and K are mirror ratios of M22-M21, M27-M26, and M22-M23 current mirrors, respectively, and M24-M25 are self-sourced common-gate transistors. Since the M27-M26 current mirror operates in the subthreshold region and the mirror ratio is greater than 1 (J>1), the gate-source voltage VGS of M27 and M26 will be different, that is, VGS27>VGS26. The M26 source produces a voltage equal to VGS27-VGS26.
  • M25 operates in the linear region and is equivalent to a resistor in electrical characteristics, while the drain of M25 is biased by the source voltage of M26 above, so the output current generated is equal to the voltage. Take the M25 equivalent resistance.
  • I1 and I2 tubes in FIG. 7 can replace the symbols of the current sources I1 and I2 in FIG. 3, and the I3 and I4 in FIG. 7 can be respectively connected to the M5 drain of FIG. 5 and FIG. M13 drain.
  • the size of the sequence numbers of the foregoing processes does not mean the order of execution sequence, and the order of execution of each process should be determined by its function and internal logic, and should not be applied to the embodiment of the present application.
  • the implementation process constitutes any limitation.
  • the disclosed systems, devices, and methods may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner for example, multiple units or components may be combined or may be Integrate into another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be in an electrical, mechanical or other form.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the above integrated unit can be implemented in the form of hardware or in the form of a software functional unit.
  • the integrated unit if implemented in the form of a software functional unit and sold or used as a standalone product, may be stored in a computer readable storage medium.
  • the technical solution of the present application which is essential or contributes to the prior art, or a part of the technical solution, may be embodied in the form of a software product, which is stored in a storage medium, including
  • the instructions are used to cause a computer device (which may be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present application.
  • the foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and the like, which can store program codes.

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Abstract

一种RC振荡器，包括：参考电压产生单元（210），用于生成参考电压；电压控制张弛振荡单元（220）包括第一恒流源和第一充放电回路和第二充放电回路，该第一恒流源用于交替对该第一充放电回路和该第二充放电回路进行充电分别生成第一振荡信号或第二振荡信号，该第一振荡信号和该第二振荡信号叠加得到第三振荡信号，其中，该第一充放电回路的结构与该第二充放电回路的结构对称；有源滤波器单元（230），用于对该参考电压和该第三振荡信号进行积分得到第四信号；电压控制单元（240），用于对该第四信号和该第一振荡信号进行比较生成第五信号，或对该第四信号和该第二振荡信号进行比较生成第六信号。

Description

电阻电容RC振荡器 技术领域
本申请涉及电子技术领域，并且更具体地，涉及一种电阻电容(RC)振荡器。
背景技术
在生物信息检测芯片、低功耗标准无线传输芯片等系统通常需要一个高精度的时钟来实现系统所需的高精度的计时功能。
传统RC振荡器的电路结构包括电压转电流单元、带隙基准单元、有源滤波器单元和对称的电压控制张弛振荡单元。其中，电压转电流单元用于为对称的电压控制张弛振荡单元输入电流；对称的电压控制张弛振荡单元通常是包括电压源的结构对称的两个充放电回路，并输出两路电压分别为V1和V2；带隙基准单元用于产生参考电压；有源滤波器单元通过V1与V2的叠加信号和参考电压作为正负输入和该有源滤波器单元的输出形成负反馈回路，从而输出频率精度较高的信号，但是该传统RC振荡器的电路结构的结构比较复杂。
发明内容
本申请实施例提供一种电阻电容RC振荡器，能够在保证输出信号的频率精度的基础上，降低RC振荡器的结构复杂度。
第一方面，提供了一种RC振荡器。该RC振荡器包括：参考电压产生单元210，电压控制张弛振荡单元220，有源滤波器单元230，电压控制单元240，该参考电压产生单元210，用于生成参考电压；该电压控制张弛振荡单元220包括第一恒流源和第一充放电回路和第二充放电回路，该第一恒流源用于交替对该第一充放电回路和该第二充放电进行充电分别生成第一振荡信号或第二振荡信号，该第一振荡信号和该第二振荡信号叠加得到第三振荡信号，其中，该第一充放电回路的结构与该第二充放电回路的结构对称；该有源滤波器单元230，用于对该参考电压和该第三振荡信号进行积分得到第四信号；该电压控制单元240，用于对该第四信号和该第一振荡信号进行比较生成第五信号，或对该第四信号和该第二振荡信号进行比较生成第六信 号。
该对称的电压控制张弛振荡单元220包括第一恒流源和结构对称的充放电回路，该第一恒流源可以交替地对结构对称的充放电回路中的充电回路进行充电，并生成第一振荡信号V1和第二振荡信号V2。本申请实施例通过恒流源生成V1和V2，相比传统方案中通过电压源和电压转电流单元生成进行充电生成V1和V2，降低了RC振荡器结构的复杂度。
在一些可能的实现方式中，该参考电压产生单元210包括：第二恒流源和第一电阻。
RC振荡器采用参考电压单元210生成参考电压能够避免采用带隙基准单元造成的温度误差，进而能够提高RC振荡器输出信号的频率精度，此外本申请实施例的参考电压产生单元相比带隙基准单元减小了RC振荡器的功耗和芯片面积。
在一些可能的实现方式中，该第一恒流源与该第二恒流源通过同一个电流源系统提供。
RC振荡器通过采用同一个电流源系统能够节省RC振荡器的面积，且输出电流是正温度系数，能够减少高温下运算放大器的性能退化。
在一些可能的实现方式中，该第一电阻为温度系数小于预设系数阈值的电阻。
第一电阻的温度系数可以由负温度系数的多晶电阻和正温度系数的扩散电阻构成，并通过合理的设计它们之间的比率可以使得温度系数小于预设系数阈值，该预设系数阈值可以尽可能的接近于零，这样通过对第一电阻的改进进一步提高了输出信号的频率精度。
例如，该第一电阻可以是片外高精度电阻。
在一些可能的实现方式中，该比较器由两级放大器、施密特反相器和反相缓冲器构成。
通过第一级差分放大器和第二级共源放大器，以及施密特反相器INV1和起缓冲作用的INV2反相器，进一步提高了RC振荡器的信号输出频率。
在一些可能的实现方式中，该电压控制单元240包括比较器，该比较器包括第一正输入端、第一负输入端和第一输出端，且该第一正输入端用于交替输入该第四信号和该第二振荡信号，该第一负输入端用于交替输入该第四信号和该第一振荡信号，且在同一时刻存在该第一正输入端和该第一负输入 端中的任一个用于输入该第四信号，该第一输出端用于输出该第五信号或该第六信号。
本申请实施例的电压控制单元通过将对称的电压控制张弛振荡单元的输出信号交替地输入到比较器，可以仅需要一个比较器，节省了RC振荡器的功耗以及芯片的面积。
在一些可能的实现方式中，该RC振荡器还包括：逻辑控制单元250，用于对该第五信号或该第六信号进行逻辑处理生成第一控制信号和第二控制信号，该第一控制信号和该第二控制信号为相位相反的信号，且该第一控制信号和该第二控制信号用于控制该第一恒流源交替对该结构对称的充放电回路进行充电。
通过逻辑控制单元自动控制第一恒流源交替对架构对称的充放电回路进行充电，避免设置专门的交替控制设备，节省RC振荡器的功耗。
在一些可能的实现方式中，该电压控制张弛振荡单元还包括第二输出端和第三输出端，该第一充放电回路包括第一充电回路和第一放电回路，该第二充放电回路包括第二充电回路和第二放电回路，该第一充电回路由第一开关管和第一电容组成，该第一放电回路由该第一电容和第三开关管组成，该第二充电回路由第二开关管和第二电容组成，该第二放电回路由该第二电容和第四开关管组成，该第三开关管和该第二开关管的开关状态通过该第一控制信号控制，该第一开关管和该第四开关管的开关状态通过该第二控制信号控制，该第二输出端用于输出该第一振荡信号，该第三输出端用于输出该第二振荡信号。
通过设置多个开关管，并通过相位相反的控制信号控制多个开关管的开关状态，避免设置专门的开关管控制设备，节省RC振荡器的功耗。
在一些可能的实现方式中，该第二输出端和该第三输出端之间依次设置有第一开关和第二开关，该第一开关的开关状态通过该第一控制信号控制，该第二开关的开关状态通过该第二控制信号控制；该对称的电压控制张弛振荡单元220还包括第四输出端，该第四输出端设置于该第一开关和该第二开关之间，且该第四输出端用于输出该第三振荡信号。
通过设置开关，并通过相位相反的控制信号控制开关的开关状态，避免设置专门的开关控制设备，节省RC振荡器的功耗。
在一些可能的实现方式中，该有源滤波器单元230包括运算放大器、第 二电阻和第三电容，该运算放大器包括第二正输入端、第二负输入端和第五输出端，该第二负输入端分别与该第二电阻的一端以及该第三电容的一端连接，该第二电阻的另一端与该第三振荡信号的输出端连接，该第三电容的另一端与该第五输出端连接，该第二正输入端用于输入该参考电压，该第五输出端用于输出该第四信号。
通过电压平均反馈环路的控制机制，维持第四信号在一个固定直流电压值，提高了输出信号的频率的稳定性，此外，该电压平均反馈环路还可以消除比较器的迟滞时间，进一步提高输出信号的频率精度。
在一些可能的实现方式中，该电压控制单元240还包括第三开关、第四开关、第五开关和第六开关，该第三开关设置于该第五输出端和该第一正输入端之间，该第四开关设置于该第三输出端和该第一正输入端之间，该第五开关设置于该第二输出端和该第一负输入端之间，该第六开关设置于该第五输出端与该第一负输入端之间，且该第三开关和该第五开关的开关状态通过该第一控制信号控制，该第四开关和该第六开关的开关状态通过该第二控制信号控制。
通过设置多个开关，并通过相位相反的控制信号控制该多个开关的开关状态，避免了设置两个比较器，减少了比较器的设置个数，从而节省了RC振荡器的功耗和芯片面积。
在一些可能的实现方式中，该运算放大器为采用密勒补偿的两级运算放大器。
该运算放大器中的晶体管面积可以设计的比较大以提高运算放大器的噪声性能，从而提高了输出信号的频率精度。
在一些可能的实现方式中，该逻辑控制单元包括第一反相器、第二反相器、第三反相器、第一与非门和第二与非门，该第一反相器包括第三输入端和第六输出端，该第一与非门包括该第三输入端、第四输入端和第七输出端，该第二与非门包括第五输入端、第六输入端和第八输出端，该第二反相器包括第七输入端和第九输出端，该第三反相器包括第八输入端和第十输出端，该第四输入端与该第八输出端连接，该第五输入端与该第七输出端连接，该第六输出端与该第六输入端连接，该第七输出端与该第七输入端连接，该第八输出端与该第八输入端连接，该第三输入端用于输入该第五信号或该第六信号，该第九输出端用于输出该第一控制信号，该第十输出端用于输出该第 二控制信号。
通过逻辑控制单元自动控制第一恒流源交替对架构对称的充放电回路进行充电，避免设置专门的交替控制设备，节省RC振荡器的功耗。
在一些可能的实现方式中，该第五信号和该第六信号的相位相反。
在一些可能的实现方式中，该电压控制单元将该第五信号和该第六信号输出为时钟信号。
第二方面，本申请提供了一种信号处理的方法，该方法由上述第一方面或上述第一方面任一种可能的实现方式所述的RC振荡器的单元执行。
第三方面，提供了一种计时芯片，该计时芯片包括第一方面或第一方面任一种可能的实现方式所述RC振荡器和存储器，所述存储器存储程序，所述RC振荡器用作执行存储器中程序的系统时钟。
基于上述技术方案，该参考电压产生单元生成参考电压，该对称的电压控制张弛振荡单元通过该第一恒流源用于交替对该结构对称的充放电回路进行充电生成第一振荡信号或第二振荡信号，有源滤波器单元对参考电压和叠加该第一振荡信号和该第二振荡信号得到的第三振荡信号进行积分得到第四信号，电压控制单元对该第四信号和该第一振荡信号进行比较生成第五信号或对该第四信号和该第二振荡信号进行比较生成第六信号，这样通过第一恒流源生成V1和V2，相比传统方案中通过电压源和电压转电流单元生成进行充电生成V1和V2，降低了RC振荡器结构的复杂度。
附图说明
图1是传统的RC振荡器的电路结构的示意图；
图2是本申请的RC振荡器中信号传输的示意图；
图3是本申请RC振荡器的结构示意图；
图4是本申请实施例的RC振荡器中的信号在不同单元间传输的波形示意图；
图5是本申请实施例的运算放大器的结构示意图；
图6是本申请实施例的比较器的结构示意图；
图7是本申请实施例的电流源的结构示意图。
具体实施方式
图1示出了传统RC振荡器的电路结构的示意图，如图1所示，该传统RC振荡器的电路结构由电压转电流单元110、带隙基准单元120、有源滤波器单元130和对称的电压控制张弛振荡单元140组成。电压转电流单元110通过放大器控制的反馈环路使得输入的电压被线性的转化为电流，将该电流输入到对称的电压控制张弛振荡单元140中，由该对称的电压控制张弛振荡单元140输出第一信号V1和第二信号V2，以及输出叠加V1和V2得到的连续的振荡信号Vosc；带隙基准单元120产生零温度参考电压VREF1；有源滤波器单元130通过形成反馈回路的轨到轨输入运算放大器(Rail to RaiInput Amplifier amplifier，RtR Input AMP)将Vosc和VREF1进行积分生成Vc；Vc和V1输入到第一比较器(Rail to Rai Input comparator，RtR InputCMP1)得到第一CLK信号，Vc和V2输入到第二比较器RtR Input CMP2得到第二时钟(clock，CLK)信号，该第一CLK信号和该第二CLK信号为相位相反的信号。其中，所述运算放大器RtR Input AMP、第一比较器RtRInput CMP1和第二比较器RtR Input CMP2为轨到轨输入型。
轨到轨输入，是指运算放大器或比较器的共模输入范围是电源轨(如，VSS or GND)到电源轨(如，VDD)之间的范围。
该传统RC振荡器的电路结构通过有源滤波器单元130的电压平均反馈技术特有的负反馈调节特性使得振荡器的输出信号的频率精度提高。但是该传统电路结构中对称的电压控制张弛振荡单元140需要通过电压源以及由电压转电流单元110输出的电流生成第一信号V1和第二信号V2，由此可见该传统RC振荡器的电路结构比较复杂。
需要说明的是，通常情况下RC振荡器输出信号的频率精度的影响因素主要包括温度、电流源的闪烁噪声以及延时等。
图2示出了本申请实施例的一种RC振荡器的结构示意图。如图2所示，该RC振荡器包括参考电压产生单元210、电压控制张弛振荡单元220、有源滤波器单元230和电压控制单元240。该参考电压产生单元210用于生成参考电压；
该电压控制张弛振荡单元220包括第一恒流源和结构对称的充放电回路，即，该电压控制张弛振荡单元220具有对称的电路结构或者说它是对称的电压控制张弛振荡单元，该对称的电路结构分别可以是第一充放电回路和第二充放电回路，该第一恒流源用于交替对第一充放电回路和第二充放电回 路进行充电分别生成第一振荡信号或第二振荡信号，该第一振荡信号和该第二振荡信号进行叠加可以得到的第三振荡信号；
该有源滤波器单元230，用于对该参考电压和第三振荡信号进行积分得到第四信号；
该电压控制单元240，用于对该第四信号和该第一振荡信号进行比较生成第五信号，或对该第四信号和该第二振荡信号进行比较生成第六信号。
具体而言，该对称的电压控制张弛振荡单元220包括第一恒流源和结构对称的充放电回路，该第一恒流源可以交替地对结构对称的充放电回路中的充电回路进行充电，并生成第一振荡信号V1和第二振荡信号V2。本申请实施例通过恒流源生成第一振荡信号V1和第二振荡信号V2，相比传统方案中通过电压源和电压转电流单元生成进行充电生成第一振荡信号V1和第二振荡信号V2，降低了RC振荡器结构的复杂度。
其中，第五信号和第六信号具有高精度的计时功能，可以应用于生物信息检测芯片、低功耗标准无线传输芯片等系统。
例如，如图2所示，该对称的电压控制张弛振荡单元220可以是通过第一恒流源I1和电容C1构成第一充电回路，通过第一恒流源和电容C2构成与第一充电回路对称的第二充电回路；开关SW1闭合构成电容C1的放电回路，开关SW2闭合构成电容C2的放电回路。
应理解，开关SW1或SW2可以是晶体管或开关管等，本申请对此不进行限定。
还应理解，本申请实施例的参考电压产生单元可以是图1中的带隙基准单元130，也可以是其他能够产生参考电压的单元；该电压控制单元240可以通过两个比较器分别对第四信号和第一振荡信号V1、第四信号和第二振荡信号V2进行比较得到第五信号和第六信号，第五信号和第六信号为相位相反的信号，本申请对此不进行限定。
可选地，所述RC振荡器还包括一个反相器，如图3所示，该反相器用于缓冲第五信号或第六信号，使得缓冲后的信号的驱动能力更高。
应理解，第五信号或第六信号也可以通过二分频的方式输出，用于缓冲所述第五信号或第六信号，或者也可以通过其他缓冲器缓冲第五信号或第六信号，本申请对此不进行限定。
可选地，本申请实施例中的参考电压产生单元210可以包括第二恒流源 I2和第一电阻R1。如图3所示，参考电压产生单元210可以通过I2偏置在R1得到，由于带隙基准单元提供的零温度参考电压在实际中是非理想的温度系数，因此带隙基准单元提供的参考电压会造成温度误差，本申请实施例能够避免该温度误差，进而能够提高RC振荡器输出信号的频率精度，此外本申请实施例的参考电压产生单元(如图3中的参考电压产生单元210)相比带隙基准单元减小了RC振荡器的功耗和芯片面积。
可选地，本申请实施例中的电压控制单元240可以包括一个比较器CMP，该比较器CMP包括正输入端、负输入端和输出端，为了与振荡器中其他单元的比较器相区分，电压控制单元240所包括的比较器CMP可以被描述为包括第一正输入端、第一负输入端和第一输出端，该第一正输入端用于交替输入该第四信号和该第二振荡信号，该第一负输入端用于交替输入该第四信号和该第一振荡信号，且在同一时刻存在该第一正输入端和该第一负输入端中的一个用于输入该第四信号，该第一输出端用于输出该第五信号或该第六信号。
具体而言，在同一时刻存在该第一正输入端和该第一负输入端中的一个用于输入该第四信号，即为该比较器可以对第四信号和第一振荡信号进行比较得到第五信号，也可以对第四信号和第二振荡信号进行比较得到第六信号，并通过第一输出端输出该第五信号或第六信号。这样本申请实施例的电压控制单元可以仅需要一个比较器，节省了RC振荡器的功耗以及芯片的面积。
需要说明的是，这里的在同一时刻存在该第一正输入端和该第一负输入端中的一个用于输入该第四信号是指在RC振荡器处理工作状态时，在RC振荡器处于关闭状态时，第一正输入端和第一负输入端可以都没有信号输入。
应理解，该电压控制单元可以简称为“交叉输入结构的电压控制单元”。
可选地，有源滤波器单元230可以是图1中的有源滤波器单元130，有源滤波器单元230包括运算放大器AMP、第二电阻R2和第三电容C3，AMP、R2和C3形成一个积分器。具体地，AMP的第二负输入端分别与R2和C3的一端连接，R2的另一端与输出第三信号的输出端连接，C3的另一端与AMP的第五输出端连接，AMP的第二正输入端用于输入参考电压，第五输出端用于输出第四信号，这样通过运算放大器AMP的负反馈结构提高了输 出信号的噪声特性，即提高了输出信号的频率精度。
可选地，参考电压产生单元210生成的参考电压小于电压阈值，该电压阈值为该第二恒流源能够生成的最大电压值。这样，有源滤波器单元230中的运算放大器AMP和电压控制单元240中的比较器就不需要设置轨到轨输入的结构，从而减少了RC振荡器的功耗和芯片面积。
可选地，RC振荡器还可以包括逻辑控制单元250，该逻辑控制单元250可以对第五信号或第六信号进行逻辑处理生成第一控制信号和第二控制信号，第一控制信号和第二控制信号为相位相反的信号，即第一控制信号为高电平1时，第二控制信号为低电平0。第一控制信号和第二控制信号可以用于控制RC振荡器的启动或关闭，或者RC振荡器中的某个单元的启动或关闭等，本申请实施例对此不进行限定。
可选地，如图3所示，结构对称的充放电回路具体可以是包括第一充电回路、第一放电回路、第二充电回路、第二放电回路、第二输出端和第三输出端。第一充电回路由第一开关管M1和第一电容C1组成，第一放电回路由C1和第三开关管M3组成，M3的漏极与C1的一端连接。第二充电回路由第二开关管M2和第二电容C2组成，第二放电回路由C2和第四开关管M4组成，M4的漏极与C2的一端连接。第二开关管和第三开关管的开关状态可以通过第一控制信号控制，第一开关管和第四开关管的开关状态可以通过第二控制信号。
需要说明的是，M1和M3的开关状态可以是通过相同的控制信号控制，例如，第一控制信号，这时可以将M1和M3设置分别为P型或N型，这样当第一控制信号为高电平1时，M1关断，M3导通。同样地，M2和M4也可以设置为与M1和M3类似，为避免重复，在此不再赘述。
应理解，由于所述对称的电压控制张弛振荡单元220包括结构对称的充放电回路，因此，M1和M2、M3和M4以及C1和C2应分别为相同的器件。
可选地，如图3所示，第二输出端和第三输出端之间可以依次设置有第一开关和第二开关，该第一开关的开关状态通过第一控制信号控制，第二开关的开关状态通过第二控制信号控制。对称的电压控制张弛振荡单元220还可以设置第四输出端，第四输出端可以设置于第一开关和第二开关之间，第四输出端用于输出叠加V1和V2得到的振荡信号Vosc。
可选地，电压控制单元240还可以包括第三开关、第四开关、第五开关 和第六开关，具体地，第三开关设置于第四信号输出端和所述第一正输入端之间，所述第四开关设置于第二振荡信号输出端和所述第一正输入端之间，所述第五开关设置于第一振荡信号输出端和所述第一负输入端之间，所述第六开关设置于第四信号输出端与所述第一负输入端之间。其中，第三开关和第五开关的开关状态通过第一控制信号控制，第四开关和第六开关的开关状态通过第二控制信号控制，从而能够实现对第四信号和第一振荡信号进行比较生成第五信号，对第四信号和第二振荡信号进行比较生成第六信号。也就是说，电压控制单元240通过不同开关的开关状态实现交替输入比较器不同的信号，这样可以通过逻辑控制单元统一控制电压控制单元240的连通状态，节省时延。
可选地，逻辑控制单元250具体结构可以如图3所示，该逻辑控制单元包括第一反相器、第二反相器、第三反相器、第一与非门和第二与非门，该第一反相器包括第三输入端和第六输出端，该第一与非门包括该第三输入端、第四输入端和第七输出端，该第二与非门包括第五输入端、第六输入端和第八输出端，该第二反相器包括第七输入端和第九输出端，该第三反相器包括第八输入端和第十输出端，该第四输入端与该第八输出端连接，该第五输入端与该第七输出端连接，该第六输出端与该第六输入端连接，该第七输出端与该第七输入端连接，该第八输出端与该第八输入端连接，该第三输入端用于输入该第五信号或该第六信号，该第九输出端用于输出该第一控制信号，该第十输出端用于输出该第二控制信号。
下面以图3为例说明本申请实施例的RC振荡器的工作原理。
(1)假设初始时刻
Figure PCTCN2017077344-appb-000001
(
Figure PCTCN2017077344-appb-000002
下同)且Vc有一定的初始电压值，M1导通、M2关断，M3关断、M4导通，SW1闭合、SW2断开，恒流源I2给C3充电，V1电压呈线性上升，V2被导通的M2拉至地电位，即左边的张弛振荡电路工作而右边的张弛振荡电路处于复位状态；
(2)与此同时，SW3、SW5闭合，SW4、SW6断开，比较器正相输入端VP等于振荡电压控制信号Vc，负相输入端VN等于振荡信号V1。当V1小于Vc时，比较器的输出Vo＝1，则
Figure PCTCN2017077344-appb-000003
I2继续给C3充电；
(3)I2继续给C3充电，当V1大于Vc时，比较器的输出Vo＝0，则
Figure PCTCN2017077344-appb-000004
Figure PCTCN2017077344-appb-000005
M1关断、M2导通，M3导通、M4导通，SW1断开、SW2闭合，恒流源I2给C4充电，V2电压呈线性上升，V1被导通的M3拉至地电位，即 右边的张弛振荡电路工作而左边的张弛振荡电路处于复位状态；
(4)此时，SW3、SW5断开，SW4、SW6闭合，比较器正相输入端VP等于振荡信号V2而负相输入端VN等于振荡电压控制信号Vc。当V2小于Vc时，比较器的输出Vo＝0，则
Figure PCTCN2017077344-appb-000006
I2继续给C4充电；
(5)I2继续给C4充电，当V2大于Vc时，比较器的输出Vo＝1，则
Figure PCTCN2017077344-appb-000007
Figure PCTCN2017077344-appb-000008
则回到上述的步骤1，即左边的张弛振荡电路工作而右边的张弛振荡电路处于复位状态，重复上述步骤(1)～(5)即可在比较器的输出端得到一定周期的振荡信号。
图4示出了本申请实施例的RC振荡器中的信号在不同单元间传输的波形示意图。如图4所示，第一恒流源交替对结构对称的充放电回路进行充电生成振荡信号V1和V2，并通过开关SW1和SW2将V1和V2叠加在一起得到连续的锯齿振荡信号Vosc，然后Vosc送至有源滤波器与参考电压VREF做积分得到对称的电压控制张弛振荡电路的振荡电压控制信号Vc，从而形成一个负反馈控制环路。基于电压平均反馈的控制机制，有源滤波器总是想维持振荡电压控制信号Vc在一个固定直流电压值从而维持输出频率的稳定性，即输出频率有很好的电压、温度及噪声特性。
因此，忽略开关、运算放大器及比较器的非理想特性，并假设C3＝C4＝C，则振荡信号V1及V2可以表示为：
Figure PCTCN2017077344-appb-000009
如前文所述，电压平均反馈环路总是维持锯齿振荡信号Vosc的等效直流值等于参考电压VREF，即：
Figure PCTCN2017077344-appb-000010
式中T为输出振荡信号的振荡周期，且根据已知条件：
VREF＝I2×R  (3)
I2＝I1×a,a>0  (4)
将式(1)、(3)、(4)代入式(2)可得：
T＝4a×R×C  (5)
由式(5)可知，本申请的电压平均反馈RC振荡器的输出频率仅由RC及电流比率系数a决定，即输出频率是RC的线性函数。
具体而言，本发明的振荡器噪声可以按电压平均反馈环路分为两部分： 第一部分是参考电压产生单元及有源滤波器在振荡电压控制信号Vc上等效的噪声，称之为电压平均反馈噪声；第二部分是对称的电压控制张弛振荡单元及其电压控制单元(包括逻辑处理单元)对振荡信号Vosc的相位噪声，称之为电压控制振荡电路的相位噪声。
根据上述的电压平均反馈控制环路的特性，比较器及恒流源I2的闪烁噪声及热燥声被电压平均反馈环路的高通特性给衰减，同时参考电压产生单元和有源滤波器的热燥声会被电压平均反馈环路的低通特性给衰减，因此本发明的振荡器的噪声主要由运算放大器的闪烁噪声贡献。而运算放大器的闪烁噪声可以通过设计足够大的晶体管面积来减小，且增大面积带来的寄生电容在电压平均反馈环路上是不影响输出频率的，因此本申请实施例可以使得RC振荡器保持比较低的功耗。
可选地，有源滤波器单元330中的运算放大器可以为采用密勒补偿的两级运算放大器。如图5所示，其中，开关管M6、M8～M11组成第一级差分放大器，M7与M12是第二级共源放大器，Cc是密勒补偿电容，用于保证运算放大器具有足够的相位裕度。M5是运算放大器的偏置电流接入管，偏置电流I3从M5的漏极输入。P型金属氧化物半导体场效应管(P ChannelMetal Oxide Semiconductor，PMOS)PMOS输入保证运算放大器可以在很低的共模电压下工作。
应理解，本申请实施例的运算放大器还可以是其他可以在低共模电压下工作的运算放大器，本申请对此不进行限定。
可选地，本申请实施例的该第一电阻为温度系数小于预设系数阈值的电阻。
具体而言，对于工艺的偏差，根据式(5)，我们可以通过校正R或者C来消除工艺偏差对输出频率的影响，由本发明的振荡器电路结构可知，输出频率与电源电压的变化是没有关系的，而且一般振荡器是在线性稳压器提供电压下工作的，线性稳压器由良好的输出电压精度，因此电源电压的变化对输出频率的影响比较小。由式(5)可知输出频率仅由电阻R与电容C决定，因此输出频率的温度系数也是由RC的温度系数共同决定的，在互补金属氧化物半导体(Complementary Metal Oxide Semiconductor，CMOS)工艺中金属绝缘体金属(Metal Insulator Metal，MIM)电容的温度系数很小几乎可以忽略不计，而第一电阻的温度系数可以由负温度系数的多晶电阻和正温度系 数的扩散电阻构成，并通过合理的设计它们之间的比率可以使得温度系数小于预设系数阈值，该预设系数阈值可以尽可能的接近于零，这样通过对第一电阻的改进进一步提高了输出信号的频率精度。
可选地，电压控制单元240中的一个比较器具体可以是由两级放大器、施密特反相器和反相缓冲器构成。
具体而言，如图6所示，M13～M20构成了两级放大器，M14～M18是第一级差分放大器，M19与M20是第二级共源放大器，M13是比较器的偏置电流接入管，偏置电流I4从M13的漏极输入。PMOS输入保证比较器可以在很低的共模电压下工作，INV1是施密特反相器，可以防止噪声带来信号抖动引起比较状态误翻转，INV2是起缓冲作用的反相器。这样的比较器进一步提高了RC振荡器的输出信号的频率精度。
应理解，本申请实施例的比较器还可以是其他可以在低共模电压下工作的比较器，本申请对此不进行限定。
可选地，该第一恒流源与该第二恒流源通过同一个电流源系统提供。
具体而言，该RC振荡器可以通过图7所示的电流源系统统一提供电流。如图7所示，N、J、K分别是M22-M21、M27-M26、M22-M23电流镜的镜像比率，M24-M25是自共源共栅晶体管。由于M27-M26电流镜工作在亚阈值区且镜像比率大于1(J>1)，因此M27、M26的栅-源电压VGS将不同，即VGS27>VGS26。M26源极产生一个电压，该电压等于VGS27-VGS26。M24-M25自共源共栅晶体管中，M25工作在线性区，电气特性上等效成一个电阻，而M25的漏极由上述M26的源极电压偏置，因此产生的输出电流等于该电压除以M25等效电阻。通过采用此结构产生电流源能够节省面积，且输出电流是正温度系数，能够减少高温下运算放大器的性能退化。
需要说明的是，图7中的I1、I2管子可以代替图3中的电流源I1、I2的符号，而图7中的I3、I4则可以分别接在图5的M5漏极和图6的M13漏极。
应理解，在本申请的各种实施例中，上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本申请实施例的实施过程构成任何限定。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结 合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，该单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
所述集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(ROM，Read-OnlyMemory)、随机存取存储器(RAM，Random Access Memory)、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限 于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以该权利要求的保护范围为准。

Claims (15)

  1. 一种电阻电容RC振荡器，其特征在于，包括：参考电压产生单元，电压控制张弛振荡单元，有源滤波器单元和电压控制单元，其中：
    所述参考电压产生单元用于生成参考电压；
    所述电压控制张弛振荡单元包括第一恒流源和第一充放电回路和第二充放电回路，所述第一恒流源用于交替对所述第一充放电回路和所述第二充放电进行充电分别生成第一振荡信号和第二振荡信号，所述第一振荡信号和所述第二振荡信号叠加得到第三振荡信号，其中，所述第一充放电回路的结构与所述第二充放电回路的结构对称；
    所述有源滤波器单元，用于对所述参考电压和所述第三振荡信号进行积分得到第四信号；
    所述电压控制单元，用于对所述第四信号和所述第一振荡信号进行比较生成第五信号，或对所述第四信号和所述第二振荡信号进行比较生成第六信号。
  2. 根据权利要求1所述的RC振荡器，其特征在于，所述参考电压产生单元包括：第二恒流源和第一电阻，所述第二恒流源与所述第一电阻连接用于生成所述参考电压。
  3. 根据权利要求2所述的RC振荡器，其特征在于，所述第一恒流源与所述第二恒流源通过电流源系统提供。
  4. 根据权利要求2所述的RC振荡器，其特征在于，所述第一电阻为温度系数小于预设系数阈值的电阻。
  5. 根据权利要求1至4中任一项所述的RC振荡器，其特征在于，所述电压控制单元包括比较器，所述比较器包括第一正输入端、第一负输入端和第一输出端，且所述第一正输入端用于交替输入所述第四信号和所述第二振荡信号，所述第一负输入端用于交替输入所述第四信号和所述第一振荡信号，且在同一时刻存在所述第一正输入端和所述第一负输入端中的任一个用于输入所述第四信号，所述第一输出端用于输出所述第五信号或所述第六信号。
  6. 根据权利要求5所述的RC振荡器，其特征在于，所述比较器包括两级放大器、施密特反相器和反相缓冲器。
  7. 根据权利要求1至6中任一项所述的RC振荡器，其特征在于，所 述RC振荡器还包括：
    逻辑控制单元，用于对所述第五信号或所述第六信号进行逻辑处理生成第一控制信号和第二控制信号，所述第一控制信号和所述第二控制信号为相位相反的信号，且所述第一控制信号和所述第二控制信号用于控制所述第一恒流源交替对所述结构对称的充放电回路进行充电。
  8. 根据权利要求7所述的RC振荡器，其特征在于，所述电压控制张弛振荡单元还包括第二输出端和第三输出端，所述第一充放电回路包括第一充电回路和第一放电回路，所述第二充放电回路包括第二充电回路和第二放电回路，所述第一充电回路由第一开关管和第一电容组成，所述第一放电回路由所述第一电容和第三开关管组成，所述第二充电回路由第二开关管和第二电容组成，所述第二放电回路由所述第二电容和第四开关管组成，所述第三开关管和所述第二开关管的开关状态通过所述第一控制信号控制，所述第一开关管和所述第四开关管的开关状态通过所述第二控制信号控制，所述第二输出端用于输出所述第一振荡信号，所述第三输出端用于输出所述第二振荡信号。
  9. 根据权利要求8所述的RC振荡器，其特征在于，所述第二输出端和所述第三输出端之间依次设置有第一开关和第二开关，所述第一开关的开关状态通过所述第一控制信号控制，所述第二开关的开关状态通过所述第二控制信号控制；
    所述对称的电压控制张弛振荡单元还包括第四输出端，所述第四输出端设置于所述第一开关和所述第二开关之间，且所述第四输出端用于输出所述第三振荡信号。
  10. 根据权利要求7至9中任一项所述的RC振荡器，其特征在于，所述有源滤波器单元包括运算放大器、第二电阻和第三电容，所述运算放大器包括第二正输入端、第二负输入端和第五输出端，所述第二负输入端分别与所述第二电阻的一端以及所述第三电容的一端连接，所述第二电阻的另一端与所述第三振荡信号的输出端连接，所述第三电容的另一端与所述第五输出端连接，所述第二正输入端用于输入所述参考电压，所述第五输出端用于输出所述第四信号。
  11. 根据权利要求10所述的RC振荡器，其特征在于，所述电压控制单元还包括第三开关、第四开关、第五开关和第六开关，所述第三开关设置于 所述第五输出端和所述第一正输入端之间，所述第四开关设置于所述第三输出端和所述第一正输入端之间，所述第五开关设置于所述第二输出端和所述第一负输入端之间，所述第六开关设置于所述第五输出端与所述第一负输入端之间，且所述第三开关和所述第五开关的开关状态通过所述第一控制信号控制，所述第四开关和所述第六开关的开关状态通过所述第二控制信号控制。
  12. 根据权利要求10或11所述的RC振荡器，其特征在于，所述运算放大器为采用密勒补偿的两级运算放大器。
  13. 根据权利要求7至12中任一项所述的RC振荡器，其特征在于，所述逻辑控制单元包括第一反相器、第二反相器、第三反相器、第一与非门和第二与非门，所述第一反相器包括第三输入端和第六输出端，所述第一与非门包括所述第三输入端、第四输入端和第七输出端，所述第二与非门包括第五输入端、第六输入端和第八输出端，所述第二反相器包括第七输入端和第九输出端，所述第三反相器包括第八输入端和第十输出端，所述第四输入端与所述第八输出端连接，所述第五输入端与所述第七输出端连接，所述第六输出端与所述第六输入端连接，所述第七输出端与所述第七输入端连接，所述第八输出端与所述第八输入端连接，所述第三输入端用于输入所述第五信号或所述第六信号，所述第九输出端用于输出所述第一控制信号，所述第十输出端用于输出所述第二控制信号。
  14. 根据权利要求1至13中任一项所述的RC振荡器，其特征在于，所述第五信号和所述第六信号的相位相反。
  15. 根据权利要求1至14中任一项所述的RC振荡器，其特征在于，所述电压控制单元将所述第五信号和所述第六信号输出为时钟信号。
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