WO2019041156A1 - 动态放大电路 - Google Patents

动态放大电路 Download PDF

Info

Publication number
WO2019041156A1
WO2019041156A1 PCT/CN2017/099594 CN2017099594W WO2019041156A1 WO 2019041156 A1 WO2019041156 A1 WO 2019041156A1 CN 2017099594 W CN2017099594 W CN 2017099594W WO 2019041156 A1 WO2019041156 A1 WO 2019041156A1
Authority
WO
WIPO (PCT)
Prior art keywords
driving
time
control signal
period
capacitor
Prior art date
Application number
PCT/CN2017/099594
Other languages
English (en)
French (fr)
Inventor
范硕
Original Assignee
深圳市汇顶科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市汇顶科技股份有限公司 filed Critical 深圳市汇顶科技股份有限公司
Priority to CN201780001051.8A priority Critical patent/CN109729758B/zh
Priority to EP17905899.5A priority patent/EP3477863B1/en
Priority to PCT/CN2017/099594 priority patent/WO2019041156A1/zh
Priority to US16/147,857 priority patent/US10693423B2/en
Publication of WO2019041156A1 publication Critical patent/WO2019041156A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
    • H03F1/301—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters in MOSFET amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/04—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/4508—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using bipolar transistors as the active amplifying circuit
    • H03F3/45085—Long tailed pairs
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45278—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using BiFET transistors as the active amplifying circuit
    • H03F3/45295—Pl types
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/129—Indexing scheme relating to amplifiers there being a feedback over the complete amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/447—Indexing scheme relating to amplifiers the amplifier being protected to temperature influence
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45376—Indexing scheme relating to differential amplifiers the AAC comprising one or more discrete resistors as shunts between collectors or drains
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45396—Indexing scheme relating to differential amplifiers the AAC comprising one or more switches
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Definitions

  • Embodiments of the present application relate to the field of circuits and, more particularly, to dynamic amplification circuits.
  • Dynamic Amplifier has low power consumption and no overshoot compared to traditional feedback-based op amp implementations.
  • the gain of a dynamic amplifier varies with, for example, semiconductor process, supply voltage, and temperature (Process, Voltage, Temperature, PVT), which limits its application to some extent.
  • the present application provides a dynamic amplification circuit that provides a relatively stable gain.
  • a dynamic amplification circuit comprising:
  • a first driving circuit configured to generate a first driving voltage according to the first control signal and the first driving current, the first driving current is generated by a first reference voltage, and the first reference voltage is a constant voltage;
  • a second driving circuit configured to generate a first driving signal according to the first driving voltage and the second driving voltage, wherein the first driving voltage changes with time, and the second driving voltage is the first reference a multiple of the voltage;
  • a third driving circuit configured to generate a second control signal according to the first control signal and the first driving signal
  • a dynamic amplifier DA comprising a first branch and a second branch, the first branch comprising a first capacitor, the second branch comprising a second capacitor, the first capacitor and the second capacitor being identical a capacitor, the first branch and the second branch are connected by a first resistor and a second resistor, the first resistor and the second resistor being the same resistor;
  • the DA is configured to receive the first control signal and the second control signal, and control an operation state of the DA by using the first control signal and the second control signal, where the DA is in an amplification manner a duration of the phase followed by a resistance value of the first resistor and a power of the first capacitor
  • the product of the capacitance is proportional.
  • the dynamic amplifying circuit of the embodiment of the present application controls the voltage value of the first driving voltage by the first control signal, and further controls the length of the DA in the amplification phase and the resistor in the DA according to the first driving voltage and the second driving voltage.
  • the resistance value is proportional to the product of the capacitance value of the capacitor, so that the dynamic amplification circuit can still provide a relatively stable gain when the PVT changes.
  • the first branch includes a first control switch, a second control switch, and a first transistor
  • the DA is specifically used to:
  • the working state of the first control signal is:
  • the first control signal In the first period of time, the first control signal outputs a high level
  • the second control period outputs a low level during a second period of time after the first period of time, and the duration of the second period of time is a duration of the DA being in an amplification phase;
  • the first control signal outputs a low level during a third period of time after the second period of time.
  • the first driving circuit is specifically configured to:
  • the first driving voltage of the control output is zero
  • the first driving voltage of the control output starts to increase, but is smaller than the second driving voltage
  • the first driving voltage of the control output is greater than or equal to the second driving voltage during the third period of time.
  • the length of time during which the first driving voltage is increased from zero to the second driving voltage is the length of time during which the DA is in the amplification phase.
  • the first driving circuit includes a first current source and a third capacitor
  • the first current source is configured to: charge the third capacitor during the second period of time and the third period of time, and a voltage drop across the third capacitor is the first driving voltage ,among them,
  • the current value of the first current source is equal to the first driving current, and the first driving current is generated by the first reference voltage acting on the third resistor.
  • the amplification factor of the dynamic amplification circuit is proportional to R 3 *C 3 /(R 1 *C 1 ), where R 3 is The resistance value of the third resistor, C 3 is the capacitance value of the third capacitor, R 1 is the resistance value of the first resistor, and C 1 is the capacitance value of the first capacitor.
  • the first resistor, the second resistor, and the third resistor are the same type of resistor
  • the first The capacitor, the second capacitor, and the third capacitor are the same type of capacitor.
  • the second driving circuit is specifically configured to:
  • the first driving signal of the control output is at a high level during the third period of time.
  • the second driving circuit includes a fourth capacitor, a first inverter, and a second inverter;
  • One end of the fourth capacitor receives the first driving voltage through a first switching device, and receives the second driving voltage through a second switching device, the other end of the fourth capacitor and the first inverter Input connection;
  • An input end and an output end of the first inverter are connected by a third switching device, and an output end of the first inverter is connected to an input end of the second inverter, the second inverter The output is for outputting the first drive signal.
  • the first control signal is further used to:
  • the first control signal is specifically used to:
  • Controlling in the first period of time, that the first switching device is turned off, the second switching device and the third switching device are closed, and in the second period of time and the third period of time, the control station The first switching device is closed, and the second switching device and the third switching device are disconnected.
  • the second driving circuit is a continuous time comparator
  • the first input end of the connection time comparator is configured to receive the first a driving voltage, a second input of the connection time comparator for receiving the second driving voltage, and an output of the continuous time comparator for outputting the first driving signal.
  • the third driving circuit is specifically configured to:
  • the second control signal is controlled to output a low level.
  • the third driving circuit includes a third inverter, a fourth inverter, and a summing circuit;
  • An input end of the third inverter is configured to receive the first control signal, and an output end of the third inverter is connected to a first input end of the summing circuit;
  • An input end of the fourth inverter is configured to receive the first driving signal, and an output end of the fourth inverter is connected to a second input end of the sourcing circuit;
  • An output of the summing circuit is for outputting the second control signal.
  • the first reference voltage is a bandgap reference voltage.
  • the first control signal is specifically used to:
  • Controlling in the first period of time, that the first control switch is closed, and in the second time period and the third time period, controlling the first control switch to be turned off;
  • the second control signal is specifically used to:
  • the first branch includes a first transistor
  • the second branch includes a second transistor
  • a source level of the first transistor and the A source stage of the second transistor is coupled through the first resistor and the second resistor.
  • a product of a transconductance of the first transistor in a saturation region and a resistance value of the first resistor is greater than a multiple threshold.
  • the dynamic amplifying circuit of the embodiment of the present application controls the voltage value of the first driving voltage by the first control signal, and further controls the DA to be amplified according to the first driving voltage and the second driving voltage.
  • the duration of the phase is proportional to the product of the resistance of the resistor in the DA and the capacitance of the capacitor, so that the dynamic amplification circuit can still provide a relatively stable gain when the PVT changes.
  • FIG. 1 is a schematic structural diagram of a dynamic amplifier according to an embodiment of the present application.
  • FIG. 2 is another schematic diagram of a dynamic amplifier according to an embodiment of the present application.
  • FIG. 3 is a logic timing diagram of a dynamic amplifier in accordance with an embodiment of the present application.
  • FIG. 4 is an equivalent circuit diagram of a dynamic amplifier in accordance with an embodiment of the present application.
  • FIG. 5 is a schematic diagram of a dynamic amplification circuit in accordance with an embodiment of the present application.
  • FIG. 6 is a logic timing diagram of a dynamic amplification circuit in accordance with an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of an example of a first driving circuit according to an embodiment of the present application.
  • Fig. 8 is a view showing an example of the structure of a second drive voltage generating circuit.
  • FIG. 9 is a schematic structural diagram of an example of a second driving circuit according to an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of another example of a second driving circuit according to an embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of an example of a third driving circuit according to an embodiment of the present application.
  • FIGS. 1 and 2 are schematic structural diagrams of a dynamic amplifier according to an embodiment of the present application.
  • the dynamic amplifier 100 includes a first branch 101 and a second branch 102, and a first branch 101 and The second branch 102 is a symmetrical structure, and the first branch 101 and the second branch 102 comprise the same device and the parameters of the device are the same.
  • the first branch 101 is mainly taken as an example, and the second branch 102 is used.
  • the operating state of the device is the same as that of the corresponding device in the first branch 101. For brevity, no further details are provided herein.
  • the first branch 101 includes a first transistor 110, a first capacitor 120, a first control switch 130, and a second control switch 140.
  • the DA of the embodiment of the present application is different from the existing DA in that the source of the two symmetric transistors is connected by two symmetric resistors (ie, the first shown in FIG. 1).
  • a resistor 150 and a second resistor 160 therefore, the amplification factor of the DA of the embodiment of the present application is slightly different from the amplification factor of the existing DA, and the amplification factor of the DA of the embodiment of the present application will be described in detail later.
  • the DA shown in FIG. 1 is different from the DA shown in FIG. 2 in that the first resistor 150 and the second resistor 160 in the DA shown in FIG. 1 have a current, and therefore, the first resistor There is a voltage drop across the 150 and the second resistor 160, and there is no voltage drop across the first resistor 150 and the second resistor 160 in the DA shown in FIG. 2, which results in the output voltage of the DA in FIG.
  • the range is narrower than the range of the output voltage of the DA in FIG. 2, but this does not affect the dynamic amplifying circuit based on the DA shown in FIG. 1 and the DA design shown in FIG. 2, which can provide stable gain, but is based on
  • the gain of the dynamic amplifying circuit of the DA shown in FIG. 1 may be smaller than the gain of the dynamic amplifying circuit based on the DA shown in FIG. 2.
  • the first control switch 130 is closed, the second control switch 140 is turned off, the first capacitor 120 is connected to the positive pole (V CC ) of the power source, and the first capacitor 120 is in a charged state;
  • the first control switch 130 is turned off, the second control switch 140 is closed, and the first capacitor 120 is connected to the drain of the first transistor 110 through the second control switch 140, and the first capacitor 120 is in a discharged state.
  • FIG. 3 is a logical timing diagram of the DA 100 of the embodiment of the present application, where For the timing of the first control switch 130, The timing for the output voltage of the second control switch timing, V out 140 of.
  • the first control switch 130 in the first phase (denoted as T R ), the first control switch 130 is closed, the second control switch 140 is open, the DA is in a reset state; in the second phase (denoted as T A ) The first control switch 130 is turned off, the second control switch 140 is closed, and the DA is in an amplified state, that is, the duration in which the DA is in the amplified state is the duration T A of the second phase.
  • FIG. 4 is an equivalent circuit diagram of the DA100 shown in FIG. 1 or FIG. 2, wherein g mA is a transconductance of the first transistor 110 in a saturation region, C 1 is a capacitance value of the first capacitor 120, and R 1 is a first resistance. The resistance value of the device 150.
  • V inp and Vinn due to the difference between V inp and Vinn , the drain voltages of the transistors in the first branch and the second branch may be slightly different, which may cause the differential amplifier gain of the dynamic amplifier to change, but V The influence of the difference between inp and Vinn is relatively small. When calculating the amplification factor in the embodiment of the present application, the influence of this part is ignored.
  • V in V X +g mA *V X *R 1 Formula (1)
  • V x V in / (1 + g mA * R 1 ).
  • the output voltage V out of DA can be determined according to formula (2):
  • V out g mA *V X *T A /C 1 Formula (2)
  • the amplification factor (gain) Av of the DA is as shown in the formula (4):
  • the product of the transconductance g mA of the first transistor in the saturation region and the resistance value R 1 of the first resistor is greater than a multiple threshold, for example, the multiple threshold may be 10 Or 20, etc., in this case, g mA *R 1 >>1 can be considered, then 1+g mA *R 1 is approximately equal to g mA *R 1 , so that formula (4) can be simplified to formula (5):
  • the gain of the existing DA is related to g mA and C 1 , and since g mA and C 1 vary with PVT, the gain of the DA is unstable, and the embodiment of the present application provides a dynamic amplification.
  • the circuit, by design T A is proportional to R 1 *C 1 such that the dynamic amplification circuit still provides a relatively stable gain when the PVT changes.
  • FIG. 5 is a schematic structural diagram of a dynamic amplifying circuit 300 according to an embodiment of the present application. As shown in FIG. 5, the dynamic amplifying circuit 300 includes:
  • the first driving circuit 310 is configured to generate a first driving voltage according to the first control signal and the first driving current, the first driving current is generated by the first reference voltage, and the first reference voltage is a constant voltage.
  • the first reference voltage is a constant voltage and does not change with the PVT.
  • the first reference voltage may be a bandgap reference voltage V BG , and those skilled in the art may know that the V BG may be
  • the first reference driving current is generated by the first reference voltage, and the first driving voltage is generated by the first reference voltage.
  • the following is a description of the first reference voltage as V BG .
  • the first reference voltage of the example may also be other voltages that do not vary with PVT.
  • the first control signal herein can be used to control the first control switch 130 in the DA shown in FIG. 1 or FIG. 2, that is, the first control signal can correspond to the control signal in FIG. Therefore, during the first time period (corresponding to the first phase described above), the first control signal may be a high level, and during the second time period (corresponding to the second phase described above), the first The control signal can be low, and the first control switch can be controlled to close and open by the first control signal.
  • the first driving circuit 310 can control the change of the first driving voltage according to the first control signal and the first driving current. For example, the first driving circuit 310 can control the first driving voltage to be zero during the first time period. During the second period, the first driving voltage begins to increase.
  • the first driving circuit 310 includes a first current source and a third capacitor, wherein the first current source is configured to: after the second period of time, charge the third capacitor to obtain a first driving voltage, where A current source has a current value equal to the first drive current, and the first drive current may be generated by the first reference voltage acting on the third resistor.
  • the amplification factor of the dynamic amplification circuit may be proportional to R 3 *C 3 /(R 1 *C 1 ), where R 3 is the resistance value of the third resistor, and C 3 is the third The capacitance value of the capacitor, R 1 is the resistance value of the first resistor, and C 1 is the capacitance value of the first capacitor.
  • the amplification factor Av of the dynamic amplification circuit is as shown in the formula (5):
  • the first resistor, the second resistor, and the third resistor are the same type of resistor, and the first capacitor, the second capacitor, and the third capacitor are The same type of capacitor.
  • the same type of resistor or capacitor can be considered to be at the same process angle, and the first capacitor and the third capacitor, and The first resistor and the third resistor are in the same environment (for example, the temperature is the same), and therefore, when the PVT changes, the first capacitor and the third capacitor, and the first resistor and the third resistor have the same rate of change
  • the ratio of the capacitance values of the first capacitor and the third capacitor is a constant value, that is, C 3 /C 1 does not vary with the PVT
  • the ratio of the resistance values of the first resistor and the third resistor is a constant value, that is, R 3 /R 1 does not vary with PVT
  • the coefficient K can be controlled by the designer and does not vary with PVT. Therefore, the amplification factor of the dynamic amplification circuit of the embodiment of the present application is a constant gain that does not vary with PVT.
  • the second driving circuit 320 is configured to generate a first driving signal according to the first driving voltage and the second driving voltage, wherein the first driving voltage changes with time, and the second driving voltage is a multiple of the first reference voltage.
  • the second driving voltage may be equal to aV BG , where a may be equal to 1, or less than 1, or may be greater than 1, the first driving voltage may initially be zero, and at a certain moment, the first driving voltage begins to increase, The first driving voltage may be increased to be greater than or equal to the second driving voltage, and the first driving voltage and the second driving voltage may be used to control a level value of the first driving signal output.
  • the second driving circuit may be configured to control the first driving signal to output a low level when the first driving voltage is less than the second driving voltage, and control the first driving signal when the first driving voltage is greater than or equal to the second driving voltage. The output is high.
  • the duration of the first driving voltage increasing from zero to the second driving voltage can be regarded as the aforementioned TA. Therefore, by controlling the voltage difference between the first driving voltage and the second driving voltage, the TA can be controlled by controlling the TA and the The resistance of a resistor is proportional to the product of the capacitance of the first capacitor, thereby enabling the dynamic amplification circuit to provide a stable gain.
  • the third driving circuit 330 is configured to generate a second control signal according to the first control signal and the first driving signal.
  • the second control signal herein can be used to control the second control switch 140 in the DA shown in FIG. 1 or FIG. 2, that is, the first control signal can correspond to the control signal in FIG. Therefore, in the first time period (corresponding to the first phase described above), the second control signal may be a low level, in a second time period (corresponding to the second phase described above), the second The control signal can be high, ie the second control switch can be controlled to close and open by the second control signal.
  • the dynamic amplifier DA340 includes a first branch and a second branch, the first branch includes a first capacitor, the second branch includes a second capacitor, the first capacitor and the second capacitor are the same capacitor, the first branch and The second branch is connected by a first resistor and a second resistor, the first resistor and the second resistor being the same resistor.
  • the DA 340 may be the DA 100 shown in FIG. 1 or 2, or may be other equivalent circuits.
  • the first branch and the second branch may respectively correspond to the first branch 101 and the second branch 102 in the DA100 shown in FIG. 1 or FIG. 2, and the first capacitor may correspond to the one shown in FIG. 1 or FIG.
  • the first capacitor 120, the first resistor and the second resistor in the DA100 may correspond to the first resistor 150 and the second resistor 160 in the DA100 shown in FIG. 1 or FIG.
  • first resistor And the second resistor is the same resistor, that is, the first resistor and the second resistor are of the same type, and the resistance values are the same
  • the first capacitor and the second capacitor are the same capacitor, that is, the first capacitor and the second capacitor
  • the types are the same and the capacitance values are the same.
  • the DA is configured to receive the first control signal and the second control signal, and control the working state of the DA by using the first control signal and the second control signal, wherein the DA is in the amplification phase and the resistance value of the first resistor is The product of the capacitance values of the first capacitor is proportional.
  • the first control signal and the second control signal can be used as the control signal in FIG. with
  • the first control switch 130 and the second control switch 140 for controlling the DA 100 respectively can control whether the DA is in a reset state (corresponding to the first stage in the foregoing) or in an amplification phase by the first control signal and the second control signal ( Corresponding to the second stage in the previous article).
  • the first control signal is configured to: in the first time period, control the first control switch to be closed, in the second time period and the third time period, control the first control switch to be turned off;
  • the second control signal is used to: In the first period of time, the second control switch is controlled to be turned off, in the second period of time, the second control switch is controlled to be closed, and in the third period of time, the second control switch is controlled to be turned off.
  • the dynamic amplifying circuit of the embodiment of the present application controls the length of the DA in the amplification phase by the first control signal and the second control signal to be proportional to the product of the resistance value of the first resistor and the capacitance value of the first capacitor, thereby The gain of the dynamic amplification circuit does not vary with the PVT.
  • a first period of time (corresponding to the first phase described above, or may also be referred to as a reset phase), ie, a period between t 1 and t 2 , the first control signal is at a high level, the first drive The first driving voltage V 1 of the circuit output is zero, the second driving voltage V 2 is a constant voltage value, and the second control signal output by the third driving circuit is a low level.
  • the first driving signal may output a low level or a high level during the first time period
  • FIG. 6 only takes the first driving signal as a low level as an example.
  • the first control signal is at a high level and the second control signal is at a low level during the first time period.
  • the first control signal is low during a second time period after the first time period (corresponding to the second phase described above, or may also be referred to as an amplification phase), ie, a time period between t 2 and t 3 Level, in the second period of time, the first driving voltage outputted by the first driving circuit starts to increase, but is still smaller than the second driving voltage, and the second driving circuit outputs the first according to the first driving voltage and the second driving voltage.
  • the driving signal is still at a low level, and the third driving circuit is at a high level according to the first control signal and the second control signal output by the first driving signal.
  • the first control signal is at a low level
  • the first driving voltage outputted by the first driving circuit is greater than or equal to the second driving voltage
  • the second driving The first driving signal outputted by the circuit changes from a low level to a high level
  • the second control signal outputted by the third driving circuit changes from a high level to a low level.
  • V 1 may increase to be equal to V 2 and then no longer increase, or may continue to increase to a certain voltage value after being equal to V 2 and then no longer increase, etc.
  • the embodiment of the present application does not limit the magnitude of the voltage value of the first driving voltage in the third period of time, as long as the first driving signal is inverted when V 1 is equal to V 2 .
  • the second driving circuit is capable of outputting the first driving signal according to the first driving voltage and the second driving voltage that change with time, that is, when the first driving voltage is lower than the second driving voltage, outputting a low level, in the first driving When the voltage is greater than or equal to the second driving voltage, the output is high.
  • the second drive circuit can be implemented with a comparator, and in particular, the comparator can be a continuous time comparator.
  • the third driving circuit outputs the second control signal according to the first control signal and the first driving signal, wherein the third driving circuit only needs to control when the first control signal and the first driving signal are both low
  • the second control signal outputs a high level, and when the first control signal and the first driving signal are in other states, the second control signal outputs a low level.
  • the third driving circuit can be implemented by a combination circuit of an inverter and an AND gate.
  • the first control signal and the first driving signal can be inverted and input to the two inputs of the AND gate.
  • the output of the AND gate outputs a high level. In other states, the output of the AND gate outputs a low level.
  • the dynamic amplifying circuit of the embodiment of the present application controls the first driving voltage outputted by the first driving circuit by the first control signal, and further controls the duration T A of the second time period according to the first driving voltage and the second driving voltage. It is proportional to the product of the capacitance value C 1 of the first capacitor in the DA and the resistance value R 1 of the first resistor, so that the dynamic amplification circuit can still provide a stable gain when the PVT changes.
  • the first driving circuit 310 includes a first current source 311, a third capacitor 312, a third control switch 313, and a fourth.
  • the switch 314 is controlled, wherein the first current source 311 is connected to the third capacitor 312 through the third control switch 313, and the fourth control switch 314 is connected in parallel with the third capacitor 312.
  • the current value of the first current source 311 is equal to the first drive described above. Current, the first driving current is generated by the first reference voltage acting on the third resistor;
  • the first driving current I 1 V BG /R 3 .
  • the first driving circuit 310 is specifically configured to:
  • the first control signal is specifically used to:
  • the third control switch In the first time period, the third control switch is controlled to be turned off, and the fourth control switch is closed; in the second time period and the third time period, the third control switch is controlled to be closed, and the fourth control switch is turned off.
  • the third control switch is turned off, the fourth control switch is closed, and the voltage drop across the third capacitor is zero, that is, the first driving voltage is zero, and at time t 2 , the third control The switch is closed, the fourth control switch is turned off, and the first current source starts to charge the third capacitor. Therefore, during the second time period, the voltage drop on the third capacitor, that is, the first driving voltage V 1 starts to increase until Increase to be equal to the second driving voltage V 2 .
  • the duration T A of the second period of time between the time t 2 and the time t 3 is the time required for the voltage value of the third capacitor to increase from zero to V 2
  • the duration T A of the second period of time may be Determine according to formula (6):
  • T A V 2 * C 3 / I 1 formula (6)
  • C 3 is the capacitance value of the third capacitor 312
  • I 1 is the current value of the first current source 311.
  • the first resistor and the third resistor may be the same type of resistor, and the first capacitor and the third capacitor may be the same type of capacitor, then, when the PVT changes, the first capacitor and the first The three capacitors, and the first resistor and the third resistor have the same rate of change, that is, C 3 /C 1 is a constant value, R 3 /R 1 is a constant value, and the coefficient a can be controlled by the designer without changing with the PVT. Therefore, the amplification factor A v shown in the formula (8) is a constant value, that is, the amplification factor of the dynamic amplification circuit of the embodiment of the present application is a constant gain that does not vary with the PVT.
  • FIG. 8 The following is a detailed description of the second driving voltage generating circuit in conjunction with FIG. 8. It should be understood that the circuit shown in FIG. 8 is used to help those skilled in the art to better understand the embodiments of the present application, and is not intended to limit the embodiments of the present application. range. A person skilled in the art can also generate the second driving voltage according to other circuits, which is not limited by the embodiment of the present application.
  • the circuit may include an operational amplifier 801, a transistor 802, a transistor 803, a resistor 804, and a resistor 805.
  • transistor 802 and transistor 803 have the same W/L, where W is the gate width of the transistor and L is the gate length of the transistor.
  • the a can control the magnitude of a by controlling the resistance values of the resistor 804 and the resistor 805.
  • the resistor 804 and the resistor 805 may be the same type of resistor, so that when the PVT changes, it is ensured that R 5 /R 4 is a constant value, that is, a is a constant value.
  • FIG. 9 is a schematic structural diagram of an example of a second driving circuit according to an embodiment of the present application, and FIG. 9 shows a possible implementation manner of the second driving circuit, or a preferred implementation manner, but the embodiment of the present application It is not limited to the implementations, and various equivalent modifications or variations of the implementations are within the scope of the embodiments of the present application.
  • the second driving circuit 320 includes a fourth capacitor 321, a first inverter 322, and a second inverter 323.
  • One end of the fourth capacitor 321 receives the first driving voltage through the first switching device 324, and receives the second driving voltage through the second switching device 325, and the other end of the fourth capacitor 321 is connected to the input end of the first inverter 322;
  • the input terminal and the output terminal of the first inverter 322 are connected by a third switching device 326, the output terminal of the first inverter 322 is connected to the input terminal of the second inverter 323, and the output terminal of the second inverter 323 is output. For outputting the first drive signal.
  • the first control signal is used to:
  • the third switching device is turned off.
  • first switching device 324 turned off at time t 1
  • a second switching device 325 is closed
  • the third switching device 326 is closed
  • the voltage at one end of the fourth capacitor 321 is
  • the second driving voltage V 2 and the voltage at the other end are the threshold voltage V TH of the first inverter 322
  • the voltage drop across the fourth capacitor 321 is V TH -V 2 .
  • the third driving circuit The output second control signal is low.
  • the first switching device 324 is closed, the second switching device 325 is turned off, and the third switching device 326 is turned off, and the voltage at one end of the fourth capacitor 321 is
  • the first driving voltage V 1 based on the principle of conservation of charge, the voltage drop across the fourth capacitor 321 does not change, then the voltage at the input of the first inverter is V 1 +V TH ⁇ V 2 , since in the second period of time V 1 ⁇ V 2 , then V 1 +V TH -V 2 ⁇ V TH , after passing through the first inverter, outputting a high level, and then passing the second inverter, the first driving signal outputs a low level .
  • V 1 ⁇ V 2 is V 1 + V TH -V 2 ⁇ V TH, through the first inverter, the output low, then after the second inverter After the inverter is reversed, the first drive signal outputs a high level.
  • the embodiment of the present application may also adopt other equivalent circuits to implement the function of the second driving circuit, that is, if the first driving voltage is greater than or equal to the second driving voltage, the first driving voltage is greater than or equal to When the second driving voltage is output, a high level can be output.
  • the second driving circuit since the first control signal can be used to control the closing and opening of the first switching device, the second driving circuit further includes an input end of the first control signal, for inputting the first The control signal controls the closing and opening of the first switching device, the second switching device, and the third switching device by the first control signal.
  • the first control signal is used to control the closing and opening of the first switching device, the second switching device, the third switching device and the first control switch
  • the second control signal is used for controlling
  • the closing and opening of the second control switch only indicates that the control signals have the function of controlling the respective corresponding switching devices, and it is not indicated that the input terminals of the control signals must have a direct connection relationship with the respective switching devices. As long as the input control signal can be controlled to control the closing and opening of the corresponding switching device.
  • the second driving circuit 320 is a continuous time comparator 327, and is connected to the first input terminal of the time comparator 327.
  • the second input terminal of the connection time comparator is for receiving the second driving voltage V 2
  • the output of the continuous time comparator 327 is for outputting the first driving signal.
  • the continuous time comparator 327 outputs a low level
  • V 1 ⁇ V 2 the output voltage of the continuous time comparator 327 is inverted from a low level to a high level.
  • both the continuous time comparator shown in FIG. 10 and the combined circuit shown in FIG. 9 can realize the function of the second driving circuit, that is, output low level when the first driving voltage is smaller than the second driving voltage, in the first driving When the voltage is greater than or equal to the second driving voltage, the high level is output.
  • the combined circuit shown in FIG. 9 does not have to perform continuous comparison with respect to the continuous time comparator shown in FIG. 10, and thus the power consumption is relatively low.
  • FIG. 11 is a schematic diagram showing an example of a third driving circuit according to an embodiment of the present application.
  • the third driving circuit 330 includes a third inverter 331, a fourth inverter 332, and a summing circuit 333.
  • the input end of the third inverter 331 is configured to receive the first control signal, and the output end of the third inverter 331 is connected to the first input end of the summing circuit 333;
  • the input end of the fourth inverter 332 is configured to receive the first driving signal, and the output end of the fourth inverter 332 is connected to the second input end of the summing circuit 333;
  • the output of the summing circuit 333 is for outputting a second control signal.
  • the third driving circuit shown in FIG. 11 can control that the second control signal outputs a high level when both the first control signal and the first driving signal are at a low level, when the first control signal and the first driving signal are In other working states, the second control signal outputs a low level.
  • the summing circuit 333 can be implemented with an AND gate, or other equivalent circuit.
  • the dynamic amplifying circuit of the embodiment of the present application controls the voltage value of the first driving voltage output through the first control signal, and further controls the duration of the second time period to satisfy the DA in accordance with the first driving voltage and the second driving voltage.
  • the capacitance of the capacitor is proportional to the product of the resistance of the resistor such that the dynamic amplification circuit still provides a relatively stable gain as the PVT changes.
  • first, second, third, fourth, and various numerical numbers eg, the first driving circuit 310 and the second driving circuit 320, etc.
  • referred to herein are merely for convenience of description and are not intended to be limiting. The scope of protection of the embodiments of the present application.
  • the negative pole of the power source involved in the above embodiment may be set to the ground potential (ie, ground).
  • ground potential ie, ground
  • other potentials such as a negative potential, may be used.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)

Abstract

一种动态放大电路，能够提供稳定的增益，包括：第一驱动电路（310），用于根据第一控制信号和第一驱动电流，产生第一驱动电压；第二驱动电路（320），用于根据所述第一驱动电压和第二驱动电压，产生第一驱动信号；第三驱动电路（330），用于根据所述第一控制信号和所述第一驱动信号，产生第二控制信号；动态放大器DA（340），包括第一支路（101）和第二支路（102），所述第一支路（101）包括第一电容器（120），所述第二支路（102）包括第二电容器，所述第一支路（101）和所述第二支路（102）通过第一电阻器（150）和第二电阻器（160）连接；所述动态放大器DA（340），用于通过所述第一控制信号和所述第二控制信号控制所述动态放大器DA（340）的工作状态，其中，所述动态放大器DA（340）处于放大阶段的时长跟所述第一电阻器（150）的电阻值和所述第一电容器（120）的电容值的乘积成正比。

Description

动态放大电路 技术领域
本申请实施例涉及电路领域，并且更具体地，涉及动态放大电路。
背景技术
动态放大器(Dynamic Amplifier，DA)相比于传统的基于带反馈的运算放大器实现而言，具有低功耗，无过冲的优点。
但是，动态放大器的增益会随着例如，半导体工艺、供电电压和温度(Process、Voltage、Temperature，PVT)的变化而变化，在一定程度上限制了它的应用。
因此，需要一种动态放大电路，能够提供相对稳定的增益。
发明内容
本申请提供一种动态放大电路，能够提供相对稳定的增益。
第一方面，提供了一种动态放大电路，包括：
第一驱动电路，用于根据第一控制信号和第一驱动电流，产生第一驱动电压，所述第一驱动电流是由第一基准电压产生的，所述第一基准电压为恒定电压；
第二驱动电路，用于根据所述第一驱动电压和第二驱动电压，产生第一驱动信号，其中，所述第一驱动电压随时间变化，所述第二驱动电压为所述第一基准电压的倍数；
第三驱动电路，用于根据所述第一控制信号和所述第一驱动信号，产生第二控制信号；
动态放大器DA，包括第一支路和第二支路，所述第一支路包括第一电容器，所述第二支路包括第二电容器，所述第一电容器和所述第二电容器为相同的电容器，所述第一支路和所述第二支路通过第一电阻器和第二电阻器连接，所述第一电阻器和所述第二电阻器为相同的电阻器；
所述DA，用于接收所述第一控制信号和所述第二控制信号，通过所述第一控制信号和所述第二控制信号控制所述DA的工作状态，其中，所述DA处于放大阶段的时长跟所述第一电阻器的电阻值和所述第一电容器的电 容值的乘积成正比。
因此，本申请实施例的动态放大电路，通过第一控制信号控制第一驱动电压的电压值，进而根据第一驱动电压和第二驱动电压，控制DA处于放大阶段的时长跟DA中的电阻器的电阻值和电容器的电容值的乘积成正比，从而使得在PVT变化时，该动态放大电路依然能够提供相对稳定的增益。
结合第一方面，在第一方面的一种可能的实现方式中，所述第一支路包括第一控制开关、第二控制开关和第一晶体管；
所述DA具体用于：
接收所述第一控制信号和所述第二控制信号，通过所述第一控制信号和所述第二控制信号分别控制所述第一控制开关和所述第二控制开关的闭合和断开。
结合第一方面，在第一方面的一种可能的实现方式中，所述第一控制信号的工作状态为：
在第一时间段，所述第一控制信号输出高电平；
在所述第一时间段之后的第二时间段内，所述第一控制信号输出低电平，所述第二时间段的时长为所述DA处于放大阶段的时长；
在所述第二时间段之后的第三时间段内，所述第一控制信号输出低电平。
结合第一方面，在第一方面的一种可能的实现方式中，所述第一驱动电路具体用于：
在所述第一时间段，控制输出的所述第一驱动电压为零；
在所述第二时间段内，控制输出的所述第一驱动电压开始增大，但小于所述第二驱动电压；
在所述第三时间段内，控制输出的所述第一驱动电压大于或等于所述第二驱动电压。
也就是说，第一驱动电压从零增大到第二驱动电压的时长为DA处于放大阶段的时长。
结合第一方面，在第一方面的一种可能的实现方式中，所述第一驱动电路包括第一电流源和第三电容器；
所述第一电流源用于：在所述第二时间段和所述第三时间段内，对所述第三电容器进行充电，所述第三电容器上的压降为所述第一驱动电压，其中， 所述第一电流源的电流值等于所述第一驱动电流，所述第一驱动电流是由所述第一基准电压作用于第三电阻器上产生的。
结合第一方面，在第一方面的一种可能的实现方式中，所述动态放大电路的放大系数与R3*C3/(R1*C1)成正比，其中，R3为所述第三电阻器的电阻值，C3为所述第三电容器的电容值，R1为所述第一电阻器的电阻值，C1为所述第一电容器的电容值。
结合第一方面，在第一方面的一种可能的实现方式中，所述第一电阻器、所述第二电阻器和所述第三电阻器为同一种类型的电阻器，所述第一电容器、所述第二电容器和所述第三电容器为同一种类型的电容器。
结合第一方面，在第一方面的一种可能的实现方式中，所述第二驱动电路具体用于：
在所述第二时间段内，控制输出的所述第一驱动信号为低电平；
在所述第三时间段内，控制输出的所述第一驱动信号为高电平。
结合第一方面，在第一方面的一种可能的实现方式中，所述第二驱动电路包括第四电容器、第一反相器和第二反相器；
所述第四电容器的一端通过第一开关器件接收所述第一驱动电压，以及通过第二开关器件接收所述第二驱动电压，所述第四电容器的另一端与所述第一反相器的输入端连接；
所述第一反相器的输入端和输出端通过第三开关器件连接，所述第一反相器的输出端与所述第二反相器的输入端连接，所述第二反相器的输出端用于输出所述第一驱动信号。
结合第一方面，在第一方面的一种可能的实现方式中，所述第一控制信号还用于：
控制所述第一开关器件、所述第二开关器件和所述第三开关器件的闭合与断开；
其中，所述第一控制信号具体用于：
在所述第一时间段，控制所述第一开关器件断开，所述第二开关器件和所述第三开关器件闭合，在所述第二时间段和所述第三时间段，控制所述第一开关器件闭合，所述第二开关器件和所述第三开关器件断开。
结合第一方面，在第一方面的一种可能的实现方式中，所述第二驱动电路为连续时间比较器，所述连接时间比较器的第一输入端用于接收所述第一 驱动电压，所述连接时间比较器的第二输入端用于接收所述第二驱动电压，所述连续时间比较器的输出端用于输出所述第一驱动信号。
结合第一方面，在第一方面的一种可能的实现方式中，所述第三驱动电路具体用于：
在所述第一时间段，控制所述第二控制信号输出低电平；
在所述第二时间段内，控制所述第二控制信号输出高电平；
在所述第三时间段内，控制所述第二控制信号输出低电平。
结合第一方面，在第一方面的一种可能的实现方式中，所述第三驱动电路包括第三反相器、第四反相器和求与电路；
所述第三反相器的输入端用于接收所述第一控制信号，所述第三反相器的输出端与所述求与电路的第一输入端连接；
所述第四反相器的输入端用于接收所述第一驱动信号，所述第四反相器的输出端与所述求与电路的第二输入端连接；
所述求与电路的输出端用于输出所述第二控制信号。
结合第一方面，在第一方面的一种可能的实现方式中，所述第一基准电压是带隙基准电压。
结合第一方面，在第一方面的一种可能的实现方式中，所述第一控制信号具体用于：
在所述第一时间段，控制所述第一控制开关闭合，在所述第二时间段和所述第三时间段，控制所述第一控制开关断开；
所述第二控制信号具体用于：
在所述第一时间段，控制所述第二控制开关断开，在所述第二时间段，控制所述第二控制开关闭合，在所述第三时间段，控制所述第二控制开关断开。
结合第一方面，在第一方面的一种可能的实现方式中所述第一支路包括第一晶体管，所述第二支路包括第二晶体管，所述第一晶体管的源级和所述第二晶体管的源级通过所述第一电阻器和所述第二电阻器连接。
结合第一方面，在第一方面的一种可能的实现方式中，所述第一晶体管处于饱和区的跨导与所述第一电阻器的电阻值的乘积大于倍数阈值。
因此，本申请实施例的动态放大电路，通过第一控制信号控制第一驱动电压的电压值，进而根据第一驱动电压和第二驱动电压，控制DA处于放大 阶段的时长跟DA中的电阻器的电阻值和电容器的电容值的乘积成正比，从而使得在PVT变化时，该动态放大电路依然能够提供相对稳定的增益。
附图说明
图1是根据本申请实施例的动态放大器的结构示意图。
图2是根据本申请实施例的动态放大器的另一结构示意图。
图3是根据本申请实施例的动态放大器的逻辑时序图。
图4是根据本申请实施例的动态放大器的等效电路图。
图5是根据本申请实施例的动态放大电路的示意图。
图6是根据本申请实施例的动态放大电路的逻辑时序图。
图7是根据本申请实施例的第一驱动电路的一例结构示意图。
图8是第二驱动电压的产生电路的一例结构示意图。
图9是根据本申请实施例的第二驱动电路的一例结构示意图。
图10是根据本申请实施例的第二驱动电路的另一例结构示意图。
图11是根据本申请实施例的第三驱动电路的一例结构示意图。
具体实施方式
下面将结合附图，对本申请中的技术方案进行描述。
图1和图2是根据本申请实施例的动态放大器的结构示意图，如图1和图2所示，该动态放大器100包括第一支路101和第二支路102，第一支路101和第二支路102为对称结构，第一支路101和第二支路102包括的器件，以及器件的参数相同，这里主要以第一支路101为例进行介绍，第二支路102中的器件的工作状态和第一支路101中的对应器件的工作状态相同，为了简洁，这里不再赘述。
具体地，第一支路101包括第一晶体管110、第一电容器120、第一控制开关130和第二控制开关140。
从图1和图2可以看出，本申请实施例的DA相对于现有的DA不同的是：对称的两个晶体管的源级通过对称的两个电阻器相连(即图1所示的第一电阻器150以及与第二电阻器160)，因此，本申请实施例的DA的放大系数与现有的DA的放大系数稍有不同，后面对本申请实施例的DA的放大系数做详细介绍。
需要说明的是，图1所示的DA与图2所示的DA不同的是：图1所示的DA中的第一电阻器150和第二电阻器160上有电流，因此，第一电阻器150和第二电阻器160上会有压降，而图2所示的DA中的第一电阻器150和第二电阻器160上没有压降，这就使得图1中的DA的输出电压的范围相对于图2中的DA的输出电压的范围窄，但是，这并不影响基于图1所示的DA和图2所示的DA设计的动态放大电路，能够提供稳定的增益，只是基于图1所示的DA的动态放大电路的增益可能比基于图2所示的DA的动态放大电路的增益小。
本申请实施例的DA的工作状态包括两个阶段：
第一阶段，第一控制开关130闭合，第二控制开关140断开，第一电容器120连接至电源的正极(VCC)，第一电容器120处于充电状态；
第二阶段，第一控制开关130断开，第二控制开关140闭合，第一电容器120通过第二控制开关140连接至第一晶体管110的漏极，第一电容器120处于放电状态。
图3是本申请实施例的DA100的逻辑时序图，其中，
Figure PCTCN2017099594-appb-000001
为第一控制开关130的时序，
Figure PCTCN2017099594-appb-000002
为第二控制开关140的时序，Vout为输出电压的时序。
如图3所示，在第一阶段(记为TR)，第一控制开关130闭合，第二控制开关140断开，DA处于复位(reset)状态；在第二阶段(记为TA)，第一控制开关130断开，第二控制开关140闭合，DA处于放大状态，即DA处于放大状态的时长为第二阶段的时长TA。
图4为图1或图2所示的DA100的等效电路图，其中，gmA为第一晶体管110处于饱和区的跨导，C1为第一电容器120的电容值，R1为第一电阻器150的电阻值。
需要说明的是，由于Vinp和Vinn的差异，可能导致第一支路和第二支路中的晶体管的漏极电压略有差异，进而可能导致动态放大器的差模增益发生变化，但是Vinp和Vinn的差异带来的影响相对较小，本申请实施例计算放大系数时，忽略此部分影响。
由图4所示的等效电路图可知，DA的输入电压Vin如公式(1)所示：
Vin＝VX+gmA*VX*R1      公式(1)
由公式(1)可知，Vx＝Vin/(1+gmA*R1)。
DA的输出电压Vout可以根据公式(2)确定：
Vout＝gmA*VX*TA/C1        公式(2)
将Vx＝Vin/(1+gmA*R1)代入公式(2)可得：
Figure PCTCN2017099594-appb-000003
因此，该DA的放大系数(增益)Av如公式(4)所示：
Figure PCTCN2017099594-appb-000004
可选地，在本申请实施例中，所述第一晶体管处于饱和区的跨导gmA与所述第一电阻器的电阻值R1的乘积大于倍数阈值，例如，该倍数阈值可以为10或20等，此情况下，可以认为gmA*R1>>1，那么1+gmA*R1近似认为等于gmA*R1，从而公式(4)可以简化为公式(5)：
Figure PCTCN2017099594-appb-000005
本领域技术人员可知，现有的DA的增益跟gmA和C1有关，由于gmA和C1会随PVT变化，因此，导致DA的增益不稳定，本申请实施例提供了一种动态放大电路，通过设计TA与R1*C1成正比，从而使得在PVT变化时，动态放大电路依然能够提供相对稳定的增益。
图5是本申请实施例提供的动态放大电路300的示意性结构图，如图5所示，该动态放大电路300包括：
第一驱动电路310，用于根据第一控制信号和第一驱动电流，产生第一驱动电压，第一驱动电流是由第一基准电压产生的，第一基准电压为恒定电压。
需要说明的是，在本申请实施例中，第一基准电压为恒定电压，不随PVT变化，例如，第一基准电压可以为带隙基准电压VBG，本领域技术人员可知，VBG可以由带隙基准电路产生，第一驱动电流可以由第一基准电压作用在电阻器上产生，以下，以第一基准电压为VBG为例介绍，但不应对本申请实施例构成任何限定，本申请实施例的第一基准电压也可以为其他不随PVT变化的电压。
这里的第一控制信号可以用于控制图1或图2所示的DA中的第一控制开关130，即所述第一控制信号可以对应于图3中的控制信号
Figure PCTCN2017099594-appb-000006
因此，在第一时间段(对应于前文所述的第一阶段)内，第一控制信号可以为高电平，在第二时间段内(对应于前文所述的第二阶段)，第一控制信号可以为 低电平，通过第一控制信号可以控制第一控制开关的闭合和断开。
第一驱动电路310可以根据第一控制信号和第一驱动电流，控制第一驱动电压的变化，例如，第一驱动电路310可以控制在第一时间段内，第一驱动电压为零，在第二时间段内，第一驱动电压开始增大。
可选地，第一驱动电路310包括第一电流源和第三电容器，其中，第一电流源用于：在第二时间段内，对第三电容器进行充电得到第一驱动电压，其中，第一电流源的电流值等于第一驱动电流，第一驱动电流可以是由第一基准电压作用于第三电阻器上产生的。
此情况下，动态放大电路的放大系数可以与R3*C3/(R1*C1)成正比，其中，R3为所述第三电阻器的电阻值，C3为所述第三电容器的电容值，R1为所述第一电阻器的电阻值，C1为所述第一电容器的电容值。
也就是说，动态放大电路的放大系数Av如公式(5)所示：
Figure PCTCN2017099594-appb-000007
可选地，所述第一电阻器、所述第二电阻器和所述第三电阻器为同一种类型的电阻器，所述第一电容器、所述第二电容器和所述第三电容器为同一种类型的电容器。
本领域技术人员可知，在互补金属氧化物半导体(Complementary Metal Oxide Semiconductor,CMOS)工艺中，同一种类型的电阻器或电容器可以认为是处于同一工艺角，并且，第一电容器和第三电容器，以及第一电阻器和第三电阻器所处的环境相同(例如，温度相同)，因此，在PVT变化时，第一电容器和第三电容器，以及第一电阻器和第三电阻器的变化率相同，这样，可以认为第一电容器和第三电容器的电容值的比值为恒定值，即C3/C1不随PVT变化，第一电阻器和第三电阻器的电阻值的比值为恒定值，即R3/R1不随PVT变化，而系数K可以由设计者控制，也不随PVT变化，因此，本申请实施例的动态放大电路的放大系数为不随PVT变化的恒定增益。
第二驱动电路320，用于根据第一驱动电压和第二驱动电压，产生第一驱动信号，其中，第一驱动电压随时间变化，第二驱动电压为第一基准电压的倍数。
例如，第二驱动电压可以等于aVBG，其中，a可以等于1，或小于1，或者也可以大于1，第一驱动电压初始可以为零，在某个时刻，第一驱动电 压开始增大，第一驱动电压可以增大到大于或等于第二驱动电压，第一驱动电压和第二驱动电压可以用于控制第一驱动信号输出的电平值。例如，第二驱动电路可以用于在第一驱动电压小于第二驱动电压时，控制第一驱动信号输出低电平，当第一驱动电压大于或等于第二驱动电压时，控制第一驱动信号输出高电平。其中，第一驱动电压从零增大到第二驱动电压的时长可以认为是前述的TA，因此，通过控制第一驱动电压和第二驱动电压的电压差，可以控制TA，通过控制TA与第一电阻器的电阻值和第一电容器的电容值的乘积成正比，从而使得动态放大电路能够提供稳定的增益。
第三驱动电路330，用于根据第一控制信号和第一驱动信号，产生第二控制信号。
这里的第二控制信号可以用于控制图1或图2所示的DA中的第二控制开关140，即所述第一控制信号可以对应于图3中的控制信号
Figure PCTCN2017099594-appb-000008
因此，在第一时间段(对应于前文所述的第一阶段)内，第二控制信号可以为低电平，在第二时间段内(对应于前文所述的第二阶段)，第二控制信号可以为高电平，即通过第二控制信号可以控制第二控制开关的闭合和断开。
动态放大器DA340，包括第一支路和第二支路，第一支路包括第一电容器，第二支路包括第二电容器，第一电容器和第二电容器为相同的电容器，第一支路和第二支路通过第一电阻器和第二电阻器连接，第一电阻器和第二电阻器为相同的电阻器。
可选地，DA340可以为图1或2所示的DA100，或者，也可以为其他等效电路。第一支路和第二支路可以分别对应于图1或图2所示的DA100中的第一支路101和第二支路102，第一电容器可以对应于图1或图2所示的DA100中的第一电容器120，第一电阻器和第二电阻器可以分别对应于图1或图2所示的DA100中的第一电阻器150和第二电阻器160，其中，第一电阻器和第二电阻器为相同的电阻器，即第一电阻器和第二电阻器的类型相同，并且电阻值相同，第一电容器和第二电容器为相同的电容器，即第一电容器和第二电容器的类型相同，并且电容值相同。
所述DA，用于接收第一控制信号和第二控制信号，通过第一控制信号和第二控制信号控制DA的工作状态，其中，DA处于放大阶段的时长跟第一电阻器的电阻值和第一电容器的电容值的乘积成正比。
也就是说，第一控制信号和第二控制信号可以用作图3中的控制信号
Figure PCTCN2017099594-appb-000009
和
Figure PCTCN2017099594-appb-000010
分别用于控制DA100的第一控制开关130和第二控制开关140，通过第一控制信号和第二控制信号可以控制DA是处于reset状态(对应前文中的第一阶段)，还是处于放大阶段(对应前文中的第二阶段)。具体地，第一控制信号用于：在第一时间段，控制第一控制开关闭合，在第二时间段和第三时间段，控制第一控制开关断开；第二控制信号用于：在第一时间段，控制第二控制开关断开，在第二时间段，控制第二控制开关闭合，在第三时间段控制第二控制开关断开。
因此，本申请实施例的动态放大电路，通过第一控制信号和第二控制信号，控制DA处于放大阶段的时长跟第一电阻器的电阻值和第一电容器的电容值的乘积成正比，从而使得动态放大电路的增益不随PVT变化。
以下，结合图6，详细说明根据本申请实施例的动态放大电路的逻辑时序图。
在第一时间段内(对应于前文所述的第一阶段，或者也可以称为reset阶段)，即t1至t2之间的时间段，第一控制信号为高电平，第一驱动电路输出的第一驱动电压V1为零，第二驱动电压V2为恒定电压值，第三驱动电路输出的第二控制信号为低电平。
需要说明的是，在本申请实施例中，在第一时间段内，第一驱动信号可以输出低电平，也可以输出高电平，图6仅以第一驱动信号为低电平作为示例，只要在第一时间段内，第一控制信号为高电平，第二控制信号为低电平即可。
在第一时间段之后的第二时间段内(对应于前文所述的第二阶段，或者也可以称为放大阶段)，即t2至t3之间的时间段，第一控制信号为低电平，在第二时间段内，第一驱动电路输出的第一驱动电压开始增大，但仍小于第二驱动电压，第二驱动电路根据第一驱动电压和第二驱动电压输出的第一驱动信号仍为低电平，第三驱动电路根据第一控制信号和第一驱动信号输出的第二控制信号为高电平。
在第二时间段之后的第三时间段，即t3之后的时间段，第一控制信号为低电平，第一驱动电路输出的第一驱动电压大于或等于第二驱动电压，第二驱动电路输出的第一驱动信号由低电平转变为高电平，第三驱动电路输出的第二控制信号从高电平转变为低电平。
也就是说，本申请实施例的第一驱动电路可以根据第一控制信号输出第 一驱动电压V1，其中，在第一时间段内，V1＝0，在第二时间段内，V1开始增大，但是依然小于第二驱动电压V2，在第三时间段内，V1增大到大于或等于V2，即第二时间段和第三时间段的分界线为V1等于V2的时刻，即t3。
可选地，在第三时间段内，V1可以增大到等于V2之后不再增大，或者，也可以在等于V2之后继续增大到某个电压值后不再增大等，本申请实施例并不限定第一驱动电压在第三时间段内的电压值的大小，只要第一驱动信号在V1等于V2的时刻发生翻转即可。
进一步地，第二驱动电路能够根据随时间变化的第一驱动电压和第二驱动电压输出第一驱动信号，即在第一驱动电压小于第二驱动电压时，输出低电平，在第一驱动电压大于或等于第二驱动电压时，输出高电平。
例如，第二驱动电路可以用比较器实现，具体地，该比较器可以为连续时间比较器。
更进一步地，第三驱动电路根据第一控制信号和第一驱动信号输出第二控制信号，其中，第三驱动电路只需控制在第一控制信号和第一驱动信号都为低电平时，第二控制信号输出高电平，在第一控制信号和第一驱动信号为其他状态时，第二控制信号输出低电平即可。
例如，第三驱动电路可以用反相器和与门的组合电路实现，例如，可以将第一控制信号和第一驱动信号反向后，输入到与门的两个输入端，此时，可以控制在第一控制信号和第一驱动信号都为低电平时，与门的输出端输出高电平，其他状态下，与门的输出端都输出低电平。
因此，本申请实施例的动态放大电路，通过第一控制信号控制第一驱动电路输出的第一驱动电压，进而根据第一驱动电压和第二驱动电压，控制第二时间段的时长TA满足跟DA中的第一电容器的电容值C1和第一电阻器的电阻值R1的乘积成正比，从而使得在PVT变化时，该动态放大电路依然能够提供稳定的增益。
以下，结合图7至图11所示的具体示例，详细介绍本申请实施例的动态放大电路的实现方式。
应理解，图7至图11所示的例子是为了帮助本领域技术人员更好地理解本申请实施例，而非要限制本申请实施例的范围。本领域技术人员根据所给出的图7至图11，显然可以进行各种等价的修改或变化，这样的修改或变化也落入本申请实施例的范围内。
图7是根据本申请实施例的第一驱动电路的一例结构示意图，如图7所示，该第一驱动电路310包括第一电流源311、第三电容器312、第三控制开关313和第四控制开关314，其中，第一电流源311通过第三控制开关313与第三电容器312连接，第四控制开关314与第三电容器312并联，第一电流源311的电流值等于前述的第一驱动电流，第一驱动电流是由第一基准电压作用于第三电阻器上产生的；
可选地，若第一基准电压为VBG，第三电阻器的电阻值为R3，那么第一驱动电流I1＝VBG/R3。
在该实施例中，第一驱动电路310具体用于：
接收第一控制信号，通过第一控制信号控制第三控制开关和第四控制开关的断开和闭合，以及通过第三控制开关控制第一电流源对第三电容器进行充电，产生第一驱动电压。
可选地，在该实施例中，第一控制信号具体用于：
在第一时间段，控制第三控制开关断开，第四控制开关闭合；在第二时间段和第三时间段，控制第三控制开关闭合，第四控制开关断开。
具体而言，在第一时间段内，第三控制开关断开，第四控制开关闭合，第三电容器上的压降为零，即第一驱动电压为零，在t2时刻，第三控制开关闭合，第四控制开关断开，第一电流源开始对第三电容器进行充电，因此，在第二时间段内，第三电容器上的压降即第一驱动电压V1开始增大，直到增大到等于第二驱动电压V2。
从图6所示的时序图可以看出，当V1<V2时，第一驱动信号输出低电平，在t2时刻之后的t3时刻，第一驱动电压等于第二驱动电压，即V1＝V2，此时，第二驱动电路输出的第一驱动信号由低电平翻转为高电平。
因此，t2时刻至t3时刻之间的第二时间段的时长TA，即为第三电容器的电压值从零增大到V2所需的时间，第二时间段的时长TA可以根据公式(6)确定：
TA＝V2*C3/I1        公式(6)
其中，C3为第三电容器312的电容值，I1为第一电流源311的电流值。
由上文描述可知，第二驱动电压可以为基准电压的倍数，即V2＝aVBG，I1＝VBG/R3，将其代入公式(6)可得：
Figure PCTCN2017099594-appb-000011
进一步地，将公式(7)代入公式(5)可得动态放大电路的放大系数Av为：
Figure PCTCN2017099594-appb-000012
如上文所述，第一电阻器和第三电阻器可以为同一种类型的电阻器，第一电容器和第三电容器可以为同一种类型的电容器，那么，在PVT变化时，第一电容器和第三电容器，以及第一电阻器和第三电阻器的变化率相同，即C3/C1为恒定值，R3/R1为恒定值，而系数a可以由设计者控制，不随PVT变化，因此，公式(8)所示的放大系数Av为恒定值，即本申请实施例的动态放大电路的放大系数为不随PVT变化的恒定增益。
以下，结合图8，详细介绍第二驱动电压的产生电路，应理解，图8所示的电路是为了帮助本领域技术人员更好地理解本申请实施例，而非要限制本申请实施例的范围。本领域技术人员也可以根据其他电路产生所述第二驱动电压，本申请实施例对此不作限定。
如图8所示，该电路可以包括：运算放大器801、晶体管802、晶体管803、电阻器804和电阻器805。
其中，晶体管802和晶体管803具有相同的W/L，其中，W为晶体管的栅宽，L为晶体管的栅长。
在该实施例中，运算放大器801的输入端可以接收带隙基准电压VBG，因此，晶体管802上的漏极电流为VBG/R4，其中，R4为电阻器804的电阻值。由于晶体管803和晶体管802上的驱动电压相同，因此，晶体管803的漏极电流和晶体管802的漏极电流相同，因此，电阻器805上的压降为VBG*R5/R4，其中，R5为电阻器805的电阻值，电阻器805上的压降可以作为上述的第二驱动电压，即V2＝R5/R4*VBG，这里的R5/R4可以对应于前文所述的a，可以通过控制电阻器804和电阻器805的电阻值控制a的大小。
跟前述实施例类似，电阻器804和电阻器805可以为同一类型的电阻器，从而在PVT变化时，可以保证R5/R4为恒定值，即a为恒定值。
图9是根据本申请实施例的第二驱动电路的一例示意性结构图，图9示出了第二驱动电路的一种可能的实现方式，或者说，优选的实现方式，但本申请实施例并不限于此实现方式，根据此实现方式的各种等价的修改或变化都落入本申请实施例的范围内。
如图9所示，该第二驱动电路320包括第四电容器321、第一反相器322和第二反相器323。
第四电容器321的一端通过第一开关器件324接收第一驱动电压，以及通过第二开关器件325接收第二驱动电压，第四电容器321的另一端与第一反相器322的输入端连接；
第一反相器322的输入端和输出端通过第三开关器件326连接，第一反相器322的输出端与第二反相器323的输入端连接，第二反相器323的输出端用于输出第一驱动信号。
在该实施例中，第一控制信号用于：
在第一时间段，控制第一开关器件断开，第二开关器件和第三开关器件闭合，在第二时间段和所述第三时间段，控制第一开关器件闭合，第二开关器件和第三开关器件断开。
这样，在t1时刻至t2时刻之间的第一时间段，第一开关器件324断开，第二开关器件325闭合，第三开关器件326闭合，第四电容器321的一端的电压为第二驱动电压V2，另一端的电压为第一反相器322的阈值电压VTH，则第四电容器321上的压降为VTH-V2。
如上文所述，在第一时间段内，我们并不关心第一驱动信号输出低电平还是高电平，只要在第一时间段内，第一控制信号为高电平，第三驱动电路输出的第二控制信号为低电平即可。
在t2时刻至t3时刻之间的第二时间段内，第一开关器件324闭合，第二开关器件325断开，第三开关器件326断开，则第四电容器321的一端的电压为第一驱动电压V1，基于电荷守恒原理，第四电容器321上的压降不变，那么第一反相器的输入端的电压为V1+VTH-V2，由于在第二时间段内，V1<V2，则V1+VTH-V2<VTH，经过第一反相器后，输出高电平，再经过第二反相器后，第一驱动信号输出低电平。
在t3时刻之后的第三时间段内，V1≥V2，则V1+VTH-V2≥VTH，经过第一反相器后，输出低电平，再经过第二反相器反向后，第一驱动信号输出高电平。
可选地，本申请实施例还可以采用其他等效电路来实现第二驱动电路的功能，即只要在第一驱动电压小于第二驱动电压时输出低电平，在第一驱动电压大于或等于第二驱动电压时输出高电平即可。
可选地，在本申请实施例中，由于第一控制信号可以用于控制第一开关器件的闭合和断开，那么第二驱动电路还包括第一控制信号的输入端，用于输入第一控制信号，从而通过第一控制信号控制第一开关器件、第二开关器件和第三开关器件的闭合和断开。
应理解，在本申请实施例中，第一控制信号用于控制第一开关器件、第二开关器件、第三开关器件和第一控制开关的闭合和断开，以及第二控制信号用于控制第二控制开关的闭合和断开，仅表示控制信号具有控制各自对应的开关器件的功能，并非表示这些控制信号的输入端与各自对应的开关器件一定存在直接的连接关系。只要保证输入的控制信号可以控制对应的开关器件的闭合和断开即可。
图10是根据本申请实施例的第二驱动电路的另一例的示意性结构图，如图10所示，第二驱动电路320为连续时间比较器327，连接时间比较器327的第一输入端用于接收第一驱动电压V1，连接时间比较器的第二输入端用于接收第二驱动电压V2，连续时间比较器327的输出端用于输出第一驱动信号。
具体地，在第一时间段和第二时间段内，V1<V2，连续时间比较器327输出低电平；
在第三时间段内，V1≥V2，连续时间比较器327的输出电压由低电平翻转为高电平。
因此，图10所示的连续时间比较器和图9所示的组合电路都可以实现第二驱动电路的功能，即在第一驱动电压小于第二驱动电压时输出低电平，在第一驱动电压大于或等于第二驱动电压时输出高电平，图9所示的组合电路相对于图10所示的连续时间比较器而言，不必进行连续的比较，因此功耗相对较低。
图11是根据本申请实施例的第三驱动电路的一例结构示意图，如图11所示，第三驱动电路330包括第三反相器331、第四反相器332和求与电路333。
第三反相器331的输入端用于接收第一控制信号，第三反相器331的输出端与求与电路333的第一输入端连接；
第四反相器332的输入端用于接收第一驱动信号，第四反相器332的输出端与求与电路333的第二输入端连接；
求与电路333的输出端用于输出第二控制信号。
因此，图11所示的第三驱动电路可以控制在第一控制信号和第一驱动信号都为低电平时，第二控制信号才输出高电平，当第一控制信号和第一驱动信号为其他工作状态时，第二控制信号输出低电平。
可选地，求与电路333可以用与门，或者其他等效电路来实现。
因此，本申请实施例的动态放大电路，通过第一控制信号控制第一驱动电压输出的电压值，进而根据第一驱动电压和第二驱动电压，控制第二时间段的时长满足跟DA中的电容器的电容值和电阻器的电阻值的乘积成正比，从而使得在PVT变化时，该动态放大电路依然能够提供相对稳定的增益。
应理解，本文中涉及的第一、第二、第三、第四以及各种数字编号(例如第一驱动电路310和第二驱动电路320等)仅为描述方便进行的区分，并不用来限制本申请实施例的保护范围。
在上述实施例中涉及的电源的负极可以设置为地电位(即接地)，当然在具体实现中可以为其他电位如负电位，本申请实施例对此不作限制。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (17)

  1. 一种动态放大电路，其特征在于，包括：
    第一驱动电路，用于根据第一控制信号和第一驱动电流，产生第一驱动电压，所述第一驱动电流是由第一基准电压产生的，所述第一基准电压为恒定电压；
    第二驱动电路，用于根据所述第一驱动电压和第二驱动电压，产生第一驱动信号，其中，所述第一驱动电压随时间变化，所述第二驱动电压为所述第一基准电压的倍数；
    第三驱动电路，用于根据所述第一控制信号和所述第一驱动信号，产生第二控制信号；
    动态放大器DA，包括第一支路和第二支路，所述第一支路包括第一电容器，所述第二支路包括第二电容器，所述第一电容器和所述第二电容器为相同的电容器，所述第一支路和所述第二支路通过第一电阻器和第二电阻器连接，所述第一电阻器和所述第二电阻器为相同的电阻器；
    所述DA，用于接收所述第一控制信号和所述第二控制信号，通过所述第一控制信号和所述第二控制信号控制所述DA的工作状态，其中，所述DA处于放大阶段的时长跟所述第一电阻器的电阻值和所述第一电容器的电容值的乘积成正比。
  2. 根据权利要求1所述的动态放大电路，其特征在于，所述第一支路包括第一控制开关、第二控制开关和第一晶体管；
    所述DA具体用于：
    接收所述第一控制信号和所述第二控制信号，通过所述第一控制信号和所述第二控制信号分别控制所述第一控制开关和所述第二控制开关的闭合和断开。
  3. 根据权利要求2所述的动态放大电路，其特征在于，所述第一控制信号的工作状态为：
    在第一时间段，所述第一控制信号输出高电平；
    在所述第一时间段之后的第二时间段内，所述第一控制信号输出低电平，所述第二时间段的时长为所述DA处于放大阶段的时长；
    在所述第二时间段之后的第三时间段内，所述第一控制信号输出低电平。
  4. 根据权利要求3所述的动态放大电路，其特征在于，所述第一驱动电路具体用于：
    在所述第一时间段，控制输出的所述第一驱动电压为零；
    在所述第二时间段内，控制输出的所述第一驱动电压开始增大，但小于所述第二驱动电压；
    在所述第三时间段内，控制输出的所述第一驱动电压大于或等于所述第二驱动电压。
  5. 根据权利要求4所述的动态放大电路，其特征在于，所述第一驱动电路包括第一电流源和第三电容器；
    所述第一电流源用于：在所述第二时间段和所述第三时间段内，对所述第三电容器进行充电，所述第三电容器上的压降为所述第一驱动电压，其中，所述第一电流源的电流值等于所述第一驱动电流，所述第一驱动电流是由所述第一基准电压作用于第三电阻器上产生的。
  6. 根据权利要求5所述的动态放大电路，其特征在于，所述动态放大电路的放大系数与R3*C3/(R1*C1)成正比，其中，R3为所述第三电阻器的电阻值，C3为所述第三电容器的电容值，R1为所述第一电阻器的电阻值，C1为所述第一电容器的电容值。
  7. 根据权利要求6所述的动态放大电路，其特征在于，所述第一电阻器、所述第二电阻器和所述第三电阻器为同一种类型的电阻器，所述第一电容器、所述第二电容器和所述第三电容器为同一种类型的电容器。
  8. 根据权利要求3至7中任一项所述的动态放大电路，其特征在于，所述第二驱动电路具体用于：
    在所述第二时间段内，控制输出的所述第一驱动信号为低电平；
    在所述第三时间段内，控制输出的所述第一驱动信号为高电平。
  9. 根据权利要求8所述的动态放大电路，其特征在于，所述第二驱动电路包括第四电容器、第一反相器和第二反相器；
    所述第四电容器的一端通过第一开关器件接收所述第一驱动电压，以及通过第二开关器件接收所述第二驱动电压，所述第四电容器的另一端与所述第一反相器的输入端连接；
    所述第一反相器的输入端和输出端通过第三开关器件连接，所述第一反相器的输出端与所述第二反相器的输入端连接，所述第二反相器的输出端用 于输出所述第一驱动信号。
  10. 根据权利要求9所述的动态放大电路，其特征在于，所述第一控制信号还用于：
    控制所述第一开关器件、所述第二开关器件和所述第三开关器件的闭合与断开；
    其中，所述第一控制信号具体用于：
    在所述第一时间段，控制所述第一开关器件断开，所述第二开关器件和所述第三开关器件闭合，在所述第二时间段和所述第三时间段，控制所述第一开关器件闭合，所述第二开关器件和所述第三开关器件断开。
  11. 根据权利要求8所述的动态放大电路，其特征在于，所述第二驱动电路为连续时间比较器，所述连接时间比较器的第一输入端用于接收所述第一驱动电压，所述连接时间比较器的第二输入端用于接收所述第二驱动电压，所述连续时间比较器的输出端用于输出所述第一驱动信号。
  12. 根据权利要求3至11中任一项所述的动态放大电路，其特征在于，所述第三驱动电路具体用于：
    在所述第一时间段，控制所述第二控制信号输出低电平；
    在所述第二时间段内，控制所述第二控制信号输出高电平；
    在所述第三时间段内，控制所述第二控制信号输出低电平。
  13. 根据权利要求12所述的动态放大电路，其特征在于，所述第三驱动电路包括第三反相器、第四反相器和求与电路；
    所述第三反相器的输入端用于接收所述第一控制信号，所述第三反相器的输出端与所述求与电路的第一输入端连接；
    所述第四反相器的输入端用于接收所述第一驱动信号，所述第四反相器的输出端与所述求与电路的第二输入端连接；
    所述求与电路的输出端用于输出所述第二控制信号。
  14. 根据权利要求1至13中任一项所述的动态放大电路，其特征在于，所述第一基准电压是带隙基准电压。
  15. 根据权利要求3至14中任一项所述的动态放大电路，其特征在于，所述第一控制信号具体用于：
    在所述第一时间段，控制所述第一控制开关闭合，在所述第二时间段和所述第三时间段，控制所述第一控制开关断开；
    所述第二控制信号具体用于：
    在所述第一时间段，控制所述第二控制开关断开，在所述第二时间段，控制所述第二控制开关闭合，在所述第三时间段，控制所述第二控制开关断开。
  16. 根据权利要求1至15中任一项所述的动态放大电路，其特征在于，所述第一支路包括第一晶体管，所述第二支路包括第二晶体管，所述第一晶体管的源级和所述第二晶体管的源级通过所述第一电阻器和所述第二电阻器连接。
  17. 根据权利要求16所述的动态放大电路，其特征在于，所述第一晶体管处于饱和区的跨导与所述第一电阻器的电阻值的乘积大于倍数阈值。
PCT/CN2017/099594 2017-08-30 2017-08-30 动态放大电路 WO2019041156A1 (zh)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CN201780001051.8A CN109729758B (zh) 2017-08-30 2017-08-30 动态放大电路
EP17905899.5A EP3477863B1 (en) 2017-08-30 2017-08-30 Dynamic amplifying circuit
PCT/CN2017/099594 WO2019041156A1 (zh) 2017-08-30 2017-08-30 动态放大电路
US16/147,857 US10693423B2 (en) 2017-08-30 2018-09-30 Dynamic amplification circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2017/099594 WO2019041156A1 (zh) 2017-08-30 2017-08-30 动态放大电路

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US16/147,857 Continuation US10693423B2 (en) 2017-08-30 2018-09-30 Dynamic amplification circuit

Publications (1)

Publication Number Publication Date
WO2019041156A1 true WO2019041156A1 (zh) 2019-03-07

Family

ID=65437888

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/099594 WO2019041156A1 (zh) 2017-08-30 2017-08-30 动态放大电路

Country Status (4)

Country Link
US (1) US10693423B2 (zh)
EP (1) EP3477863B1 (zh)
CN (1) CN109729758B (zh)
WO (1) WO2019041156A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI761274B (zh) * 2021-08-04 2022-04-11 瑞昱半導體股份有限公司 電荷引導式放大電路及其控制方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6988409B2 (en) * 2003-03-25 2006-01-24 Denso Corporation Dynamic quantity sensor
CN101364119A (zh) * 2008-07-07 2009-02-11 武汉大学 宽动态范围低压差线性稳压器
CN101515798A (zh) * 2008-02-18 2009-08-26 瑞昱半导体股份有限公司 动态电压产生装置与其使用方法
CN205646432U (zh) * 2016-03-08 2016-10-12 西安绿竹电子科技有限公司 一种半导体激光器驱动电路

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5202645A (en) * 1991-12-12 1993-04-13 National Semiconductor Corporation Stabilized transient response of a cascode CMOS amplifier
US5475342A (en) * 1993-04-19 1995-12-12 Nippon Telegraph And Telephone Corporation Amplifier for stably maintaining a constant output
US6653895B1 (en) * 2002-06-12 2003-11-25 Texas Instruments Incorporated Gain-boost nulling amplifier for auto-zero circuit
CN101471636B (zh) * 2007-12-26 2011-11-23 财团法人工业技术研究院 可变增益高动态范围放大器
JP5618733B2 (ja) * 2009-12-09 2014-11-05 ローム株式会社 半導体装置及びこれを用いたスイッチングレギュレータ
US8633764B2 (en) * 2011-06-10 2014-01-21 International Business Machines Corporation Restoring output common-mode of amplifier via capacitive coupling
US8964825B2 (en) * 2012-02-17 2015-02-24 International Business Machines Corporation Analog signal current integrators with tunable peaking function

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6988409B2 (en) * 2003-03-25 2006-01-24 Denso Corporation Dynamic quantity sensor
CN101515798A (zh) * 2008-02-18 2009-08-26 瑞昱半导体股份有限公司 动态电压产生装置与其使用方法
CN101364119A (zh) * 2008-07-07 2009-02-11 武汉大学 宽动态范围低压差线性稳压器
CN205646432U (zh) * 2016-03-08 2016-10-12 西安绿竹电子科技有限公司 一种半导体激光器驱动电路

Also Published As

Publication number Publication date
EP3477863A4 (en) 2019-05-08
EP3477863B1 (en) 2022-05-04
EP3477863A1 (en) 2019-05-01
US20190068130A1 (en) 2019-02-28
US10693423B2 (en) 2020-06-23
CN109729758B (zh) 2023-05-26
CN109729758A (zh) 2019-05-07

Similar Documents

Publication Publication Date Title
KR20190141868A (ko) 발진기
TWI430564B (zh) Differential amplifier
US7312651B2 (en) Cascode current mirror circuit operable at high speed
TWI623194B (zh) 運算放大器及其差分放大電路
JP5038710B2 (ja) レベル変換回路
KR100877626B1 (ko) 클래스 ａｂ 증폭기 및 이를 위한 입력 스테이지 회로
WO2017049710A1 (zh) 一种环路补偿电路及开关电源电路
US20080048728A1 (en) Stable sense amplifier
JP2010136001A (ja) 発振器
JP2015146497A (ja) 増幅回路
KR101362474B1 (ko) Cmos 서브밴드갭 기준발생기
TW201931045A (zh) 電流產生電路
WO2019041156A1 (zh) 动态放大电路
TW201605174A (zh) 高速時脈比較器與其方法
US8482317B2 (en) Comparator and method with adjustable speed and power consumption
JP4773991B2 (ja) ソースフォロア回路及び半導体装置
CN111800101A (zh) 用于运算放大器的转换升压电路
CN110710105B (zh) 放大器装置和具有这种放大器装置的传感器装置
JP2007189600A (ja) のこぎり波発生回路
US9432015B2 (en) Hysteresis comparator circuit having differential input transistors with switched bulk bias voltages
US9755588B2 (en) Signal output circuit
JP4331550B2 (ja) 位相補償回路
JP2008017566A (ja) 電源発生回路
Gajjar et al. Analysis of CMOS second generation current conveyors
US9130547B1 (en) Rail-to-rail comparator circuit and method thereof

Legal Events

Date Code Title Description
ENP Entry into the national phase

Ref document number: 2017905899

Country of ref document: EP

Effective date: 20181022

NENP Non-entry into the national phase

Ref country code: DE