WO2018157438A1 - 阵列基板测试电路及其制作方法、显示面板 - Google Patents

阵列基板测试电路及其制作方法、显示面板 Download PDF

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Publication number
WO2018157438A1
WO2018157438A1 PCT/CN2017/079441 CN2017079441W WO2018157438A1 WO 2018157438 A1 WO2018157438 A1 WO 2018157438A1 CN 2017079441 W CN2017079441 W CN 2017079441W WO 2018157438 A1 WO2018157438 A1 WO 2018157438A1
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Prior art keywords
display unit
display
test
array
test electrode
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Ceased
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PCT/CN2017/079441
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English (en)
French (fr)
Inventor
王倩
虞晓江
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Publication of WO2018157438A1 publication Critical patent/WO2018157438A1/zh
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Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/282—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere
    • G01R31/2825—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere in household appliances or professional audio/video equipment
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136254—Checking; Testing
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an array substrate test circuit, a method for fabricating the same, and a display panel.
  • LTPS Low Temperature Poly Silicon
  • TFT LCD Thin Film Transistor Liquid Crystal Display, thin film transistor liquid crystal display
  • LTPS TFT The LCD has the advantages of high resolution, fast response speed, high brightness, high aperture ratio, etc.
  • LTPS TFT The array process in the LCD is uniformly arranged on a large glass substrate to form an array circuit. After the array test item is passed and the standard is reached, the glass substrate is cut into a cutting section in the subsequent box process. Batch display units, each display unit has a separate array circuit for controlling the display of the final finished LCD panel.
  • LTPS TFT LCD panel in one of the array circuit structure design, for a single display unit (as shown in Figure 1 and Figure 2), through several vertical metal traces running through the left and right sides of the display area (collectively referred to as array substrate test) Aligning the array test circuit related signals located above the display area to the boxed test circuit located below the display area to drive the output of the vertical display signal by using part of the line of the test circuit of the box to complete the array test project.
  • the longitudinal array substrate test traces and the horizontal metal traces at the edge of the display area are always vertically staggered.
  • the staggered positional relationship causes the lateral display signals to be affected by the coupling, causing Display differences on the left and right sides of the display panel; in addition, leakage may occur in staggered positions, and even abnormal problems such as damage may occur, which may affect the yield of the display panel.
  • the technical problem to be solved by the present invention is to provide an array substrate test circuit and method thereof, and a display panel, which avoids staggering the metal traces of the array substrate test traces and the edge of the display area, thereby reducing the occurrence of coupling, leakage, and damage. Thereby achieving the purpose of improving the production yield of the display panel.
  • a technical solution adopted by the present invention is to provide an array substrate test circuit, the array substrate test circuit is disposed on a substrate, the substrate includes at least two display units, and the at least two displays
  • the unit includes a first display unit and a second display unit, each of the first and second display units includes an array test electrode area and a boxed test electrode area, the array test electrode area includes a plurality of array test electrodes, and the box is formed
  • the test electrode area includes a plurality of cassette test electrodes, and the box test electrodes of the first display unit are electrically connected to the array test electrodes of the second display unit in one-to-one correspondence to pass the box test of the first display unit.
  • the electrode area drives the output of the display signal.
  • a display panel includes an array substrate test circuit, and the array substrate test circuit is disposed on a substrate, and the substrate includes at least two a display unit, the at least two display units include a first display unit and a second display unit, the first and second display units each include an array test electrode region and a boxed test electrode region, and the array test electrode region includes a plurality of array test electrodes, the boxed test electrode region includes a plurality of cassette test electrodes, and the box test electrode of the first display unit and the array test electrode of the second display unit are electrically connected in one-to-one correspondence to pass through The boxed test electrode region of the first display unit drives the output of the display signal.
  • another technical solution adopted by the present invention is to provide a method for fabricating an array substrate test circuit, the method comprising:
  • the at least two display units comprising a first display unit and a second display unit;
  • An array test electrode region and a box test electrode region are disposed on the first and second display units, the array test electrode region includes a plurality of array test electrodes, and the box test electrode region includes a plurality of boxed test electrodes;
  • the box-shaped test electrodes of the first display unit are electrically connected to the array test electrodes of the second display unit in a one-to-one correspondence to drive the output of the display signals through the cassette test electrode regions of the first display unit.
  • the array substrate test circuit of the present invention electrically connects the boxed test electrode of the first display unit of the at least two display units to the Array test electrodes of the second display unit to avoid a staggered positional relationship between the longitudinal array test traces and the lateral metal traces at the edges of the display area, thereby controlling the display signals by the boxed test electrodes of the first display unit Output, thereby completing the array test item of the first display unit, reducing the occurrence of coupling, leakage and damage, thereby achieving the purpose of improving the production yield of the display panel.
  • FIG. 1 is a schematic structural view of a display unit of the prior art
  • FIG. 2 is a schematic structural view of a prior art array substrate test circuit
  • FIG. 3 is a schematic structural view of a first embodiment of an array substrate test circuit of the present invention.
  • FIG. 4 is a schematic structural view of a second embodiment of an array substrate test circuit of the present invention.
  • FIG. 5 is a schematic structural view of a third embodiment of an array substrate test circuit of the present invention.
  • FIG. 6 is a schematic structural view of a display panel of the present invention.
  • FIG. 7 is a flow chart showing a method of fabricating an array substrate test circuit of the present invention.
  • FIG. 1 and FIG. 2 are schematic structural diagrams of an array substrate test circuit of a display unit in the prior art.
  • a plurality of array test electrodes located above the display area of each display unit in FIG. 1 such as four array test electrodes 1 respectively connected to display areas located in the same display unit via longitudinal metal traces 3 running through the left and right sides of the display area
  • the lower four test boxes 2, the four metal wires 3 ie, the array substrate test traces
  • the lateral metal traces not shown
  • the staggered positional relationship causes the horizontal display signals to be affected by the coupling, causing display differences on the left and right sides of the display panel, and the staggered positions may also leak, and may even cause abnormal problems such as damage, so that the display panel The yield is affected.
  • FIG. 3 is a schematic structural diagram of a first embodiment of the array substrate test circuit of the present invention.
  • the array substrate test circuit is disposed on the substrate 20, the substrate 20 includes at least two display units 10, and the at least two display units 10 include a first display unit and a second display unit, the first and second
  • the display unit includes an array test electrode region 11 and a cassette test electrode region 12, the array test electrode 11 region includes a plurality of array test electrodes 111, and the cassette test electrode region 12 includes a plurality of cassette test electrodes 121,
  • the cassette test electrodes 121 of a display unit are electrically connected in one-to-one correspondence with the array test electrodes 111 of the second display unit to drive the output of the display signals through the cassette test electrode regions 12 of the first display unit.
  • the first display unit and the second display unit each include a display area 13 , the array test electrode area 11 is located above the display area 13 , and the boxed test electrode area 12 is located on the display. Below the area 13.
  • the display area 13 refers to an area of the array substrate which is inside the sealant when the cassette is formed, and this area is used to fill the liquid crystal to display an image.
  • Other components and functions of the first and second display units are the same as those in the prior art, and are not described herein again.
  • the array test electrode region 11 includes four array test electrodes 111, and the boxed electrode region 12 includes four packaged test electrodes 121.
  • the The number of array test electrodes 111 and the set of test electrodes 121 can be set as needed.
  • the second display unit is located directly below the first display unit.
  • the array test traces 14 electrically connected to the array test electrodes 121 of the first display unit and the array test electrodes 111 of the second display unit are all cut off in the cutting process to ensure that the array test items are normal.
  • the longitudinal array test trace 14 on the display signal of the lateral direction of the display area including the leakage of the leakage and the staggered position
  • the array test area in the subsequent cutting process can be effectively eliminated.
  • the resulting electrostatic damage affects the boxed test project.
  • the array substrate test circuit is electrically connected to the array test electrode of the first display unit of the at least two display units to the array test electrode of the second display unit to avoid longitudinal array test traces and
  • the lateral metal traces at the edge of the display area generate an interlaced positional relationship, thereby controlling the output of the display signal through the boxed test electrodes of the first display unit, thereby completing the array test item of the first display unit, reducing coupling
  • the occurrence of leakage and damage problems has been achieved to improve the production yield of the display panel.
  • FIG. 4 is a structural diagram of a second embodiment of the array substrate test circuit of the present invention.
  • the second embodiment of the array substrate test circuit is different from the above-described first embodiment in that the second display unit is located on the right side of the first display unit.
  • the second display unit may also be located on the left side of the first display unit, and the connection relationship and working principle are the same as those in the foregoing embodiment, and details are not described herein again.
  • FIG. 5 is a structural diagram of a third embodiment of the array substrate test circuit of the present invention.
  • the third embodiment of the array substrate test circuit is different from the above first or second embodiment in that the second display unit is located at the lower left of the first display unit.
  • the second display unit may also be located at the lower right of the first display unit, and its connection relationship and working principle are the same as those of the foregoing embodiment, and details are not described herein again.
  • the specific positions of the first and second display units will change, specifically
  • the package test electrode 121 of a display unit is electrically connected to the array test electrode 111 of the second display unit with the shortest trace, and the box test of the first display unit can be tested in a subsequent box test item.
  • the routing of the electrodes 121 electrically connected to the array test electrodes 111 of the second display unit is optimal. Therefore, the specific positional relationship between the first and second display units is not limited to the embodiment of the present invention. Field technicians can make changes and settings according to specific needs.
  • FIG. 6 is a structural diagram of a display panel according to the present invention.
  • the display panel includes the foregoing array substrate test circuit, and other devices and functions in the display panel are the same as those of the existing display panel, and are not described herein again.
  • FIG. 7 is a schematic flow chart of a method for fabricating an array substrate test circuit of the present invention. The method includes:
  • Step S1 providing a substrate 20.
  • the substrate 20 is a glass substrate, and other devices and functions on the substrate are the same as those of the prior art substrate, and details are not described herein again.
  • Step S2 at least two display units 10 are disposed on the substrate 20, and the at least two display units include a first display unit and a second display unit.
  • Step S3 arranging an array test electrode region 11 and a cassette test electrode region 12 on the first and second display units, the array test electrode region 11 includes a plurality of array test electrodes 111, and the box test electrode region 12 includes a number of cassette test electrodes 121.
  • the second display unit is located directly below the first display unit, or the second display unit is located on the left or right side of the first display unit; or the second display unit is located at the The lower left or lower right of the first display unit.
  • the step of providing the array test electrode region 11 and the box-forming test electrode region 12 on the first and second display units is specifically that the first display unit and the second display unit each include a display area 13
  • the array test electrode region 11 is located above the display region 13, and the cassette test electrode region 12 is located below the display region 13.
  • Step S4 electrically connecting the box test electrode 121 of the first display unit and the array test electrode 111 of the second display unit in one-to-one correspondence to be driven by the box test electrode region 12 of the first display unit Displays the output of the signal.
  • the array substrate test circuit is electrically connected to the array test electrode of the first display unit of the at least two display units to the array test electrode of the second display unit to avoid longitudinal array test traces and
  • the lateral metal traces at the edge of the display area generate an interlaced positional relationship, thereby controlling the output of the display signal through the boxed test electrodes of the first display unit, thereby completing the array test item of the first display unit, reducing coupling
  • the occurrence of leakage and damage problems has been achieved to improve the production yield of the display panel.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • General Engineering & Computer Science (AREA)
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Abstract

一种阵列基板测试电路及其制作方法、显示面板，阵列基板测试电路设置于基板（20）上，基板（20）包括至少两个显示单元（10），至少两个显示单元（10）包括第一及第二显示单元，第一及第二显示单元均包括阵列测试电极区（11）及成盒测试电极区（12），第一显示单元的成盒测试电极（121）与第二显示单元的阵列测试电极（111）一一对应电连接，以通过第一显示单元的成盒测试电极区（12）驱动显示信号的输出。

Description

阵列基板测试电路及其制作方法、显示面板
【技术领域】
本发明涉及显示技术领域，特别是涉及一种阵列基板测试电路及其制作方法、显示面板。
【背景技术】
LTPS（Low temperature Poly Silicon，低温多晶硅）TFT LCD（Thin Film Transistor Liquid Crystal Display，薄膜晶体管液晶显示器）近年来在手机上得到广泛应用，其高电路整合特性与低成本的优势，在中小尺寸显示面板的应用中有着绝对的优势。LTPS TFT LCD具有高分辨率、反应速度快、高亮度、高开口率等优点，通过将外围驱动电路同时制作在玻璃基板上，达到系统整合的目标、节省空间及驱动芯片的成本。
LTPS TFT LCD中的阵列制程是在一块很大的玻璃基板上均匀有序排布形成一个个阵列电路，所述玻璃基板在经过阵列测试项目并达标后，将在后续成盒制程的切割段被切割成一批小片的显示单元，每个显示单元都有一个独立的阵列电路，用于控制最终成品LCD面板的显示。
LTPS TFT LCD面板在其中一种阵列线路结构设计中，对于单个显示单元来说（如图1及图2所示），通过几根贯穿于显示区域左右两侧的纵向金属走线（统称为阵列基板测试走线），将位于显示区域上方的阵列测试电路相关信号连接到位于显示区域下方的成盒测试电路中，以借用成盒测试电路的部分线路来驱动纵向的显示信号的输出，从而完成阵列测试项目。这几根纵向的阵列基板测试走线与显示区域边缘的横向金属走线始终呈垂直交错的位置关系，在成盒测试项目中，这种交错的位置关系使横向的显示信号受到耦合影响，引起显示面板左右两侧的显示差异；另外交错位置也可能发生漏电，甚至会产生炸伤等异常问题，使显示面板的良率受到影响。
【发明内容】
本发明主要解决的技术问题是提供一种阵列基板测试电路及其方法、显示面板，避免阵列基板测试走线与显示区域边缘的金属走线产生交错，减少耦合、漏电及炸伤问题的发生，从而达到提升显示面板生产良率的目的。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种阵列基板测试电路，所述阵列基板测试电路设置于基板上，所述基板包括至少两个显示单元，所述至少两个显示单元包括第一显示单元及第二显示单元，所述第一及第二显示单元均包括阵列测试电极区及成盒测试电极区，所述阵列测试电极区包括若干阵列测试电极，所述成盒测试电极区包括若干成盒测试电极，所述第一显示单元的成盒测试电极与所述第二显示单元的阵列测试电极一一对应电连接，以通过所述第一显示单元的成盒测试电极区驱动显示信号的输出。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种显示面板，所述显示面板包括阵列基板测试电路，所述阵列基板测试电路设置于基板上，所述基板包括至少两个显示单元，所述至少两个显示单元包括第一显示单元及第二显示单元，所述第一及第二显示单元均包括阵列测试电极区及成盒测试电极区，所述阵列测试电极区包括若干阵列测试电极，所述成盒测试电极区包括若干成盒测试电极，所述第一显示单元的成盒测试电极与所述第二显示单元的阵列测试电极一一对应电连接，以通过所述第一显示单元的成盒测试电极区驱动显示信号的输出。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种阵列基板测试电路的制作方法，所述方法包括：
提供一基板；
在所述基板上设置至少两个显示单元，所述至少两个显示单元包括第一显示单元及第二显示单元；
在所述第一及第二显示单元上均设置阵列测试电极区及成盒测试电极区，所述阵列测试电极区包括若干阵列测试电极，所述成盒测试电极区包括若干成盒测试电极；及
将所述第一显示单元的成盒测试电极与所述第二显示单元的阵列测试电极一一对应电连接，以通过所述第一显示单元的成盒测试电极区驱动显示信号的输出。
本发明的有益效果是：区别于现有技术的情况，本发明的所述阵列基板测试电路通过将所述至少两个显示单元中的第一显示单元的成盒测试电极电性连接至所述第二显示单元的阵列测试电极，以避免纵向的阵列测试走线与显示区域边缘的横向金属走线产生交错的位置关系，以此通过所述第一显示单元的成盒测试电极控制显示信号的输出，从而完成对所述第一显单元的阵列测试项目，减少耦合、漏电及炸伤问题的发生，从而达到提升显示面板生产良率的目的。
【附图说明】
图1是现有技术的一个显示单元的结构示意图；
图2是现有技术的阵列基板测试电路的结构示意图；
图3是本发明的阵列基板测试电路的第一实施例的结构示意图；
图4是本发明的阵列基板测试电路的第二实施例的结构示意图；
图5是本发明的阵列基板测试电路的第三实施例的结构示意图；
图6是本发明的显示面板的结构示意图；
图7是本发明的阵列基板测试电路的制作方法的流程示意图。
【具体实施方式】
请参阅图1及图2，是现有技术中显示单元的阵列基板测试电路的结构示意图。图1中位于每个显示单元的显示区域上方的若干阵列测试电极，如四个阵列测试电极1分别经由贯穿于显示区域左右两侧的纵向金属走线3分别连接到位于同一显示单元的显示区域下方的四个成盒测试电极2，这四根金属线3（即阵列基板测试走线）都与显示区域边缘的横向的金属走线（未示出）呈垂直交错的位置关系，在成盒测试项目中，这种交错的位置关系使横向的显示信号受到耦合影响，引起显示面板左右两侧的显示差异，另外交错位置也可能发生漏电，甚至会产生炸伤等异常问题，使显示面板的良率受到影响。
请参考图3，是本发明的阵列基板测试电路的第一实施例的结构示意图。所述阵列基板测试电路设置于基板20上，所述基板20包括至少两个显示单元10，所述至少两个显示单元10包括第一显示单元及第二显示单元，所述第一及第二显示单元均包括阵列测试电极区11及成盒测试电极区12，所述阵列测试电极11区包括若干阵列测试电极111，所述成盒测试电极区12包括若干成盒测试电极121，所述第一显示单元的成盒测试电极121与所述第二显示单元的阵列测试电极111一一对应电连接，以通过所述第一显示单元的成盒测试电极区12驱动显示信号的输出。
具体地，所述第一显示单元及所述第二显示单元均包括显示区域13，所述阵列测试电极区11位于所述显示区域13的上方，所述成盒测试电极区12位于所述显示区域13的下方。其中，在本发明所有实施例中，显示区域13是指阵列基板在成盒时处于密封胶内侧的区域，此区域用于填充液晶以显示图像。所述第一及第二显示单元的其他元件及功能与现有技术相同，在此不再赘述。
其中，在本发明的所有实施例中，所述阵列测试电极区11包括四个阵列测试电极111，所述成盒电极区12包括四个成盒测试电极121，在其他实施例中，所述阵列测试电极111及成盒测试电极121的数量可以根据需要进行设置。
在本实施例中，所述第二显示单元位于所述第一显示单元的正下方。
将所述第一显示单元的成盒测试电极121与所述第二显示单元的阵列测试电极111一一对应电连接的阵列测试走线14在切割制程中被全部切断，以保证阵列测试项目正常完成的前提下，不仅能避免纵向的阵列测试走线14对于显示区域边缘横向的显示信号的影响（包括漏电及交错位置发生炸伤的问题），而且能有效地消除后续切割过程中阵列测试区域产生的静电击伤对于成盒测试项目造成的影响。
所述阵列基板测试电路通过将所述至少两个显示单元中的第一显示单元的成盒测试电极电性连接至所述第二显示单元的阵列测试电极，以避免纵向的阵列测试走线与显示区域边缘的横向金属走线产生交错的位置关系，以此通过所述第一显示单元的成盒测试电极控制显示信号的输出，从而完成对所述第一显单元的阵列测试项目，减少耦合、漏电及炸伤问题的发生，从而达到提升显示面板生产良率的目的。
请参阅图4，是本发明的阵列基板测试电路的第二实施例的结构示意图。所述阵列基板测试电路的第二实施例与上述第一实施例的区别之处在于：所述第二显示单元位于所述第一显示单元的右侧。
在其他实施例中，所述第二显示单元也可位于所述第一显示单元的左侧，其连接关系及工作原理与上述实施例相同，在此不再赘述。
请参阅图5，是本发明的阵列基板测试电路的第三实施例的结构示意图。所述阵列基板测试电路的第三实施例与上述第一或第二实施例的区别之处在于：所述第二显示单元位于所述第一显示单元的左下方。
在其他实施例中，所述第二显示单元也可位于所述第一显示单元的右下方，其连接关系及工作原理与上述实施例相同，在此不再赘述。
在其他实施例中根据所述第一及第二显示单元中阵列测试电极111及成盒测试电极121设置位置的不同，所述第一与第二显示单元的具体位置将发生变化，具体以第一显示单元的成盒测试电极121电性连接至所述第二显示单元的阵列测试电极111的走线为最短、且在后续成盒测试项目中能将所述第一显示单元的成盒测试电极121电性连接至所述第二显示单元的阵列测试电极111的走线切断为最佳，因此所述第一及第二显示单元的具体位置关系并不限定于本发明的实施例，本领域技术人员可以根据具体需要进行变更和设置。
请参阅图6，为本发明一种显示面板的结构示意图。所述显示面板包括前述的阵列基板测试电路，所述显示面板中的其他器件及功能与现有显示面板的器件及功能相同，在此不再赘述。
请参阅图7，是本发明的阵列基板测试电路的制作方法的流程示意图。所述方法包括：
步骤S1：提供一基板20。
具体地，所述基板20为玻璃基板，所述基板上的其他器件及功能与现有技术的基板相同，在此不再赘述。
步骤S2：在所述基板20上设置至少两个显示单元10，所述至少两个显示单元包括第一显示单元及第二显示单元。
步骤S3：在所述第一及第二显示单元上均设置阵列测试电极区11及成盒测试电极区12，所述阵列测试电极区11包括若干阵列测试电极111，所述成盒测试电极区12包括若干成盒测试电极121。
具体地，所述第二显示单元位于所述第一显示单元的正下方，或者所述第二显示单元位于所述第一显示单元的左侧或右侧；或者所述第二显示单元位于所述第一显示单元的左下方或者右下方。
其中，在所述第一及第二显示单元上均设置阵列测试电极区11及成盒测试电极区12的步骤具体为所述第一显示单元及所述第二显示单元均包括显示区域13，所述阵列测试电极区11位于所述显示区域13的上方，所述成盒测试电极区12位于所述显示区域13的下方。
步骤S4：将所述第一显示单元的成盒测试电极121与所述第二显示单元的阵列测试电极111一一对应电连接，以通过所述第一显示单元的成盒测试电极区12驱动显示信号的输出。
所述阵列基板测试电路通过将所述至少两个显示单元中的第一显示单元的成盒测试电极电性连接至所述第二显示单元的阵列测试电极，以避免纵向的阵列测试走线与显示区域边缘的横向金属走线产生交错的位置关系，以此通过所述第一显示单元的成盒测试电极控制显示信号的输出，从而完成对所述第一显单元的阵列测试项目，减少耦合、漏电及炸伤问题的发生，从而达到提升显示面板生产良率的目的。
以上仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (10)

  1. 一种阵列基板测试电路，其中，所述阵列基板测试电路设置于基板上，所述基板包括至少两个显示单元，所述至少两个显示单元包括第一显示单元及第二显示单元，所述第一及第二显示单元均包括阵列测试电极区及成盒测试电极区，所述阵列测试电极区包括若干阵列测试电极，所述成盒测试电极区包括若干成盒测试电极，所述第一显示单元的成盒测试电极与所述第二显示单元的阵列测试电极一一对应电连接，以通过所述第一显示单元的成盒测试电极区驱动显示信号的输出。
  2. 根据权利要求1所述的阵列基板测试电路，其中，所述第二显示单元位于所述第一显示单元的正下方。
  3. 根据权利要求1所述的阵列基板测试电路，其中，所述第二显示单元位于所述第一显示单元的左侧或右侧，或者所述第二显示单元位于所述第一显示单元的左下方或右下方。
  4. 根据权利要求1所述的阵列基板测试电路，其中，所述第一显示单元及所述第二显示单元均包括显示区域，所述阵列测试电极区位于所述显示区域的上方，所述成盒测试电极区位于所述显示区域的下方。
  5. 一种显示面板，其中，所述显示面板包括阵列基板测试电路，所述阵列基板测试电路设置于基板上，所述基板包括至少两个显示单元，所述至少两个显示单元包括第一显示单元及第二显示单元，所述第一及第二显示单元均包括阵列测试电极区及成盒测试电极区，所述阵列测试电极区包括若干阵列测试电极，所述成盒测试电极区包括若干成盒测试电极，所述第一显示单元的成盒测试电极与所述第二显示单元的阵列测试电极一一对应电连接，以通过所述第一显示单元的成盒测试电极区驱动显示信号的输出。
  6. 根据权利要求5所述的显示面板，其中，所述第二显示单元位于所述第一显示单元的正下方，或者所述第二显示单元位于所述第一显示单元的左侧或右侧，或者所述第二显示单元位于所述第一显示单元的左下方或者右下方。
  7. 根据权利要求1所述的显示面板，其中，所述第一显示单元及所述第二显示单元均包括显示区域，所述阵列测试电极区位于所述显示区域的上方，所述成盒测试电极区位于所述显示区域的下方。
  8. 一种阵列基板测试电路的制作方法，其中，所述方法包括：
    提供一基板；
    在所述基板上设置至少两个显示单元，所述至少两个显示单元包括第一显示单元及第二显示单元；
    在所述第一及第二显示单元上均设置阵列测试电极区及成盒测试电极区，所述阵列测试电极区包括若干阵列测试电极，所述成盒测试电极区包括若干成盒测试电极；及
    将所述第一显示单元的成盒测试电极与所述第二显示单元的阵列测试电极一一对应电连接，以通过所述第一显示单元的成盒测试电极区驱动显示信号的输出。
  9. 根据权利要求8所述的阵列基板测试电路的制作方法，其中，所述在所述基板上设置至少两个显示单元，所述至少两个显示单元包括第一显示单元及第二显示单元包括：所述第二显示单元位于所述第一显示单元的正下方，或者所述第二显示单元位于所述第一显示单元的左侧或右侧，或者所述第二显示单元位于所述第一显示单元的左下方或者右下方。
  10. 根据权利要求8所述的阵列基板测试电路的制作方法，其中，所述在所述第一及第二显示单元上均设置阵列测试电极区及成盒测试电极区包括：所述第一显示单元及所述第二显示单元均包括显示区域，所述阵列测试电极区位于所述显示区域的上方，所述成盒测试电极区位于所述显示区域的下方。
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JP7096721B2 (ja) * 2018-07-13 2022-07-06 株式会社ジャパンディスプレイ 表示装置
CN109212799B (zh) * 2018-10-26 2021-10-29 Tcl华星光电技术有限公司 液晶面板的外围电路结构以及液晶显示母板
CN109633302A (zh) * 2018-12-05 2019-04-16 武汉华星光电半导体显示技术有限公司 阻抗测试结构
CN110444117B (zh) * 2019-07-24 2021-09-28 苏州清越光电科技股份有限公司 封装基板及显示面板的制备方法
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