WO2018152952A1 - 一种三维存储器读出电路及读出方法 - Google Patents

一种三维存储器读出电路及读出方法 Download PDF

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WO2018152952A1
WO2018152952A1 PCT/CN2017/081816 CN2017081816W WO2018152952A1 WO 2018152952 A1 WO2018152952 A1 WO 2018152952A1 CN 2017081816 W CN2017081816 W CN 2017081816W WO 2018152952 A1 WO2018152952 A1 WO 2018152952A1
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Prior art keywords
read
bit line
current
memory cell
dimensional memory
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PCT/CN2017/081816
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English (en)
French (fr)
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雷宇
陈后鹏
宋志棠
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中国科学院上海微系统与信息技术研究所
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Priority to US15/739,723 priority Critical patent/US11568931B2/en
Publication of WO2018152952A1 publication Critical patent/WO2018152952A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0023—Address circuits or decoders
    • G11C13/0026—Bit-line or column circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0023—Address circuits or decoders
    • G11C13/0028—Word-line or row circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/003—Cell access
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0038—Power supply circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0061—Timing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/062—Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G11C2013/0045—Read using current through the cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G11C2013/0054—Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/71—Three dimensional array

Definitions

  • the present invention relates to the field of integrated circuit technology, and in particular, to a three-dimensional memory readout circuit and a readout method.
  • Integrated circuit memories are widely used in industrial and consumer electronics, and can be classified into volatile memory and nonvolatile memory depending on whether the memory can be powered down.
  • the nonvolatile memory includes a flash memory, a magnetoresistive random-access memory (MRAM), a resistive random-access memory (RRAM), a phase change memory (PCM), and the like.
  • the phase change memory is based on the Ovsinsky electronic effect memory proposed by Oversinsky in the late 1960s. Its working principle is to use the phase change material processed to nanometer size in the low resistance state (crystalline state). High resistance state (amorphous state) when different resistance states are used to achieve data storage.
  • Magnetic memory and resistive memory also use different resistance states of materials or devices in low resistance state (LRS) and high resistance state (HRS) to achieve data storage.
  • the three-dimensional memory can increase the storage density by three-dimensionally arranging the memory cells on the substrate compared to the two-dimensional memory.
  • a cross-point three-dimensional memory structure is widely used in each nonvolatile memory.
  • the word line and the bit line are at an angle of 90 degrees, and are stacked in layers, and the memory cells are present at the respective intersections.
  • 1 is a schematic diagram of a three-dimensional nonvolatile memory of a cross-stack structure.
  • a memory cell may be composed of a memory device and a selector.
  • the three-dimensional memory is different from the two-dimensional memory.
  • the parasitic device is mainly in the planar direction, and in the three-dimensional memory, the parasitic device exists in the vertical direction and the planar direction at the same time, and the number and complexity of the parasitic parameters in the three-dimensional memory are much larger than Two-dimensional memory; at the same time, the three-dimensional memory adopts a new type of gating device, which needs to increase the unselected bit line and the unselected word line.
  • the three-dimensional memory offset method is completely different from the two-dimensional memory, and the complexity is higher; The unique biasing of the 3D memory introduces leakage current.
  • the reading of data can be realized by measuring the size of the resistor: applying a certain voltage to the memory cell through the clamping circuit, reading the corresponding current flowing through the memory cell, and comparing with a reference current, Determine the status of the storage unit.
  • the read current is affected by parasitic devices in the array, resulting in longer read times.
  • the reference current is often a constant value.
  • the sense amplifier needs to simultaneously charge the parasitic capacitances in the vertical parasitic device, the planar parasitic device, and the sense amplifier in the array, and then the current is stabilized, and the prior art is stabilized.
  • the reference current in the current is always between the high-resistance current stable value and the low-resistance current stable value.
  • a pseudo-read phenomenon occurs. The large limit on the speed characteristics of the three-dimensional memory.
  • Factors affecting the read speed and accuracy of the three-dimensional memory include, but are not limited to, the following:
  • bit line parasitic parameters include the parasitic capacitance of the memory cell connected to the selected bit line, which is related to the number of word lines connected to the same bit line in the array.
  • the transmission gate parasitic parameters include the parasitic resistance and parasitic capacitance of the transmission gate, which are related to the number of local bit lines connected to the same global bit line in the memory array and the number of bit lines connected to the same fundamental bit line.
  • the parasitic parameters of the current mirror in the sense amplifier include the parasitic capacitance of the current mirror, which is related to the number of sense amplifiers connected to the same read reference circuit.
  • leakage When the voltage across the memory cell is 0, the memory cell is not strobed; when the voltage across the memory cell is V, the memory cell is strobed, and V is the bit line voltage when the memory cell performs read and write operations; when the voltage across the memory cell is At V/2, the memory cell is half-strobed, and the strobe is in the off state, but there is leakage current.
  • Leakage includes leakage of memory cells on selected bit lines and leakage of memory cells on selected word lines. The size of the leakage is mainly related to the electrical performance of the gating pipe.
  • the leakage of the semi-strobe memory cell is small (such as ⁇ 1pA), the effect of leakage can be ignored; if the leakage of the semi-strobe memory cell is large (such as >5pA), the leakage will cause mis-reading and affect the reading speed.
  • an object of the present invention is to provide a three-dimensional memory readout circuit and a readout method for solving the problem that the readout time of the three-dimensional memory readout circuit is too long in the prior art.
  • the present invention provides a three-dimensional memory readout circuit, the three-dimensional memory readout circuit comprising at least:
  • the three-dimensional memory cell array includes at least one three-dimensional memory cell sub-array and a plurality of sense amplifiers corresponding to the three-dimensional memory cell sub-array, wherein each of the three-dimensional memory cell arrays is connected to a corresponding sense amplifier through a transmission gate;
  • the sense amplifier is connected to the read reference circuit and the corresponding memory unit, and compares the read reference current with the current read in the selected memory cell to generate a read voltage signal of the selected memory cell;
  • Reading a reference circuit for generating a read reference voltage or a read reference current comprising: a reference unit, a bit line matching module, a transmission gate parasitic parameter matching module, and a first clamping tube;
  • the reference unit is connected between the reference word line and the reference bit line for providing a reference resistance value
  • the bit line matching module is connected between the reference bit line and the unselected word line for providing bit line parasitic parameters and leakage. To match the bit line parasitic parameters in the three-dimensional memory cell array and the leakage of the memory cells on the bit lines;
  • the transmission gate parasitic parameter matching module is connected between the reference bit line and a source end of the first clamp tube for providing a transmission gate parasitic parameter to match a transmission gate parasitic parameter in the three-dimensional memory cell array ;
  • the first clamp tube obtains a read reference current according to the reference resistance value, a bit line parasitic parameter and a leakage provided by the bit line matching module, and a transmission gate parasitic parameter provided by the transmission gate parasitic parameter matching module.
  • the three-dimensional memory readout circuit further includes: a word line matching module connected between the reference word line and the unselected bit line, for providing leakage on the word line to match the word in the three-dimensional memory cell array Leakage of the line storage unit; the first clamp tube is based on the reference resistance value, the bit line parasitic parameter and leakage provided by the bit line matching module, the leakage provided by the word line matching module, and the transmission gate
  • the parasitic parameter matching module provides a transmission gate parasitic parameter to obtain a read reference current.
  • the word line matching module includes (a-1) parallel storage units, where a is the number of bit lines connected to the same word line in the three-dimensional memory cell array.
  • the reference unit includes a reference resistor and a strobe tube, wherein one end of the strobe tube is connected to the reference word line, one end is connected to one end of the reference resistor; and the other end of the reference resistor is connected to the Reference bit line.
  • the resistance of the reference resistor is set between a highest value of the low resistance state resistance and a minimum value of the high resistance state resistance.
  • the gating tube is of the same type as the gating tube in the storage unit.
  • the bit line matching module includes (n-1) parallel storage units, where n is the number of word lines connected to the same bit line in the three-dimensional memory cell array.
  • the transmission gate parasitic parameter matching module includes a first transmission gate, a second transmission gate, a local transmission gate parasitic parameter matching unit, and a global transmission gate parasitic parameter matching unit;
  • the first transmission gate and the second transmission a gate is connected between the reference bit line and a source end of the first clamp tube, and a connection between the first transmission gate and the second transmission gate is used as a local reference bit line, and the second a connection between the transmission gate and the first clamp tube as a global reference bit line;
  • the local transmission gate parasitic parameter matching unit is connected between the local reference bit line and the unselected bit line for providing transmission a gate parasitic parameter to match a local transmission gate parasitic parameter in the three-dimensional memory cell array;
  • the global transmission gate parasitic parameter matching unit is coupled between the global reference bit line and ground for providing a transmission gate parasitic parameter to match Global transmission gate parasitic parameters in the three dimensional memory cell array.
  • the local transmission gate parasitic parameter matching unit comprises (m-1) parallel third transmission gates, where m is the number of bit lines connected to the same fundamental bit line in the three-dimensional memory cell array;
  • the structure and size of the third transmission gate are the same as the first transmission gates in the read reference circuit and the local transmission gates in the three-dimensional memory cell array; one end of each third transmission gate is connected to the local reference bit line, The other end is connected to the unselected bit line, and the control terminal is grounded.
  • the global transmission gate parasitic parameter matching unit comprises (c-1) parallel fourth transmission gates, where c is the number of local status lines connected to the same global bit line in the three-dimensional memory cell array
  • c is the number of local status lines connected to the same global bit line in the three-dimensional memory cell array
  • the structure and size of each fourth transmission gate are the same as the second transmission gates in the read reference circuit and the global transmission gates in the three-dimensional memory cell array; one end of each fourth transmission gate is connected to the global reference bit The line is grounded at the other end and the control terminal is grounded.
  • the read reference circuit further includes: a voltage conversion module, configured to convert the read reference current into a read reference voltage; including a first PMOS transistor, a source end of the first PMOS transistor connected to a power supply voltage, a gate terminal The output terminal connected to the drain terminal and serving as the read reference voltage and the drain terminal are also connected to the drain terminal of the first clamp tube.
  • a voltage conversion module configured to convert the read reference current into a read reference voltage; including a first PMOS transistor, a source end of the first PMOS transistor connected to a power supply voltage, a gate terminal The output terminal connected to the drain terminal and serving as the read reference voltage and the drain terminal are also connected to the drain terminal of the first clamp tube.
  • the read reference circuit further includes: a bit line driving module connected to an input end of the reference bit line, configured to drive the reference bit line; the bit line driving module includes a first NMOS transistor, the The source terminal of an NMOS transistor is connected to the unselected bit line signal, the back signal of the gate terminal connection enable signal, and the drain terminal are connected to the reference bit line.
  • the read reference circuit further includes: a word line driving module connected to an input end of the reference word line, configured to drive the reference word line;
  • the word line driving module includes a second NMOS transistor and a second PMOS a source end of the second NMOS transistor is grounded, a gate terminal is connected with an enable signal, and a drain terminal is connected to the reference word line; and a source end of the second PMOS transistor is connected to the unselected word line and the gate terminal
  • the enable signal and the drain terminal are connected to the reference word line.
  • the sense amplifier comprises a second clamp tube whose source is connected to the storage unit, a current mirror connected to the drain end of the second clamp tube, and a current conversion module connected to the read reference voltage.
  • a comparison module a gate voltage of the second clamp tube is connected to the clamp voltage; the current mirror extracts a read current in the selected memory cell; and the current conversion module converts the read reference voltage into a read reference a current module; the comparison module is connected to the current mirror and the current conversion module, compares a read current in the selected memory cell with the read reference current, and compares the result to represent a signal stored in the selected memory cell .
  • the sense amplifier further comprises a current mirror parasitic parameter matching module for canceling the current mirror parasitic effect in each sense amplifier; the third NMOS transistor including the gate terminal and the source terminal grounded, and 2 (b-1) Parallel to the third PMOS transistor, the source end of each third PMOS transistor is connected to the power supply voltage, the drain terminal is connected to the drain terminal of the third NMOS transistor, and the gate terminal is connected to the input end of the current mirror, and the size of each third PMOS transistor is The transistors in the current mirror are the same size, wherein b is the number of sense amplifiers connected to the same read reference circuit in the three-dimensional memory cell array.
  • the unselected word line is connected to a non-selected word line voltage source, the voltage of which causes the memory cell not to be selected.
  • the unselected bit line connection does not select a bit line voltage source, the voltage of which causes the memory cell not to be selected.
  • the present invention provides a readout method of the above-described three-dimensional memory readout circuit, the three-dimensional memory readout method comprising at least:
  • the sense amplifier reads a read current of the memory unit
  • the read reference circuit starts to work, generating a dynamic read reference current, and the read reference current transient value is read. Between low-resistance current and high-impedance current;
  • the sense amplifier compares the read current of the selected memory cell with the read reference current to generate a read voltage signal of the selected memory cell.
  • bit line parasitic parameter and the leakage on the bit line are introduced in the read reference current to cancel the array bit line parasitic effect generated when the memory cell is read and the leakage of the memory cell on the bit line, thereby eliminating the pseudo read phenomenon.
  • a leakage on the word line is introduced in the read reference current to cancel the leakage of the memory cell on the word line when the memory cell is read, eliminating the false read phenomenon and reducing the signal read time.
  • a transmission gate parasitic parameter is introduced in the read reference current to cancel the array transmission gate parasitic effect generated when the memory cell is read, eliminate the pseudo read phenomenon, and reduce the signal readout time.
  • a current mirror parasitic parameter is introduced in the read current of the selected memory cell to achieve matching of the mirror parameter of the read current of the selected memory cell and the mirror parameter of the reference current to eliminate the pseudo read phenomenon. , reduce the signal read time.
  • the memory cell when the read current of the selected memory cell is greater than the reference current, the memory cell is in a low resistance state; when the read current of the selected memory cell is less than the reference current, the memory cell is high Resistance state.
  • the three-dimensional memory readout circuit and the readout method of the present invention have the following advantageous effects:
  • the read reference circuit starts to work, and the matching of the parasitic parameters of the bit line and the matching of the parasitic parameters of the transmission gate are introduced in the read reference current. Matching the bit line and word line leakage, introducing a matching of the current mirror parasitic parameters in the read current, so that the transient curve of the read reference current is between the read high-resistance current and the read low-resistance current, and the maximum elimination
  • the pseudo-reading phenomenon reduces the readout time.
  • the read reference current and the read current have the same leakage current, which reduces erroneous reading.
  • the three-dimensional memory readout circuit and the readout method of the present invention can greatly reduce the readout time for a three-dimensional memory having a size of from 1 Mb to 1 Tb, and have a wide application range.
  • Figure 1 shows a schematic diagram of a three-dimensional non-volatile memory of a cross-stacked structure.
  • FIG. 2 shows a schematic diagram of the principle of the pseudo read phenomenon in the prior art affecting the read time.
  • Figure 3 shows a schematic diagram of a three dimensional memory cell array of the present invention.
  • Figure 4 shows an embodiment of a read reference circuit of the present invention.
  • Figure 5 is a diagram showing the operation of the sense amplifier of the present invention.
  • Figure 6 shows another embodiment of the read reference circuit of the present invention.
  • Figure 7 is a diagram showing the comparison of the read current and the read reference current in the three-dimensional memory read circuit of the present invention.
  • FIG. 8 shows a simulation result when the three-dimensional memory readout circuit of the present invention is applied to a 64 Mbit phase change memory chip when reading a low resistance state.
  • FIG. 9 shows a simulation result when the three-dimensional memory readout circuit of the present invention is applied to a 64 Mbit phase change memory chip when reading a high resistance state.
  • the present invention provides a three-dimensional memory readout circuit including a three-dimensional memory cell array 1 and a read reference circuit 2.
  • the three-dimensional memory cell array 1 includes at least one three-dimensional memory cell sub-array 11 and a plurality of sense amplifiers 12 corresponding to the three-dimensional memory cell sub-array. Connected to the corresponding sense amplifier 12 through a transmission gate; the sense amplifier 12 is connected to the read reference circuit 2 and the corresponding memory unit, and compares the read reference current with the current read in the selected memory cell to generate The read voltage signal of the selected memory cell.
  • the three-dimensional memory cell array 1 includes three three-dimensional memory cell sub-arrays 11 , which can be set according to requirements in actual design, and is not limited to this embodiment.
  • the upper memory cell and the lower memory cell use the same bit line
  • the global bit line GBL is in one-to-one correspondence with the sense amplifier
  • the number of the sense amplifiers 12 is set to b
  • this b A sense amplifier is connected to the same read reference circuit to receive the read reference voltage or read the reference current.
  • the number of word lines or memory cells connected to the same bit line in the three-dimensional memory cell sub-array 11 is set to n, and the three-dimensional memory cell sub-array 11 is connected to the same word line.
  • the number of bit lines or memory cells is set to a; the three-dimensional memory cell sub-array 11 is connected to the same fundamental bit line LBL
  • the number of bit lines BL is set to m, and the bit lines BL are respectively connected to the local bit line LBL through a local transfer gate;
  • the number of local bit lines LBL connected to the same global bit line GBL in the three-dimensional memory cell sub-array 11 Set to c, each of the local bit lines LBL is connected to the global bit line GBL through a global transfer gate, that is, the number of bit lines BL connected to the same sense amplifier 12 is set to mc.
  • the specific values can be set according to actual needs, and are not limited here.
  • the memory cell sub-array 11 includes a plurality of memory cells 111, wherein (n*m) memory cells 111 are arrayed and connected to the same local bit line; the row control signal is a word line. Signals WL UP_1 WL WL UP_n/2 and WL DN_1 ⁇ WL DN_n/2 (control the upper and lower memory cells 111, respectively); the column transfer signals are bit line signals BL 1 ⁇ BL m , and only one word line WL and at the same time A bit line BL is turned on, and a memory cell 111 is connected to the local bit line LBL.
  • the bit line BL is connected to the local bit line LBL through the local transfer gate LTG, and the local bit line LBL is connected to the global bit line GBL through the global transfer gate GTG.
  • the memory unit 111 includes a first memory device 1111 and a first strobe tube 1112.
  • the memory device can be an OMS effect device, and the strobe can be an OTS effect device, not limited to this embodiment.
  • the first storage device 1111 is connected to the first local transmission gate LTG 1 and the first global transmission gate GTG 1 in turn , and is first sensitive.
  • the amplifier is connected to the other end of the first strobe tube 1112, and the other end of the first strobe tube 1112 is connected to the first word line WL DN_1 .
  • the read reference circuit 2 is connected to the sense amplifier 12 for generating a read reference voltage Vref or a read reference current Iref.
  • the read reference voltage Vref is taken as an example.
  • the read reference circuit 2 includes a reference unit 21, a bit line drive module 22, a word line drive module 23, a bit line matching module 24, a transmission gate parasitic parameter matching module 25, a first clamp tube 26, and a voltage conversion module 27.
  • the reference unit 21 is connected between the reference word line WL' and the reference bit line BL' for providing a reference resistance value.
  • the reference unit 21 includes a reference resistor Rref and a second strobe tube 211, wherein one end of the second strobe tube 211 is connected to the output end of the word line driving module 25 through the reference word line WL', and the other end One end of the reference resistor Rref is connected, and the other end of the reference resistor Rref is connected to the reference bit line BL'.
  • the resistance of the reference resistor Rref is set between the highest value of the low resistance state resistance and the lowest value of the high resistance state resistance.
  • the second gating pipe 211 is of the same type as the first gating pipe 1112 of the storage unit 111.
  • the bit line driving module 22 is connected to the reference bit line BL' for driving the reference bit line BL'.
  • the bit line driving module 22 includes a first NMOS transistor NM1, and the source end of the first NMOS transistor NM1 is connected to the unselected bit line signal DESBL and the back signal of the gate terminal connection enable signal EN (in this embodiment, The enable signal EN is connected to the inverter to obtain an inverse signal, and the drain terminal is connected to the reference bit line BL'.
  • the first NMOS transistor NM1 is not selectively driven as a bit line; when the enable signal EN is ineffective (low level), the first NMOS transistor NM1 is turned on, and the reference bit line BL' passes through The unselected bit line DESBL is connected to the unselected bit line voltage source, and the reference bit line BL' Not selected; when the enable signal EN is active (high level), the first NMOS transistor NM1 is disabled.
  • the local line voltage is VBL
  • the voltage of the unselected bit line voltage source is VBL/2.
  • the word line driving module 23 is connected to an input terminal of the reference word line WL' for driving the reference word line WL'.
  • the word line driving module 23 includes a second NMOS transistor NM2 and a second PMOS transistor PM2.
  • the source terminal of the second NMOS transistor NM2 is grounded (0V), the gate terminal connection enable signal EN, and the drain terminal is connected to the reference word.
  • a line WL'; a source end of the second PMOS transistor PM2 is connected to the unselected word line DESWL, a gate terminal is connected to the enable signal EN, and a drain terminal is connected to the reference word line WL'.
  • the second NMOS transistor NM2 and the second PMOS transistor PM2 are respectively selected as word line drive and word line unselected driving; when the enable signal EN is inactive (low level), the second PMOS The tube PM2 is turned on, the reference word line WL' is connected to the unselected word line voltage source through the unselected word line DESWL, the reference unit 21 is not selected; when the enable signal EN is active (high level When the second NMOS transistor NM2 is turned on, the reference word line WL' is connected to a low level (0 V), and the reference unit 21 is selected.
  • the local word line voltage is VBL
  • the voltage of the unselected word line voltage source is VBL/2.
  • the bit line matching module 24 is connected between the reference bit line BL' and the unselected word line DESWL for providing bit line parasitic parameters and leakage to match the The bit line parasitic parameters in the three-dimensional memory cell array 1 and the leakage of the memory cells on the bit lines.
  • the bit line matching module 24 includes (n-1) parallel memory cells, where n is the number of word lines connected to the same bit line in the three-dimensional memory cell array 1.
  • the bit line matching module 24 can be divided into a first bit line matching unit 241 and a second bit line matching unit 242, wherein the first bit line matching unit 241 includes (n/2-1).
  • the first bit line matching unit 241 includes (n/2-1).
  • the second bit line matching unit 242 includes (n/2) memory cells for matching
  • the bit line parasitic parameters of the upper memory cell and its leakage on the first bit line BL1 (corresponding to the memory cell selected in the embodiment is the lower memory cell of the first row and the first column).
  • n is the number of word lines WL connected to the same bit line BL in the three-dimensional memory cell array 1.
  • the remaining (n-1) memory cells in the column thereof are in an off state, and the parasitic capacitance of the first memory device 1111 and the first strobe transistor 1112 is read current Iread.
  • An influence is generated by setting the first bit line matching unit 241 and the second bit line matching unit 242 to introduce a parasitic charging current matching the three-dimensional memory cell array 1 in the read reference current Iref, thereby obtaining a read reference current.
  • the change trend of Iref is consistent with the read current Iread, thereby eliminating the pseudo read phenomenon and reducing the signal read time.
  • the transmission gate parasitic parameter matching module 25 is connected between the reference bit line BL' and the source end of the first clamp tube 26 for providing a transmission gate parasitic parameter.
  • the transmission gate parasitic parameters in the three-dimensional memory cell array 1 are matched.
  • the transmission gate parasitic parameter matching module 25 includes a first transmission gate LTG0, a second transmission gate GTG0, The local transmission gate parasitic parameter matching unit 251 and the global transmission gate parasitic parameter matching unit 252.
  • first transmission gate LTG0 and the second transmission gate GTG0 are connected in series between the reference bit line BL' and the source end of the first clamp tube 26, the first transmission gate LTG0 a local transmission gate, the second transmission gate GTG0 is a global transmission gate, and a connection between the first transmission gate LTG0 and the second transmission gate GTG0 serves as a local reference bit line LBL', the second transmission A line connecting the gate GTG0 and the first clamp tube 26 serves as a global reference bit line GBL'.
  • the local transmission gate parasitic parameter matching unit 251 is connected between the local reference bit line LBL' and the unselected bit line DESBL for providing a transmission gate parasitic parameter to match the three-dimensional memory cell array.
  • the local transmission gate parasitic parameter in 1.
  • the local transmission gate parasitic parameter matching unit 251 includes (m-1) parallel third transmission gates LTG, where m is the number of bit lines connected to the same fundamental bit line LBL in the three-dimensional memory cell array 1;
  • the structure and size of the third transmission gate LTG are the same as the first transmission gates LTG0 and the local transmission gates in the three-dimensional memory cell array 1; one end of each of the third transmission gates LTG is connected to the local reference bit line LBL' The other end is connected to the unselected bit line DESBL, and the control terminal is grounded, and is always in a non-conducting state.
  • the local transmission gate parasitic parameter matching unit 251 is configured to match the local transmission gate parasitic parameter.
  • the local transmission gate connected thereto is turned on, and the remaining (m-1) local transmission gates are in the off state, and the transmission is performed.
  • the parasitic capacitance and the parasitic resistance on the gate have an influence on the read current Iread, and the local transmission gate matching the three-dimensional memory cell array 1 can be further introduced in the read current Iread by setting the local transmission gate parasitic parameter matching unit 251
  • the parasitic current, the change trend of the read reference current Iref obtained in this way is consistent with the read current Iread, thereby eliminating the pseudo-read phenomenon and reducing the signal readout time.
  • the global transmission gate parasitic parameter matching unit 252 is connected between the global reference bit line GBL' and the ground for providing a transmission gate parasitic parameter to match the global transmission gate in the three-dimensional memory cell array 1. Parasitic parameters.
  • the global transmission gate parasitic parameter matching unit 252 includes (c-1) fourth parallel transmission gates GTG, where c is the number of local status lines connected to the same global bit line GBL in the three-dimensional memory cell array 1.
  • each fourth transmission gate GTG are the same as the second transmission gate GTG0 and each global transmission gate in the three-dimensional memory cell array 1; one end of each fourth transmission gate GTG is connected to the global reference bit line GBL', the other end is grounded, the control terminal is grounded, and it is always in a non-conducting state.
  • the global transmission gate parasitic parameter matching unit 252 is configured to match the global transmission gate parasitic parameter. When the storage unit is read, the global transmission gate connected thereto is turned on, and the remaining (c-1) global transmission gates are in the off state, and the transmission is performed.
  • the parasitic capacitance and the parasitic resistance on the gate have an influence on the read current Iread, and the global transfer gate matching the three-dimensional memory cell array 1 can be further introduced in the read current Iread by setting the global transfer gate parasitic parameter matching unit 252
  • the parasitic current, the change trend of the read reference current Iref obtained in this way is consistent with the read current Iread, thereby eliminating the pseudo-read phenomenon and reducing the signal readout time.
  • the first clamp tube 26 is based on the reference resistance value, the first bit line matching unit 241, and the The bit line parasitic parameters and leakage provided by the two bit line matching unit 242 and the transmission gate parasitic parameters provided by the local transmission gate parasitic parameter matching unit 251 and the global transmission gate parasitic parameter matching unit 252 obtain the read reference current Iref.
  • the source terminal of the first clamp tube 26 is connected to the global reference bit line GBL', the gate terminal connection clamp voltage Vclamp, and the drain terminal is connected to the voltage conversion module 27.
  • the voltage conversion module 27 is connected to the drain terminal of the first clamp tube 26 for converting the read reference current Iref into a read reference voltage Vref.
  • the voltage conversion module 27 includes a first PMOS transistor PM1, and a source terminal of the first PMOS transistor PM1 is connected to a power supply voltage V DD , and a gate terminal and a drain terminal are connected as the read reference. The output end and the drain end of the voltage Vref are also connected to the drain end of the first clamp tube 26.
  • the structure of the voltage conversion module 27 is not limited, and any circuit having a current-to-voltage function is applicable, and is not limited to the embodiment.
  • the sense amplifier 12 corresponds to the three-dimensional memory unit sub-array 11.
  • the mc root bit lines are connected to the same sense amplifier, and the sense amplifier 12 is respectively connected to the three-dimensional through the transmission gate.
  • the bit lines in the memory cell sub-array 11 are connected and connected to the read reference circuit 2 to receive the read reference current Iref or the read reference voltage Vref (in the present embodiment, the read reference voltage Vref is received).
  • the sense amplifier 12 restores the read reference voltage Vref to a read reference current Iref, and compares the read reference current Iref with a read current Iread in the selected memory cell 111 in the three-dimensional memory cell array 1. To generate a read voltage signal of the selected memory cell 111.
  • the sense amplifier 12 includes a second clamp tube 121 whose source is connected to the storage unit 111, and a current mirror connected to the drain end of the second clamp tube 121.
  • the gate terminal of the second clamp tube 121 is connected to the clamp voltage Vclamp, and the read current Iread in the selected memory cell 111 is generated under the control of the clamp voltage Vclamp.
  • the current mirror extracts the read current Iread in the selected memory cell 111, and includes a fourth PMOS transistor PM4 and a fifth PMOS transistor PM5.
  • the current mirror parasitic parameter matching module 122 includes a third NMOS transistor NM3 and 2 (b-1) parallel third PMOS transistors PM3 with the gate terminal and the source terminal grounded, and the source terminal of each third PMOS transistor PM3 is connected to the power supply voltage V.
  • the drain terminal is connected to the drain end of the third NMOS transistor NM3, the gate terminal is connected to the input end of the current mirror, and the size of each third PMOS transistor PM3 is different from the fourth PMOS transistor PM4, the fifth PMOS transistor PM5, and the sixth
  • the PMOS transistor PM6, the seventh PMOS transistor PM7, the eighth PMOS transistor PM8, and the first PMOS transistor PM1 of the read reference circuit 2 have the same size, wherein b is the same read reference in the three-dimensional memory cell array 1 The number of sense amplifiers in the circuit.
  • the current mirror parasitic parameter matching module 122 is configured to match the current mirror parasitic parameters, and the read reference voltage Vref is simultaneously connected with the b sense amplifiers, and the (b-1) sensitive ones are inevitably introduced into the read reference voltage Vref.
  • the current mirror parasitic parameter of the read reference current Iref is converted in the amplifier.
  • the mirror of the read reference current Iref is realized by the sixth PMOS transistor PM6 and the eighth PMOS transistor PM8, so the third PMOS transistor PM3 The number is set to 2 (b-1). At this time, there are (2b+1) PMOS transistors at the read current terminal. At the reference current terminal, there are also (2b+1) PMOS transistors, and the number of current mirrors on both sides. Balanced with current mirror parasitic parameters.
  • the number of the third PMOS transistors PM3 in different circuit configurations is also different, and can be set according to the specific circuit result, and is not limited to this embodiment.
  • a current mirror parasitic current matching the current mirror in each sense amplifier can be introduced into the read current Iref, so that the change trend of the read reference current Iref and the read current Iread Consistent, thereby eliminating the pseudo-reading phenomenon and reducing the signal readout time.
  • the current conversion module restores the read reference voltage Vref to a read reference current Iref, including a sixth PMOS transistor PM6.
  • the comparison module is connected to the current mirror and the current conversion module, and compares the read current Iread in the selected memory unit 111 with the read reference current Iref, and compares the result to indicate that the selected memory unit 111 stores
  • the signal includes a seventh PMOS transistor PM7, an eighth PMOS transistor P8, a fourth NMOS transistor NM4, a fifth NMOS transistor NM5, a sixth NMOS transistor NM6, and a seventh NMOS transistor NM7.
  • the drain terminal of the fourth PMOS transistor PM4 is connected to the second clamp transistor 121, and the fifth PMOS transistor PM5 and the seventh PMOS transistor PM7 form a current mirror, and the read current Iread of the selected memory cell 111 is mirrored to the fifth PMOS transistor PM5.
  • the drain terminal of the fourth NMOS transistor NM4 is connected to the drain terminal of the fifth PMOS transistor PM5, and constitutes a current mirror with the seventh NMOS transistor NM7.
  • the first PMOS transistor PM1 and the sixth PMOS transistor PM6 and the eighth PMOS transistor PM8 in the read reference circuit 2 form a current mirror, and the read reference current Iref is mirrored to the sixth PMOS transistor PM6 and the eighth PMOS transistor PM8.
  • the drain terminal of the fifth NMOS transistor NM5 is connected to the drain terminal of the sixth PMOS transistor PM6, and constitutes a current mirror with the sixth NMOS transistor NM6.
  • the drain end of the sixth NMOS transistor NM6 is connected to the drain terminal of the seventh PMOS transistor PM7 as the first output terminal of the comparison module.
  • the drain end of the seventh NMOS transistor NM17 is connected to the drain terminal of the eighth PMOS transistor PM8 as the second output terminal of the comparison module.
  • the first output and the second output of the comparison module are differential outputs.
  • the R terminal of the SR latch is connected to the first output end of the comparison module, and the S end of the SR latch is connected to the second output end of the comparison module, and is obtained according to an output signal of the comparison module.
  • the read voltage of the selected memory cell 111 is connected to the drain terminal of the seventh PMOS transistor PM7 as the first output terminal of the comparison module.
  • the drain end of the seventh NMOS transistor NM17 is connected to the drain terminal of the eighth PMOS transistor PM8 as the second output terminal of the comparison module.
  • the first output and the second output of the comparison module are differential outputs.
  • the R terminal of the SR latch is
  • the embodiment provides a three-dimensional memory readout circuit
  • the structure of the three-dimensional memory readout circuit is similar to that of the first embodiment, except that the three-dimensional memory readout circuit further includes:
  • a word line matching module between the reference word line W1' and the unselected bit line DESBL is configured to provide leakage on the word line to match the leakage of the memory cells on the word line in the three-dimensional memory cell array 1.
  • the word line matching module 28 includes (a-1) parallel storage units, where a is the number of bit lines connected to the same word line in the three-dimensional memory cell array 1. .
  • the first clamp tube 26 is based on the reference resistance value, the bit line parasitic parameter and leakage provided by the bit line matching module 24, the leakage provided by the word line matching module 28, and the transmission gate parasitic.
  • the transmission gate parasitic parameter provided by the parameter matching module 25 obtains the read reference current Iref.
  • the present invention further provides a three-dimensional memory reading method, where the three-dimensional memory reading method at least includes:
  • Step S1 selecting a word line and a bit line, connecting one memory cell in the three-dimensional memory cell array to the sense amplifier, the sense amplifier reading the read current of the memory cell; in the one word line
  • the read reference circuit starts to work, generating a dynamic read reference current, the read reference current transient value is in the read low resistance state cell current and read Between high resistance state cell currents.
  • the lower memory cell of the first row and the first column is taken as an example, the first word line WL DN_1 is placed at a low level, and the remaining word lines are set to be unselected.
  • the line voltage simultaneously turns on the first local transfer gate LTG1 and the first GTG1.
  • the current signal connected to the first bit line BL1 is output to the sense amplifier 12, and the signal connected to the first bit line BL1 includes the selected
  • the current in the lower memory cell of the first row and the first column, the current generated by the parasitic capacitance of the semi-strobed memory cell and the parasitic resistance, the leakage current of the semi-strobed memory cell, and the non-conducting transmission gates The current generated by the parasitic capacitance and the parasitic resistance, and the read current Iread received by the sense amplifier 12 gradually increases with the charging process of the parasitic capacitance, and then slowly decreases, as shown in FIG.
  • the first word line WL DN_1 when the first word line WL DN_1 is set to a low level, the first local transfer gate LTG1 and the first global transfer gate GTG1 are turned on, and the sense amplifier 12 starts to work,
  • the enable signal EN is active, and the read reference current Iref is generated at a source end of the first clamp tube 26, and the read reference current Iref includes a current on the reference resistor in the reference unit 21,
  • the current generated by the parasitic capacitance of the memory cell provided by the bit line matching module 24 and the leakage of the memory cell, the leakage of the memory cell provided by the word line matching module 28, and the local transmission gate parasitic parameter matching unit 251 and the global transmission gate The parasitic capacitance provided by the parasitic parameter matching unit 252 and the current generated by the parasitic resistance.
  • the read reference current Iref gradually increases with the charging process of the parasitic capacitance, and then gradually decreases, and the trend of change is as described.
  • the read current Iread is consistent, thereby eliminating the pseudo read phenomenon and reducing the signal read time.
  • the read reference current Iref is a dynamic value whose transient value is between the read low resistance state cell current and the read high resistance state cell current.
  • Step S2 Acquire a read current of the selected memory cell, and compare the read current of the selected memory cell with the read reference current to generate a read voltage signal of the selected memory cell.
  • the second clamp tube 121 is controlled by the clamp voltage Vclamp to generate a read current Iread of the memory unit 111, and is transmitted to the seventh NMOS transistor NM7 through a current mirror.
  • the current mirror parasitic parameter matching module 122 introduces a current mirror parasitic parameter in the read current Iread to achieve a mirror parameter of the read current of the selected memory cell and a mirror parameter of the reference current.
  • the matching is such that the change trend of the read reference current Iref coincides with the read current Iread, thereby eliminating the pseudo read phenomenon and reducing the signal readout time, as shown in FIG.
  • the read reference voltage Vref is restored to the read reference current Iref and is transmitted to the gate terminal of the sixth NMOS transistor NM6.
  • Iread>Iref the drain current of the fourth NMOS transistor NM4 rises; the connection mode of the fourth NMOS transistor NM4 makes it equivalent to a diode, so The gate voltage of the fourth NMOS transistor NM4 will rise, the gate voltage of the seventh NMOS transistor NM7 will also rise, and the gate voltage of the sixth NMOS transistor NM6 will decrease; at this time, the output voltage V 2 of the second output terminal of the comparison module will decrease.
  • the output voltage V 1 of the first output of the comparison module rises to be close to the power supply voltage V DD .
  • the memory cell 111 is a high-resistance memory cell, Iread ⁇ Iref; the drain current of the fourth NMOS transistor NM4 decreases; the fourth NMOS transistor NM4 is connected in such a way that it can be equivalent to a diode, so The gate voltage of the fourth NMOS transistor NM4 will decrease, the gate voltage of the seventh NMOS transistor NM7 will also decrease, and the gate voltage of the sixth NMOS transistor NM6 will rise; at this time, the output voltage V 2 of the second output terminal of the comparison module will rise.
  • the output voltage V 1 of the first output of the comparison module rises to near 0V.
  • the output voltages V 1 and V 2 of the comparison module are outputted to the SR latch to obtain an output signal DO.
  • the SR latch When the read current Iread of the selected memory cell is greater than the reference current Iref, the SR latch output a high level; when the read current Iread of the selected memory cell is less than the reference current Iref, the SR latch outputs a low level.
  • the read reference current of the present invention is already between the read low resistance state cell current and the read high resistance state cell current during the current rising phase, which is greatly reduced compared to the pseudo read time of FIG.
  • the chip uses a 40nm process with a capacity of 64Mbit and uses a cross-stacked three-dimensional memory structure.
  • the EN signal is an enable signal, and as the voltage of the EN signal increases, the sense amplifier starts reading.
  • the read time is 39.67 ns when reading low impedance (low resistance), and less than 0.5 ns when reading high impedance (high resistance).
  • the random read time of the three-dimensional memory readout circuit of the present invention is 39.67 ns.
  • the 64Mbit three-dimensional memory chip with the traditional readout method has a read time of 185.3ns left. right.
  • the three-dimensional memory readout circuit and the readout method of the present invention have the following advantageous effects:
  • the read reference circuit starts to work, and the matching of the parasitic parameters of the bit line and the matching of the parasitic parameters of the transmission gate are introduced in the read reference current.
  • the matching of the current mirror parasitic parameters is introduced in the read current, so that the transient curve of the read reference current is between the read high-resistance current and the read low-resistance current, thereby eliminating the pseudo-read phenomenon to the greatest extent. , reducing the read time.
  • the read reference current and the read current have the same leakage current, which reduces erroneous reading.
  • the three-dimensional memory readout circuit and the readout method of the present invention can greatly reduce the readout time for a three-dimensional memory having a size of from 1 Mb to 1 Tb, and have a wide application range.
  • the present invention provides a three-dimensional memory readout circuit and readout method, including: a read reference circuit to generate a read reference current that can quickly distinguish between reading a low-resistance cell current and reading a high-resistance cell current; Sensitive amplifier.
  • the read reference circuit includes a reference unit, a bit line matching module, a word line matching module, and a transmission gate parasitic parameter matching module.
  • the invention is directed to the parasitic effect and leakage of the three-dimensional memory in the plane and the vertical direction, and introduces the matching of the parasitic parameters of the bit line, the leakage and the parasitic parameters of the transmission gate in the read reference current, and introduces the matching of the parasitic parameters of the current mirror in the read current, thereby eliminating the matching.
  • the pseudo-reading phenomenon reduces the readout time; and the signal transmission speed is fast, the applicable range is wide, and the readout correct rate is high. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

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Abstract

本发明提供一种三维存储器读出电路及读出方法，包括：读参考电路，产生一个可以快速区分读低阻态单元电流和读高阻态单元电流的读参考电流；以及灵敏放大器。读参考电路包括参考单元、位线匹配模块、字线匹配模块和传输门寄生参数匹配模块。本发明针对三维存储器在平面和垂直方向的寄生效应和漏电，在读参考电流中引入对位线寄生参数、漏电和传输门寄生参数的匹配，在读电流中引入对电流镜寄生参数的匹配，消除了伪读取现象，减小了读出时间；且适用范围广、读出正确率高。

Description

一种三维存储器读出电路及读出方法 技术领域
本发明涉及集成电路技术领域，特别是涉及一种三维存储器读出电路及读出方法。
背景技术
集成电路存储器被广泛应用于工业界和消费类电子产品，根据存储器能否掉电存储，又可被划分为易失存储器和非易失存储器。非易失存储器，包括闪存(flash memory)、磁存储器(magnetoresistive random-access memory，MRAM)、阻变存储器(resistance random-access memory，RRAM)、相变存储器(phase change memory，PCM)等。相变存储器是基于奥弗辛斯基在20世纪60年代末提出的奥弗辛斯基电子效应的存储器，其工作原理是利用加工到纳米尺寸的相变材料在低阻态(晶态)与高阻态(非晶态)时不同的电阻状态来实现数据的存储。磁存储器和阻变存储器同样使用材料或器件在低阻态(low resistance state，LRS)与高阻态(high resistance state，HRS)时不同的电阻状态来实现数据的存储。
三维存储器，通过将存储单元三维地布置在衬底之上，相比于二维存储器，可以提高存储密度。其中，一种交叉堆叠(cross point)的三维存储结构被广泛应用于各非易失存储器。该结构中，字线和位线呈90度夹角，并层层堆叠，存储单元存在于各个交点。图1为交叉堆叠结构三维非易失存储器示意图。在交叉堆叠结构三维非易失存储器中，存储单元可由存储器件和选通管(Selector)组成。
三维存储器不同于二维存储器，在二维存储器中寄生器件主要在平面方向，而在三维存储器中寄生器件同时存在于垂直方向和平面方向，三维存储器中寄生参数的个数和复杂性远远大于二维存储器；同时，三维存储器采用了新型的选通器件，需要增加不选位线和不选字线，三维存储器的偏置方法和二维存储器完全不一样，复杂性更高；此外，由于三维存储器独特的偏置方式会带来漏电流。
非易失存储器中，数据的读出可通过测量电阻的大小来实现：通过钳位电路给存储单元施加一定电压，读取流过存储单元的相应电流，再与一个参考电流相比较，即可判断存储单元的状态。读电流会受到阵列中的寄生器件影响，导致读取时间变长。在以往的三维存储器和二维存储器设计中，参考电流往往采用恒定值。如图2所示，三维存储器进行读取操作时，灵敏放大器需要同时对阵列中垂直方向寄生器件、平面方向寄生器件和灵敏放大器中的寄生电容充电，之后电流才会稳定下来，而现有技术中的参考电流始终保持在介于读高阻态电流稳定值和读低阻态电流稳定值之间，在给寄生电容充电的这段时间就会产生伪读取现象，大 大的制约了三维存储器的速度特性。
影响三维存储器读出速度与正确率的因素包括但不限于以下几点：
一、位线寄生参数。位线寄生参数包括与被选中位线连接的存储单元的寄生电容，与阵列中连接于同一根位线的字线个数有关。
二、传输门寄生参数。传输门寄生参数包括传输门的寄生电阻和寄生电容，与存储阵列中连接于同一根全局位线的本地位线个数和连接于同一根本地位线的位线个数有关。
三、灵敏放大器中电流镜的寄生参数。灵敏放大器中电流镜的寄生参数包括电流镜的寄生电容，与连接于同一个读参考电路的灵敏放大器个数有关。
四、漏电。当存储单元两端电压为0，存储单元不选通；当存储单元两端电压为V，存储单元选通，V为存储单元进行读写操作时的位线电压；当存储单元两端电压为V/2时，存储单元半选通，此时选通管处于关断状态，但会有漏电流。漏电包括被选中位线上存储单元的漏电和被选中字线上存储单元的漏电。漏电的大小主要跟选通管的电学性能有关。若半选通存储单元的漏电较小(如<1pA)，可以忽略漏电的影响；若半选通存储单元的漏电较大(如>5pA)，漏电会导致误读取并影响读取速度。
因此，如何改善上述读出时间过长，以及如何提高三维存储器的速度特性，实已成为本领域技术人员亟待解决的技术课题。
发明内容
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种三维存储器读出电路及读出方法，用于解决现有技术中三维存储器读出电路读出时间过长的问题。
为实现上述目的及其他相关目的，本发明提供一种三维存储器读出电路，所述三维存储器读出电路至少包括：
三维存储单元阵列，包括至少一个三维存储单元子阵列以及与所述三维存储单元子阵列对应的多个灵敏放大器，所述三维存储单元阵列中各位线分别通过传输门与对应的灵敏放大器连接；所述灵敏放大器连接所述读参考电路及对应的存储单元，将读参考电流与被选中的存储单元中读出的电流相比较，以产生被选中的存储单元的读出电压信号；
读参考电路，用于产生读参考电压或读参考电流，包括：参考单元、位线匹配模块、传输门寄生参数匹配模块以及第一钳位管；
其中，所述参考单元连接于参考字线与参考位线之间，用于提供参考电阻值；
所述位线匹配模块连接于所述参考位线与不选字线之间，用于提供位线寄生参数和漏电， 以匹配所述三维存储单元阵列中的位线寄生参数和位线上存储单元的漏电；
所述传输门寄生参数匹配模块连接于所述参考位线与所述第一钳位管的源端之间，用于提供传输门寄生参数以匹配所述三维存储单元阵列中的传输门寄生参数；
所述第一钳位管根据所述参考电阻值、所述位线匹配模块提供的位线寄生参数和漏电及所述传输门寄生参数匹配模块提供的传输门寄生参数，得到读参考电流。
优选地，所述三维存储器读出电路还包括：连接于所述参考字线与不选位线之间的字线匹配模块，用于提供字线上的漏电以匹配所述三维存储单元阵列中字线上存储单元的漏电；所述第一钳位管根据所述参考电阻值、所述位线匹配模块提供的位线寄生参数和漏电、所述字线匹配模块提供的漏电及所述传输门寄生参数匹配模块提供的传输门寄生参数，得到读参考电流。
更优选地，所述字线匹配模块包括(a-1)个并联的存储单元，其中a为所述三维存储单元阵列中连接于同一根字线的位线个数。
优选地，所述参考单元包括参考电阻和选通管，其中，所述选通管的一端接所述参考字线、一端连接所述参考电阻的一端；所述参考电阻的另一端连接所述参考位线。
更优选地，所述参考电阻的阻值设在低阻态电阻最高值和高阻态电阻最低值之间。
更优选地，所述选通管与存储单元中的选通管为同一类型。
优选地，所述位线匹配模块包括(n-1)个并联的存储单元，其中n为所述三维存储单元阵列中连接于同一根位线的字线个数。
优选地，所述传输门寄生参数匹配模块包括第一传输门、第二传输门、本地传输门寄生参数匹配单元及全局传输门寄生参数匹配单元；所述第一传输门及所述第二传输门串联于所述参考位线及所述第一钳位管的源端之间，所述第一传输门与所述第二传输门之间的连线作为本地参考位线，所述第二传输门与所述第一钳位管之间的连线作为全局参考位线；所述本地传输门寄生参数匹配单元连接于所述本地参考位线和不选位线之间，用于提供传输门寄生参数以匹配所述三维存储单元阵列中的本地传输门寄生参数；所述全局传输门寄生参数匹配单元连接于所述全局参考位线与地之间，用于提供传输门寄生参数以匹配所述三维存储单元阵列中的全局传输门寄生参数。
更优选地，所述本地传输门寄生参数匹配单元包括(m-1)个并联的第三传输门，其中m为所述三维存储单元阵列中连接于同一根本地位线的位线个数；各第三传输门的结构、尺寸与所述读参考电路中的第一传输门和所述三维存储单元阵列中的各本地传输门相同；各第三传输门的一端连接所述本地参考位线、另一端接所述不选位线、控制端接地
更优选地，所述全局传输门寄生参数匹配单元包括(c-1)个并联的第四传输门，其中c为所述三维存储单元阵列中连接于同一根全局位线的本地位线个数；各第四传输门的结构、尺寸与所述读参考电路中的第二传输门和所述三维存储单元阵列中的各全局传输门相同；各第四传输门的一端连接所述全局参考位线、另一端接地、控制端接地。
优选地，所述读参考电路还包括：电压转换模块，用于将所述读参考电流转化为读参考电压；包括第一PMOS管，所述第一PMOS管的源端连接电源电压、栅端与漏端连接并作为所述读参考电压的输出端、漏端还连接于第一钳位管的漏端。
优选地，所述读参考电路还包括：连接于所述参考位线的输入端的位线驱动模块，用于驱动所述参考位线；所述位线驱动模块包括第一NMOS管，所述第一NMOS管的源端连接不选位线信号、栅端连接使能信号的反信号、漏端连接所述参考位线。
优选地，所述读参考电路还包括：连接于所述参考字线的输入端的字线驱动模块，用于驱动所述参考字线；所述字线驱动模块包括第二NMOS管及第二PMOS管，所述第二NMOS管的源端接地、栅端连接使能信号、漏端连接所述参考字线；所述第二PMOS管的源端连接所述不选字线、栅端连接所述使能信号、漏端连接所述参考字线。
优选地，所述灵敏放大器包括源端与所述存储单元连接的第二钳位管，与所述第二钳位管的漏端连接的电流镜，与所述读参考电压连接的电流转换模块，以及比较模块；所述第二钳位管的栅端连接钳位电压；所述电流镜提取被选中的存储单元中的读电流；所述电流转换模块将所述读参考电压转化为读参考电流；所述比较模块与所述电流镜及所述电流转换模块连接，将被选中的存储单元中的读电流与所述读参考电流比较，以比较结果表示被选中的存储单元中存储的信号。
更优选地，所述灵敏放大器还包括电流镜寄生参数匹配模块，用于抵消各灵敏放大器中的电流镜寄生效应；包括栅端和源端接地的第三NMOS管及2(b-1)个并联第三PMOS管，各第三PMOS管的源端连接电源电压、漏端连接所述第三NMOS管的漏端、栅端连接所述电流镜的输入端，各第三PMOS管的尺寸与所述电流镜中各晶体管的尺寸相同，其中b为所述三维存储单元阵列中连接于同一个读参考电路的灵敏放大器的个数。
优选地，所述不选字线连接不选字线电压源，其电压使存储单元不被选中。
更优选地，所述不选位线连接不选位线电压源，其电压使存储单元不被选中。
为实现上述目的及其他相关目的，本发明提供一种如上述三维存储器读出电路的读出方法，所述三维存储器读出方法至少包括：
选中一根字线和一根位线，将三维存储单元阵列中的一个存储单元连接至灵敏放大器， 所述灵敏放大器读取所述存储单元的读电流；
在所述一根字线、所述一根位线和所述灵敏放大器开始工作的同一时刻，读参考电路开始工作，产生一动态的读参考电流，所述读参考电流的瞬态值处于读低阻态电流和读高阻态电流之间；
所述灵敏放大器将被选中的所述存储单元的读电流和所述读参考电流进行比较，以产生被选中的所述存储单元的读出电压信号。
优选地，在所述读参考电流中引入位线寄生参数和位线上的漏电，以抵消读取存储单元时产生的阵列位线寄生效应和位线上存储单元的漏电，消除伪读取现象，减小信号读出时间，减少误读取。
优选地，在所述读参考电流中引入字线上的漏电，以抵消读取存储单元时字线上存储单元的漏电，消除伪读取现象，减小信号读出时间。
优选地，在所述读参考电流中引入传输门寄生参数，以抵消读取存储单元时产生的阵列传输门寄生效应，消除伪读取现象，减小信号读出时间。
优选地，在被选中的存储单元的读电流中引入电流镜寄生参数，以实现被选中的所述存储单元的读电流的镜像参数和所述参考电流的镜像参数的匹配，消除伪读取现象，减小信号读出时间。
优选地，当被选中的存储单元的读电流大于所述参考电流时，所述存储单元呈低阻态；当被选中的存储单元的读电流小于所述参考电流时，所述存储单元呈高阻态。
如上所述，本发明的三维存储器读出电路及读出方法，具有以下有益效果：
1、本发明的三维存储器读出电路及读出方法中，在读取信号发出后，读参考电路才开始工作，在读参考电流中引入对位线寄生参数的匹配、对传输门寄生参数的匹配、对位线和字线漏电的匹配，在读电流中引入对电流镜寄生参数的匹配，使得读参考电流的瞬态曲线处在读高阻态电流和读低阻态电流之间，最大程度的消除了伪读取现象，减小了读出时间。
2、本发明的三维存储器读出电路及读出方法中，读参考电流和读电流有相同的漏电流，减少了误读取。
3、本发明的三维存储器读出电路及读出方法对于规模从1Mb到1Tb的三维存储器都能大幅减小读出时间，适用范围广。
附图说明
图1显示为交叉堆叠结构三维非易失存储器示意图。
图2显示为现有技术中的伪读取现象影响读取时间的原理示意图。
图3显示为本发明的三维存储单元阵列的示意图。
图4显示为本发明读参考电路的一种实施方式。
图5显示为本发明的灵敏放大器的工作原理示意图。
图6显示为本发明的读参考电路的另一种实施方式。
图7显示为本发明的三维存储器读电路中读电流与读参考电流的对比示意图。
图8显示为本发明的三维存储器读出电路应用于64Mbit相变存储器芯片时，在读取低阻态时的仿真结果。
图9显示为本发明的三维存储器读出电路应用于64Mbit相变存储器芯片时，在读取高阻态时的仿真结果。
元件标号说明
1                     三维存储单元阵列
11                    三维存储单元子阵列
111                   存储单元
1111                  第一存储器件
1112                  第一选通管
12                    灵敏放大器
121                   第二钳位管
122                   电流镜寄生参数匹配模块
2                     读参考电路
21                    参考单元
211                   第二选通管
22                    位线驱动模块
23                    字线驱动模块
24                    位线匹配模块
241                   第一位线匹配单元
242                   第二位线匹配单元
25                    传输门寄生参数匹配模块
251                   本地传输门寄生参数匹配单元
252                   全局传输门寄生参数匹配单元
26                    第一钳位管
27                    电压转换模块
28                    字线匹配模块
S1～S2                步骤
具体实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。
请参阅图3～图9。需要说明的是，本实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图式中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。
实施例一
如图3～图5所示，本发明提供一种三维存储器读出电路，所述三维存储器读出电路包括三维存储单元阵列1及读参考电路2。
如图3所示，所述三维存储单元阵列1包括至少一个三维存储单元子阵列11以及与所述三维存储单元子阵列对应的多个灵敏放大器12，所述三维存储单元阵列1中各位线分别通过传输门与对应的灵敏放大器12连接；所述灵敏放大器12连接所述读参考电路2及对应的存储单元，将读参考电流与被选中的存储单元中读出的电流相比较，以产生被选中的存储单元的读出电压信号。
具体地，如图3所示，在本实施例中，所述三维存储单元阵列1包括三个三维存储单元子阵列11，在实际设计中可根据需要进行设定，不以本实施例为限。所述三维存储单元阵列1中，上层存储单元和下层存储单元均使用同一根位线，全局位线GBL与灵敏放大器一一对应，所述灵敏放大器12的数量设定为b个，且这b个灵敏放大器连接于同一个读参考电路以接收读参考电压或读参考电流。在本实施例中，所述三维存储单元子阵列11中连接于同一根位线的字线或存储单元的个数设定为n，所述三维存储单元子阵列11中连接于同一根字线的位线或存储单元的个数设定为a；所述三维存储单元子阵列11中连接于同一根本地位线LBL 的位线BL个数设定为m，各位线BL分别通过本地传输门与本地位线LBL连接；所述三维存储单元子阵列11中连接于同一根全局位线GBL的本地位线LBL个数设定为c，各本地位线LBL分别通过全局传输门与全局位线GBL连接，即连接于同一所述灵敏放大器12的位线BL的个数设定为mc。具体数值可根据实际需要做设定，在此不一一限定。
更具体地，如图3所示，所述存储单元子阵列11包括多个存储单元111，其中，(n*m)个存储单元111组成阵列连接于同一本地位线；行控制信号为字线信号WLUP_1～WLUP_n/2和WLDN_1～WLDN_n/2(分别控制上层和下层的存储单元111)；列传输信号为位线信号BL1～BLm，同一时间仅有一根字线WL和一根位线BL导通，以本地位线LBL连接一个存储单元111。位线BL通过本地传输门LTG与本地位线LBL相连，本地位线LBL通过全局传输门GTG与全局位线GBL相连。所述存储单元111包括第一存储器件1111和第一选通管1112。存储器件可为OMS效应器件，选通管可为OTS效应器件，不以本实施例为限。在本实施例中，以第一行第一列的下层存储单元为例，所述第一存储器件1111一端依次连接第一本地传输门LTG1和第一全局传输门GTG1后与第一灵敏放大器相连、另一端接所述第一选通管1112的一端，所述第一选通管1112的另一端接第一字线WLDN_1。
如图4所示，所述读参考电路2连接所述灵敏放大器12，用于产生读参考电压Vref或读参考电流Iref，在本实施例中，以读参考电压Vref为例。所述读参考电路2包括：参考单元21、位线驱动模块22、字线驱动模块23、位线匹配模块24、传输门寄生参数匹配模块25、第一钳位管26以及电压转换模块27。
具体地，如图4所示，所述参考单元21连接于参考字线WL’与参考位线BL’之间，用于提供参考电阻值。所述参考单元21包括参考电阻Rref和第二选通管211，其中，所述第二选通管211一端通过所述参考字线WL’连接所述字线驱动模块25的输出端、另一端连接所述参考电阻Rref的一端，所述参考电阻Rref的另一端连接所述参考位线BL’。所述参考电阻Rref的阻值设在低阻态电阻最高值和高阻态电阻最低值之间。所述第二选通管211与所述存储单元111中的第一选通管1112为同一类型。
具体地，如图4所示，所述位线驱动模块22连接于所述参考位线BL’，用于驱动所述参考位线BL’。所述位线驱动模块22包括第一NMOS管NM1，所述第一NMOS管NM1的源端连接不选位线信号DESBL、栅端连接使能信号EN的反信号(在本实施例中，通过所述使能信号EN连接反相器得到反信号)、漏端连接所述参考位线BL’。所述第一NMOS管NM1作为位线不选择驱动；当所述使能信号EN不起效(低电平)时，所述第一NMOS管NM1导通，所述参考位线BL’通过所述不选位线DESBL连接不选位线电压源，所述参考位线BL’ 不被选中；当所述使能信号EN起效(高电平)时，所述第一NMOS管NM1不通。在本实施例中，存储器进行读操作时，本地位线电压为VBL，不选位线电压源的电压为VBL/2。
具体地，如图4所示，所述字线驱动模块23连接于所述参考字线WL’的输入端，用于驱动所述参考字线WL’。所述字线驱动模块23包括第二NMOS管NM2及第二PMOS管PM2，所述第二NMOS管NM2的源端接地(0V)、栅端连接使能信号EN、漏端连接所述参考字线WL’；所述第二PMOS管PM2的源端连接所述不选字线DESWL、栅端连接所述使能信号EN、漏端连接所述参考字线WL’。所述第二NMOS管NM2及所述第二PMOS管PM2分别作为字线选择驱动和字线不选择驱动；当所述使能信号EN不起效(低电平)时，所述第二PMOS管PM2导通，所述参考字线WL’通过所述不选字线DESWL连接不选字线电压源，所述参考单元21不被选中；当所述使能信号EN起效(高电平)时，所述第二NMOS管NM2导通，所述参考字线WL’连接低电平(0V)，所述参考单元21被选中。在本实施例中，存储器进行读操作时，本地字线电压为VBL，不选字线电压源的电压为VBL/2。
具体地，如图4所示，所述位线匹配模块24连接于所述参考位线BL’与所述不选字线DESWL之间，用于提供位线寄生参数和漏电，以匹配所述三维存储单元阵列1中的位线寄生参数和位线上存储单元的漏电。
更具体地，所述位线匹配模块24包括(n-1)个并联的存储单元，其中n为所述三维存储单元阵列1中连接于同一根位线的字线个数。如图4所示，所述位线匹配模块24可分为第一位线匹配单元241及第二位线匹配单元242，其中，所述第一位线匹配单元241包括(n/2-1)个存储单元，用于匹配下层存储单元的位线寄生参数和其在第一位线BL1上的漏电；所述第二位线匹配单元242包括(n/2)个存储单元，用于匹配上层存储单元的位线寄生参数和其在第一位线BL1上的漏电(对应于本实施例中选中的存储单元为第一行第一列的下层存储单元)。n为所述三维存储单元阵列1中连接于同一根位线BL的字线WL个数。当读取某一存储单元时，其所在列中其余(n-1)个存储单元处于关断状态，所述第一存储器件1111和所述第一选通管1112的寄生电容对读电流Iread产生影响，通过设置所述第一位线匹配单元241和第二位线匹配单元242可以在读参考电流Iref中引入与所述三维存储单元阵列1匹配的寄生充电电流，以此得到的读参考电流Iref的变化趋势与所述读电流Iread一致，进而消除伪读取现象，减小信号读出时间。
具体地，如图4所示，所述传输门寄生参数匹配模块25连接于所述参考位线BL’与所述第一钳位管26的源端之间，用于提供传输门寄生参数以匹配所述三维存储单元阵列1中的传输门寄生参数。所述传输门寄生参数匹配模块25包括第一传输门LTG0、第二传输门GTG0、 本地传输门寄生参数匹配单元251及全局传输门寄生参数匹配单元252。
更具体地，所述第一传输门LTG0及所述第二传输门GTG0串联于所述参考位线BL’及所述第一钳位管26的源端之间，所述第一传输门LTG0为本地传输门、所述第二传输门GTG0为全局传输门，所述第一传输门LTG0与所述第二传输门GTG0之间的连线作为本地参考位线LBL’，所述第二传输门GTG0与所述第一钳位管26之间的连线作为全局参考位线GBL’。
更具体地，所述本地传输门寄生参数匹配单元251连接于所述本地参考位线LBL’和所述不选位线DESBL之间，用于提供传输门寄生参数以匹配所述三维存储单元阵列1中的本地传输门寄生参数。所述本地传输门寄生参数匹配单元251包括(m-1)个并联的第三传输门LTG，其中m为所述三维存储单元阵列1中连接于同一根本地位线LBL的位线个数；各第三传输门LTG的结构、尺寸与所述第一传输门LTG0和所述三维存储单元阵列1中的各本地传输门相同；各第三传输门LTG的一端连接所述本地参考位线LBL’、另一端接所述不选位线DESBL、控制端接地，始终处于不导通的状态。所述本地传输门寄生参数匹配单元251用于匹配本地传输门寄生参数，当读取存储单元时，与其连接的本地传输门开启，其余(m-1)个本地传输门处于关断状态，传输门上的寄生电容和寄生电阻对读电流Iread产生影响，通过设置所述本地传输门寄生参数匹配单元251可以在所述读电流Iread中进一步引入与所述三维存储单元阵列1匹配的本地传输门寄生电流，以此得到的读参考电流Iref的变化趋势与所述读电流Iread一致，进而消除伪读取现象，减小信号读出时间。
更具体地，所述全局传输门寄生参数匹配单元252连接于所述全局参考位线GBL’与地之间，用于提供传输门寄生参数以匹配所述三维存储单元阵列1中的全局传输门寄生参数。所述全局传输门寄生参数匹配单元252包括(c-1)个并联的第四传输门GTG，其中c为所述三维存储单元阵列1中连接于同一根全局位线GBL的本地位线个数；各第四传输门GTG的结构、尺寸与所述第二传输门GTG0和所述三维存储单元阵列1中的各全局传输门相同；各第四传输门GTG的一端连接所述全局参考位线GBL’、另一端接地、控制端接地，始终处于不导通的状态。所述全局传输门寄生参数匹配单元252用于匹配全局传输门寄生参数，当读取存储单元时，与其连接的全局传输门开启，其余(c-1)个全局传输门处于关断状态，传输门上的寄生电容和寄生电阻对读电流Iread产生影响，通过设置所述全局传输门寄生参数匹配单元252可以在所述读电流Iread中进一步引入与所述三维存储单元阵列1匹配的全局传输门寄生电流，以此得到的读参考电流Iref的变化趋势与所述读电流Iread一致，进而消除伪读取现象，减小信号读出时间。
如图4所示，所述第一钳位管26根据所述参考电阻值、所述第一位线匹配单元241和第 二位线匹配单元242提供的位线寄生参数和漏电及所述本地传输门寄生参数匹配单元251和全局传输门寄生参数匹配单元252提供的传输门寄生参数，得到读参考电流Iref。
具体地，如图4所示，所述第一钳位管26的源端连接所述全局参考位线GBL’、栅端连接钳位电压Vclamp、漏端连接所述电压转换模块27。
如图4所示，所述电压转换模块27连接于所述第一钳位管26的漏端，用于将所述读参考电流Iref转化为读参考电压Vref。
具体地，如图4所示，所述电压转换模块27包括第一PMOS管PM1，所述第一PMOS管PM1的源端连接电源电压VDD、栅端与漏端连接并作为所述读参考电压Vref的输出端、漏端还连接于第一钳位管26的漏端。所述电压转换模块27的结构不限，任意具有电流转电压功能的电路均适用，不限于本实施例。
如图3所示，所述灵敏放大器12与所述三维存储单元子阵列11对应，在本实施例中，mc根位线连接同一灵敏放大器，所述灵敏放大器12通过传输门分别与所述三维存储单元子阵列11中的位线连接，并且与所述读参考电路2连接，接收所述读参考电流Iref或所述读参考电压Vref(在本实施例中，接收读参考电压Vref)。所述灵敏放大器12将所述读参考电压Vref还原为读参考电流Iref，并将所述读参考电流Iref与所述三维存储单元阵列1中被选中的存储单元111中的读电流Iread相比较，以产生被选中的存储单元111的读出电压信号。
具体地，如图5所示，所述灵敏放大器12包括源端与所述存储单元111连接的第二钳位管121，与所述第二钳位管121的漏端连接的电流镜，电流镜寄生参数匹配模块122，与所述读参考电压Vref连接的电流转换模块，比较模块以及SR锁存器。
更具体地，所述第二钳位管121的栅端连接所述钳位电压Vclamp，在所述钳位电压Vclamp的控制下产生被选中的存储单元111中的读电流Iread。所述电流镜提取被选中的存储单元111中的读电流Iread，包括第四PMOS管PM4、第五PMOS管PM5。所述电流镜寄生参数匹配模块122包括栅端和源端接地的第三NMOS管NM3及2(b-1)个并联第三PMOS管PM3，各第三PMOS管PM3的源端连接电源电压VDD、漏端连接所述第三NMOS管NM3的漏端、栅端连接所述电流镜的输入端，各第三PMOS管PM3的尺寸与第四PMOS管PM4、第五PMOS管PM5、第六PMOS管PM6、第七PMOS管PM7、第八PMOS管PM8及所述读参考电路2中的第一PMOS管PM1的尺寸相同，其中b为所述三维存储单元阵列1中连接于同一个读参考电路的灵敏放大器个数。所述电流镜寄生参数匹配模块122用于匹配电流镜寄生参数，所述读参考电压Vref同时与b个灵敏放大器连接，势必会在所述读参考电压Vref中引入其余(b-1)个灵敏放大器中转换所述读参考电流Iref的电流镜寄生参数，在本实 施例中，通过第六PMOS管PM6、第八PMOS管PM8实现所述读参考电流Iref的镜像，因此第三PMOS管PM3的数量设定为2(b-1)，此时，在读电流端，有(2b+1)个PMOS管；在参考电流端，同样有(2b+1)个PMOS管，两边的电流镜个数和电流镜寄生参数实现了平衡。不同电路结构中第三PMOS管PM3的数量也不相同，可根据具体电路结果做设定，不以本实施例为限。通过设置所述电流镜寄生参数匹配模块122可以在所述读电流Iref中引入与各灵敏放大器中电流镜匹配的电流镜寄生电流，以此使得读参考电流Iref的变化趋势与所述读电流Iread一致，进而消除伪读取现象，减小信号读出时间。所述电流转换模块将所述读参考电压Vref还原为读参考电流Iref，包括第六PMOS管PM6。所述比较模块与所述电流镜及所述电流转换模块连接，将被选中的存储单元111中的读电流Iread与所述读参考电流Iref比较，以比较结果表示被选中的存储单元111中存储的信号，包括第七PMOS管PM7、第八PMOS管P8、第四NMOS管NM4、第五NMOS管NM5、第六NMOS管NM6以及第七NMOS管NM7。第四PMOS管PM4的漏端连接第二钳位管121，与第五PMOS管PM5、第七PMOS管PM7组成电流镜，将被选中的存储单元111的读电流Iread镜像到第五PMOS管PM5、第七PMOS管PM7的漏端。第四NMOS管NM4的漏端连接第五PMOS管PM5的漏端，与第七NMOS管NM7组成电流镜。所述读参考电路2中的第一PMOS管PM1与第六PMOS管PM6、第八PMOS管PM8组成电流镜，将所述读参考电流Iref镜像到第六PMOS管PM6、第八PMOS管PM8的漏端。第五NMOS管NM5的漏端连接于第六PMOS管PM6的漏端，与第六NMOS管NM6组成电流镜。第六NMOS管NM6的漏端与第七PMOS管PM7的漏端相连，作为所述比较模块的第一输出端。第七NMOS管NM17的漏端与第八PMOS管PM8的漏端相连，作为所述比较模块的第二输出端。所述比较模块的第一输出端和第二输出端为差分输出。所述SR锁存器的R端连接所述比较模块的第一输出端，所述SR锁存器的S端连接所述比较模块的第二输出端，根据所述比较模块的输出信号得到被选中的存储单元111的读电压。
实施例二
如图6所示，本实施例提供一种三维存储器读出电路，所述三维存储器读出电路的结构与实施例一类似，不同之处在于，所述三维存储器读出电路还包括：连接于所述参考字线Wl’与不选位线DESBL之间的字线匹配模块，用于提供字线上的漏电以匹配所述三维存储单元阵列1中字线上存储单元的漏电。
具体地，如图6所示，所述字线匹配模块28包括(a-1)个并联的存储单元，其中a为所述三维存储单元阵列1中连接于同一根字线的位线个数。
相应地，所述第一钳位管26根据所述参考电阻值、所述位线匹配模块24提供的位线寄生参数和漏电、所述字线匹配模块28提供的漏电及所述传输门寄生参数匹配模块25提供的传输门寄生参数，得到读参考电流Iref。
其他模块的结构及作用于实施例一相同，在此不一一赘述。
如图3～图9所示，本发明还提供一种三维存储器读出方法，所述三维存储器读出方法至少包括：
步骤S1：选中一根字线和一根位线，将三维存储单元阵列中的一个存储单元连接至灵敏放大器，所述灵敏放大器读取所述存储单元的读电流；在所述一根字线、所述一根位线和所述灵敏放大器开始工作的同一时刻，读参考电路开始工作，产生一动态的读参考电流，所述读参考电流的瞬态值处于读低阻态单元电流和读高阻态单元电流之间。
具体地，如图3所示，在本实施例中，以第1行第1列的下层存储单元为例，将第一字线WLDN_1置于低电平，其余字线置为不选字线电压，同时开启第一本地传输门LTG1和第一GTG1，此时，与第一位线BL1连接的电流信号被输出至所述灵敏放大器12，与第一位线BL1连接的信号包括被选中的第1行第1列的下层存储单元中的电流、半选通的存储单元的寄生电容和寄生电阻产生的电流、半选通的存储单元的漏电流以及未导通的各传输门上的寄生电容和寄生电阻产生的电流，且所述灵敏放大器12接收到的读电流Iread会随着寄生电容的充电过程慢慢增大，再慢慢减小，如图7所示。
具体地，如图4及图6所示，在第一字线WLDN_1置为低电平，第一本地传输门LTG1和第一全局传输门GTG1开启，所述灵敏放大器12开始工作的同时，所述使能信号EN起效，并在所述第一钳位管26的源端产生所述读参考电流Iref，所述读参考电流Iref包括所述参考单元21中参考电阻上的电流、所述位线匹配模块24提供的存储单元的寄生电容产生的电流和存储单元的漏电、所述字线匹配模块28提供的存储单元的漏电及所述本地传输门寄生参数匹配单元251和全局传输门寄生参数匹配单元252提供的寄生电容和寄生电阻产生的电流，同理，所述读参考电流Iref会随着寄生电容的充电过程慢慢增大，再慢慢减小，且变化趋势与所述读电流Iread一致，进而消除了伪读取现象，减小了信号的读出时间。在所述读参考电流Iref中引入位线寄生参数和漏电，以抵消读取存储单元时产生的阵列位线寄生效应和漏电；在所述读参考电流Iref中引入字线上的漏电，以抵消读取存储单元时字线上的漏电；在所述读参考电流Iref中引入传输门寄生参数，以抵消读取存储单元时产生的阵列传输门寄生效应。如图7所示，所述读参考电流Iref为动态值，其瞬态值处于读低阻态单元电流和读高阻态单 元电流之间。
步骤S2：获取被选中的存储单元的读电流，并将被选中的存储单元的读电流和所述读参考电流进行比较，以产生被选中的存储单元的读出电压信号。
具体地，如图6所示，所述第二钳位管121受所述钳位电压Vclamp的控制产生所述存储单元111的读电流Iread，并通过电流镜传输到所述第七NMOS管NM7的栅端，同时，所述电流镜寄生参数匹配模块122在所述读电流Iread中引入电流镜寄生参数，以实现被选中的存储单元的读电流的镜像参数和所述参考电流的镜像参数的匹配，使得所述读参考电流Iref的变化趋势与所述读电流Iread一致，进而消除伪读取现象，减小信号读出时间，如图7所示。所述读参考电压Vref被还原为所述读参考电流Iref，并传输到所述第六NMOS管NM6的栅端。当所述存储单元111是一个低阻态存储单元时，Iread>Iref；第四NMOS管NM4的漏端电流会上升；第四NMOS管NM4的连线方式使它可以等效为一个二极管，所以第四NMOS管NM4的栅电压会上升，第七NMOS管NM7栅电压同样会上升，而第六NMOS管NM6栅电压会下降；此时所述比较模块的第二输出端的输出电压V2会下降到0V左右，而所述比较模块的第一输出端的输出电压V1会上升到接近于电源电压VDD。当所述存储单元111是一个高阻态存储单元时，Iread<Iref；第四NMOS管NM4的漏端电流会下降；第四NMOS管NM4的连线方式使它可以等效为一个二极管，所以第四NMOS管NM4的栅电压会下降，第七NMOS管NM7栅电压同样会下降，而第六NMOS管NM6栅电压会上升；此时所述比较模块的第二输出端的输出电压V2会上升到接近于电源电压VDD，而所述比较模块的第一输出端的输出电压V1会上升到接近于0V。所述比较模块的输出电压V1和V2输出到SR锁存器中，得到输出信号DO，当被选中的存储单元的读电流Iread大于所述参考电流Iref时，所述SR锁存器输出高电平；当被选中的存储单元的读电流Iread小于所述参考电流Iref时，所述SR锁存器输出低电平。
如图7所示，本发明的读参考电流在电流上升阶段就已处在读低阻态单元电流和读高阻态单元电流之间，相比图2伪读取时间大大减小。
如图8～图9所示，为本发明的三维存储器读出电路应用于相变存储器时的仿真结果。该芯片采用40nm工艺，容量为64Mbit，采用交叉堆叠的三维存储结构。芯片有两层存储单元，两层字线，一层位线，n＝1024,a＝1024,m＝16,c＝16,b＝16。其中，EN信号为使能信号，随着EN信号电压的升高，灵敏放大器开始读取。在读取低阻(低阻态)时，读取时间为39.67ns；在读取高阻(高阻态)时，读取时间小于0.5ns。本发明的三维存储器读出电路的随机读取时间为39.67ns。与之对比，采用传统读出方法的64Mbit三维存储器芯片读出时间在185.3ns左 右。
如上所述，本发明的三维存储器读出电路及读出方法，具有以下有益效果：
1、本发明的三维存储器读出电路及读出方法中，在读取信号发出后，读参考电路才开始工作，在读参考电流中引入对位线寄生参数的匹配、对传输门寄生参数的匹配、对漏电的匹配，在读电流中引入对电流镜寄生参数的匹配，使得读参考电流的瞬态曲线处在读高阻态电流和读低阻态电流之间，最大程度的消除了伪读取现象，减小了读出时间。
2、本发明的三维存储器读出电路及读出方法中，读参考电流和读电流有相同的漏电流，减少了误读取。
3、本发明的三维存储器读出电路及读出方法对于规模从1Mb到1Tb的三维存储器都能大幅减小读出时间，适用范围广。
综上所述，本发明提供一种三维存储器读出电路及读出方法，包括：读参考电路，产生一个可以快速区分读低阻态单元电流和读高阻态单元电流的读参考电流；以及灵敏放大器。读参考电路包括参考单元、位线匹配模块、字线匹配模块和传输门寄生参数匹配模块。本发明针对三维存储器在平面和垂直方向的寄生效应和漏电，在读参考电流中引入对位线寄生参数、漏电和传输门寄生参数的匹配，在读电流中引入对电流镜寄生参数的匹配，消除了伪读取现象，减小了读出时间；且信号传递速度快、适用范围广、读出正确率高。所以，本发明有效克服了现有技术中的种种缺点而具高度产业利用价值。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (23)

  1. 一种三维存储器读出电路，其特征在于，所述三维存储器读出电路至少包括：
    三维存储单元阵列，包括至少一个三维存储单元子阵列以及与所述三维存储单元子阵列对应的多个灵敏放大器，所述三维存储单元阵列中各位线分别通过传输门与对应的灵敏放大器连接；所述灵敏放大器连接所述读参考电路及对应的存储单元，将读参考电流与被选中的存储单元中读出的电流相比较，以产生被选中的存储单元的读出电压信号；
    读参考电路，用于产生读参考电压或读参考电流，包括：参考单元、位线匹配模块、传输门寄生参数匹配模块以及第一钳位管；
    其中，所述参考单元连接于参考字线与参考位线之间，用于提供参考电阻值；
    所述位线匹配模块连接于所述参考位线与不选字线之间，用于提供位线寄生参数和漏电，以匹配所述三维存储单元阵列中的位线寄生参数和位线上存储单元的漏电；
    所述传输门寄生参数匹配模块连接于所述参考位线与所述第一钳位管的源端之间，用于提供传输门寄生参数以匹配所述三维存储单元阵列中的传输门寄生参数；
    所述第一钳位管根据所述参考电阻值、所述位线匹配模块提供的位线寄生参数和漏电及所述传输门寄生参数匹配模块提供的传输门寄生参数，得到读参考电流。
  2. 根据权利要求1所述的三维存储器读出电路，其特征在于：所述三维存储器读出电路还包括：连接于所述参考字线与不选位线之间的字线匹配模块，用于提供字线上的漏电以匹配所述三维存储单元阵列中字线上存储单元的漏电；所述第一钳位管根据所述参考电阻值、所述位线匹配模块提供的位线寄生参数和漏电、所述字线匹配模块提供的漏电及所述传输门寄生参数匹配模块提供的传输门寄生参数，得到读参考电流。
  3. 根据权利要求2所述的三维存储器读出电路，其特征在于：所述字线匹配模块包括(a-1)个并联的存储单元，其中a为所述三维存储单元阵列中连接于同一根字线的位线个数。
  4. 根据权利要求1所述的三维存储器读出电路，其特征在于：所述参考单元包括参考电阻和选通管，其中，所述选通管的一端接所述参考字线、一端连接所述参考电阻的一端；所述参考电阻的另一端连接所述参考位线。
  5. 根据权利要求4所述的三维存储器读出电路，其特征在于：所述参考电阻的阻值设在低阻态电阻最高值和高阻态电阻最低值之间。
  6. 根据权利要求4所述的三维存储器读出电路，其特征在于：所述选通管与存储单元中的选通管为同一类型。
  7. 根据权利要求1所述的三维存储器读出电路，其特征在于：所述位线匹配模块包括(n-1)个并联的存储单元，其中n为所述三维存储单元阵列中连接于同一根位线的字线个数。
  8. 根据权利要求1所述的三维存储器读出电路，其特征在于：所述传输门寄生参数匹配模块包括第一传输门、第二传输门、本地传输门寄生参数匹配单元及全局传输门寄生参数匹配单元；所述第一传输门及所述第二传输门串联于所述参考位线及所述第一钳位管的源端之间，所述第一传输门与所述第二传输门之间的连线作为本地参考位线，所述第二传输门与所述第一钳位管之间的连线作为全局参考位线；所述本地传输门寄生参数匹配单元连接于所述本地参考位线和不选位线之间，用于提供传输门寄生参数以匹配所述三维存储单元阵列中的本地传输门寄生参数；所述全局传输门寄生参数匹配单元连接于所述全局参考位线与地之间，用于提供传输门寄生参数以匹配所述三维存储单元阵列中的全局传输门寄生参数。
  9. 根据权利要求8所述的三维存储器读出电路，其特征在于：所述本地传输门寄生参数匹配单元包括(m-1)个并联的第三传输门，其中m为所述三维存储单元阵列中连接于同一根本地位线的位线个数；各第三传输门的结构、尺寸与所述读参考电路中的第一传输门和所述三维存储单元阵列中的各本地传输门相同；各第三传输门的一端连接所述本地参考位线、另一端接所述不选位线、控制端接地。
  10. 根据权利要求8所述的三维存储器读出电路，其特征在于：所述全局传输门寄生参数匹配单元包括(c-1)个并联的第四传输门，其中c为所述三维存储单元阵列中连接于同一根全局位线的本地位线个数；各第四传输门的结构、尺寸与所述读参考电路中的第二传输门和所述三维存储单元阵列中的各全局传输门相同；各第四传输门的一端连接所述全局参考位线、另一端接地、控制端接地。
  11. 根据权利要求1所述的三维存储器读出电路，其特征在于：所述读参考电路还包括：电压转换模块，用于将所述读参考电流转化为读参考电压；包括第一PMOS管，所述第一 PMOS管的源端连接电源电压、栅端与漏端连接并作为所述读参考电压的输出端、漏端还连接于第一钳位管的漏端。
  12. 根据权利要求1所述的三维存储器读出电路，其特征在于：所述读参考电路还包括：连接于所述参考位线的输入端的位线驱动模块，用于驱动所述参考位线；所述位线驱动模块包括第一NMOS管，所述第一NMOS管的源端连接不选位线信号、栅端连接使能信号的反信号、漏端连接所述参考位线。
  13. 根据权利要求1所述的三维存储器读出电路，其特征在于：所述读参考电路还包括：连接于所述参考字线的输入端的字线驱动模块，用于驱动所述参考字线；所述字线驱动模块包括第二NMOS管及第二PMOS管，所述第二NMOS管的源端接地、栅端连接使能信号、漏端连接所述参考字线；所述第二PMOS管的源端连接所述不选字线、栅端连接所述使能信号、漏端连接所述参考字线。
  14. 根据权利要求1所述的三维存储器读出电路，其特征在于：所述灵敏放大器包括源端与所述存储单元连接的第二钳位管，与所述第二钳位管的漏端连接的电流镜，与所述读参考电压连接的电流转换模块，以及比较模块；所述第二钳位管的栅端连接钳位电压；所述电流镜提取被选中的存储单元中的读电流；所述电流转换模块将所述读参考电压转化为读参考电流；所述比较模块与所述电流镜及所述电流转换模块连接，将被选中的存储单元中的读电流与所述读参考电流比较，以比较结果表示被选中的存储单元中存储的信号。
  15. 根据权利要求14所述的三维存储器读出电路，其特征在于：所述灵敏放大器还包括电流镜寄生参数匹配模块，用于抵消各灵敏放大器中的电流镜寄生效应；包括栅端和源端接地的第三NMOS管及2(b-1)个并联第三PMOS管，各第三PMOS管的源端连接电源电压、漏端连接所述第三NMOS管的漏端、栅端连接所述电流镜的输入端，各第三PMOS管的尺寸与所述电流镜中各晶体管的尺寸相同，其中b为所述三维存储单元阵列中连接于同一个读参考电路的灵敏放大器的个数。
  16. 根据权利要求1所述的三维存储器读出电路，其特征在于：所述不选字线连接不选字线电压源，其电压使存储单元不被选中。
  17. 根据权利要求2、8、9或12所述的三维存储器读出电路，其特征在于：所述不选位线连接不选位线电压源，其电压使存储单元不被选中。
  18. 一种如权利要求1～17任意一项所述的三维存储器读出电路的读出方法，其特征在于，所述三维存储器读出方法至少包括：
    选中一根字线和一根位线，将三维存储单元阵列中的一个存储单元连接至灵敏放大器，所述灵敏放大器读取所述存储单元的读电流；
    在所述一根字线、所述一根位线和所述灵敏放大器开始工作的同一时刻，读参考电路开始工作，产生一动态的读参考电流，所述读参考电流的瞬态值处于读低阻态电流和读高阻态电流之间；
    所述灵敏放大器将被选中的所述存储单元的读电流和所述读参考电流进行比较，以产生被选中的所述存储单元的读出电压信号。
  19. 根据权利要求18所述的三维存储器读出方法，其特征在于：在所述读参考电流中引入位线寄生参数和位线上的漏电，以抵消读取存储单元时产生的阵列位线寄生效应和位线上存储单元的漏电，消除伪读取现象，减小信号读出时间，减少误读取。
  20. 根据权利要求18所述的三维存储器读出方法，其特征在于：在所述读参考电流中引入字线上的漏电，以抵消读取存储单元时字线上存储单元的漏电，消除伪读取现象，减小信号读出时间。
  21. 根据权利要求18所述的三维存储器读出方法，其特征在于：在所述读参考电流中引入传输门寄生参数，以抵消读取存储单元时产生的阵列传输门寄生效应，消除伪读取现象，减小信号读出时间。
  22. 根据权利要求18所述的三维存储器读出方法，其特征在于：在被选中的存储单元的读电流中引入电流镜寄生参数，以实现被选中的所述存储单元的读电流的镜像参数和所述参考电流的镜像参数的匹配，消除伪读取现象，减小信号读出时间。
  23. 根据权利要求18所述的三维存储器读出方法，其特征在于：当被选中的存储单元的读电流大于所述参考电流时，所述存储单元呈低阻态；当被选中的存储单元的读电流小于所 述参考电流时，所述存储单元呈高阻态。
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