WO2018149017A1 - 一种锡掺杂 n 型氧化镓制备方法 - Google Patents

一种锡掺杂 n 型氧化镓制备方法 Download PDF

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WO2018149017A1
WO2018149017A1 PCT/CN2017/078235 CN2017078235W WO2018149017A1 WO 2018149017 A1 WO2018149017 A1 WO 2018149017A1 CN 2017078235 W CN2017078235 W CN 2017078235W WO 2018149017 A1 WO2018149017 A1 WO 2018149017A1
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gallium oxide
tin
oxide material
doping
doped
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PCT/CN2017/078235
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French (fr)
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梁红伟
夏晓川
张贺秋
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大连理工大学
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Priority to US16/314,601 priority Critical patent/US10615038B2/en
Publication of WO2018149017A1 publication Critical patent/WO2018149017A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/38—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions
    • H01L21/385—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2258—Diffusion into or out of AIIIBV compounds

Definitions

  • the invention belongs to the technical field of semiconductor material preparation, and particularly provides a method for preparing tin-doped n-type gallium oxide.
  • gallium oxide The third generation of wide bandgap semiconductor materials represented by gallium oxide is a high-efficiency ultraviolet detector due to its large forbidden band width, high breakdown field strength, high electron saturation drift velocity, corrosion resistance and radiation resistance. Gas sensors, friendly biosensors, and high-frequency, high-power, anti-radiation and other electronic devices have important applications.
  • Gallium oxide materials with electronic or hole-conducting properties are the basis for the preparation of these various types of devices. Research hotspots in the field of material preparation. At present, most of the undoped gallium oxide materials exhibit high resistivity characteristics, but they can exhibit electron or hole conduction characteristics by incorporating an appropriate amount of dopants, and at the same time, the resistivity thereof is remarkably lowered.
  • the control of the conductivity type of the gallium oxide material is achieved by performing related doping during the growth process.
  • the doping of the gallium oxide single crystal is to add appropriate tin or silicon element to the precursor to obtain the electronic conductive property; the gallium oxide film is Doping is the addition of tin or silicon in the reaction source to obtain electronic conductivity.
  • the corresponding device can be designed only in the longitudinal direction, that is, along the growth direction, and the lateral structure design of the device cannot be performed, especially in the integration of multiple types of devices, which is not conducive to the development and application of the new device.
  • tin and silicon materials The vapor pressure is lower than 1000 degrees, and it is difficult to enter the gallium oxide body by vapor phase diffusion to form n-type conductivity.
  • the object of the present invention is to provide a tin diffusion doping method for the above-mentioned lack of effective post-doping technology of gallium oxide material, which is to pre-deposit a suitable amount of tin doping source in a suitable method in gallium oxide.
  • the gallium oxide material is then placed in a high temperature resistant tube in an appropriate form, and then heat treated at a certain temperature for a certain period of time, so that the tin atoms can be controlled to diffuse into the gallium oxide material and activated as an effective donor, thereby achieving oxidation.
  • Gallium material N-type doping is then placed in a high temperature resistant tube in an appropriate form, and then heat treated at a certain temperature for a certain period of time, so that the tin atoms can be controlled to diffuse into the gallium oxide material and activated as an effective donor, thereby achieving oxidation.
  • a method for preparing tin-doped n-type gallium oxide the steps are as follows:
  • Step 1 Pre-deposit a tin doping source on the gallium oxide material or directly cover the tin doping source on the gallium oxide material, the thickness of the tin doping source is 1nm ⁇ 1mm;
  • Step 2 Place the gallium oxide material and choose one of the following methods:
  • the gallium oxide material processed in the step 1 is placed in a quartz boat or a quartz tube under normal pressure conditions;
  • the gallium oxide material processed in the step 1 is enclosed in a quartz tube, and the degree of vacuum in the quartz tube is less than 1 ⁇ 10 -3 Pa;
  • the gallium oxide material and the tin doping source processed in step 1 are enclosed in a quartz tube, and the degree of vacuum in the quartz tube is less than 1 ⁇ 10 -3 Pa;
  • Step 3 Heat treatment of the placed gallium oxide material in step 2, the heat treatment temperature is 100 ° C ⁇ 1500 ° C; the heat treatment time is 1h ⁇ 24h;
  • the heat treatment is performed under the protection of high purity nitrogen or argon gas
  • Step 4 After the temperature is lowered to room temperature, the tin-doped n-type gallium oxide is taken out;
  • Step 5 Subsequent treatment of tin-doped n-type gallium oxide: doping tin with a cleaning solution n The residue of the surface of the gallium oxide is cleaned once, and the residue produced is secondarily cleaned with deionized water; the gallium oxide material is blown dry and properly preserved.
  • the gallium oxide material is a single crystal, a polycrystal, and an epitaxial film prepared on a substrate;
  • the tin doping source is an oxide of tin or tin.
  • the preferred heat treatment temperature is from 700 ° C to 1200 ° C; preferably, the heat treatment time is from 2 h to 12 h.
  • the tin-doped source layer preferably has a thickness of 10 nm to 10 ⁇ m.
  • the cleaning liquid is one or a mixture of two or more of hydrochloric acid, hydrofluoric acid, sulfuric acid, nitric acid, hydrogen peroxide, sodium hydroxide, and potassium hydroxide.
  • the heater equipment used in the heat treatment process includes a box furnace, a tube furnace and an RTP rapid annealing furnace controlled by a single temperature zone or multiple temperature zones.
  • the deposition method is a sol-gel method, a thermal evaporation method, an electron beam evaporation method, a magnetron sputtering method, a laser pulse deposition method, an atomic layer epitaxy or a molecular beam epitaxy method.
  • the outstanding advantage of the present invention is that the doping can be realized after the preparation of the gallium oxide material is completed, and the required equipment and process are simple, and the doping controllability is high; and the tin doping technology adopted by the present invention is utilized.
  • Fig. 1 is a schematic view showing the structure of a gallium oxide single crystal having a tin elemental pre-deposited layer.
  • Figure 2 is an X-ray photoelectron spectroscopy of a tin-doped gallium oxide single crystal.
  • Fig. 3 is a schematic view showing the structure of a gallium oxide film having a tin elemental pre-deposited layer.
  • This embodiment provides a method for tin doping a gallium oxide single crystal, comprising the following process steps:
  • Step 1 The selected gallium oxide material has semi-insulating properties, thickness 600 ⁇ m, surface 5mm See square; the selected dopant source is high purity metal tin;
  • Step 2 pre-deposit a 100 nm thick tin layer on the above gallium oxide single crystal by a thermal evaporation method, as shown in FIG. 1;
  • Step 3 The gallium oxide single crystal and the 5 g metal tin treated in the step 2 are enclosed in a quartz tube, and the quartz tube has a high vacuum, and the degree of vacuum is 3 ⁇ 10 -4 Pa;
  • Step 4 Place the closed quartz tube placed in step 3 into a single-temperature zone tube furnace for heat treatment; the treatment temperature is 1000 °C. , the processing time is 6h;
  • Step 5 After the temperature is lowered to room temperature, the gallium oxide material is taken out;
  • Step 6 Clean the residue on the surface of the gallium oxide material with dilute hydrochloric acid
  • Step 7 Secondary cleaning the residue produced in step 6 with deionized water
  • Step 8 Dry the gallium oxide material and store it properly.
  • the surface of the gallium oxide doped with tin in the present embodiment was tested to exhibit electrical conductivity, and its surface resistivity was 3,400 ⁇ /sq, and the surface electron concentration was 3.5 ⁇ 10 15 /cm 2 .
  • Figure 2 shows the X-ray photoelectron spectroscopy on the surface of a gallium oxide single crystal. The secondary results show that with the technique of the present invention, we have successfully prepared tin-doped n-type gallium oxide.
  • This embodiment provides a method for tin doping a gallium oxide film, comprising the following process steps:
  • Step 1 The selected gallium oxide material is 2 ⁇ m thick and 10 mm surface prepared on the sapphire substrate by MOCVD. See square gallium oxide film; the selected doping source is high purity metal tin;
  • Step 2 pre-deposit a 10 nm thick tin layer on the gallium oxide film by thermal evaporation method, as shown in FIG. 3;
  • Step 3 The gallium oxide material treated in the step 2 and the 5 g metal tin are enclosed in a quartz tube, and the quartz tube has a high vacuum, and the degree of vacuum is 3 ⁇ 10 -4 Pa;
  • Step 4 Place the closed quartz tube placed in step 3 into a single-temperature zone tube furnace for heat treatment; the treatment temperature is 1000 °C. , processing time is 6 hours;
  • Step 5 After the temperature is lowered to room temperature, the gallium oxide material is taken out;
  • Step 6 Clean the residue on the surface of the gallium oxide material with dilute hydrochloric acid
  • Step 7 Secondary cleaning the residue produced in step 6 with deionized water
  • Step 8 Dry the gallium oxide material and store it properly.
  • the present embodiment has been tested for tin-doped gallium oxide has been shown in the embodiment conductive properties, a surface resistivity of sq., A surface electron concentration 4500 ⁇ / of 2.5 ⁇ 10 15 / cm 2.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
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Abstract

本发明属于半导体材料制备技术领域，具体提供了一种锡掺杂 n 型氧化镓制备方法。将适量的锡掺杂源以适当的方法预沉积在氧化镓材料上，然后将氧化镓材料以适当的形式放置在耐高温管内，而后在一定的温度下热处理一定时间，使得锡原子能可控的扩散到氧化镓材料中，并激活为有效施主，进而实现氧化镓材料的 n 型掺杂。本发明能够在氧化镓材料制备完成后实现掺杂，并且其所需设备和工艺过程简单，掺杂可控性高；利用本发明所提锡掺杂技术，不仅能够进行基于 n 型氧化镓材料的纵向器件结构制备，特别是还可以进行横向器件结构制备和多种类器件集成制造，进而研制出传统掺杂技术无法制备出的氧化镓基新型器件。

Description

一种锡掺杂 n 型氧化镓制备方法
技术领域
本发明属于半导体材料制备技术领域，具体提供了一种锡掺杂 n 型氧化镓制备方法。
背景技术
以氧化镓为代表的第三代宽禁带半导体材料因其禁带宽度大、击穿场强高、电子饱和漂移速度高、耐腐蚀和抗辐照等突出优点，在制作高效率紫外探测器、气体传感器、友好型生物传感器，以及高频、高功率、抗辐射等电子器件方面具有重要应用，具有电子或者空穴导电特性的氧化镓材料是制备上述各类器件的基础，也是当今氧化镓材料制备领域的研究热点。目前，非掺杂的氧化镓材料大多表现出高电阻率特性，但可通过掺入适量掺杂剂使得其表现出电子或者空穴导电特性，与此同时其电阻率得以显著降低。目前氧化镓材料导电类型的控制均是在生长过程中进行相关掺杂而实现，例如氧化镓单晶的掺杂就是在前驱体中加入适当的锡或者硅元素获得电子导电特性；氧化镓薄膜的掺杂是在反应源增加锡或者硅元素获得电子导电特性。利用上述方法仅可在纵向，即沿生长方向设计相应的器件，而无法进行器件横向结构设计，特别是在多类型器件集成方面显得无能为力，这不利于新型器件的研发与应用。特别是锡与硅材料在 1000 度以下时的蒸汽压较低，难以通过气相扩散的方式进入到氧化镓体内形成 n 型导电。
发明内容
本发明的目的在于，针对上述缺乏行之有效的氧化镓材料后掺杂技术问题，提出一种锡扩散掺杂方法，该方法是将适量的锡掺杂源以适当的方法预沉积在氧化镓材料上，然后将氧化镓材料以适当的形式放置在耐高温管内，而后在一定的温度下热处理一定时间，使得锡原子能可控的扩散到氧化镓材料中，并激活为有效施主，进而实现氧化镓材料的 n 型掺杂。
本发明的技术方案：
一种锡掺杂 n 型氧化镓制备方法，步骤如下：
步骤 1 . 在氧化镓材料上预沉积锡掺杂源或将锡掺杂源直接覆盖在氧化镓材料上，锡掺杂源的厚度为 1nm~1mm ；
步骤 2 . 安放氧化镓材料，选择如下方法中的一种：
方法一，在常压条件下，将步骤 1 处理后的 氧化镓材料置于石英舟或者石英管内；
方法二，将步骤 1 处理后的 氧化镓材料封闭在石英管内，石英管内的真空度小于 1×10-3Pa ；
方法三，将步骤 1 处理后的 氧化镓材料和锡掺杂源共同封闭在石英管内，石英管内的真空度小于 1×10-3Pa ；
步骤 3 . 对步骤 2 放置好的氧化镓材料进行热处理，热处理温度为 100℃~1500℃ ；热处理时间为 1h~24h ；
当选择方法一放置氧化镓材料时，在高纯氮气或氩气气体保护下进行热处理；
步骤 4. 温度降到室温后，取出锡掺杂 n 型氧化镓；
步骤 5. 锡掺杂 n 型氧化镓的后续处理：用清洗液对锡掺杂 n 型氧化镓表面的残留物进行一次清洁，再用去离子水对产生的残留物进行二次清洁；将氧化镓材料吹干，妥善保存。
所述的氧化镓材料是单晶、多晶和制备在衬底上的外延薄膜；所述的锡掺杂源是锡单质或锡的氧化物。
所述的优选热处理温度为 700℃~1200℃ ；优选热处理时间为 2h~12h 。
所述的锡掺杂源层的优选厚度为 10nm~10μm 。
所述的清洗液是盐酸、氢氟酸、硫酸、硝酸、双氧水、氢氧化钠、氢氧化钾中的一种或两种以上混合。
热处理过程中所用的加热器设备包括有单温区或多温区控制的箱式炉、管式炉和 RTP 快速退火炉。
所述的沉积方法是溶胶凝胶法、热蒸发法、电子束蒸发法、磁控溅射法、激光脉冲沉积、原子层外延或分子束外延法。
本发明的有益效果：本发明突出的优势是能够在氧化镓材料制备完成后实现掺杂，并且其所需设备和工艺过程简单，掺杂可控性高；利用本发明所提锡掺杂技术，不仅能够进行基于 n 型氧化镓材料的纵向器件结构制备，特别是还可以进行横向器件结构制备和多种类器件集成制造，进而研制出传统掺杂技术无法制备出的氧化镓基新型器件。
附图说明
图 1 是 具有锡单质预沉积层的氧化镓单晶的结构示意图。
图 2 是 锡掺杂氧化镓单晶的 X 射线光电能谱图。
图 3 是 具有锡单质预沉积层的氧化镓薄膜的结构示意图。
具体实施方式
以下结合附图和技术方案，进一步说明本发明的具体实施方式。
实施例 1
本实施例提供了一种对氧化镓单晶进行锡掺杂的方法，包括以下工艺步骤：
步骤 1 ：所选氧化镓材料具有半绝缘特性，厚度为 600μm 、表面 5mm 见方；所选掺杂源为高纯金属锡；
步骤 2 ：采用热蒸发方法，在上述氧化镓单晶上预沉积一层 100nm 厚的锡层，如图 1 所示；
步骤 3 ：将步骤 2 处理后的氧化镓单晶和 5g 金属锡，共同封闭在石英管内，石英管内为高真空，真空度为 3×10-4Pa ；
步骤 4 ：将步骤 3 所放置好的封闭石英管，放入单温区管式炉中进行热处理；处理温度为 1000℃ ，处理时间为 6h ；
步骤 5 ：温度降到室温后，取出氧化镓材料；
步骤 6 ：利用稀盐酸对氧化镓材料表面的残留物进行一次清洁；
步骤 7 ：利用去离子水对步骤 6 中的产生的残留物进行二次清洁；
步骤 8 ：将氧化镓材料吹干，妥善保存。
经检测本实施例中进行锡掺杂的氧化镓表面已经表现出导电特性，其表面电阻率为 3400Ω/sq ，表面电子浓度为 3.5×1015/cm2 。图 2 所示为在氧化镓单晶表面的 X 射线光电能谱图，次结果表明，利用本发明所述技术，我们成功制备出具有锡掺杂 n 型氧化镓。
实施例 2
本实施例提供了一种对氧化镓薄膜进行锡掺杂的方法，包括以下工艺步骤：
步骤 1 ：所选氧化镓材料为，采用 MOCVD 方法在蓝宝石衬底上制备的厚度为 2μm 、表面 10 mm 见方的氧化镓薄膜；所选掺杂源为高纯金属锡；
步骤 2 ：采用热蒸发方法，在上述氧化镓薄膜上预沉积一层 10nm 厚的锡层，如图 3 所示；
步骤 3 ：将步骤 2 处理后的氧化镓材料和 5g 金属锡，共同封闭在石英管内，石英管内为高真空，真空度为 3×10-4Pa ；
步骤 4 ：将步骤 3 所放置好的封闭石英管，放入单温区管式炉中进行热处理；处理温度为 1000℃ ，处理时间为 6 小时；
步骤 5 ：温度降到室温后，取出氧化镓材料；
步骤 6 ：利用稀盐酸对氧化镓材料表面的残留物进行一次清洁；
步骤 7 ：利用去离子水对步骤 6 中的产生的残留物进行二次清洁；
步骤 8 ：将氧化镓材料吹干，妥善保存。
经检测本实施例中进行锡掺杂的氧化镓已经表现出导电特性，其表面电阻率为 4500Ω/sq ，表面电子浓度为 2.5×1015/cm2 。
最后应说明的是：以上各实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述各实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。

Claims (5)

  1. 一种锡掺杂 n 型氧化镓制备方法，其特征在于，步骤如下：
    步骤 1 . 在氧化镓材料上预沉积锡掺杂源或将锡掺杂源直接覆盖在氧化镓材料上，锡掺杂源的厚度为 1nm~1mm ；
    步骤 2 . 安放氧化镓材料，选择如下方法中的一种：
    方法一，在常压条件下，将步骤 1 处理后的 氧化镓材料置于石英舟或石英管内；
    方法二，将步骤 1 处理后的 氧化镓材料封闭在石英管内，石英管内的真空度小于 1×10-3Pa ；
    方法三，将步骤 1 处理后的 氧化镓材料和锡掺杂源共同封闭在石英管内，石英管内的真空度小于 1×10-3Pa ；
    步骤 3 . 对步骤 2 放置好的氧化镓材料进行热处理，热处理温度为 100℃~1500℃ ；热处理时间为 1h~24h ；
    当选择方法一放置氧化镓材料时，在高纯氮气或氩气气体保护下进行热处理；
    步骤 4. 温度降到室温后，取出锡掺杂 n 型氧化镓；
    步骤 5. 锡掺杂 n 型氧化镓的后续处理：用清洗液对锡掺杂 n 型氧化镓表面的残留物进行一次清洁，再用去离子水对残留物进行二次清洁；将氧化镓材料吹干，妥善保存。
  2. 根据权利要求 1 所述的 锡掺杂 n 型氧化镓制备方法，其特征在于，所述的氧化镓材料是单晶、多晶和制备在衬底上的外延薄膜；所述的锡掺杂源是锡单质或锡的氧化物。
  3. 根据权利要求 1 或 2 所述的 锡掺杂 n 型氧化镓制备方法，其特征在于，热处理温度为 700℃~1200℃ ；热处理时间为 2h~12h 。
  4. 根据权利要求 1-3 所述的 锡掺杂 n 型氧化镓制备方法，其特征在于，锡掺杂源的厚度为 10nm~10μm 。
  5. 根据权利要求 1-4 所述的 锡掺杂 n 型氧化镓制备方法，其特征在于，所述的清洗液是盐酸、氢氟酸、硫酸、硝酸、双氧水、氢氧化钠、氢氧化钾中的一种或两种以上混合。
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CN103469299A (zh) * 2013-09-05 2013-12-25 大连理工大学 掺杂氧化镓膜的制备方法及掺杂氧化镓膜

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