WO2018146887A1 - Dispositif de vérification d'aspect externe - Google Patents

Dispositif de vérification d'aspect externe Download PDF

Info

Publication number
WO2018146887A1
WO2018146887A1 PCT/JP2017/041061 JP2017041061W WO2018146887A1 WO 2018146887 A1 WO2018146887 A1 WO 2018146887A1 JP 2017041061 W JP2017041061 W JP 2017041061W WO 2018146887 A1 WO2018146887 A1 WO 2018146887A1
Authority
WO
WIPO (PCT)
Prior art keywords
element chip
inspection
chip
pattern
defective
Prior art date
Application number
PCT/JP2017/041061
Other languages
English (en)
Japanese (ja)
Inventor
英一 大▲美▼
翔太 稲生
Original Assignee
東レエンジニアリング株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 東レエンジニアリング株式会社 filed Critical 東レエンジニアリング株式会社
Publication of WO2018146887A1 publication Critical patent/WO2018146887A1/fr

Links

Images

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
    • G01N21/84—Systems specially adapted for particular applications
    • G01N21/88—Investigating the presence of flaws or contamination
    • G01N21/95—Investigating the presence of flaws or contamination characterised by the material or shape of the object to be examined
    • G01N21/956—Inspecting patterns on the surface of objects

Definitions

  • the present invention relates to an appearance inspection apparatus, and more particularly to an appearance inspection apparatus including an inspection unit that determines whether or not an element chip to be inspected is a non-defective product by comparing it with a non-defective image.
  • an appearance inspection apparatus including an inspection unit that determines whether or not an element chip to be inspected is a non-defective product by comparing with a non-defective image (for example, see Patent Document 1).
  • Patent Document 1 discloses an appearance inspection method for obtaining a difference between a standard image (non-defective product image) and an inspection image and inspecting a workpiece for defects based on the difference between the standard image and the inspection image.
  • this inspection method first, a large number of non-defective workpieces are imaged in the teaching process, and an average value (standard image) of gray values for each pixel of the image is obtained. Then, in the inspection process, the workpiece is imaged, and the presence / absence of a defect (whether or not it is a non-defective product) is determined based on a comparison between the image of the inspected workpiece inspection image and the standard image of the non-defective workpiece. Is done. Note that only a standard image of one type of non-defective workpiece is used as the standard image of the non-defective workpiece.
  • imaging of a plurality of workpieces is sequentially performed in a state where a standard image of one non-defective workpiece among a plurality of types is prepared (a state in which the workpiece is called into a memory or the like). For example, imaging is performed by causing the imaging unit to scan a plurality of workpieces. Then, the picked-up inspection images of the plurality of workpieces are sequentially compared with the standard images of the non-defective workpieces to determine whether or not each workpiece is a non-defective product.
  • a standard image of a non-defective workpiece of a type (pattern) different from the type (pattern) that has been inspected is prepared, and a plurality of workpieces are imaged to determine whether each workpiece is non-defective.
  • the present invention has been made to solve the above-described problems, and one object of the present invention is to reduce the time required for inspection in a state where a plurality of element chips having different patterns are mixed. It is an object to provide an appearance inspection apparatus capable of performing the above.
  • an appearance inspection apparatus is an appearance inspection apparatus that inspects each of a plurality of element chips in a state where a plurality of element chips having different patterns are mixed.
  • An image pickup unit that picks up the element chip, a storage unit that stores in advance a non-defective image serving as an inspection reference for element chips having different patterns, and a type of pattern of the element chip to be inspected that is picked up by the image pickup unit.
  • an inspection unit for performing discrimination.
  • the type of the pattern of the element chip to be inspected imaged by the imaging unit is identified, and the image of the element chip to be inspected imaged by the imaging unit And a non-defective image corresponding to the identified pattern of the element chip to be inspected, and an inspection unit that determines whether the element chip to be inspected is non-defective.
  • the type of pattern of the element chip to be inspected imaged by the inspection unit is identified, so that the pattern of the element chip to be inspected imaged from the storage unit corresponds to each element chip of the imaged inspection object A good product image can be read out.
  • the plurality of element chips are preferably provided on the substrate, and the element chip provided at any position on the substrate has any pattern in the storage unit.
  • the chip arrangement information is stored in advance, and the inspection unit is configured to identify the type of pattern of the element chip for inspection imaged by the imaging unit based on the chip arrangement information stored in the storage unit Has been. If comprised in this way, since the chip
  • a plurality of element chip groups each including a plurality of element chips each having a different pattern are provided on the substrate, and a plurality of element chips each having a different pattern formed therein.
  • the arrangement positions of the element chips are the same in each of the element chip groups, and chip storage information of a plurality of element chips including the plurality of element chip groups is stored in advance in the storage unit. If comprised in this way, since the arrangement position of several element chip is the same in each element chip group, an element chip can be formed for every element chip group using the same mask.
  • the imaging of the element chip for inspection by the imaging unit and the inspection are performed while the substrate and the imaging unit are relatively moved. Identifying the type of pattern of the imaged element chip for inspection by the unit, switching the non-defective image to a non-defective image having a pattern corresponding to the pattern of the identified element chip for inspection, and an element for inspection. The determination of whether the element chip is non-defective by comparing the chip image with the non-defective image is sequentially performed for each of the plurality of inspection element chips provided on the substrate. ing. If comprised in this way, in the state where the several element chip which has a mutually different pattern was mixed, the test
  • FIG. 1 is an overall view of an appearance inspection apparatus according to an embodiment of the present invention. It is a figure for demonstrating operation
  • the appearance inspection apparatus 100 is configured to inspect each of the plurality of element chips 210 in a state where a plurality of element chips 210 (see FIG. 4) having different patterns are mixed.
  • the appearance inspection apparatus 100 includes a moving stage 10.
  • the moving stage 10 includes an X-axis slider 11 and a Y-axis slider 12.
  • the X-axis slider 11 is disposed on the base 20.
  • the Y-axis slider 12 is disposed on the X-axis slider 11.
  • the appearance inspection apparatus 100 includes a mounting table 30.
  • the mounting table 30 is disposed on the Y-axis slider 12.
  • the mounting table 30 is configured to be moved in the X direction and the Y direction by the moving stage 10.
  • the mounting table 30 is configured to mount the wafer 220 (the element chip 210 to be inspected, see FIG. 4).
  • the wafer 220 is an example of the “substrate” in the claims.
  • the appearance inspection apparatus 100 includes an imaging unit 40.
  • the imaging unit 40 captures the non-defective element chip 210 in order to create the element chip 210 to be inspected and the non-defective image P serving as the inspection reference (image of the non-defective element chip 210, see FIG. 3). It is configured.
  • the imaging unit 40 includes a lens barrel 41, a half mirror 42, an objective lens 43, and an imaging camera 44.
  • the imaging camera 44 includes a light receiving element 44a. The imaging camera 44 is configured to output the captured image of the element chip 210 to the control unit 60 described later.
  • the imaging unit 40 is configured to sequentially capture a plurality of element chips 210 that move relative to the imaging unit 40. Specifically, the element chip 210 is moved relative to the imaging unit 40 in the X direction or the Y direction by the moving stage 10.
  • the appearance inspection apparatus 100 includes a storage unit 50.
  • the storage unit 50 stores in advance a non-defective image P that serves as an inspection reference for the element chips 210 having different patterns (patterns A to D).
  • “in advance” means before the element chip 210 to be inspected is inspected.
  • a plurality of non-defective images P are stored.
  • the non-defective image P includes a non-defective image P1 corresponding to the pattern A (see FIG. 3A), a non-defective image P2 corresponding to the pattern B (see FIG. 3B), and a pattern C.
  • a non-defective image P4 (see FIG. 3D) corresponding to the pattern D.
  • the non-defective images P1 to P4 are individually stored in the storage unit 50.
  • the non-defective images P1 to P4 are images of non-defective element chips 210a to 210d (see FIG. 4) configured so that the wiring patterns provided in the effective area 211 are different from each other. For example, the arrangement positions and sizes of the wiring patterns are different from each other.
  • the peripheral regions 212 surrounding the effective regions 211 of the element chips 210a to 210d have the same pattern, while the patterns of the peripheral regions 212 of the element chips 210a to 210d may be different from each other.
  • the plurality of element chips 210 are provided on the wafer 220.
  • the wafer 220 has a substantially circular shape in plan view.
  • the plurality of element chips 210 are provided in a matrix on the wafer 220.
  • the storage unit 50 stores in advance chip arrangement information indicating which pattern A to D the element chip 210 provided at which position on the wafer 220 has. It is remembered. Specifically, which of the non-defective images P1 to P4 corresponds to the non-defective image P among the plurality of element chips 210 provided in a matrix on the wafer 220 (the same pattern A as any non-defective image P).
  • Chip arrangement information on whether or not to have D) is stored in the storage unit 50 in advance.
  • the chip arrangement information is input by, for example, the user before the inspection of the element chip 210 for inspection.
  • the patterns A to D are described for some of the element chips 210, but actually, the patterns A to D of all the element chips 210 are stored in the storage unit 50 in advance.
  • an element chip group 230 (see FIG. 6) including a plurality of element chips 210 (inspection element chips 210) each having a different pattern formed on the wafer 220. A plurality of areas surrounded by a square of 6 thick lines) are provided.
  • one element chip group 230 includes four element chips 210a to 210d each formed with a different pattern.
  • the arrangement positions of the plurality of element chips 210a to 210d on which different patterns are formed are the same in each element chip group 230.
  • four element chips 210a to 210d are arranged in a state of 2 rows and 2 columns.
  • the element chip 210a is disposed on the upper left, and the element chip 210b is disposed on the upper right.
  • an element chip 210c is arranged at the lower left, and an element chip 210d is arranged at the lower right. This arrangement position is the same in any element chip group 230.
  • the four element chips 210a to 210d cannot be arranged because the wafer 220 is substantially circular. Therefore, on the outer edge side of the wafer 220, one element chip group 230 is in a state where any one (or a plurality) of the four element chips 210a to 210d is missing.
  • the reason why the arrangement positions of the element chips 210a to 210d are the same in each of the element chip groups 230 is that when the element chips 210a to 210d are formed on the wafer 220, the same mask (not shown) is used. This is because the element chips 210a to 210d are formed.
  • the storage unit 50 stores in advance chip arrangement information of a plurality of element chips 210 including a plurality of element chip groups 230. That is, chip arrangement information as shown in FIG. 6 is stored in the storage unit 50 in advance.
  • the appearance inspection apparatus 100 includes an inspection unit 61.
  • the inspection unit 61 is included in the control unit 60 configured by, for example, a CPU.
  • the control unit 60 is configured to control the overall operation of the appearance inspection apparatus 100.
  • the inspection unit 61 identifies the types of the patterns A to D of the element chip 210 to be inspected that is imaged by the imaging unit 40.
  • the inspection unit 61 compares the image of the element chip 210 to be inspected imaged by the imaging unit 40 with the non-defective image P corresponding to the identified patterns A to D of the element chip 210 to be inspected.
  • it is determined whether or not the element chip 210 to be inspected is a non-defective product.
  • the inspection unit 61 determines the types of patterns A to D of the inspection element chip 210 imaged by the imaging unit 40 based on the chip arrangement information (see FIG. 6) stored in the storage unit 50. Configured to identify.
  • condition setting operation (flow) will be described with reference to FIG.
  • the registration described below is performed, for example, when a screen for receiving information is displayed on a display unit (not shown) or the like and information is input by the user.
  • the registered (input) information is registered (stored) in the storage unit 50.
  • step S1 map information is registered. Specifically, the size of the wafer 220, the size of the element chip 210, and the like are registered.
  • step S2 the pattern of the element chip 210 is registered. Specifically, as shown in FIG. 6, chip arrangement information indicating which pattern the element chip 210 provided at which position on the wafer 220 has is registered.
  • step S3 global alignment information of the element chip 210 is registered. For example, information such as the angle and center position of the element chip 210 is registered.
  • step S4 inspection conditions are registered. Specifically, the optical conditions when imaging the element chip 210 by the imaging unit 40, the inspection area on the element chip 210, and the like are registered.
  • the inspection area is, for example, an area surrounded by a dotted line on the element chip 210 in FIG. As a result, the condition setting operation ends.
  • the non-defective product image P is created by the control unit 60.
  • the created non-defective image P is registered in the storage unit 50.
  • the creation (training) of the non-defective product image P is performed in advance before the inspection of the inspection element chip 210 described later.
  • the inspection condition is read from the storage unit 50 in step S11.
  • the inspection conditions are those registered in step S4.
  • step S12 the wafer 220 is transferred. Specifically, the wafer 220 is placed on the moving stage 10 (mounting table 30). In addition, a plurality of element chips 210 having different patterns are arranged on the wafer 220 in a mixed state. Note that all of the plurality of element chips 210 arranged on the wafer 220 may be non-defective element chips 210, or one of the plurality of element chips 210 may include a defective element chip 210. Good. Note that information on which of the plurality of element chips 210 is a non-defective element chip 210 and which of the plurality of element chips 210 is a defective element chip 210 is provided by the user (control unit 60). Assume that you are aware in advance.
  • step S13 global alignment of the wafer 220 (element chip 210) is performed. For example, the angle and center position of the element chip 210 are determined. The global alignment information is registered in step S3.
  • the imaging unit 40 relatively moves above the target element chip 210. Specifically, when the wafer 220 is moved to the moving stage 10, the target element chip 210 is disposed immediately below the imaging unit 40. Which of the plurality of element chips 210 is the target element chip 210 is registered in the storage unit 50 in advance. For example, if all of the plurality of element chips 210 on the wafer 220 are non-defective, all the element chips 210 may be targeted. Further, if a defective product is included in the plurality of device chips 210 on the wafer 220, only the good device chip 210 may be set as the target device chip 210. Alternatively, not all non-defective element chips 210 may be targeted, but some non-defective element chips 210 may be targeted.
  • step S15 the target element chip 210 is imaged.
  • the element chip 210 is imaged for each element chip 210.
  • step S16 the pattern type of the non-defective element chip 210 imaged by the imaging unit 40 is recognized. That is, it is recognized which of the patterns A to D corresponds to the imaged non-defective element chip 210. It should be noted that whether the pattern of the plurality of element chips 210 arranged on the wafer 220 corresponds to one of the patterns A to D is stored in advance corresponding to the position (coordinates) of the element chip 210 on the wafer 220. Stored in the unit 50. Based on the positional information (coordinates) of the imaging unit 40 with respect to the wafer 220, it is recognized which of the patterns A to D corresponds to the pattern of the element chip 210 photographed this time.
  • step S17 the imaged element chip 210 is aligned. For example, based on alignment marks provided in advance in the element chip 210, the effective area 211 (area where the element is formed, see FIG. 4) and the peripheral area 212 (area where the element surrounding the effective area 211 is not formed) are formed. ) Are aligned.
  • step S18 the captured image of the non-defective element chip 210 (non-defective product image P) is sorted into patterns A to D and stored in the storage unit 50.
  • step S19 it is determined whether or not imaging of all target non-defective element chips 210 has been completed. If it is determined that imaging of all target non-defective element chips 210 has not been completed, the process returns to step S14. If it is determined that the imaging of all target non-defective element chips 210 has been completed, the process proceeds to step S20.
  • steps S14 to S19 are continuously performed in a state where the wafer 220 and the imaging unit 40 are relatively moved.
  • the wafer 220 and the imaging unit 40 are relatively moved so that the plurality of element chips 210 provided on the wafer 220 are imaged in a single stroke.
  • the wafer 220 is moved relative to the imaging unit 40 in the Y1 direction, and imaging (and identification, registration, alignment, registration) of the plurality of element chips 210 arranged along the Y direction is performed. Done.
  • the wafer 220 is moved relative to the imaging unit 40 by the size of one element chip 210 in the X1 direction. . Thereafter, the wafer 220 is moved relative to the imaging unit 40 in the Y2 direction, and imaging of the plurality of element chips 210 arranged along the Y direction is performed. Then, after the imaging of the element chip 210 arranged at the end on the Y2 direction side is completed, the wafer 220 is moved relative to the imaging unit 40 by the size of one element chip 210 in the X1 direction. . Thereafter, the above operation is repeated.
  • a non-defective image P (training data) is generated. Specifically, a plurality of non-defective element chips 210 are stored (stored) for each of patterns A to D. Then, the luminance values of the image of the non-defective element chip 210 are added for each pixel and then averaged. This addition and averaging are performed individually for each of the patterns A to D. As a result, a non-defective image P (non-defective image P1 to P4) is generated for each of the patterns A to D.
  • step S21 the wafer 220 is stored at a predetermined position, and the operation for generating the non-defective image P is completed.
  • step S31 the inspection conditions are read from the storage unit 50.
  • the inspection conditions are those registered in step S4.
  • step S32 the wafer 220 is transferred. Specifically, the wafer 220 is placed on the moving stage 10 (mounting table 30). In addition, a plurality of element chips 210 having different patterns are arranged on the wafer 220 in a mixed state. The plurality of element chips 210 arranged on the wafer 220 may be scribed or not scribed.
  • step S33 global alignment of the element chip 210 of the wafer 220 (element chip 210) is performed. For example, the angle and center position of the element chip 210 are determined. The global alignment information is registered in step S3.
  • step S34 the imaging unit 40 relatively moves above the element chip 210 as a target (inspection target). Specifically, when the wafer 220 is moved to the moving stage 10, the target element chip 210 is disposed immediately below the imaging unit 40.
  • step S35 the target (inspection target) element chip 210 is imaged.
  • the element chip 210 is imaged for each element chip 210.
  • a plurality of element chips 210 are continuously imaged for each element chip 210 while the wafer 220 and the imaging unit 40 are relatively moving.
  • step S36 the type (pattern A to D) of the pattern of the element chip 210 to be inspected imaged by the imaging unit 40 is identified.
  • the storage unit 50 stores in advance chip arrangement information indicating which pattern the element chip 210 provided at which position on the wafer 220 has. For example, which pattern the element chip 210 provided at which position on the wafer 220 has is stored in correspondence with the position (coordinates) of the element chip 210 on the wafer 220.
  • the inspection unit 61 identifies the type of pattern of the inspection element chip 210 imaged by the imaging unit 40 based on the chip arrangement information stored in the storage unit 50. For example, based on the positional information (coordinates) of the imaging unit 40 with respect to the wafer 220, it is recognized which of the patterns A to D corresponds to the pattern of the element chip 210 photographed this time.
  • step S37 the imaged element chip 210 is aligned. For example, based on alignment marks provided in advance in the element chip 210, the effective area 211 (area where the element is formed, see FIG. 4) and the peripheral area 212 (area where the element surrounding the effective area 211 is not formed) are formed. ) Are aligned.
  • a non-defective image P having a pattern corresponding to the pattern of the imaged element chip 210 to be inspected is read from the storage unit 50.
  • the pattern of the imaged element chip 210 to be inspected is the pattern A
  • the non-defective image P1 having the pattern A is read from the storage unit 50. That is, the non-defective image P is switched in correspondence with the pattern of the element chip 210 to be inspected, which is imaged by the imaging unit 40.
  • step S39 the image of the element chip 210 to be inspected imaged by the imaging unit 40 is compared with the non-defective image P corresponding to the identified pattern of the element chip 210 to be inspected.
  • the image of the element chip 210 to be inspected having the imaged pattern A and the good product image P1 having the pattern A are compared.
  • the luminance values for each pixel of both images are compared.
  • the image of the element chip 210 to be inspected is different from the image of the non-defective image P1.
  • a defect or the like may occur in a portion where the difference in luminance value of the element chip 210 to be inspected is relatively large.
  • the difference in luminance value from the non-defective image P ⁇ b> 1 increases in the pixel corresponding to the defect 213. Therefore, when the difference between the compared luminance values is relatively large, it is determined that the element chip 210 to be inspected is not a good product (a defective product).
  • the image of the inspection element chip 210 for which the determination of whether or not the inspection element 61 is a non-defective product is erased every time the determination of whether or not the inspection element chip 210 is a non-defective product is completed. As a result, it is possible to suppress an increase in the data capacity of the element chip 210 stored in the memory (not shown).
  • step S40 it is determined whether or not all the element chips 210 to be inspected have been inspected. If it is determined that the inspection of all the element chips 210 to be inspected has not been completed, the process returns to step S34.
  • the operations in steps S34 to S40 are continuously performed in a state where the wafer 220 and the imaging unit 40 are relatively moved. For example, as shown in a path B in FIG. 6, the wafer 220 and the imaging unit 40 are relatively moved so that the plurality of element chips 210 provided on the wafer 220 are imaged in a single stroke.
  • the wafer 220 and the imaging unit 40 can be moved relative to each other without wasteful movement that goes back along the path, so that the time required for imaging all the element chips 210 can be shortened.
  • the relative movement between the wafer 220 and the imaging unit 40 is the same as that at the time of creating the non-defective image.
  • step S40 If it is determined in step S40 that the inspection of all the element chips 210 to be inspected has been completed, the process proceeds to step S41.
  • step S41 the wafer 220 is stored at a predetermined position, and the operation of inspecting the element chip 210 to be inspected is completed.
  • the types of patterns A to D of the element chip 210 to be inspected imaged by the imaging unit 40 are identified, and the image of the element chip 210 to be inspected imaged by the imaging unit 40 is identified.
  • the non-defective product image P corresponding to the pattern (A to D) of the identified element chip 210 to be inspected the inspection unit 61 that determines whether or not the element chip 210 to be inspected is non-defective Prepare.
  • the type of pattern of the element chip 210 to be inspected imaged by the inspection unit 61 is identified, so that the element chip to be inspected imaged from the storage unit 50 for each imaged element chip 210 to be inspected.
  • a non-defective product image P corresponding to the pattern 210 can be read out.
  • the element chips are obtained by one scan without repeating the imaging of the plurality of element chips 210 by the imaging unit 40 (scanning by the imaging unit 40). It is possible to determine whether 210 is a non-defective product. Thereby, the time required for the inspection can be shortened in a state where a plurality of element chips 210 having different patterns are mixed.
  • the plurality of element chips 210 are provided on the wafer 220, and the element chip 210 provided at any position on the wafer 220 is stored in the storage unit 50.
  • the chip arrangement information indicating whether or not the pattern has the above-described pattern is stored in advance, and the inspection unit 61 is based on the chip arrangement information stored in the storage unit 50 and the pattern of the element chip 210 for inspection imaged by the imaging unit 40 Is configured to identify the type.
  • a plurality of element chip groups 230 each including a plurality of element chips 210 each having a different pattern formed thereon are provided on the wafer 220.
  • the element chip group 230 as shown in FIG.
  • the arrangement positions of the plurality of element chips 210 each having a different pattern are the same in each of the element chip groups 230, and the storage unit 50 includes a plurality of element chips 210 including the plurality of element chip groups 230.
  • Chip arrangement information is stored in advance. Thereby, since the arrangement positions of the plurality of element chips 210 are the same in each of the element chip groups 230, the element chip 210 is formed for each element chip group 230 using the same mask (not shown). Can do.
  • the imaging of the element chip 210 for inspection by the imaging unit 40 and the imaging by the inspection unit 61 are performed. Identifying the pattern type of the identified inspection element chip 210, switching the non-defective image P to the non-defective image P having a pattern corresponding to the identified pattern of the inspection element chip 210, and an inspection element
  • the comparison of the image of the chip 210 and the non-defective image P to determine whether the element chip 210 is non-defective is sequentially performed for each of the plurality of inspection element chips 210 provided on the wafer 220. It is configured to be Thereby, in a state where a plurality of element chips 210 having different patterns are mixed, the plurality of element chips 210 can be inspected continuously and smoothly.
  • the inspection unit 61 is included in the control unit 60 , but the present invention is not limited to this.
  • the inspection unit 61 may be provided separately from the control unit 60.
  • the example in which the element chips 210 having four different patterns are mixed is shown, but the present invention is not limited to this.
  • the number of patterns of the element chip 210 may be a number other than four.
  • chip arrangement information indicating which pattern the element chip 210 provided at which position on the wafer 220 has is stored in the storage unit 50 in advance.
  • the invention is not limited to this. For example, each time the element chip 210 is imaged, the image of the imaged element chip 210 for inspection is compared with a plurality of non-defective images P. It may be identified which pattern of the non-defective product image P matches.
  • the arrangement positions of the plurality of element chips 210 formed with different patterns in the element chip group 230 are the same in each of the element chip groups 230 . It is not limited to this.
  • the arrangement positions of the plurality of element chips 210 each having a different pattern may be different for each element chip group 230.
  • the present invention is not limited to this.
  • an element chip 210 that is not provided on the wafer 220 may be inspected.
  • Image pickup unit 50 Storage unit 61 Inspection unit 100

Landscapes

  • Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Chemical & Material Sciences (AREA)
  • Analytical Chemistry (AREA)
  • Biochemistry (AREA)
  • General Health & Medical Sciences (AREA)
  • General Physics & Mathematics (AREA)
  • Immunology (AREA)
  • Pathology (AREA)
  • Investigating Materials By The Use Of Optical Means Adapted For Particular Applications (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

L'invention concerne un dispositif de vérification d'aspect externe qui peut raccourcir le temps nécessaire à la vérification quand une pluralité de puces à éléments ayant des motifs mutuellement différents sont mélangées. Plus spécifiquement, le dispositif de vérification d'aspect externe 100 comprend : une unité de capture d'images 40 qui capture des images de puces à éléments cibles soumises à vérification 210 ; une unité de stockage 50 dans laquelle sont pré-stockées des images de bons produits P servant de référence de vérification pour les puces à éléments 210 ayant des motifs A-D mutuellement différents ; et une unité de vérification qui identifie le type des motifs A-D des puces à éléments cibles soumises à vérification capturées par l'unité de capture d'images, et qui détermine si les puces à éléments cibles soumises à vérification sont de bons produits ou non par comparaison : des images des puces à éléments cibles soumises à vérification 210 capturées par l'unité de capture d'images 40 ; et des images de bons produits P qui correspondent aux motifs identifiés des puces à éléments cibles soumises à vérification 210.
PCT/JP2017/041061 2017-02-10 2017-11-15 Dispositif de vérification d'aspect externe WO2018146887A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2017022822A JP2018128406A (ja) 2017-02-10 2017-02-10 外観検査装置
JP2017-022822 2017-02-10

Publications (1)

Publication Number Publication Date
WO2018146887A1 true WO2018146887A1 (fr) 2018-08-16

Family

ID=63108329

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2017/041061 WO2018146887A1 (fr) 2017-02-10 2017-11-15 Dispositif de vérification d'aspect externe

Country Status (3)

Country Link
JP (1) JP2018128406A (fr)
TW (1) TWI755460B (fr)
WO (1) WO2018146887A1 (fr)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6128809A (ja) * 1984-07-20 1986-02-08 Hitachi Ltd 外観検査装置
JPH05187842A (ja) * 1992-01-09 1993-07-27 Dainippon Screen Mfg Co Ltd 画像パターンの検査方法及びその装置
JP2008244197A (ja) * 2007-03-28 2008-10-09 Hitachi High-Technologies Corp 検査装置及び検査方法
JP2010091361A (ja) * 2008-10-07 2010-04-22 Yamatake Corp 画像検査方法および画像検査装置
JP2012204703A (ja) * 2011-03-28 2012-10-22 Shindengen Electric Mfg Co Ltd ウェーハ外観検査装置、ウェーハ外観検査方法、及び半導体装置
US20140168418A1 (en) * 2012-12-13 2014-06-19 Kla-Tencor Corporation Delta die intensity map measurement

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007149837A (ja) * 2005-11-25 2007-06-14 Tokyo Seimitsu Co Ltd 画像欠陥検査装置、画像欠陥検査システム及び画像欠陥検査方法
US8780358B2 (en) * 2011-06-07 2014-07-15 Sick, Inc. Inspection apparatus, system, and method

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6128809A (ja) * 1984-07-20 1986-02-08 Hitachi Ltd 外観検査装置
JPH05187842A (ja) * 1992-01-09 1993-07-27 Dainippon Screen Mfg Co Ltd 画像パターンの検査方法及びその装置
JP2008244197A (ja) * 2007-03-28 2008-10-09 Hitachi High-Technologies Corp 検査装置及び検査方法
JP2010091361A (ja) * 2008-10-07 2010-04-22 Yamatake Corp 画像検査方法および画像検査装置
JP2012204703A (ja) * 2011-03-28 2012-10-22 Shindengen Electric Mfg Co Ltd ウェーハ外観検査装置、ウェーハ外観検査方法、及び半導体装置
US20140168418A1 (en) * 2012-12-13 2014-06-19 Kla-Tencor Corporation Delta die intensity map measurement

Also Published As

Publication number Publication date
TW201834102A (zh) 2018-09-16
JP2018128406A (ja) 2018-08-16
TWI755460B (zh) 2022-02-21

Similar Documents

Publication Publication Date Title
US7505149B2 (en) Apparatus for surface inspection and method and apparatus for inspecting substrate
KR100738693B1 (ko) 프로브 마크 판독 장치 및 프로브 마크 판독 방법
KR100805486B1 (ko) 디스플레이의 다각도 계측 시스템 및 방법
JP2004226128A (ja) 外観検査装置および外観検査方法
JP2007172397A (ja) エッジ勾配検出方法、シミ欠陥検出方法、エッジ勾配検出装置、シミ欠陥検出装置
JP2013140042A (ja) 画像処理装置及び画像処理方法
WO2013183471A1 (fr) Dispositif d'inspection d'apparence et procédé d'inspection d'apparence
JPWO2007132925A1 (ja) 表面検査装置
JP2000346627A (ja) 検査装置
WO2021033396A1 (fr) Dispositif et procédé d'inspection d'apparence de tranche
JP2008068284A (ja) 欠陥修正装置、欠陥修正方法、及びパターン基板の製造方法
KR20120105149A (ko) 평판패널 기판의 자동광학검사 방법 및 그 장치
JP2006258713A (ja) シミ欠陥検出方法及び装置
JP2006251561A (ja) 欠陥画素リペア方法
JP6140255B2 (ja) 画像処理装置及び画像処理方法
JP5832167B2 (ja) 部品有無判定装置及び部品有無判定方法
JP2000283929A (ja) 配線パターン検査方法及びその装置
WO2019176614A1 (fr) Dispositif de traitement d'image, procédé de traitement d'image et programme informatique
WO2018146887A1 (fr) Dispositif de vérification d'aspect externe
CN109804730B (zh) 基板检查装置及利用其的基板歪曲补偿方法
JP5615252B2 (ja) 外観検査装置
JPH1031730A (ja) キャリブレーション方法
JP3311628B2 (ja) 薄型表示機器の欠陥箇所位置決め装置
JP2006145228A (ja) ムラ欠陥検出方法及び装置
JP2006284543A (ja) 実装回路基板検査方法および実装回路基板検査装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17896208

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 17896208

Country of ref document: EP

Kind code of ref document: A1