WO2018146887A1 - External-appearance examination device - Google Patents

External-appearance examination device Download PDF

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Publication number
WO2018146887A1
WO2018146887A1 PCT/JP2017/041061 JP2017041061W WO2018146887A1 WO 2018146887 A1 WO2018146887 A1 WO 2018146887A1 JP 2017041061 W JP2017041061 W JP 2017041061W WO 2018146887 A1 WO2018146887 A1 WO 2018146887A1
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WO
WIPO (PCT)
Prior art keywords
element chip
inspection
chip
pattern
defective
Prior art date
Application number
PCT/JP2017/041061
Other languages
French (fr)
Japanese (ja)
Inventor
英一 大▲美▼
翔太 稲生
Original Assignee
東レエンジニアリング株式会社
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Publication date
Application filed by 東レエンジニアリング株式会社 filed Critical 東レエンジニアリング株式会社
Publication of WO2018146887A1 publication Critical patent/WO2018146887A1/en

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
    • G01N21/84—Systems specially adapted for particular applications
    • G01N21/88—Investigating the presence of flaws or contamination
    • G01N21/95—Investigating the presence of flaws or contamination characterised by the material or shape of the object to be examined
    • G01N21/956—Inspecting patterns on the surface of objects

Definitions

  • the present invention relates to an appearance inspection apparatus, and more particularly to an appearance inspection apparatus including an inspection unit that determines whether or not an element chip to be inspected is a non-defective product by comparing it with a non-defective image.
  • an appearance inspection apparatus including an inspection unit that determines whether or not an element chip to be inspected is a non-defective product by comparing with a non-defective image (for example, see Patent Document 1).
  • Patent Document 1 discloses an appearance inspection method for obtaining a difference between a standard image (non-defective product image) and an inspection image and inspecting a workpiece for defects based on the difference between the standard image and the inspection image.
  • this inspection method first, a large number of non-defective workpieces are imaged in the teaching process, and an average value (standard image) of gray values for each pixel of the image is obtained. Then, in the inspection process, the workpiece is imaged, and the presence / absence of a defect (whether or not it is a non-defective product) is determined based on a comparison between the image of the inspected workpiece inspection image and the standard image of the non-defective workpiece. Is done. Note that only a standard image of one type of non-defective workpiece is used as the standard image of the non-defective workpiece.
  • imaging of a plurality of workpieces is sequentially performed in a state where a standard image of one non-defective workpiece among a plurality of types is prepared (a state in which the workpiece is called into a memory or the like). For example, imaging is performed by causing the imaging unit to scan a plurality of workpieces. Then, the picked-up inspection images of the plurality of workpieces are sequentially compared with the standard images of the non-defective workpieces to determine whether or not each workpiece is a non-defective product.
  • a standard image of a non-defective workpiece of a type (pattern) different from the type (pattern) that has been inspected is prepared, and a plurality of workpieces are imaged to determine whether each workpiece is non-defective.
  • the present invention has been made to solve the above-described problems, and one object of the present invention is to reduce the time required for inspection in a state where a plurality of element chips having different patterns are mixed. It is an object to provide an appearance inspection apparatus capable of performing the above.
  • an appearance inspection apparatus is an appearance inspection apparatus that inspects each of a plurality of element chips in a state where a plurality of element chips having different patterns are mixed.
  • An image pickup unit that picks up the element chip, a storage unit that stores in advance a non-defective image serving as an inspection reference for element chips having different patterns, and a type of pattern of the element chip to be inspected that is picked up by the image pickup unit.
  • an inspection unit for performing discrimination.
  • the type of the pattern of the element chip to be inspected imaged by the imaging unit is identified, and the image of the element chip to be inspected imaged by the imaging unit And a non-defective image corresponding to the identified pattern of the element chip to be inspected, and an inspection unit that determines whether the element chip to be inspected is non-defective.
  • the type of pattern of the element chip to be inspected imaged by the inspection unit is identified, so that the pattern of the element chip to be inspected imaged from the storage unit corresponds to each element chip of the imaged inspection object A good product image can be read out.
  • the plurality of element chips are preferably provided on the substrate, and the element chip provided at any position on the substrate has any pattern in the storage unit.
  • the chip arrangement information is stored in advance, and the inspection unit is configured to identify the type of pattern of the element chip for inspection imaged by the imaging unit based on the chip arrangement information stored in the storage unit Has been. If comprised in this way, since the chip
  • a plurality of element chip groups each including a plurality of element chips each having a different pattern are provided on the substrate, and a plurality of element chips each having a different pattern formed therein.
  • the arrangement positions of the element chips are the same in each of the element chip groups, and chip storage information of a plurality of element chips including the plurality of element chip groups is stored in advance in the storage unit. If comprised in this way, since the arrangement position of several element chip is the same in each element chip group, an element chip can be formed for every element chip group using the same mask.
  • the imaging of the element chip for inspection by the imaging unit and the inspection are performed while the substrate and the imaging unit are relatively moved. Identifying the type of pattern of the imaged element chip for inspection by the unit, switching the non-defective image to a non-defective image having a pattern corresponding to the pattern of the identified element chip for inspection, and an element for inspection. The determination of whether the element chip is non-defective by comparing the chip image with the non-defective image is sequentially performed for each of the plurality of inspection element chips provided on the substrate. ing. If comprised in this way, in the state where the several element chip which has a mutually different pattern was mixed, the test
  • FIG. 1 is an overall view of an appearance inspection apparatus according to an embodiment of the present invention. It is a figure for demonstrating operation
  • the appearance inspection apparatus 100 is configured to inspect each of the plurality of element chips 210 in a state where a plurality of element chips 210 (see FIG. 4) having different patterns are mixed.
  • the appearance inspection apparatus 100 includes a moving stage 10.
  • the moving stage 10 includes an X-axis slider 11 and a Y-axis slider 12.
  • the X-axis slider 11 is disposed on the base 20.
  • the Y-axis slider 12 is disposed on the X-axis slider 11.
  • the appearance inspection apparatus 100 includes a mounting table 30.
  • the mounting table 30 is disposed on the Y-axis slider 12.
  • the mounting table 30 is configured to be moved in the X direction and the Y direction by the moving stage 10.
  • the mounting table 30 is configured to mount the wafer 220 (the element chip 210 to be inspected, see FIG. 4).
  • the wafer 220 is an example of the “substrate” in the claims.
  • the appearance inspection apparatus 100 includes an imaging unit 40.
  • the imaging unit 40 captures the non-defective element chip 210 in order to create the element chip 210 to be inspected and the non-defective image P serving as the inspection reference (image of the non-defective element chip 210, see FIG. 3). It is configured.
  • the imaging unit 40 includes a lens barrel 41, a half mirror 42, an objective lens 43, and an imaging camera 44.
  • the imaging camera 44 includes a light receiving element 44a. The imaging camera 44 is configured to output the captured image of the element chip 210 to the control unit 60 described later.
  • the imaging unit 40 is configured to sequentially capture a plurality of element chips 210 that move relative to the imaging unit 40. Specifically, the element chip 210 is moved relative to the imaging unit 40 in the X direction or the Y direction by the moving stage 10.
  • the appearance inspection apparatus 100 includes a storage unit 50.
  • the storage unit 50 stores in advance a non-defective image P that serves as an inspection reference for the element chips 210 having different patterns (patterns A to D).
  • “in advance” means before the element chip 210 to be inspected is inspected.
  • a plurality of non-defective images P are stored.
  • the non-defective image P includes a non-defective image P1 corresponding to the pattern A (see FIG. 3A), a non-defective image P2 corresponding to the pattern B (see FIG. 3B), and a pattern C.
  • a non-defective image P4 (see FIG. 3D) corresponding to the pattern D.
  • the non-defective images P1 to P4 are individually stored in the storage unit 50.
  • the non-defective images P1 to P4 are images of non-defective element chips 210a to 210d (see FIG. 4) configured so that the wiring patterns provided in the effective area 211 are different from each other. For example, the arrangement positions and sizes of the wiring patterns are different from each other.
  • the peripheral regions 212 surrounding the effective regions 211 of the element chips 210a to 210d have the same pattern, while the patterns of the peripheral regions 212 of the element chips 210a to 210d may be different from each other.
  • the plurality of element chips 210 are provided on the wafer 220.
  • the wafer 220 has a substantially circular shape in plan view.
  • the plurality of element chips 210 are provided in a matrix on the wafer 220.
  • the storage unit 50 stores in advance chip arrangement information indicating which pattern A to D the element chip 210 provided at which position on the wafer 220 has. It is remembered. Specifically, which of the non-defective images P1 to P4 corresponds to the non-defective image P among the plurality of element chips 210 provided in a matrix on the wafer 220 (the same pattern A as any non-defective image P).
  • Chip arrangement information on whether or not to have D) is stored in the storage unit 50 in advance.
  • the chip arrangement information is input by, for example, the user before the inspection of the element chip 210 for inspection.
  • the patterns A to D are described for some of the element chips 210, but actually, the patterns A to D of all the element chips 210 are stored in the storage unit 50 in advance.
  • an element chip group 230 (see FIG. 6) including a plurality of element chips 210 (inspection element chips 210) each having a different pattern formed on the wafer 220. A plurality of areas surrounded by a square of 6 thick lines) are provided.
  • one element chip group 230 includes four element chips 210a to 210d each formed with a different pattern.
  • the arrangement positions of the plurality of element chips 210a to 210d on which different patterns are formed are the same in each element chip group 230.
  • four element chips 210a to 210d are arranged in a state of 2 rows and 2 columns.
  • the element chip 210a is disposed on the upper left, and the element chip 210b is disposed on the upper right.
  • an element chip 210c is arranged at the lower left, and an element chip 210d is arranged at the lower right. This arrangement position is the same in any element chip group 230.
  • the four element chips 210a to 210d cannot be arranged because the wafer 220 is substantially circular. Therefore, on the outer edge side of the wafer 220, one element chip group 230 is in a state where any one (or a plurality) of the four element chips 210a to 210d is missing.
  • the reason why the arrangement positions of the element chips 210a to 210d are the same in each of the element chip groups 230 is that when the element chips 210a to 210d are formed on the wafer 220, the same mask (not shown) is used. This is because the element chips 210a to 210d are formed.
  • the storage unit 50 stores in advance chip arrangement information of a plurality of element chips 210 including a plurality of element chip groups 230. That is, chip arrangement information as shown in FIG. 6 is stored in the storage unit 50 in advance.
  • the appearance inspection apparatus 100 includes an inspection unit 61.
  • the inspection unit 61 is included in the control unit 60 configured by, for example, a CPU.
  • the control unit 60 is configured to control the overall operation of the appearance inspection apparatus 100.
  • the inspection unit 61 identifies the types of the patterns A to D of the element chip 210 to be inspected that is imaged by the imaging unit 40.
  • the inspection unit 61 compares the image of the element chip 210 to be inspected imaged by the imaging unit 40 with the non-defective image P corresponding to the identified patterns A to D of the element chip 210 to be inspected.
  • it is determined whether or not the element chip 210 to be inspected is a non-defective product.
  • the inspection unit 61 determines the types of patterns A to D of the inspection element chip 210 imaged by the imaging unit 40 based on the chip arrangement information (see FIG. 6) stored in the storage unit 50. Configured to identify.
  • condition setting operation (flow) will be described with reference to FIG.
  • the registration described below is performed, for example, when a screen for receiving information is displayed on a display unit (not shown) or the like and information is input by the user.
  • the registered (input) information is registered (stored) in the storage unit 50.
  • step S1 map information is registered. Specifically, the size of the wafer 220, the size of the element chip 210, and the like are registered.
  • step S2 the pattern of the element chip 210 is registered. Specifically, as shown in FIG. 6, chip arrangement information indicating which pattern the element chip 210 provided at which position on the wafer 220 has is registered.
  • step S3 global alignment information of the element chip 210 is registered. For example, information such as the angle and center position of the element chip 210 is registered.
  • step S4 inspection conditions are registered. Specifically, the optical conditions when imaging the element chip 210 by the imaging unit 40, the inspection area on the element chip 210, and the like are registered.
  • the inspection area is, for example, an area surrounded by a dotted line on the element chip 210 in FIG. As a result, the condition setting operation ends.
  • the non-defective product image P is created by the control unit 60.
  • the created non-defective image P is registered in the storage unit 50.
  • the creation (training) of the non-defective product image P is performed in advance before the inspection of the inspection element chip 210 described later.
  • the inspection condition is read from the storage unit 50 in step S11.
  • the inspection conditions are those registered in step S4.
  • step S12 the wafer 220 is transferred. Specifically, the wafer 220 is placed on the moving stage 10 (mounting table 30). In addition, a plurality of element chips 210 having different patterns are arranged on the wafer 220 in a mixed state. Note that all of the plurality of element chips 210 arranged on the wafer 220 may be non-defective element chips 210, or one of the plurality of element chips 210 may include a defective element chip 210. Good. Note that information on which of the plurality of element chips 210 is a non-defective element chip 210 and which of the plurality of element chips 210 is a defective element chip 210 is provided by the user (control unit 60). Assume that you are aware in advance.
  • step S13 global alignment of the wafer 220 (element chip 210) is performed. For example, the angle and center position of the element chip 210 are determined. The global alignment information is registered in step S3.
  • the imaging unit 40 relatively moves above the target element chip 210. Specifically, when the wafer 220 is moved to the moving stage 10, the target element chip 210 is disposed immediately below the imaging unit 40. Which of the plurality of element chips 210 is the target element chip 210 is registered in the storage unit 50 in advance. For example, if all of the plurality of element chips 210 on the wafer 220 are non-defective, all the element chips 210 may be targeted. Further, if a defective product is included in the plurality of device chips 210 on the wafer 220, only the good device chip 210 may be set as the target device chip 210. Alternatively, not all non-defective element chips 210 may be targeted, but some non-defective element chips 210 may be targeted.
  • step S15 the target element chip 210 is imaged.
  • the element chip 210 is imaged for each element chip 210.
  • step S16 the pattern type of the non-defective element chip 210 imaged by the imaging unit 40 is recognized. That is, it is recognized which of the patterns A to D corresponds to the imaged non-defective element chip 210. It should be noted that whether the pattern of the plurality of element chips 210 arranged on the wafer 220 corresponds to one of the patterns A to D is stored in advance corresponding to the position (coordinates) of the element chip 210 on the wafer 220. Stored in the unit 50. Based on the positional information (coordinates) of the imaging unit 40 with respect to the wafer 220, it is recognized which of the patterns A to D corresponds to the pattern of the element chip 210 photographed this time.
  • step S17 the imaged element chip 210 is aligned. For example, based on alignment marks provided in advance in the element chip 210, the effective area 211 (area where the element is formed, see FIG. 4) and the peripheral area 212 (area where the element surrounding the effective area 211 is not formed) are formed. ) Are aligned.
  • step S18 the captured image of the non-defective element chip 210 (non-defective product image P) is sorted into patterns A to D and stored in the storage unit 50.
  • step S19 it is determined whether or not imaging of all target non-defective element chips 210 has been completed. If it is determined that imaging of all target non-defective element chips 210 has not been completed, the process returns to step S14. If it is determined that the imaging of all target non-defective element chips 210 has been completed, the process proceeds to step S20.
  • steps S14 to S19 are continuously performed in a state where the wafer 220 and the imaging unit 40 are relatively moved.
  • the wafer 220 and the imaging unit 40 are relatively moved so that the plurality of element chips 210 provided on the wafer 220 are imaged in a single stroke.
  • the wafer 220 is moved relative to the imaging unit 40 in the Y1 direction, and imaging (and identification, registration, alignment, registration) of the plurality of element chips 210 arranged along the Y direction is performed. Done.
  • the wafer 220 is moved relative to the imaging unit 40 by the size of one element chip 210 in the X1 direction. . Thereafter, the wafer 220 is moved relative to the imaging unit 40 in the Y2 direction, and imaging of the plurality of element chips 210 arranged along the Y direction is performed. Then, after the imaging of the element chip 210 arranged at the end on the Y2 direction side is completed, the wafer 220 is moved relative to the imaging unit 40 by the size of one element chip 210 in the X1 direction. . Thereafter, the above operation is repeated.
  • a non-defective image P (training data) is generated. Specifically, a plurality of non-defective element chips 210 are stored (stored) for each of patterns A to D. Then, the luminance values of the image of the non-defective element chip 210 are added for each pixel and then averaged. This addition and averaging are performed individually for each of the patterns A to D. As a result, a non-defective image P (non-defective image P1 to P4) is generated for each of the patterns A to D.
  • step S21 the wafer 220 is stored at a predetermined position, and the operation for generating the non-defective image P is completed.
  • step S31 the inspection conditions are read from the storage unit 50.
  • the inspection conditions are those registered in step S4.
  • step S32 the wafer 220 is transferred. Specifically, the wafer 220 is placed on the moving stage 10 (mounting table 30). In addition, a plurality of element chips 210 having different patterns are arranged on the wafer 220 in a mixed state. The plurality of element chips 210 arranged on the wafer 220 may be scribed or not scribed.
  • step S33 global alignment of the element chip 210 of the wafer 220 (element chip 210) is performed. For example, the angle and center position of the element chip 210 are determined. The global alignment information is registered in step S3.
  • step S34 the imaging unit 40 relatively moves above the element chip 210 as a target (inspection target). Specifically, when the wafer 220 is moved to the moving stage 10, the target element chip 210 is disposed immediately below the imaging unit 40.
  • step S35 the target (inspection target) element chip 210 is imaged.
  • the element chip 210 is imaged for each element chip 210.
  • a plurality of element chips 210 are continuously imaged for each element chip 210 while the wafer 220 and the imaging unit 40 are relatively moving.
  • step S36 the type (pattern A to D) of the pattern of the element chip 210 to be inspected imaged by the imaging unit 40 is identified.
  • the storage unit 50 stores in advance chip arrangement information indicating which pattern the element chip 210 provided at which position on the wafer 220 has. For example, which pattern the element chip 210 provided at which position on the wafer 220 has is stored in correspondence with the position (coordinates) of the element chip 210 on the wafer 220.
  • the inspection unit 61 identifies the type of pattern of the inspection element chip 210 imaged by the imaging unit 40 based on the chip arrangement information stored in the storage unit 50. For example, based on the positional information (coordinates) of the imaging unit 40 with respect to the wafer 220, it is recognized which of the patterns A to D corresponds to the pattern of the element chip 210 photographed this time.
  • step S37 the imaged element chip 210 is aligned. For example, based on alignment marks provided in advance in the element chip 210, the effective area 211 (area where the element is formed, see FIG. 4) and the peripheral area 212 (area where the element surrounding the effective area 211 is not formed) are formed. ) Are aligned.
  • a non-defective image P having a pattern corresponding to the pattern of the imaged element chip 210 to be inspected is read from the storage unit 50.
  • the pattern of the imaged element chip 210 to be inspected is the pattern A
  • the non-defective image P1 having the pattern A is read from the storage unit 50. That is, the non-defective image P is switched in correspondence with the pattern of the element chip 210 to be inspected, which is imaged by the imaging unit 40.
  • step S39 the image of the element chip 210 to be inspected imaged by the imaging unit 40 is compared with the non-defective image P corresponding to the identified pattern of the element chip 210 to be inspected.
  • the image of the element chip 210 to be inspected having the imaged pattern A and the good product image P1 having the pattern A are compared.
  • the luminance values for each pixel of both images are compared.
  • the image of the element chip 210 to be inspected is different from the image of the non-defective image P1.
  • a defect or the like may occur in a portion where the difference in luminance value of the element chip 210 to be inspected is relatively large.
  • the difference in luminance value from the non-defective image P ⁇ b> 1 increases in the pixel corresponding to the defect 213. Therefore, when the difference between the compared luminance values is relatively large, it is determined that the element chip 210 to be inspected is not a good product (a defective product).
  • the image of the inspection element chip 210 for which the determination of whether or not the inspection element 61 is a non-defective product is erased every time the determination of whether or not the inspection element chip 210 is a non-defective product is completed. As a result, it is possible to suppress an increase in the data capacity of the element chip 210 stored in the memory (not shown).
  • step S40 it is determined whether or not all the element chips 210 to be inspected have been inspected. If it is determined that the inspection of all the element chips 210 to be inspected has not been completed, the process returns to step S34.
  • the operations in steps S34 to S40 are continuously performed in a state where the wafer 220 and the imaging unit 40 are relatively moved. For example, as shown in a path B in FIG. 6, the wafer 220 and the imaging unit 40 are relatively moved so that the plurality of element chips 210 provided on the wafer 220 are imaged in a single stroke.
  • the wafer 220 and the imaging unit 40 can be moved relative to each other without wasteful movement that goes back along the path, so that the time required for imaging all the element chips 210 can be shortened.
  • the relative movement between the wafer 220 and the imaging unit 40 is the same as that at the time of creating the non-defective image.
  • step S40 If it is determined in step S40 that the inspection of all the element chips 210 to be inspected has been completed, the process proceeds to step S41.
  • step S41 the wafer 220 is stored at a predetermined position, and the operation of inspecting the element chip 210 to be inspected is completed.
  • the types of patterns A to D of the element chip 210 to be inspected imaged by the imaging unit 40 are identified, and the image of the element chip 210 to be inspected imaged by the imaging unit 40 is identified.
  • the non-defective product image P corresponding to the pattern (A to D) of the identified element chip 210 to be inspected the inspection unit 61 that determines whether or not the element chip 210 to be inspected is non-defective Prepare.
  • the type of pattern of the element chip 210 to be inspected imaged by the inspection unit 61 is identified, so that the element chip to be inspected imaged from the storage unit 50 for each imaged element chip 210 to be inspected.
  • a non-defective product image P corresponding to the pattern 210 can be read out.
  • the element chips are obtained by one scan without repeating the imaging of the plurality of element chips 210 by the imaging unit 40 (scanning by the imaging unit 40). It is possible to determine whether 210 is a non-defective product. Thereby, the time required for the inspection can be shortened in a state where a plurality of element chips 210 having different patterns are mixed.
  • the plurality of element chips 210 are provided on the wafer 220, and the element chip 210 provided at any position on the wafer 220 is stored in the storage unit 50.
  • the chip arrangement information indicating whether or not the pattern has the above-described pattern is stored in advance, and the inspection unit 61 is based on the chip arrangement information stored in the storage unit 50 and the pattern of the element chip 210 for inspection imaged by the imaging unit 40 Is configured to identify the type.
  • a plurality of element chip groups 230 each including a plurality of element chips 210 each having a different pattern formed thereon are provided on the wafer 220.
  • the element chip group 230 as shown in FIG.
  • the arrangement positions of the plurality of element chips 210 each having a different pattern are the same in each of the element chip groups 230, and the storage unit 50 includes a plurality of element chips 210 including the plurality of element chip groups 230.
  • Chip arrangement information is stored in advance. Thereby, since the arrangement positions of the plurality of element chips 210 are the same in each of the element chip groups 230, the element chip 210 is formed for each element chip group 230 using the same mask (not shown). Can do.
  • the imaging of the element chip 210 for inspection by the imaging unit 40 and the imaging by the inspection unit 61 are performed. Identifying the pattern type of the identified inspection element chip 210, switching the non-defective image P to the non-defective image P having a pattern corresponding to the identified pattern of the inspection element chip 210, and an inspection element
  • the comparison of the image of the chip 210 and the non-defective image P to determine whether the element chip 210 is non-defective is sequentially performed for each of the plurality of inspection element chips 210 provided on the wafer 220. It is configured to be Thereby, in a state where a plurality of element chips 210 having different patterns are mixed, the plurality of element chips 210 can be inspected continuously and smoothly.
  • the inspection unit 61 is included in the control unit 60 , but the present invention is not limited to this.
  • the inspection unit 61 may be provided separately from the control unit 60.
  • the example in which the element chips 210 having four different patterns are mixed is shown, but the present invention is not limited to this.
  • the number of patterns of the element chip 210 may be a number other than four.
  • chip arrangement information indicating which pattern the element chip 210 provided at which position on the wafer 220 has is stored in the storage unit 50 in advance.
  • the invention is not limited to this. For example, each time the element chip 210 is imaged, the image of the imaged element chip 210 for inspection is compared with a plurality of non-defective images P. It may be identified which pattern of the non-defective product image P matches.
  • the arrangement positions of the plurality of element chips 210 formed with different patterns in the element chip group 230 are the same in each of the element chip groups 230 . It is not limited to this.
  • the arrangement positions of the plurality of element chips 210 each having a different pattern may be different for each element chip group 230.
  • the present invention is not limited to this.
  • an element chip 210 that is not provided on the wafer 220 may be inspected.
  • Image pickup unit 50 Storage unit 61 Inspection unit 100

Abstract

Provided is an external-appearance examination device that can shorten the time required for examination in a state where a plurality of element chips having mutually different patterns are mixed together. Specifically, an external-appearance examination device 100 comprises: an image capture unit 40 that captures images of examination-target element chips 210; a storage unit 50 in which are pre-stored good-product images P serving as an examination reference for the element chips 210 having mutually different patterns A-D; and an examination unit 61 that identifies the type of the patterns A-D of the examination-target element chips 210 captured by the image capture unit 40, and that determines whether the examination-target element chips 210 are good products or not by comparing: the images of the examination-target element chips 210 captured by the image capture unit 40; and the good-product images P which correspond to the identified patterns of the examination-target element chips 210.

Description

外観検査装置Appearance inspection device
　この発明は、外観検査装置に関し、特に、良品画像と比較することにより、検査対象の素子チップが良品か否かの判別を行う検査部を備える外観検査装置に関する。 The present invention relates to an appearance inspection apparatus, and more particularly to an appearance inspection apparatus including an inspection unit that determines whether or not an element chip to be inspected is a non-defective product by comparing it with a non-defective image.
　従来、良品画像と比較することにより、検査対象の素子チップが良品か否かの判別を行う検査部を備える外観検査装置が知られている（たとえば、特許文献１参照）。 Conventionally, there has been known an appearance inspection apparatus including an inspection unit that determines whether or not an element chip to be inspected is a non-defective product by comparing with a non-defective image (for example, see Patent Document 1).
　上記特許文献１には、標準画像（良品画像）と検査画像との差を求め、標準画像と検査
画像との差に基づいてワークの欠陥を検査する外観検査方法が開示されている。この検査方法では、まず、教示過程において多数の良品のワークの撮像を行って、画像の画素毎の濃淡値の平均値（標準画像）が求められる。そして、検査過程において、ワークの撮像を行い、撮像された検査対象のワークの検査画像と、良品のワークの標準画像との比較に基づいて、欠陥の有無（良品であるか否か）が判定される。なお、良品のワークの標準画像として、１種類の良品のワークの標準画像のみが用いられている。 Patent Document 1 discloses an appearance inspection method for obtaining a difference between a standard image (non-defective product image) and an inspection image and inspecting a workpiece for defects based on the difference between the standard image and the inspection image. In this inspection method, first, a large number of non-defective workpieces are imaged in the teaching process, and an average value (standard image) of gray values for each pixel of the image is obtained. Then, in the inspection process, the workpiece is imaged, and the presence / absence of a defect (whether or not it is a non-defective product) is determined based on a comparison between the image of the inspected workpiece inspection image and the standard image of the non-defective workpiece. Is done. Note that only a standard image of one type of non-defective workpiece is used as the standard image of the non-defective workpiece.
特開平１０－１２３０６４号公報Japanese Patent Laid-Open No. 10-123064
　上記特許文献１に記載の欠陥検査方法では、良品のワークの標準画像として、１種類の良品のワークの標準画像のみが用いられているため、全てのワークに同一のパターンが設けられている場合には、１種類の良品のワークの標準画像に基づいて、ワークが良品であるか否かを判定することができる。一方、互いに異なるパターンを有する複数のワークが混在した状態では、互いに異なるパターンを有する複数種類の良品のワークの標準画像を準備する必要がある。この場合、まず、複数種類のうちの１つの良品のワークの標準画像を準備した状態（メモリなどに呼び出した状態）で、複数のワークの撮像を順次行う。たとえば、撮像部を複数のワークに対して走査させることにより撮像を行う。そして、撮像された複数のワークの検査画像が、順次、良品のワークの標準画像と比較されて、個々のワークが良品であるか否かが判定される。さらに、検査が終了した種類（パターン）とは異なる種類（パターン）の良品のワークの標準画像が準備されるとともに、複数のワークが撮像され、個々のワークが良品であるか否かが判定される。 In the defect inspection method described in Patent Document 1, since only a standard image of one type of non-defective workpiece is used as a standard image of a non-defective workpiece, all the workpieces have the same pattern. It is possible to determine whether or not the workpiece is a non-defective product based on a standard image of one type of non-defective workpiece. On the other hand, in a state where a plurality of works having different patterns are mixed, it is necessary to prepare standard images of a plurality of types of non-defective works having different patterns. In this case, first, imaging of a plurality of workpieces is sequentially performed in a state where a standard image of one non-defective workpiece among a plurality of types is prepared (a state in which the workpiece is called into a memory or the like). For example, imaging is performed by causing the imaging unit to scan a plurality of workpieces. Then, the picked-up inspection images of the plurality of workpieces are sequentially compared with the standard images of the non-defective workpieces to determine whether or not each workpiece is a non-defective product. Furthermore, a standard image of a non-defective workpiece of a type (pattern) different from the type (pattern) that has been inspected is prepared, and a plurality of workpieces are imaged to determine whether each workpiece is non-defective. The
　このように、上記特許文献１に記載のような従来の欠陥検査方法では、パターンの種類の数分、撮像部の走査が複数回行われる。このため、全てのワーク（素子チップ）の検査を行うために比較的長い時間を要するという問題点がある。 As described above, in the conventional defect inspection method as described in Patent Document 1, the imaging unit is scanned a plurality of times for the number of types of patterns. For this reason, there is a problem that it takes a relatively long time to inspect all the workpieces (element chips).
　この発明は、上記のような課題を解決するためになされたものであり、この発明の１つの目的は、互いに異なるパターンを有する複数の素子チップが混在した状態において、検査に要する時間を短縮することが可能な外観検査装置を提供することである。 The present invention has been made to solve the above-described problems, and one object of the present invention is to reduce the time required for inspection in a state where a plurality of element chips having different patterns are mixed. It is an object to provide an appearance inspection apparatus capable of performing the above.
　上記目的を達成するために、この発明の一の局面による外観検査装置は、互いに異なるパターンを有する複数の素子チップが混在した状態で、複数の素子チップを各々検査する外観検査装置において、検査対象の素子チップを撮像する撮像部と、互いに異なるパターンの素子チップの検査基準となる良品画像が予め記憶された記憶部と、撮像部によって撮像された検査対象の素子チップのパターンの種類を識別するとともに、撮像部によって撮像された検査対象の素子チップの画像と、識別された検査対象の素子チップのパターンに対応する良品画像とを比較することにより、検査対象の素子チップが良品か否かの判別を行う検査部とを備える。 In order to achieve the above object, an appearance inspection apparatus according to an aspect of the present invention is an appearance inspection apparatus that inspects each of a plurality of element chips in a state where a plurality of element chips having different patterns are mixed. An image pickup unit that picks up the element chip, a storage unit that stores in advance a non-defective image serving as an inspection reference for element chips having different patterns, and a type of pattern of the element chip to be inspected that is picked up by the image pickup unit In addition, by comparing the image of the element chip to be inspected imaged by the imaging unit with a non-defective image corresponding to the pattern of the identified element chip to be inspected, whether or not the element chip to be inspected is non-defective And an inspection unit for performing discrimination.
　この発明の一の局面による外観検査装置では、上記のように、撮像部によって撮像された検査対象の素子チップのパターンの種類を識別するとともに、撮像部によって撮像された検査対象の素子チップの画像と、識別された検査対象の素子チップのパターンに対応する良品画像とを比較することにより、検査対象の素子チップが良品か否かの判別を行う検査部を備える。これにより、検査部により撮像された検査対象の素子チップのパターンの種類が識別されるので、撮像された検査対象の素子チップ毎に、記憶部から撮像された検査対象の素子チップのパターンに対応する良品画像を読み出すことができる。その結果、互いに異なるパターンを有する複数の素子チップが混在した状態において、撮像部による複数の素子チップの撮像（撮像部による走査）を繰り返すことなく、１回の走査により、素子チップが良品か否かの判別を行うことができる。これにより、互いに異なるパターンを有する複数の素子チップが混在した状態において、検査に要する時間を短縮することができる。 In the appearance inspection apparatus according to one aspect of the present invention, as described above, the type of the pattern of the element chip to be inspected imaged by the imaging unit is identified, and the image of the element chip to be inspected imaged by the imaging unit And a non-defective image corresponding to the identified pattern of the element chip to be inspected, and an inspection unit that determines whether the element chip to be inspected is non-defective. As a result, the type of pattern of the element chip to be inspected imaged by the inspection unit is identified, so that the pattern of the element chip to be inspected imaged from the storage unit corresponds to each element chip of the imaged inspection object A good product image can be read out. As a result, in the state where a plurality of element chips having different patterns are mixed, whether or not the element chip is a non-defective product by one scan without repeating the imaging of the plurality of element chips by the imaging unit (scanning by the imaging unit). Can be determined. Thereby, the time required for the inspection can be shortened in a state where a plurality of element chips having different patterns are mixed.
　上記一の局面による外観検査装置において、好ましくは、複数の素子チップは、基板上に設けられており、記憶部には、基板上のいずれの位置に設けられた素子チップがいずれのパターンを有するかのチップ配置情報が予め記憶されており、検査部は、記憶部に記憶されたチップ配置情報に基づいて、撮像部によって撮像された検査用の素子チップのパターンの種類を識別するように構成されている。このように構成すれば、記憶部に、基板上のいずれの位置に設けられた素子チップがいずれのパターンを有するかのチップ配置情報が予め記憶されているので、撮像した検査用の素子チップのパターンがいずれの良品画像に対応するかを画像認識（画像同士の比較）などにより認識する場合と比べて、検査に要する時間をより短縮することができる。 In the appearance inspection apparatus according to the above aspect, the plurality of element chips are preferably provided on the substrate, and the element chip provided at any position on the substrate has any pattern in the storage unit. The chip arrangement information is stored in advance, and the inspection unit is configured to identify the type of pattern of the element chip for inspection imaged by the imaging unit based on the chip arrangement information stored in the storage unit Has been. If comprised in this way, since the chip | tip arrangement | positioning information of which element chip | tip provided in which position on a board | substrate has which pattern is previously memorize | stored in the memory | storage part, the element chip | tip for the test | inspection imaged was imaged. Compared with the case of recognizing which non-defective image the pattern corresponds to by image recognition (comparison between images) or the like, the time required for the inspection can be further shortened.
　この場合、好ましくは、基板上には、互いに異なるパターンが各々形成された複数の素子チップを各々含む素子チップ群が複数設けられており、素子チップ群における、互いに異なるパターンが各々形成された複数の素子チップの配置位置は、素子チップ群の各々において同じであり、記憶部には、複数の素子チップ群を含む複数の素子チップのチップ配置情報が予め記憶されている。このように構成すれば、複数の素子チップの配置位置が、素子チップ群の各々において同じであるので、同一のマスクを用いて、素子チップ群毎に素子チップを形成することができる。 In this case, preferably, a plurality of element chip groups each including a plurality of element chips each having a different pattern are provided on the substrate, and a plurality of element chips each having a different pattern formed therein. The arrangement positions of the element chips are the same in each of the element chip groups, and chip storage information of a plurality of element chips including the plurality of element chip groups is stored in advance in the storage unit. If comprised in this way, since the arrangement position of several element chip is the same in each element chip group, an element chip can be formed for every element chip group using the same mask.
　上記複数の素子チップが基板上に設けられている外観検査装置において、好ましくは、基板と撮像部とが相対的に移動している状態で、撮像部による検査用の素子チップの撮像と、検査部による、撮像された検査用の素子チップのパターンの種類の識別と、良品画像を、識別された検査用の素子チップのパターンに対応するパターンを有する良品画像に切り替えることと、検査用の素子チップの画像と良品画像とを比較することにより素子チップが良品か否かの判別を行うこととが、順次、基板上に設けられた複数の検査用の素子チップ毎に行われるように構成されている。このように構成すれば、互いに異なるパターンを有する複数の素子チップが混在した状態において、複数の素子チップの検査を連続してスムーズに行うことができる。 In the appearance inspection apparatus in which the plurality of element chips are provided on the substrate, preferably, the imaging of the element chip for inspection by the imaging unit and the inspection are performed while the substrate and the imaging unit are relatively moved. Identifying the type of pattern of the imaged element chip for inspection by the unit, switching the non-defective image to a non-defective image having a pattern corresponding to the pattern of the identified element chip for inspection, and an element for inspection The determination of whether the element chip is non-defective by comparing the chip image with the non-defective image is sequentially performed for each of the plurality of inspection element chips provided on the substrate. ing. If comprised in this way, in the state where the several element chip which has a mutually different pattern was mixed, the test | inspection of a several element chip can be performed continuously and smoothly.
　本発明によれば、上記のように、互いに異なるパターンを有する複数の素子チップが混在した状態において、検査に要する時間を短縮することができる。 According to the present invention, as described above, it is possible to reduce the time required for inspection in a state where a plurality of element chips having different patterns are mixed.
本発明の一実施形態による外観検査装置の全体図である。1 is an overall view of an appearance inspection apparatus according to an embodiment of the present invention. 本発明の一実施形態による外観検査装置の撮像部の動作を説明するための図である。It is a figure for demonstrating operation | movement of the imaging part of the external appearance inspection apparatus by one Embodiment of this invention. 良品画像（良品の素子チップの画像）を示す図である。It is a figure which shows a good quality image (image of a good quality element chip). 検査用の素子チップを示す図である。It is a figure which shows the element chip | tip for a test | inspection. ウェハに設けられた複数の素子チップを示す図である。It is a figure which shows the several element chip | tip provided in the wafer. ウェハに設けられた、互いに異なるパターンを有する複数の素子チップを示す図である。It is a figure which shows the several element chip which has a mutually different pattern provided in the wafer. 素子チップ群における複数の素子チップの配置位置を示す図である。It is a figure which shows the arrangement position of the several element chip in an element chip group. 本発明の一実施形態による外観検査装置の条件設定の動作を説明するためのフロー図である。It is a flowchart for demonstrating operation | movement of the condition setting of the external appearance inspection apparatus by one Embodiment of this invention. 本発明の一実施形態による外観検査装置の良品画像を生成するための動作を説明するためのフロー図である。It is a flowchart for demonstrating the operation | movement for producing | generating the good quality image of the external appearance inspection apparatus by one Embodiment of this invention. 本発明の一実施形態による外観検査装置の素子チップを検査する動作を説明するためのフロー図である。It is a flowchart for demonstrating the operation | movement which test | inspects the element chip | tip of the external appearance inspection apparatus by one Embodiment of this invention. 不良品の素子チップを示す図である。It is a figure which shows the defective element chip.
　以下、本発明を具体化した実施形態を図面に基づいて説明する。 Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
　［本実施形態］
　（外観検査装置の構造）
　図１～図７を参照して、本実施形態による外観検査装置１００の構造について説明する。外観検査装置１００は、互いに異なるパターンを有する複数の素子チップ２１０（図４参照）が混在した状態で、複数の素子チップ２１０を各々検査するように構成されている。 [This embodiment]
(Structure of appearance inspection equipment)
With reference to FIGS. 1 to 7, the structure of the appearance inspection apparatus 100 according to the present embodiment will be described. The appearance inspection apparatus 100 is configured to inspect each of the plurality of element chips 210 in a state where a plurality of element chips 210 (see FIG. 4) having different patterns are mixed.
　図１に示すように、外観検査装置１００は、移動ステージ１０を備えている。移動ステージ１０は、Ｘ軸スライダ１１とＹ軸スライダ１２とを含む。Ｘ軸スライダ１１は、台部２０上に配置されている。また、Ｙ軸スライダ１２は、Ｘ軸スライダ１１上に配置されている。 As shown in FIG. 1, the appearance inspection apparatus 100 includes a moving stage 10. The moving stage 10 includes an X-axis slider 11 and a Y-axis slider 12. The X-axis slider 11 is disposed on the base 20. The Y-axis slider 12 is disposed on the X-axis slider 11.
　また、外観検査装置１００は、載置テーブル３０を備えている。載置テーブル３０は、Ｙ軸スライダ１２上に配置されている。そして、載置テーブル３０は、移動ステージ１０によって、Ｘ方向およびＹ方向に移動されるように構成されている。また、載置テーブル３０は、ウェハ２２０（検査対象の素子チップ２１０、図４参照）を載置するように構成されている。なお、ウェハ２２０は、特許請求の範囲の「基板」の一例である。 Further, the appearance inspection apparatus 100 includes a mounting table 30. The mounting table 30 is disposed on the Y-axis slider 12. The mounting table 30 is configured to be moved in the X direction and the Y direction by the moving stage 10. The mounting table 30 is configured to mount the wafer 220 (the element chip 210 to be inspected, see FIG. 4). The wafer 220 is an example of the “substrate” in the claims.
　また、外観検査装置１００は、撮像部４０を備えている。撮像部４０は、検査対象の素子チップ２１０、および、検査基準となる良品画像Ｐ（良品の素子チップ２１０の画像、図３参照）を作成するために、良品の素子チップ２１０を撮像するように構成されている。撮像部４０は、鏡筒４１と、ハーフミラー４２と、対物レンズ４３と、撮像カメラ４４とを含む。撮像カメラ４４は、受光素子４４ａを含んでいる。そして、撮像カメラ４４は、撮像した素子チップ２１０の画像を後述する制御部６０に出力するように構成されている。 In addition, the appearance inspection apparatus 100 includes an imaging unit 40. The imaging unit 40 captures the non-defective element chip 210 in order to create the element chip 210 to be inspected and the non-defective image P serving as the inspection reference (image of the non-defective element chip 210, see FIG. 3). It is configured. The imaging unit 40 includes a lens barrel 41, a half mirror 42, an objective lens 43, and an imaging camera 44. The imaging camera 44 includes a light receiving element 44a. The imaging camera 44 is configured to output the captured image of the element chip 210 to the control unit 60 described later.
　また、図２に示すように、撮像部４０は、撮像部４０に対して相対的に移動する複数の素子チップ２１０を、順次撮像するように構成されている。具体的には、素子チップ２１０が、移動ステージ１０により、撮像部４０に対してＸ方向またはＹ方向に相対的に移動される。 As shown in FIG. 2, the imaging unit 40 is configured to sequentially capture a plurality of element chips 210 that move relative to the imaging unit 40. Specifically, the element chip 210 is moved relative to the imaging unit 40 in the X direction or the Y direction by the moving stage 10.
　また、図１に示すように、外観検査装置１００は、記憶部５０を備えている。図３に示すように、記憶部５０には、互いに異なるパターン（パターンＡ～Ｄ）の素子チップ２１０の検査基準となる良品画像Ｐが予め記憶されている。なお、「予め」とは、検査対象の素子チップ２１０を検査する前を意味する。また、良品画像Ｐは、複数記憶されている。たとえば、図３に示すように、良品画像Ｐは、パターンＡに対応する良品画像Ｐ１（図３（ａ）参照）、パターンＢに対応する良品画像Ｐ２（図３（ｂ）参照）、パターンＣに対応する良品画像Ｐ３（図３（ｃ）参照）、および、パターンＤに対応する良品画像Ｐ４（図３（ｄ）参照）を含む。また、良品画像Ｐ１～Ｐ４は、個別に記憶部５０に記憶されている。 Further, as shown in FIG. 1, the appearance inspection apparatus 100 includes a storage unit 50. As shown in FIG. 3, the storage unit 50 stores in advance a non-defective image P that serves as an inspection reference for the element chips 210 having different patterns (patterns A to D). Note that “in advance” means before the element chip 210 to be inspected is inspected. A plurality of non-defective images P are stored. For example, as shown in FIG. 3, the non-defective image P includes a non-defective image P1 corresponding to the pattern A (see FIG. 3A), a non-defective image P2 corresponding to the pattern B (see FIG. 3B), and a pattern C. And a non-defective image P4 (see FIG. 3D) corresponding to the pattern D. The non-defective images P1 to P4 are individually stored in the storage unit 50.
　良品画像Ｐ１～Ｐ４は、それぞれ、有効領域２１１に設けられる配線パターンが、互いに異なるように構成されている良品の素子チップ２１０ａ～２１０ｄ（図４参照）の画像である。たとえば、配線パターンの配置位置、大きさなどが、互いに異なる。なお、図４では、素子チップ２１０ａ～２１０ｄの各々の有効領域２１１を取り囲む周縁領域２１２は互いに同じパターンを有する一方、素子チップ２１０ａ～２１０ｄの周縁領域２１２のパターンが互いに異なっていてもよい。 The non-defective images P1 to P4 are images of non-defective element chips 210a to 210d (see FIG. 4) configured so that the wiring patterns provided in the effective area 211 are different from each other. For example, the arrangement positions and sizes of the wiring patterns are different from each other. In FIG. 4, the peripheral regions 212 surrounding the effective regions 211 of the element chips 210a to 210d have the same pattern, while the patterns of the peripheral regions 212 of the element chips 210a to 210d may be different from each other.
　また、図５に示すように、複数の素子チップ２１０は、ウェハ２２０上に設けられている。ウェハ２２０は、平面視において、略円形状を有する。また、複数の素子チップ２１０は、ウェハ２２０上にマトリクス状に設けられている。そして、本実施形態では、図６に示すように、記憶部５０には、ウェハ２２０上のいずれの位置に設けられた素子チップ２１０がいずれのパターンＡ～Ｄを有するかのチップ配置情報が予め記憶されている。具体的には、ウェハ２２０上にマトリクス状に設けられている複数の素子チップ２１０が、良品画像Ｐ１～Ｐ４のうちのいずれの良品画像Ｐに対応するか（いずれの良品画像Ｐと同じパターンＡ～Ｄを有するか）についてのチップ配置情報が記憶部５０に予め記憶されている。なお、チップ配置情報は、検査用の素子チップ２１０の検査前に、たとえば、ユーザにより入力される。なお、図６では、一部の素子チップ２１０にパターンＡ～Ｄが記載されているが、実際には、全ての素子チップ２１０のパターンＡ～Ｄが記憶部５０に予め記憶されている。 Further, as shown in FIG. 5, the plurality of element chips 210 are provided on the wafer 220. The wafer 220 has a substantially circular shape in plan view. The plurality of element chips 210 are provided in a matrix on the wafer 220. In the present embodiment, as shown in FIG. 6, the storage unit 50 stores in advance chip arrangement information indicating which pattern A to D the element chip 210 provided at which position on the wafer 220 has. It is remembered. Specifically, which of the non-defective images P1 to P4 corresponds to the non-defective image P among the plurality of element chips 210 provided in a matrix on the wafer 220 (the same pattern A as any non-defective image P). Chip arrangement information on whether or not to have D) is stored in the storage unit 50 in advance. The chip arrangement information is input by, for example, the user before the inspection of the element chip 210 for inspection. In FIG. 6, the patterns A to D are described for some of the element chips 210, but actually, the patterns A to D of all the element chips 210 are stored in the storage unit 50 in advance.
　また、本実施形態では、図６に示すように、ウェハ２２０上には、互いに異なるパターンが各々形成された複数の素子チップ２１０（検査用の素子チップ２１０）を各々含む素子チップ群２３０（図６の太線の四角で囲われた領域）が複数設けられている。たとえば、図７に示すように、１つの素子チップ群２３０には、互いに異なるパターンが各々形成された４個の素子チップ２１０ａ～２１０ｄを含む。そして、素子チップ群２３０における、互いに異なるパターンが各々形成された複数の素子チップ２１０ａ～２１０ｄの配置位置は、素子チップ群２３０の各々において同じである。たとえば、１つの素子チップ群２３０において、４個の素子チップ２１０ａ～２１０ｄは、２行２列の状態で配置されている。そして、左上に、素子チップ２１０ａが配置され、右上に、素子チップ２１０ｂが配置されている。また、左下に、素子チップ２１０ｃが配置され、右下に、素子チップ２１０ｄが配置されている。この配置位置は、いずれの素子チップ群２３０においても同じである。 In the present embodiment, as shown in FIG. 6, an element chip group 230 (see FIG. 6) including a plurality of element chips 210 (inspection element chips 210) each having a different pattern formed on the wafer 220. A plurality of areas surrounded by a square of 6 thick lines) are provided. For example, as shown in FIG. 7, one element chip group 230 includes four element chips 210a to 210d each formed with a different pattern. In the element chip group 230, the arrangement positions of the plurality of element chips 210a to 210d on which different patterns are formed are the same in each element chip group 230. For example, in one element chip group 230, four element chips 210a to 210d are arranged in a state of 2 rows and 2 columns. The element chip 210a is disposed on the upper left, and the element chip 210b is disposed on the upper right. In addition, an element chip 210c is arranged at the lower left, and an element chip 210d is arranged at the lower right. This arrangement position is the same in any element chip group 230.
　なお、図６に示すように、ウェハ２２０の外縁側では、ウェハ２２０が略円形状であることに起因して、４個の素子チップ２１０ａ～２１０ｄが配置できない。このため、ウェハ２２０の外縁側では、１つの素子チップ群２３０において、４個の素子チップ２１０ａ～２１０ｄのうちのいずれか１つ（または複数）が欠けた状態になっている。なお、素子チップ２１０ａ～２１０ｄの配置位置が素子チップ群２３０の各々において同じである理由は、素子チップ２１０ａ～２１０ｄをウェハ２２０上に形成する際に、同一のマスク（図示せず）を用いて素子チップ２１０ａ～２１０ｄが形成されるためである。 As shown in FIG. 6, on the outer edge side of the wafer 220, the four element chips 210a to 210d cannot be arranged because the wafer 220 is substantially circular. Therefore, on the outer edge side of the wafer 220, one element chip group 230 is in a state where any one (or a plurality) of the four element chips 210a to 210d is missing. The reason why the arrangement positions of the element chips 210a to 210d are the same in each of the element chip groups 230 is that when the element chips 210a to 210d are formed on the wafer 220, the same mask (not shown) is used. This is because the element chips 210a to 210d are formed.
　そして、本実施形態では、記憶部５０には、複数の素子チップ群２３０を含む複数の素子チップ２１０のチップ配置情報が予め記憶されている。すなわち、記憶部５０には、図６に示すようなチップ配置情報が予め記憶されている。 In the present embodiment, the storage unit 50 stores in advance chip arrangement information of a plurality of element chips 210 including a plurality of element chip groups 230. That is, chip arrangement information as shown in FIG. 6 is stored in the storage unit 50 in advance.
　また、図１に示すように、外観検査装置１００は、検査部６１を備えている。検査部６１は、たとえば、ＣＰＵなどにより構成される制御部６０に含まれている。なお、制御部６０は、外観検査装置１００の全体の動作を制御するように構成されている。ここで、本実施形態では、検査部６１は、撮像部４０によって撮像された検査対象の素子チップ２１０のパターンＡ～Ｄの種類を識別する。そして、検査部６１は、撮像部４０によって撮像された検査対象の素子チップ２１０の画像と、識別された検査対象の素子チップ２１０のパターンＡ～Ｄに対応する良品画像Ｐとを比較することにより、検査対象の素子チップ２１０が良品か否かの判別を行う。具体的には、検査部６１は、記憶部５０に記憶されたチップ配置情報（図６参照）に基づいて、撮像部４０によって撮像された検査用の素子チップ２１０のパターンＡ～Ｄの種類を識別するように構成されている。 Further, as shown in FIG. 1, the appearance inspection apparatus 100 includes an inspection unit 61. The inspection unit 61 is included in the control unit 60 configured by, for example, a CPU. The control unit 60 is configured to control the overall operation of the appearance inspection apparatus 100. Here, in the present embodiment, the inspection unit 61 identifies the types of the patterns A to D of the element chip 210 to be inspected that is imaged by the imaging unit 40. Then, the inspection unit 61 compares the image of the element chip 210 to be inspected imaged by the imaging unit 40 with the non-defective image P corresponding to the identified patterns A to D of the element chip 210 to be inspected. Then, it is determined whether or not the element chip 210 to be inspected is a non-defective product. Specifically, the inspection unit 61 determines the types of patterns A to D of the inspection element chip 210 imaged by the imaging unit 40 based on the chip arrangement information (see FIG. 6) stored in the storage unit 50. Configured to identify.
　（外観検査装置の動作）
　次に、図８～図１１を参照して、外観検査装置１００の動作について説明する。 (Operation of visual inspection equipment)
Next, the operation of the appearance inspection apparatus 100 will be described with reference to FIGS.
　〈条件設定〉
　図８を参照して、条件設定の動作（フロー）について説明する。なお、下記に説明する登録は、たとえば、情報を受け付ける画面が図示しない表示部などに表示されるとともに、ユーザにより情報が入力されることにより行われる。また、登録（入力）された情報は、記憶部５０に登録（記憶）される。 <Condition setting>
The condition setting operation (flow) will be described with reference to FIG. The registration described below is performed, for example, when a screen for receiving information is displayed on a display unit (not shown) or the like and information is input by the user. The registered (input) information is registered (stored) in the storage unit 50.
　まず、ステップＳ１において、マップ情報が登録される。具体的には、ウェハ２２０のサイズや、素子チップ２１０のサイズなどが登録される。 First, in step S1, map information is registered. Specifically, the size of the wafer 220, the size of the element chip 210, and the like are registered.
　次に、ステップＳ２において、素子チップ２１０のパターンの登録が行われる。具体的には、図６に示すように、ウェハ２２０上のいずれの位置に設けられた素子チップ２１０がいずれのパターンを有するかのチップ配置情報が登録される。 Next, in step S2, the pattern of the element chip 210 is registered. Specifically, as shown in FIG. 6, chip arrangement information indicating which pattern the element chip 210 provided at which position on the wafer 220 has is registered.
　次に、ステップＳ３において、素子チップ２１０のグローバルアライメントの情報の登録が行われる。たとえば、素子チップ２１０の角度や中心位置などの情報が登録される。 Next, in step S3, global alignment information of the element chip 210 is registered. For example, information such as the angle and center position of the element chip 210 is registered.
　次に、ステップＳ４において、検査条件が登録される。具体的には、撮像部４０によって素子チップ２１０の撮像を行う際の光学的な条件や、素子チップ２１０上における検査領域などが登録される。なお、検査領域は、たとえば、図４の素子チップ２１０上において点線で囲われた領域である。これにより、条件設定の動作は、終了する。 Next, in step S4, inspection conditions are registered. Specifically, the optical conditions when imaging the element chip 210 by the imaging unit 40, the inspection area on the element chip 210, and the like are registered. The inspection area is, for example, an area surrounded by a dotted line on the element chip 210 in FIG. As a result, the condition setting operation ends.
　〈良品画像の作成〉
　図９を参照して、良品画像Ｐの作成（トレーニング）の動作（フロー）について説明する。なお、良品画像Ｐの作成は、制御部６０により行われる。また、作成された良品画像Ｐは、記憶部５０に登録される。また、良品画像Ｐの作成（トレーニング）は、後述する検査用の素子チップ２１０の検査を行う前に予め行われる。 <Creating non-defective images>
With reference to FIG. 9, the operation (flow) of creation (training) of the non-defective image P will be described. The non-defective product image P is created by the control unit 60. In addition, the created non-defective image P is registered in the storage unit 50. Further, the creation (training) of the non-defective product image P is performed in advance before the inspection of the inspection element chip 210 described later.
　まず、ステップＳ１１において、検査条件が記憶部５０から読み出される。検査条件は、上記ステップＳ４において登録されたものである。 First, the inspection condition is read from the storage unit 50 in step S11. The inspection conditions are those registered in step S4.
　次に、ステップＳ１２において、ウェハ２２０が搬送される。具体的には、ウェハ２２０は、移動ステージ１０（載置テーブル３０）に載置される。また、ウェハ２２０には、互いに異なるパターンを有する複数の素子チップ２１０が混在した状態で配置されている。なお、ウェハ２２０に配置される複数の素子チップ２１０が全て良品の素子チップ２１０であってもよいし、複数の素子チップ２１０のうちのいずれかに不良品の素子チップ２１０が含まれていてもよい。なお、複数の素子チップ２１０のうちのいずれが良品の素子チップ２１０であり、複数の素子チップ２１０のうちのいずれが不良品の素子チップ２１０であるかの情報は、ユーザ（制御部６０）が予め認知しているとする。 Next, in step S12, the wafer 220 is transferred. Specifically, the wafer 220 is placed on the moving stage 10 (mounting table 30). In addition, a plurality of element chips 210 having different patterns are arranged on the wafer 220 in a mixed state. Note that all of the plurality of element chips 210 arranged on the wafer 220 may be non-defective element chips 210, or one of the plurality of element chips 210 may include a defective element chip 210. Good. Note that information on which of the plurality of element chips 210 is a non-defective element chip 210 and which of the plurality of element chips 210 is a defective element chip 210 is provided by the user (control unit 60). Assume that you are aware in advance.
　次に、ステップＳ１３において、ウェハ２２０（素子チップ２１０）のグローバルアライメントが行われる。たとえば、素子チップ２１０の角度や中心位置などが定められる。なお、グローバルアライメントの情報は、上記ステップＳ３において登録されている。 Next, in step S13, global alignment of the wafer 220 (element chip 210) is performed. For example, the angle and center position of the element chip 210 are determined. The global alignment information is registered in step S3.
　次に、ステップＳ１４において、目標とする素子チップ２１０の上方に、撮像部４０が相対移動する。具体的には、ウェハ２２０が移動ステージ１０に移動されることにより、撮像部４０の直下に目標とする素子チップ２１０が配置される。複数の素子チップ２１０のうち、いずれの素子チップ２１０を目標の素子チップ２１０とするかは、予め記憶部５０に登録されている。たとえば、ウェハ２２０上の複数の素子チップ２１０が全て良品であれば、全ての素子チップ２１０を目標としてもよい。また、ウェハ２２０上の複数の素子チップ２１０に不良品が含まれていれば、良品の素子チップ２１０のみを目標の素子チップ２１０とすればよい。また、全ての良品の素子チップ２１０を目標とせずに、一部の良品の素子チップ２１０を目標としてもよい。 Next, in step S14, the imaging unit 40 relatively moves above the target element chip 210. Specifically, when the wafer 220 is moved to the moving stage 10, the target element chip 210 is disposed immediately below the imaging unit 40. Which of the plurality of element chips 210 is the target element chip 210 is registered in the storage unit 50 in advance. For example, if all of the plurality of element chips 210 on the wafer 220 are non-defective, all the element chips 210 may be targeted. Further, if a defective product is included in the plurality of device chips 210 on the wafer 220, only the good device chip 210 may be set as the target device chip 210. Alternatively, not all non-defective element chips 210 may be targeted, but some non-defective element chips 210 may be targeted.
　次に、ステップＳ１５において、目標の素子チップ２１０が撮像される。素子チップ２１０は、１つの素子チップ２１０毎に撮像される。 Next, in step S15, the target element chip 210 is imaged. The element chip 210 is imaged for each element chip 210.
　次に、ステップＳ１６において、撮像部４０により撮像された良品の素子チップ２１０のパターンの種類が認識される。つまり、撮像された良品の素子チップ２１０が、パターンＡ～Ｄのうちのいずれに該当するのかが認識される。なお、ウェハ２２０上に配置されている複数の素子チップ２１０のパターンがパターンＡ～Ｄのうちのいずれに該当するかは、素子チップ２１０のウェハ２２０上の位置（座標）に対応させて予め記憶部５０に記憶されている。そして、ウェハ２２０に対する撮像部４０の位置情報（座標）に基づいて、今回撮影した素子チップ２１０のパターンがパターンＡ～Ｄのうちのいずれに該当するのかが認識される。 Next, in step S16, the pattern type of the non-defective element chip 210 imaged by the imaging unit 40 is recognized. That is, it is recognized which of the patterns A to D corresponds to the imaged non-defective element chip 210. It should be noted that whether the pattern of the plurality of element chips 210 arranged on the wafer 220 corresponds to one of the patterns A to D is stored in advance corresponding to the position (coordinates) of the element chip 210 on the wafer 220. Stored in the unit 50. Based on the positional information (coordinates) of the imaging unit 40 with respect to the wafer 220, it is recognized which of the patterns A to D corresponds to the pattern of the element chip 210 photographed this time.
　次に、ステップＳ１７において、撮像された素子チップ２１０のアライメントが行われる。たとえば、素子チップ２１０に予め設けられたアライメントマークに基づいて、素子チップ２１０の有効領域２１１（素子が形成される領域、図４参照）および周縁領域２１２（有効領域２１１を取り囲む素子が形成されない領域）がアライメントされる。 Next, in step S17, the imaged element chip 210 is aligned. For example, based on alignment marks provided in advance in the element chip 210, the effective area 211 (area where the element is formed, see FIG. 4) and the peripheral area 212 (area where the element surrounding the effective area 211 is not formed) are formed. ) Are aligned.
　次に、ステップＳ１８において、撮像された良品の素子チップ２１０の画像（良品画像Ｐ）が、パターンＡ～Ｄ毎に振り分けて記憶部５０に記憶される。 Next, in step S18, the captured image of the non-defective element chip 210 (non-defective product image P) is sorted into patterns A to D and stored in the storage unit 50.
　次に、ステップＳ１９において、目標とする全ての良品の素子チップ２１０の撮像などが終了したか否かが判断される。目標とする全ての良品の素子チップ２１０の撮像などが終了していないと判断された場合には、ステップＳ１４に戻る。目標とする全ての良品の素子チップ２１０の撮像などが終了したと判断された場合には、ステップＳ２０に進む。 Next, in step S19, it is determined whether or not imaging of all target non-defective element chips 210 has been completed. If it is determined that imaging of all target non-defective element chips 210 has not been completed, the process returns to step S14. If it is determined that the imaging of all target non-defective element chips 210 has been completed, the process proceeds to step S20.
　なお、上記のステップＳ１４～ステップＳ１９の動作は、ウェハ２２０と撮像部４０とが相対的に移動している状態で連続して行われる。たとえば、図６の経路Ｂに示すように、ウェハ２２０上に設けられた複数の素子チップ２１０を一筆書き状に撮像するように、ウェハ２２０と撮像部４０とが相対的に移動される。具体的には、ウェハ２２０が撮像部４０に対してＹ１方向に相対的に移動されて、Ｙ方向に沿って配置される複数の素子チップ２１０の撮像（および識別、登録、アライメント、登録）が行われる。そして、Ｙ１方向側の端部に配置された素子チップ２１０の撮像が終了した後、ウェハ２２０が撮像部４０に対してＸ１方向に１つの素子チップ２１０の大きさ分、相対的に移動される。その後、ウェハ２２０が撮像部４０に対してＹ２方向に相対的に移動されて、Ｙ方向に沿って配置される複数の素子チップ２１０の撮像が行われる。そして、Ｙ２方向側の端部に配置された素子チップ２１０の撮像が終了した後、ウェハ２２０が撮像部４０に対してＸ１方向に１つの素子チップ２１０の大きさ分、相対的に移動される。その後、上記の動作が繰り返される。 Note that the operations in steps S14 to S19 are continuously performed in a state where the wafer 220 and the imaging unit 40 are relatively moved. For example, as shown in a path B in FIG. 6, the wafer 220 and the imaging unit 40 are relatively moved so that the plurality of element chips 210 provided on the wafer 220 are imaged in a single stroke. Specifically, the wafer 220 is moved relative to the imaging unit 40 in the Y1 direction, and imaging (and identification, registration, alignment, registration) of the plurality of element chips 210 arranged along the Y direction is performed. Done. Then, after the imaging of the element chip 210 arranged at the end on the Y1 direction side is completed, the wafer 220 is moved relative to the imaging unit 40 by the size of one element chip 210 in the X1 direction. . Thereafter, the wafer 220 is moved relative to the imaging unit 40 in the Y2 direction, and imaging of the plurality of element chips 210 arranged along the Y direction is performed. Then, after the imaging of the element chip 210 arranged at the end on the Y2 direction side is completed, the wafer 220 is moved relative to the imaging unit 40 by the size of one element chip 210 in the X1 direction. . Thereafter, the above operation is repeated.
　次に、ステップＳ２０において、良品画像Ｐ（トレーニングデータ）が生成される。具体的には、良品の素子チップ２１０の画像は、パターンＡ～Ｄ毎に複数個ずつ記憶（保存）されている。そして、良品の素子チップ２１０の画像の輝度値が画素毎に加算された後、平均化される。この加算および平均化は、パターンＡ～Ｄ毎に個別に行われる。これにより、パターンＡ～Ｄ毎に、良品画像Ｐ（良品画像Ｐ１～Ｐ４）が生成される。 Next, in step S20, a non-defective image P (training data) is generated. Specifically, a plurality of non-defective element chips 210 are stored (stored) for each of patterns A to D. Then, the luminance values of the image of the non-defective element chip 210 are added for each pixel and then averaged. This addition and averaging are performed individually for each of the patterns A to D. As a result, a non-defective image P (non-defective image P1 to P4) is generated for each of the patterns A to D.
　次に、ステップＳ２１において、ウェハ２２０が所定の位置に収納されて、良品画像Ｐの生成の動作が終了する。 Next, in step S21, the wafer 220 is stored at a predetermined position, and the operation for generating the non-defective image P is completed.
　〈素子チップの検査〉
　図１０および図１１を参照して、素子チップ２１０の検査の動作（フロー）について説明する。なお、素子チップ２１０の検査は、検査部６１（制御部６０）により行われる。 <Inspection of element chip>
With reference to FIGS. 10 and 11, the operation (flow) of the inspection of the element chip 210 will be described. The element chip 210 is inspected by the inspection unit 61 (control unit 60).
　まず、ステップＳ３１において、検査条件が記憶部５０から読み出される。検査条件は
、上記ステップＳ４において登録されたものである。 First, in step S31, the inspection conditions are read from the storage unit 50. The inspection conditions are those registered in step S4.
　次に、ステップＳ３２において、ウェハ２２０が搬送される。具体的には、ウェハ２２０は、移動ステージ１０（載置テーブル３０）に載置される。また、ウェハ２２０には、互いに異なるパターンを有する複数の素子チップ２１０が混在した状態で配置されている。なお、ウェハ２２０に配置される複数の素子チップ２１０は、スクライブされていてもよいし、スクライブされていなくてもよい。 Next, in step S32, the wafer 220 is transferred. Specifically, the wafer 220 is placed on the moving stage 10 (mounting table 30). In addition, a plurality of element chips 210 having different patterns are arranged on the wafer 220 in a mixed state. The plurality of element chips 210 arranged on the wafer 220 may be scribed or not scribed.
　次に、ステップＳ３３において、ウェハ２２０（素子チップ２１０）の素子チップ２１０のグローバルアライメントが行われる。たとえば、素子チップ２１０の角度や中心位置などが定められる。なお、グローバルアライメントの情報は、上記ステップＳ３において登録されている。 Next, in step S33, global alignment of the element chip 210 of the wafer 220 (element chip 210) is performed. For example, the angle and center position of the element chip 210 are determined. The global alignment information is registered in step S3.
　次に、ステップＳ３４において、目標（検査対象）とする素子チップ２１０の上方に、撮像部４０が相対移動する。具体的には、ウェハ２２０が移動ステージ１０に移動されることにより、撮像部４０の直下に目標とする素子チップ２１０が配置される。 Next, in step S34, the imaging unit 40 relatively moves above the element chip 210 as a target (inspection target). Specifically, when the wafer 220 is moved to the moving stage 10, the target element chip 210 is disposed immediately below the imaging unit 40.
　次に、ステップＳ３５において、目標（検査対象）の素子チップ２１０が撮像される。素子チップ２１０は、１つの素子チップ２１０毎に撮像される。また、ウェハ２２０と撮像部４０とが相対的に移動している状態で、複数の素子チップ２１０が１つの素子チップ２１０毎に連続して撮像される。 Next, in step S35, the target (inspection target) element chip 210 is imaged. The element chip 210 is imaged for each element chip 210. In addition, a plurality of element chips 210 are continuously imaged for each element chip 210 while the wafer 220 and the imaging unit 40 are relatively moving.
　次に、本実施形態では、ステップＳ３６において、撮像部４０によって撮像された検査対象の素子チップ２１０のパターンの種類（パターンＡ～Ｄ）が識別される。記憶部５０には、ウェハ２２０上のいずれの位置に設けられた素子チップ２１０がいずれのパターンを有するかのチップ配置情報が予め記憶されている。たとえば、ウェハ２２０上のいずれの位置に設けられた素子チップ２１０がいずれのパターンを有するのかが、素子チップ２１０のウェハ２２０上の位置（座標）に対応させて記憶されている。そして、検査部６１は、記憶部５０に記憶されたチップ配置情報に基づいて、撮像部４０によって撮像された検査用の素子チップ２１０のパターンの種類を識別する。たとえば、ウェハ２２０に対する撮像部４０の位置情報（座標）に基づいて、今回撮影した素子チップ２１０のパターンがパターンＡ～Ｄのうちのいずれに該当するのかが認識される。 Next, in this embodiment, in step S36, the type (pattern A to D) of the pattern of the element chip 210 to be inspected imaged by the imaging unit 40 is identified. The storage unit 50 stores in advance chip arrangement information indicating which pattern the element chip 210 provided at which position on the wafer 220 has. For example, which pattern the element chip 210 provided at which position on the wafer 220 has is stored in correspondence with the position (coordinates) of the element chip 210 on the wafer 220. The inspection unit 61 identifies the type of pattern of the inspection element chip 210 imaged by the imaging unit 40 based on the chip arrangement information stored in the storage unit 50. For example, based on the positional information (coordinates) of the imaging unit 40 with respect to the wafer 220, it is recognized which of the patterns A to D corresponds to the pattern of the element chip 210 photographed this time.
　次に、ステップＳ３７において、撮像された素子チップ２１０のアライメントが行われる。たとえば、素子チップ２１０に予め設けられたアライメントマークに基づいて、素子チップ２１０の有効領域２１１（素子が形成される領域、図４参照）および周縁領域２１２（有効領域２１１を取り囲む素子が形成されない領域）がアライメントされる。 Next, in step S37, the imaged element chip 210 is aligned. For example, based on alignment marks provided in advance in the element chip 210, the effective area 211 (area where the element is formed, see FIG. 4) and the peripheral area 212 (area where the element surrounding the effective area 211 is not formed) are formed. ) Are aligned.
　次に、ステップＳ３８において、撮像された検査対象の素子チップ２１０のパターンに対応するパターンを有する良品画像Ｐが記憶部５０から読み出される。たとえば、撮像された検査対象の素子チップ２１０のパターンがパターンＡであれば、パターンＡを有する良品画像Ｐ１が記憶部５０から読み出される。つまり、撮像部４０によって撮像された検査対象の素子チップ２１０のパターンに対応させて、良品画像Ｐが切り替えられる。 Next, in step S38, a non-defective image P having a pattern corresponding to the pattern of the imaged element chip 210 to be inspected is read from the storage unit 50. For example, if the pattern of the imaged element chip 210 to be inspected is the pattern A, the non-defective image P1 having the pattern A is read from the storage unit 50. That is, the non-defective image P is switched in correspondence with the pattern of the element chip 210 to be inspected, which is imaged by the imaging unit 40.
　次に、ステップＳ３９において、本実施形態では、撮像部４０によって撮像された検査対象の素子チップ２１０の画像と、識別された検査対象の素子チップ２１０のパターンに対応する良品画像Ｐとを比較することにより、検査対象の素子チップ２１０が良品か否かの判別が行われる。たとえば、撮像されたパターンＡを有する検査対象の素子チップ２１０の画像と、パターンＡを有する良品画像Ｐ１とが比較される。具体的には、両方の画像の画素毎の輝度値が比較される。そして、比較された輝度値の差が比較的大きい場合には、検査対象の素子チップ２１０の画像と良品画像Ｐ１の画像とが異なっていることになる。この場合、検査対象の素子チップ２１０の輝度値の差が比較的大きい部分に、欠陥などが生じている場合がある。たとえば、図１１に示す素子チップ２１０のように、素子チップ２１０に欠陥２１３がある場合には、欠陥２１３に対応する画素において、良品画像Ｐ１との輝度値の差が大きくなる。そこで、比較された輝度値の差が比較的大きい場合には、検査対象の素子チップ２１０が良品でない（不良品である）と判断される。 Next, in step S39, in this embodiment, the image of the element chip 210 to be inspected imaged by the imaging unit 40 is compared with the non-defective image P corresponding to the identified pattern of the element chip 210 to be inspected. Thus, it is determined whether or not the element chip 210 to be inspected is a non-defective product. For example, the image of the element chip 210 to be inspected having the imaged pattern A and the good product image P1 having the pattern A are compared. Specifically, the luminance values for each pixel of both images are compared. When the compared luminance value difference is relatively large, the image of the element chip 210 to be inspected is different from the image of the non-defective image P1. In this case, a defect or the like may occur in a portion where the difference in luminance value of the element chip 210 to be inspected is relatively large. For example, when the element chip 210 has a defect 213 as in the element chip 210 shown in FIG. 11, the difference in luminance value from the non-defective image P <b> 1 increases in the pixel corresponding to the defect 213. Therefore, when the difference between the compared luminance values is relatively large, it is determined that the element chip 210 to be inspected is not a good product (a defective product).
　また、検査部６１により良品か否かの判別が終了した検査用の素子チップ２１０の画像は、検査用の素子チップ２１０が良品か否かの判別が終了する毎に消去される。これにより、メモリ（図示せず）に記憶される素子チップ２１０のデータの容量が大きくなるのが抑制可能となる。 Also, the image of the inspection element chip 210 for which the determination of whether or not the inspection element 61 is a non-defective product is erased every time the determination of whether or not the inspection element chip 210 is a non-defective product is completed. As a result, it is possible to suppress an increase in the data capacity of the element chip 210 stored in the memory (not shown).
　次に、ステップＳ４０において、全ての検査対象の素子チップ２１０の検査が終了したか否かが判断される。全ての検査対象の素子チップ２１０の検査が終了していないと判断された場合には、ステップＳ３４に戻る。なお、上記のステップＳ３４～ステップＳ４０の動作は、ウェハ２２０と撮像部４０とが相対的に移動している状態で連続して行われる。たとえば、図６の経路Ｂに示すように、ウェハ２２０上に設けられた複数の素子チップ２１０を一筆書き状に撮像するように、ウェハ２２０と撮像部４０とが相対的に移動される。これにより、ウェハ２２０と撮像部４０とを、経路を遡るような無駄な移動なく相対移動させることができるので、全ての素子チップ２１０の撮像に要する時間を短縮することができる。なお、ウェハ２２０と撮像部４０との相対的な移動の動作は、上記良品画像の作成時の動作と同様である。このように、本実施形態では、ウェハ２２０と撮像部４０とが相対的に移動している状態で、撮像部４０による検査用の素子チップ２１０の撮像と、検査部６１による、撮像された検査用の素子チップ２１０のパターンの種類の識別と、良品画像Ｐを、識別された検査用の素子チップ２１０のパターンに対応するパターンを有する良品画像Ｐに切り替えることと、検査用の素子チップ２１０の画像と良品画像Ｐとを比較することにより素子チップ２１０が良品か否かの判別を行うこととが、順次、ウェハ２２０に設けられた複数の検査用の素子チップ２１０毎に行われるように構成されている。 Next, in step S40, it is determined whether or not all the element chips 210 to be inspected have been inspected. If it is determined that the inspection of all the element chips 210 to be inspected has not been completed, the process returns to step S34. Note that the operations in steps S34 to S40 are continuously performed in a state where the wafer 220 and the imaging unit 40 are relatively moved. For example, as shown in a path B in FIG. 6, the wafer 220 and the imaging unit 40 are relatively moved so that the plurality of element chips 210 provided on the wafer 220 are imaged in a single stroke. As a result, the wafer 220 and the imaging unit 40 can be moved relative to each other without wasteful movement that goes back along the path, so that the time required for imaging all the element chips 210 can be shortened. Note that the relative movement between the wafer 220 and the imaging unit 40 is the same as that at the time of creating the non-defective image. Thus, in the present embodiment, the inspection of the element chip 210 for inspection by the imaging unit 40 and the inspection imaged by the inspection unit 61 in a state where the wafer 220 and the imaging unit 40 are relatively moving. Identifying the type of the pattern of the element chip 210 for use, switching the non-defective image P to the good image P having a pattern corresponding to the pattern of the identified element chip 210 for inspection, It is configured that the determination of whether or not the element chip 210 is a non-defective product by comparing the image with the non-defective image P is sequentially performed for each of the plurality of inspection element chips 210 provided on the wafer 220. Has been.
　また、ステップＳ４０において、全ての検査対象の素子チップ２１０の検査が終了したと判断された場合には、ステップＳ４１に進む。 If it is determined in step S40 that the inspection of all the element chips 210 to be inspected has been completed, the process proceeds to step S41.
　次に、ステップＳ４１において、ウェハ２２０が所定の位置に収納されて、検査対象の素子チップ２１０の検査の動作が終了する。 Next, in step S41, the wafer 220 is stored at a predetermined position, and the operation of inspecting the element chip 210 to be inspected is completed.
　（本実施形態の効果）
　次に、本実施形態の効果について説明する。 (Effect of this embodiment)
Next, the effect of this embodiment will be described.
　本実施形態では、上記のように、撮像部４０によって撮像された検査対象の素子チップ２１０のパターンＡ～Ｄの種類を識別するとともに、撮像部４０によって撮像された検査対象の素子チップ２１０の画像と、識別された検査対象の素子チップ２１０のパターン（Ａ～Ｄ）に対応する良品画像Ｐとを比較することにより、検査対象の素子チップ２１０が良品か否かの判別を行う検査部６１を備える。これにより、検査部６１により撮像された検査対象の素子チップ２１０のパターンの種類が識別されるので、撮像された検査対象の素子チップ２１０毎に、記憶部５０から撮像された検査対象の素子チップ２１０のパターンに対応する良品画像Ｐを読み出すことができる。その結果、互いに異なるパターンを有する複数の素子チップ２１０が混在した状態において、撮像部４０による複数の素子チップ２１０の撮像（撮像部４０による走査）を繰り返すことなく、１回の走査により、素子チップ２１０が良品か否かの判別を行うことができる。これにより、互いに異なるパターンを有する複数の素子チップ２１０が混在した状態において、検査に要する時間を短縮することができる。 In the present embodiment, as described above, the types of patterns A to D of the element chip 210 to be inspected imaged by the imaging unit 40 are identified, and the image of the element chip 210 to be inspected imaged by the imaging unit 40 is identified. And the non-defective product image P corresponding to the pattern (A to D) of the identified element chip 210 to be inspected, the inspection unit 61 that determines whether or not the element chip 210 to be inspected is non-defective Prepare. As a result, the type of pattern of the element chip 210 to be inspected imaged by the inspection unit 61 is identified, so that the element chip to be inspected imaged from the storage unit 50 for each imaged element chip 210 to be inspected. A non-defective product image P corresponding to the pattern 210 can be read out. As a result, in a state where a plurality of element chips 210 having different patterns are mixed, the element chips are obtained by one scan without repeating the imaging of the plurality of element chips 210 by the imaging unit 40 (scanning by the imaging unit 40). It is possible to determine whether 210 is a non-defective product. Thereby, the time required for the inspection can be shortened in a state where a plurality of element chips 210 having different patterns are mixed.
　また、本実施形態では、上記のように、複数の素子チップ２１０は、ウェハ２２０上に設けられており、記憶部５０には、ウェハ２２０上のいずれの位置に設けられた素子チップ２１０がいずれのパターンを有するかのチップ配置情報が予め記憶されており、検査部６１は、記憶部５０に記憶されたチップ配置情報に基づいて、撮像部４０によって撮像された検査用の素子チップ２１０のパターンの種類を識別するように構成されている。これにより、記憶部５０に、ウェハ２２０上のいずれの位置に設けられた素子チップ２１０がいずれのパターンを有するかのチップ配置情報が予め記憶されているので、撮像した検査用の素子チップ２１０のパターンがいずれの良品画像Ｐに対応するかを画像認識（画像同士の比較）などにより認識する場合と比べて、検査に要する時間をより短縮することができる。 In the present embodiment, as described above, the plurality of element chips 210 are provided on the wafer 220, and the element chip 210 provided at any position on the wafer 220 is stored in the storage unit 50. The chip arrangement information indicating whether or not the pattern has the above-described pattern is stored in advance, and the inspection unit 61 is based on the chip arrangement information stored in the storage unit 50 and the pattern of the element chip 210 for inspection imaged by the imaging unit 40 Is configured to identify the type. Thereby, since the chip arrangement information indicating which pattern the element chip 210 provided at which position on the wafer 220 has is stored in the storage unit 50 in advance, the image of the element chip 210 for inspection that has been imaged is stored. Compared with the case of recognizing which non-defective image P the pattern corresponds to by image recognition (comparison between images) or the like, the time required for the inspection can be further shortened.
　また、本実施形態では、上記のように、ウェハ２２０上には、互いに異なるパターンが各々形成された複数の素子チップ２１０を各々含む素子チップ群２３０が複数設けられており、素子チップ群２３０における、互いに異なるパターンが各々形成された複数の素子チップ２１０の配置位置は、素子チップ群２３０の各々において同じであり、記憶部５０には、複数の素子チップ群２３０を含む複数の素子チップ２１０のチップ配置情報が予め記憶されている。これにより、複数の素子チップ２１０の配置位置が、素子チップ群２３０の各々において同じであるので、同一のマスク（図示せず）を用いて、素子チップ群２３０毎に素子チップ２１０を形成することができる。 In the present embodiment, as described above, a plurality of element chip groups 230 each including a plurality of element chips 210 each having a different pattern formed thereon are provided on the wafer 220. In the element chip group 230, as shown in FIG. The arrangement positions of the plurality of element chips 210 each having a different pattern are the same in each of the element chip groups 230, and the storage unit 50 includes a plurality of element chips 210 including the plurality of element chip groups 230. Chip arrangement information is stored in advance. Thereby, since the arrangement positions of the plurality of element chips 210 are the same in each of the element chip groups 230, the element chip 210 is formed for each element chip group 230 using the same mask (not shown). Can do.
　また、本実施形態では、上記のように、ウェハ２２０と撮像部４０とが相対的に移動している状態で、撮像部４０による検査用の素子チップ２１０の撮像と、検査部６１による、撮像された検査用の素子チップ２１０のパターンの種類の識別と、良品画像Ｐを、識別された検査用の素子チップ２１０のパターンに対応するパターンを有する良品画像Ｐに切り替えることと、検査用の素子チップ２１０の画像と良品画像Ｐとを比較することにより素子チップ２１０が良品か否かの判別を行うこととが、順次、ウェハ２２０上に設けられた複数の検査用の素子チップ２１０毎に行われるように構成されている。これにより、互いに異なるパターンを有する複数の素子チップ２１０が混在した状態において、複数の素子チップ２１０の検査を連続してスムーズに行うことができる。 In the present embodiment, as described above, in the state where the wafer 220 and the imaging unit 40 are relatively moved, the imaging of the element chip 210 for inspection by the imaging unit 40 and the imaging by the inspection unit 61 are performed. Identifying the pattern type of the identified inspection element chip 210, switching the non-defective image P to the non-defective image P having a pattern corresponding to the identified pattern of the inspection element chip 210, and an inspection element The comparison of the image of the chip 210 and the non-defective image P to determine whether the element chip 210 is non-defective is sequentially performed for each of the plurality of inspection element chips 210 provided on the wafer 220. It is configured to be Thereby, in a state where a plurality of element chips 210 having different patterns are mixed, the plurality of element chips 210 can be inspected continuously and smoothly.
　［変形例］
　なお、今回開示された実施形態および実施例は、すべての点で例示であって制限的なものではないと考えられるべきである。本発明の範囲は、上記した実施形態および実施例の説明ではなく特許請求の範囲によって示され、さらに特許請求の範囲と均等の意味および範囲内でのすべての変更（変形例）が含まれる。 [Modification]
The embodiments and examples disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description of the embodiments and examples but by the scope of claims for patent, and includes all modifications (modifications) within the meaning and scope equivalent to the scope of claims for patent.
　たとえば、上記実施形態では、検査部６１が制御部６０に含まれる例を示したが、本発明はこれに限られない。たとえば、検査部６１が制御部６０とは別個に設けられていてもよい。 For example, in the above-described embodiment, an example in which the inspection unit 61 is included in the control unit 60 is shown, but the present invention is not limited to this. For example, the inspection unit 61 may be provided separately from the control unit 60.
　また、上記実施形態では、互いに異なる４個のパターンの素子チップ２１０が混在している例を示したが、本発明はこれに限られない。たとえば、素子チップ２１０のパターンの数は、４個以外の数でもよい。 In the above embodiment, the example in which the element chips 210 having four different patterns are mixed is shown, but the present invention is not limited to this. For example, the number of patterns of the element chip 210 may be a number other than four.
　また、上記実施形態では、記憶部５０に、ウェハ２２０上のいずれの位置に設けられた素子チップ２１０がいずれのパターンを有するかのチップ配置情報が予め記憶されている例を示したが、本発明はこれに限られない。たとえば、素子チップ２１０を撮像する毎に、撮像された検査用の素子チップ２１０の画像と、複数の良品画像Ｐとを比較して、撮像された検査用の素子チップ２１０のパターンが、複数の良品画像Ｐのうちのいずれのパターンに一致するかを識別してもよい。 In the above embodiment, an example is shown in which chip arrangement information indicating which pattern the element chip 210 provided at which position on the wafer 220 has is stored in the storage unit 50 in advance. The invention is not limited to this. For example, each time the element chip 210 is imaged, the image of the imaged element chip 210 for inspection is compared with a plurality of non-defective images P. It may be identified which pattern of the non-defective product image P matches.
　また、上記実施形態では、素子チップ群２３０における、互いに異なるパターンが各々形成された複数の素子チップ２１０の配置位置が、素子チップ群２３０の各々において同じである例を示したが、本発明はこれに限られない。たとえば、素子チップ群２３０における、互いに異なるパターンが各々形成された複数の素子チップ２１０の配置位置が、素子チップ群２３０毎に異なっていてもよい。 In the above-described embodiment, an example in which the arrangement positions of the plurality of element chips 210 formed with different patterns in the element chip group 230 are the same in each of the element chip groups 230 has been described. It is not limited to this. For example, in the element chip group 230, the arrangement positions of the plurality of element chips 210 each having a different pattern may be different for each element chip group 230.
　また、上記実施形態では、ウェハ２２０上に設けられた素子チップ２１０を検査する例を示したが、本発明はこれに限られない。たとえば、ウェハ２２０上に設けられていない素子チップ２１０を検査してもよい。 In the above embodiment, the example in which the element chip 210 provided on the wafer 220 is inspected has been shown, but the present invention is not limited to this. For example, an element chip 210 that is not provided on the wafer 220 may be inspected.
　４０　撮像部
　５０　記憶部
　６１　検査部
　１００　外観検査装置
　２１０、２１０ａ～２１０ｄ　素子チップ
　２２０　ウェハ（基板）
　２３０　素子チップ群
　Ｐ、Ｐ１～Ｐ４　良品画像 40 Image pickup unit 50 Storage unit 61 Inspection unit 100 Appearance inspection device 210, 210a to 210d Element chip 220 Wafer (substrate)
230 Element chip group P, P1 to P4

Claims (4)

  1. 　互いに異なるパターンを有する複数の素子チップが混在した状態で、複数の前記素子チップを各々検査する外観検査装置において、
    　検査対象の前記素子チップを撮像する撮像部と、
    　互いに異なるパターンの前記素子チップの検査基準となる良品画像が予め記憶された記憶部と、
    　前記撮像部によって撮像された検査対象の前記素子チップのパターンの種類を識別するとともに、前記撮像部によって撮像された検査対象の前記素子チップの画像と、識別された検査対象の前記素子チップのパターンに対応する前記良品画像とを比較することにより、検査対象の前記素子チップが良品か否かの判別を行う検査部とを備える、外観検査装置。     In the appearance inspection apparatus for inspecting each of the plurality of element chips in a state where a plurality of element chips having different patterns are mixed,
    An imaging unit for imaging the element chip to be inspected;
    A storage unit in which a non-defective image serving as an inspection reference for the element chips having different patterns is stored in advance
    The pattern of the element chip to be inspected imaged by the imaging unit is identified, the image of the element chip to be inspected imaged by the imaging unit, and the pattern of the identified element chip to be inspected And an inspection unit that determines whether or not the element chip to be inspected is a non-defective product by comparing the non-defective image corresponding to the above.
  2. 　複数の前記素子チップは、基板上に設けられており、
    　前記記憶部には、前記基板上のいずれの位置に設けられた前記素子チップがいずれのパターンを有するかのチップ配置情報が予め記憶されており、
    　前記検査部は、前記記憶部に記憶された前記チップ配置情報に基づいて、前記撮像部によって撮像された検査用の前記素子チップのパターンの種類を識別するように構成されている、請求項１に記載の外観検査装置。     The plurality of element chips are provided on a substrate,
    In the storage unit, chip arrangement information as to which pattern the element chip provided at which position on the substrate has is stored in advance.
    The inspection unit is configured to identify the type of pattern of the element chip for inspection imaged by the imaging unit, based on the chip arrangement information stored in the storage unit. 2. An appearance inspection apparatus according to 1.
  3. 　前記基板上には、互いに異なるパターンが各々形成された複数の前記素子チップを各々含む素子チップ群が複数設けられており、
    　前記素子チップ群における、互いに異なるパターンが各々形成された複数の前記素子チップの配置位置は、前記素子チップ群の各々において同じであり、
    　前記記憶部には、複数の前記素子チップ群を含む複数の前記素子チップの前記チップ配置情報が予め記憶されている、請求項２に記載の外観検査装置。     On the substrate, there are provided a plurality of element chip groups each including a plurality of the element chips each formed with a different pattern.
    In the element chip group, the arrangement positions of the plurality of element chips each formed with a different pattern are the same in each of the element chip groups,
    The appearance inspection apparatus according to claim 2, wherein the storage unit stores in advance the chip arrangement information of the plurality of element chips including the plurality of element chip groups.
  4. 　前記基板と前記撮像部とが相対的に移動している状態で、前記撮像部による検査用の前記素子チップの撮像と、前記検査部による、撮像された検査用の前記素子チップのパターンの種類の識別と、前記良品画像を、識別された検査用の前記素子チップのパターンに対応するパターンを有する前記良品画像に切り替えることと、検査用の前記素子チップの画像と前記良品画像とを比較することにより前記素子チップが良品か否かの判別を行うこととが、順次、前記基板上に設けられた複数の検査用の前記素子チップ毎に行われるように構成されている、請求項２または３に記載の外観検査装置。 In the state where the substrate and the imaging unit are relatively moved, the imaging of the element chip for inspection by the imaging unit, and the type of pattern of the element chip for inspection taken by the inspection unit And switching the non-defective image to the non-defective image having a pattern corresponding to the identified pattern of the element chip for inspection, and comparing the image of the element chip for inspection with the non-defective image The determination as to whether or not the element chip is a non-defective product is sequentially performed for each of the plurality of element chips for inspection provided on the substrate. 3. An appearance inspection apparatus according to 3.
PCT/JP2017/041061 2017-02-10 2017-11-15 External-appearance examination device WO2018146887A1 (en)

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