JPH05187842A - Method and device for inspecting picture pattern - Google Patents

Abstract

PURPOSE:To efficiently inspect the wiring patterns of a printed wiring board having the wiring patterns on its both surfaces or of a plurality of kinds of printed wiring boards CONSTITUTION:Two kinds of reference picture patterns which are to be compared with the wiring patterns on both main surfaces of a printed wiring board 2 are stored in advance in two semiconductor memories SM1 and SM2 from which the wiring patterns can be read out at high speeds. When the wiring patterns are inspected for defects, one appropriate reference pattern is selectively read out from the memories SM1 and SM2. During the defect inspection, the number of defects is counted and, when the number exceeds a prescribed reference value, the defect detection is stopped and the defect detection is restarted after reading out the other reference pattern from the memories. Therefore, the defect inspection can be performed efficiently even when the picture pattern to be inspected does not match one of the reference picture patterns.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used, for example, for inspecting a wiring pattern of a printed wiring board having wiring patterns on both main surfaces (front surface and back surface) or a wiring pattern of plural kinds of printed wiring boards. The present invention relates to a pattern inspection method and apparatus.

[0002]

[Prior Art]

<General Prior Art of Image Pattern Inspection> The comparison method (pattern matching method) and the feature extraction method (design rule check method) are mainstream as the image pattern inspection method used for the defect inspection of the wiring pattern of the printed wiring board. Is. Of these, the former comparison method compares the image pattern of the object to be the reference (reference image pattern) with the image pattern of the object to be inspected (inspection image pattern),
This is a method of determining a difference portion as a defect (for example, Japanese Patent Publication No. 59-2069 and Japanese Patent Laid-Open Publication No. 60-61604). On the other hand, in the latter feature extraction method, various features included in the reference image pattern (for example, line width, angle, specific pattern, etc.) are stored in advance and do not belong to any of the above various features in the inspection image pattern. In this method, when a pattern is detected, that portion is determined to be a defect (for example, Japanese Patent Laid-Open No. 57-149905). <1 of typical example of prior art based on comparison method> FIG.
It is a schematic block diagram of the conventional image pattern inspection apparatus which inspects the wiring pattern of the printed wiring board by the comparison method. The transport table 1 is provided with a mechanism (not shown) that moves horizontally, on which a printed wiring board 2 having a wiring pattern to be a reference or a wiring pattern to be inspected is placed. The reading device 3 provided above the transport table 1 optically reads the wiring pattern of the placed printed wiring board 2 for each pixel. The reading device 3 is composed of an illuminating device such as an LED and a light receiving device such as a CCD, and a technique corresponding to this is disclosed in, for example, Japanese Patent Application No. 2-142889 of the present applicant. The reading device 3 outputs the wiring pattern as an analog electric signal to the A / D conversion device 4.

The A / D converter 4 converts the analog electric signal from the reading device 3 into a digital electric signal and outputs it to the binarization processing section 5. The binarization processing unit 5 binarizes the digital signal using a predetermined threshold value and generates binarized pattern data. As a result, for example, the pixel in the area where the wiring pattern exists takes the value "1", and the pixel in the area where it does not exist is "1".
Take 0 ".

The selector SL1 outputs the binary signal from the binarization processing unit 5.
The digitized pattern data is sent to the selector SL2 and the difference detection device 7.
To be selected and output. Selector S
L2 is the semiconductor memory 6, the difference detection device 7, the selector S
Either L1 or the external storage device 8 is selectively selected and connected. The operation unit 9 includes a keyboard (not shown), and the selectors SL1 and SL2 operate by manually operating the keyboard.

The semiconductor memory 6 is provided to store binary pattern data (master data MS) of a wiring pattern to be a reference. As the printed wiring board 2 to be mounted on the carrying table 1, one having a wiring pattern to be used as a reference without any defect is selected, and the selector SL1 is set to the selector SL.
2 is connected to the selector SL2 and the selector SL2 is connected to the selector SL1, the master data MS is output to the semiconductor memory 6 and the semiconductor memory 6 stores it.
The semiconductor memory 6 uses a semiconductor storage element as a storage medium and is capable of high speed writing and reading.
It has a storage capacity large enough to store the master data MS corresponding to the wiring pattern on one surface of one printed wiring board 2. Since the semiconductor memory 6 can be written at high speed, the master of the semiconductor memory 6 can be read at the same speed according to the speed at which the wiring pattern of the printed wiring board 2 to be used as a reference is read by the reading device 3 for each pixel. Data M
The writing process of S proceeds.

The external storage device 8 is provided for storing the created master data MS. When it is necessary to change the master data MS used for the inspection to another master data MS such as when inspecting a plurality of types of printed wiring boards 2, the master data MS already stored in the semiconductor memory 6 is externally stored. It is saved by outputting it to the device 8 and storing it. At this time, the selector SL2 selects and connects the external storage device 8. The external storage device 8 is a device having a large capacity writable non-volatile storage medium such as a magnetic tape. The external storage device 8 normally stores a plurality of types of master data MS corresponding to a plurality of types of wiring patterns, and when an inspection is performed, a specific master data MS required for the inspection is selected from among them. The data is output to the semiconductor memory 6 and the contents stored in the semiconductor memory 6 are rewritten with new master data MS.
Also at this time, the selector SL2 selects and connects the external storage device 8. The above operation of the external storage device 8 is performed based on the operation of the operation unit 9.

In order to carry out the inspection, the printed wiring board 2 having the wiring pattern to be inspected is placed on the carrying table 1,
The selector SL1 is connected to the difference detection device 7 side. The selector SL2 is connected to the difference detection device 7 side. At this time, the binarization processing unit 5 outputs the wiring pattern 2 to be inspected.
The digitized pattern data (object data OS) is output to the input 1 of the difference detection device 7. The master data MS read from the semiconductor memory 6 is output to the other input 1 of the difference detection device 7. The difference detection device 7 receives the input object data OS and master data MS.
And an exclusive OR between the pixels at the same position, and the difference data DIS as the calculation result is output to the determination circuit 10. As a result, the difference data DIS takes "1" in the pixel corresponding to the non-coincidence portion between the object data OS and the master data MS, and "0" in the pixel corresponding to the coincidence portion. Since the semiconductor memory 6 capable of reading at high speed is prepared and the master data MS to be the reference is stored in the semiconductor memory 6, the wiring pattern of the printed wiring board 2 to be inspected is read by the reading device 3 for each pixel. The process of creating the difference data DIS in the difference detection device 7 proceeds at the same speed according to the reading speed.

The determination circuit 10 is a pixel operator (for example, 3 pixels) which is a group of adjacent pixels each having a predetermined area.
The presence / absence of a defect and its position are determined using an operator having a width of x3 pixels. That is, in the difference data DIS, if there is a portion that can include the pixel operator in the pixel area having “1”, it is determined as a defective portion,
The defect determination is output together with the position. Normally, the difference data DIS is divided into sections (evaluation sections) having a predetermined size (for example, a size of 20 × 20 pixels), and the result of determining whether or not a defect exists in each evaluation section is described below. It outputs to the display device 11 together with the position of the evaluation section. Display device 1
1 has a display (not shown), and displays the position of the evaluation section determined to have a defect on the display. <Typical example 2 of prior art based on the comparison method> FIG.
FIG. 11 is a schematic block diagram of another example of a conventional image pattern inspection device that inspects a wiring pattern of a printed wiring board by a comparison method. In this example, instead of obtaining the master data MS by preparing the printed wiring board 2 and reading the wiring pattern, a drawing system by a computer (CAD12) for the purpose of designing the wiring pattern.
This is different from the above example in that the master data MS is obtained based on the image pattern created by using. The image pattern created by the CAD 12 is binarized, and the correction circuit 13
Is input to.

Since the wiring pattern of the printed wiring board 2 is etched in the manufacturing process, it necessarily has some differences from the wiring patterns designed by the CAD 12 which should not be regarded as defects. ing. The correction circuit 13 uses the CAD circuit to prevent the determination circuit 10 from erroneously determining the difference as a defect.
The binarized image pattern sent from 12 is output after being subjected to predetermined correction. The correction circuit 13 is disclosed in, for example, Japanese Patent Laid-Open Nos. 60-60504 and 60-113102. The output from the correction circuit 13 is input to the external storage device 8 as master data MS, and the external storage device 8 stores this. At this time, the selector SL3 is connected to the correction circuit 13 side.

The external storage device 8 normally stores a plurality of types of master data MS corresponding to a plurality of types of wiring patterns, as in the case of the representative example 1 of FIG. The specific master data MS necessary for this purpose is selected and output to the semiconductor memory 6, and the content stored in the semiconductor memory 6 is rewritten with new master data MS. At this time, the selector SL3 is the selector S.
The selector SL4 is connected to the L4 side and the selector SL3
Connected to the side of. The selectors SL3 and SL4 are the operation unit 9
It operates by the operation of. The subsequent operation is the same as that of the representative example 1. When performing the inspection, the selector SL4 is connected to the difference detection device 7 side.

[0011]

[Problems to be Solved by the Invention]

<Problems of Prior Art> Since the conventional image pattern inspection device for inspecting the wiring pattern of the printed wiring board 2 by the comparison method is configured as described above, it has the following problems. Was there. (1) In the sampling inspection performed in the manufacturing line, the sample to be inspected needs to be returned to the original position in the manufacturing line after the inspection. Also, since the production line is constantly flowing, the sampling inspection should be performed as quickly as possible. When the extraction inspection of the printed wiring board 2 having the wiring patterns on both main surfaces is performed in the manufacturing line, the extracted printed wiring board 2 needs to be returned to the original position of the line after the inspection. It is necessary to successively perform the inspection of the wiring pattern on one main surface and the inspection of the wiring pattern on the other main surface for every two. For this,
The external storage device 8 stores the master data MS for both sides in advance, but the semiconductor memory 6 stores only the master data MS corresponding to the wiring pattern on one main surface. Therefore, after the inspection of the wiring pattern of one main surface is completed and before the inspection of the wiring pattern of the other main surface is executed, the master data MS stored in the semiconductor memory 6 is transferred to the wiring of the other main surface. It is necessary to replace with the master data MS corresponding to the pattern. In order to write new master data MS to the semiconductor memory 6, it is necessary to read the corresponding master data MS from the external storage device 8. The read speed of the external storage device 8 is much slower than the read speed of the semiconductor memory 6, and if it is the master data MS regarding the wiring pattern of the printed wiring board 2 having a typical size, it takes about 5 minutes to read it. Requires. Therefore, it takes about 5 minutes to rewrite the master data MS each time one board is inspected, and the efficiency of the inspection is low. (2) When a plurality of types of printed wiring boards 2 are mixedly flowing in the manufacturing line and a wiring pattern sampling inspection is performed, a plurality of types of master data MS corresponding to a plurality of types of wiring patterns are generated. is necessary. Therefore, the plurality of types of master data MS are stored in the external storage device 8 in advance. Every time the inspection is performed, the master data MS to be compared with the inspection target needs to be selected from the external storage device 8, read out, and written in the semiconductor memory 6. Therefore, for the same reason as (1) above,
There is a problem in that the efficiency of the inspection is poor because it typically requires an excessive time of about 5 minutes for each inspection. <Objects of the Invention> The present invention has been made to solve the above problems, and it is an inspection of a wiring pattern of a printed wiring board having wiring patterns on both main surfaces, or a plurality of types of printed wiring boards. An object of the present invention is to provide an image pattern inspection technique capable of efficiently inspecting a wiring pattern and the like.

[0012]

[Means for Solving the Problems] Claim 1 according to the present invention
The image pattern inspection method described in (1) is an image pattern inspection method for detecting defects by comparing an inspection target image pattern with a reference image pattern, and (a) preparing a plurality of storage means; b) storing each one of the plurality of reference image patterns in each one of the storage means in advance as a storage signal; and (c) selecting one from the plurality of storage means and reading the storage signal. Due to
A step of obtaining the reference image pattern; (d) a step of obtaining the inspection target image pattern; and (e) a step of comparing the inspection target image pattern with the reference image pattern to detect the defect. Be prepared.

An image pattern inspection method according to a second aspect of the present invention is the image pattern inspection method according to the first aspect, in which (f) the reference value is set at least before the step (e). Further comprising: (e-1) comparing the inspection target image pattern with the reference image pattern to detect the defect; and (e-2) the process. In (e-1), the step of counting the number of defects, and (e-3) the step (e-
In 2), if the number of the counted defects exceeds the reference value and is detected, then at the step (e-).
A step of interrupting 1), and (e-4) the step (e-3)
When the step (e-1) is interrupted in step 1, the storage means 1 which has not been selected after the step (c) is selected from the plurality of storage means and the stored data is read. The step of obtaining another reference image pattern and the step (e-5) of repeating the steps (e-1) to (e-4) are replaced.

An image pattern inspection apparatus according to a third aspect of the present invention is an image pattern inspection apparatus for detecting a defect by comparing an inspection target image pattern with a reference image pattern. Storage means, (b) means for storing each one of the plurality of reference image patterns in each one of the storage means in advance as a storage signal, and (c) selecting one from the plurality of storage means. Means for obtaining the reference image pattern by reading the stored signal; and (d) means for obtaining the inspection target image pattern,
(E) means for comparing the inspection target image pattern with the reference image pattern to detect the defect.

An image pattern inspection apparatus according to a fourth aspect of the present invention is the image pattern inspection apparatus according to the third aspect, further comprising (f) means for setting a reference value,
(G) means for counting the number of defects detected by the means (e), (h) number of the defects counted by the means (g), and the reference value set by the means (f) And a means for outputting the result as a signal.

An image pattern inspection apparatus according to a fifth aspect of the present invention is the image pattern inspection apparatus according to the fourth aspect, which corresponds to (i) the number of defects exceeds the reference value. When the means (h) outputs a signal, the means (c) operates the means (c) to select a new 1 from the plurality of storage means and obtain a new reference image pattern. And means for causing it to be provided.

An image pattern inspection apparatus according to a sixth aspect of the present invention is the image pattern inspection apparatus according to the fifth aspect, which corresponds to (j) the number of defects exceeds the reference value. It further comprises means for interrupting the operation of the means (e) when the signal is output by the means (h) and controlling the operation to be performed from the beginning.

[0018]

In the image pattern inspection method and apparatus according to the present invention, a plurality of storage means, for example, a semiconductor memory capable of high-speed reading are prepared, and a plurality of reference image patterns to be compared with a plurality of types of inspection target image patterns. Each 1
Is stored in advance in each of the plurality of storage means as a storage signal, and the reference pattern to be compared with the image pattern to be inspected is read out by selecting 1 from the plurality of storage means to detect a defect. Therefore, the inspection of the wiring patterns of the printed wiring board having the wiring patterns on both main surfaces, the inspection of the wiring patterns of a plurality of types of printed wiring boards, and the like can be efficiently performed.
6).

When the inspection target image pattern is compared with the reference image pattern to detect the defect, when the number of defects is counted and the number of defects exceeds a predetermined reference value, The defect detection is interrupted, another 1 is selected from the plurality of storage means to read a new reference pattern, and the defect detection is performed again. Therefore, the type of the reference image pattern and the image pattern to be inspected are determined. Even when the type does not correspond by mistake, the error can be detected in a short time and the defect can be detected again (claims 2, 4 to 6).

In particular, the number of defects is automatically detected and the number of defects is automatically detected, and when the number of defects exceeds a predetermined reference value, the number of defects is automatically increased from other storage means. Since 1 is selected and a new reference pattern is read out,
Even when the type of the reference image pattern and the type of the image pattern to be inspected do not correspond by mistake, the defect can be detected more efficiently (claims 5 and 6).

Further, the detection of defects and the counting of the number of defects are automatically performed, and when the number of defects exceeds a predetermined reference value and becomes large, other defects are automatically selected from a plurality of storage means. Since 1 is selected to read a new reference pattern and the defect detection is automatically restarted from the beginning, the defect detection can be executed more efficiently (claim 6).

In the present invention, the plurality of storage means is a concept including a plurality of storage areas of the storage means.

[0023]

【Example】

[Embodiment 1] FIG. 1 is a flow chart showing an outline procedure of an image pattern inspection method for inspecting a wiring pattern of a printed wiring board having wiring patterns on both front and back main surfaces according to an embodiment of the present invention. .. The wiring patterns on both main surfaces are generally different types of wiring patterns. Figure 2
2 is a schematic block diagram of an image pattern inspection apparatus for implementing the method shown in the flowchart of FIG. 1, which is also an embodiment of the present invention.

The image pattern inspection apparatus includes two semiconductor memories SM1 and SM2 as a plurality of storage means, and the selector SL5 selects one of these semiconductor memories SM1 and SM2 for writing or reading. It is configured such that any one of them can be selectively selected. Selector SL5 is connected to selector SL2. The semiconductor memories SM1 and SM2 use a semiconductor storage element as a storage medium and can perform writing and reading at high speed. Each 1 is a master data MS corresponding to a wiring pattern on one side of one printed wiring board 2. Has a storage capacity large enough to store Similarly to the external storage device 8, the selectors SL1 and SL2, the selector SL5 also operates by manually operating a keyboard (not shown) included in the operation unit 9.

The two semiconductor memories SM1 and SM2 may each be two storage areas of the semiconductor memory. <Step of creating and storing reference pattern: steps S1 to S
4> In order to inspect the image pattern, first, step S1
The semiconductor memory SM1 is selected with. That is, the operation unit 9
The selector SL5 is connected to the semiconductor memory SM1 side by operating.

Next, in step S2, the semiconductor memory S
The master data MS regarding the wiring pattern to be the reference of the first main surface of the printed wiring board 2 is stored in M1. That is, the printed wiring board 2 having a wiring pattern to be used as a reference having no defect on the first main surface is selected and placed on the transport table 1 so that the first main surface is read by the reading device 3.
By connecting the selector SL1 to the selector SL2 side and the selector SL2 to the selector SL1 side,
The master data MS is output to the semiconductor memory SM1,
The semiconductor memory SM1 stores this. Semiconductor memory S
Since high-speed writing into M1 is possible, the master data MS to the semiconductor memory SM1 is read at the same speed in accordance with the reading speed of the wiring pattern of the printed wiring board 2 to be the reference for each pixel by the reading device 3. Writing process proceeds.

Next, in step S3, the semiconductor memory S
Select M2. That is, by operating the operation unit 9, the selector SL5 is connected to the semiconductor memory SM2 side.

In step S4, master data MS relating to a wiring pattern to be used as a reference for the second main surface of the printed wiring board 2 (a main surface having a front and back relationship with the first main surface) is stored in the semiconductor memory SM2. .. That is, the printed wiring board 2 having a wiring pattern to be a reference having no defect on the second main surface is selected and placed on the transport table 1 so that the second main surface is read by the reading device 3. The selector SL1 is connected to the selector SL2 side, and the selector SL2 is connected to the selector S.
By connecting to the L1 side, the master data MS is output to the semiconductor memory SM2, and the semiconductor memory SM2 stores it. Similar to the case of the semiconductor memory SM1,
The writing process of the master data MS to the semiconductor memory SM2 proceeds at the same speed according to the speed at which the reading device 3 reads the wiring pattern of the printed wiring board 2 to be the reference for each pixel. <Inspection process: steps S5 to S10> Next step S
In 5, a printed wiring board 2 having a wiring pattern to be inspected is prepared. For example, in the sampling inspection, the printed wiring board 2 to be inspected is extracted from the manufacturing line.

Next, in step S6, the semiconductor memory S
Select 1 from M1 and SM2. For example, the semiconductor memory SM1 is selected. That is, by operating the operation unit 9, the selector SL5 is connected to the semiconductor memory SM1 side.

In step S7, an inspection is performed on one wiring pattern on the main surface of the printed wiring board 2 prepared in step S5. First, the reading device 3 reads the first main surface, which is the main surface having the wiring pattern that should be based on the master data MS stored in the semiconductor memory 1 (semiconductor memory SM1 in this example) selected in step S4. With this in mind, the printed wiring board 2 is placed on the transport table 1 and the selector SL1 is connected to the difference detection device 7 side. The selector SL2 is connected to the difference detection device 7 side. At this time, the binarization processing unit 5 outputs the object data OS, which is the binarized pattern data of the wiring pattern to be inspected, to the input 1 of the difference detection device 7. The master data MS read from the semiconductor memory SM1 is output to the other input 1 of the difference detection device 7.

FIG. 3 is a block diagram showing the internal structure of the difference detection device 7. The evaluation section setting unit 14a that inputs the object data OS and the evaluation section setting unit 14b that inputs the master data MS set the evaluation section CR in the master data MS and the object data OS, respectively.
The evaluation section CR is obtained by dividing the object data OS or the master data MS into areas of a predetermined size (20 × 20 pixels in this example) as shown in FIG. For each evaluation section CR, the evaluation section setting units 14a and 14b respectively correspond to the evaluation section CR of the object data OS (evaluation object data OD) and the section corresponding to the evaluation section CR of the master data MS (evaluation master data). MD) to the comparison unit 15.

The comparing section 15 calculates the exclusive OR between the input evaluation object data OD and the evaluation master data MD for each pixel at the same position, and determines the difference data DIS which is the calculation result. Output to the circuit 10. As a result, the difference data DIS takes "1" at the pixel corresponding to the non-coincidence portion between the evaluation object data OD and the evaluation master data MD and takes "0" at the pixel corresponding to the coincidence portion. Since the semiconductor memory SM1 capable of high-speed reading is prepared and the master data MS to be the reference is stored in the semiconductor memory SM1, the wiring pattern of the printed wiring board 2 to be inspected is read by the reading device 3 for each pixel. The process of creating the difference data DIS in the difference detection device 7 proceeds at the same speed according to the reading speed.

The decision circuit 10 decides the presence or absence of a defect in the difference data DIS by using the pixel operator OP.
The pixel operator OP is a group of adjacent pixels each having a predetermined area (in this example, an area of 3 × 3 pixels) as shown in FIG. The determination circuit 10 determines the difference data D
In the area D of the pixel having "1" in IS, a portion that matches the pixel operator OP or the pixel operator OP
If there is at least one part that can include, it is determined that there is a defect, and the determination result is output together with the position of the evaluation section CR. As the output signal corresponding to the determination result, for example, the value "1" is output when there is a defect, and the value "0" is output when there is no defect. The output from the determination circuit 10 is the display device body 1
1a, the display device main body 11a is displayed on the display 1
The position of the evaluation section CR determined to have a defect is displayed in 1b.

The output from the determination circuit 10 is the display device 11
At the same time, it is also input to the counter 16. Counter 16
Is a circuit for counting a signal output from the determination circuit 10 corresponding to the determination of a defect, for example, the number of values “1” (the number of defects). The counter 16 outputs a signal corresponding to the counting result, for example, a binary value to the comparator 17. The comparator 17 outputs to the reference value setting unit 1 at the same time as the output of the counter 16.
The output from 8 is also input. In the reference value setting unit 18,
A numerical value is set in advance by manual operation, and a signal corresponding to the set numerical value, for example, a binary value is output to the comparator 17. When the main surface of the printed wiring board 2 opposite to the main surface to be inspected is erroneously placed on the transport table 1 so that the reading device 3 can read it, the determination circuit 10 determines the majority of evaluation sections C.
It is determined that R is defective. The numerical value set by the reference value setting unit 18 is an evaluation section CR that is determined to have a defect, which is appropriate for detecting that the opposite main surface of the printed wiring board 2 which is not the main surface to be inspected is erroneously read. Is set to correspond to a sufficiently large number of.

The comparator 17 compares the magnitudes of the numerical values represented by the two input signals, and the numerical value output from the counter 16 becomes larger than the numerical value output from the reference value setting section 18. Then, a predetermined signal, for example, a numerical value "1" is output. If the printed wiring board 2 is normally placed on the transport table 1 in order to read the wiring pattern on the first main surface, the comparator 17 does not output the value "1" during the inspection, and the inspection is performed normally. To finish. When the inspection is normally completed, the transport table 1 is returned to the position before the start of the inspection (end of step S7).

Subsequently, in step S8, a semiconductor memory SM2 different from the semiconductor memory SM1 selected for inspection in step S7 is selected. That is, by operating the operation unit 9, the selector SL5 is connected to the semiconductor memory SM2 side. Next, in step S9, the printed wiring board 2 is placed on the transport table 1 so that the reading device 3 can read the wiring pattern of the second main surface, which is different from the first main surface that was the object of inspection in step S7. After the placement, the wiring pattern is inspected. In step S9, the inspection is performed in the same procedure as in step S7.

In step S7, if the printed wiring board 2 is placed on the carrier table 1 in order to read the wiring pattern on the second main surface by mistake, the comparator 17 is in the middle of the inspection.
The value "1" is output from. The output from the comparator 17 is input to the controller 19. The controller 19 controls the display 21 at the same time as the operation of the motor 20 and the selector SL5 according to the input signal. Motor 2
0 drives the transport table 1 on which the printed wiring board 2 is placed. When the input signal to the controller 19 becomes "1", the controller 19 drives the motor 20 so as to return the transport table 1 to the position immediately before the start of the inspection, and a light for notifying that it has been erroneously placed, or The display 21 is driven to emit sound and the selector SL5 is set to the semiconductor memory SM2.
Operate to connect to. After that, the semiconductor memory S
Using the master data MS of M2 as reference data to be compared, the printed wiring board 2 erroneously installed on the transport table 1 is left as it is, and the inspection is performed again from the beginning.
That is, the inspection of the wiring pattern on the second main surface of the printed wiring board 2 is performed in the same procedure as described above. The inspection is executed in the same procedure as described above, but in this case, the main surface to be inspected and the master data MS to be the reference correspond to each other without error, and the value from the comparator 17 is detected in the middle of the inspection. 1 "
Is not output and the inspection ends normally (end of step 7). Subsequently, in step S8, a semiconductor memory SM1 different from the semiconductor memory SM2 finally selected for inspection in step S7 is selected.
That is, by operating the operating unit 9, the selector S
L5 is connected to the semiconductor memory SM1 side. Next, in step S9, the printed wiring board 2 is moved so that the reading device 3 can read the wiring pattern of the first main surface, which is different from the second main surface finally inspected in step S7. After mounting on No. 1, the wiring pattern is inspected. In step S9, the inspection is performed in the same procedure as in step S7.

FIG. 6 is an explanatory view of the operation of the carrying table 1 showing how the carrying table 1 is moved by driving the motor 20. Before the inspection of the printed wiring board 2 is started in step S7 or S9, the transport table 1 is at a predetermined preparation position. When the inspection is started in step S7 or S9,
The transport table 1 is transported at a high speed until just before one end of the printed wiring board 2 is positioned directly below the reading device 3, and thereafter at a relatively low speed (inspection speed) required for inspection. The inspection of the wiring pattern of the printed wiring board 2 proceeds while being sent at the inspection speed. When the number of defects input to the comparator 17 becomes larger than the reference value during the inspection process, the transport table 1 is returned to a point where one end of the printed wiring board 2 is located directly below the reading device 3, and the selector SL5 is set. , The semiconductor memory SM1 or SM2 to be connected to each other
It works to switch to. After that, the transport table 1 is sent again at the inspection speed, and the inspection progresses during that time.

When step S9 is completed, the inspection of the wiring patterns on both main surfaces of the printed wiring board 2 is completed. Step S9 is followed by step S10, in which it is determined whether another printed wiring board 2 should be inspected. If another printed wiring board 2 should be inspected, step S10 is performed.
5, a new printed wiring board 2 to be inspected is prepared. If it is determined in step S10 that it is not necessary to inspect another printed wiring board 2, the inspection is ended.

In steps S7 and S9, there is a case where a defect exists on the side of the reference pattern among the defects that are recognized when the inspection is normally completed. At this time, the master data MS stored in the semiconductor memory SM1 or SM2
The part corresponding to the above-mentioned defect in is rewritten and corrected. By operating the keyboard 11c, the semiconductor memory S
The master data MS stored in M1 or SM2 is read out to the display device main body 11a, and the defective portion displayed on the display 11b in the read master data MS is corrected by operating the keyboard 11c one by one. The corrected master data MS is the keyboard 11
By operating c, data is written from the display device main body 11a to the original semiconductor memory SM1 or SM2. By correcting the master data MS every time the inspection is performed, the master data MS approaches the defect-free master data MS as the number of inspections increases.

When the inspection of one type of printed wiring board 2 is completed and the process proceeds to the inspection of another type of printed wiring board 2, the master data MS stored in the semiconductor memories SM1 and SM2 is stored in the external storage device 8. Write and save. At this time, the selector SL2 selects and connects the external storage device 8. In this way, the external storage device 8 generally stores the master data MS of a plurality of types of printed wiring boards 2.
Is stored, and when inspecting the wiring pattern of the printed wiring board 2 to be compared with the master data MS among them, it is not necessary to newly create the master data MS, and the master data MS is read from the external storage device 8. It is only necessary to write to the semiconductor memories SM1 and SM2.
Also at this time, the selector SL2 selects the external storage device 8.

In this embodiment, as described above, each one of the two types of reference image patterns to be compared with the image patterns to be inspected on the front and back main surfaces is stored in advance as a storage signal in each one of the two semiconductor memories. Then, the reference pattern to be compared with the image pattern to be inspected is read out by selecting 1 from the two semiconductor memories to detect defects. Therefore, a printed wiring board having wiring patterns on both front and back main surfaces. The wiring pattern can be efficiently inspected. In particular, even when the reference image pattern and the image pattern to be inspected do not correspond by mistake, the error is automatically detected in a short time and the semiconductor memory to be selected is switched, and the defect is automatically detected again. Therefore, it is possible to more efficiently inspect the wiring pattern of the printed wiring board having the wiring patterns on the front and back main surfaces.

[Embodiment 2] FIG. 7 is a second embodiment for realizing a method for inspecting a wiring pattern of a printed wiring board having wiring patterns on both front and back main surfaces shown in the schematic flow chart of FIG. FIG. 3 is a schematic block diagram of an image pattern inspection device. The device according to this embodiment is CAD1
This is different from the first embodiment in that the master data MS is obtained based on the image pattern created by using No. 2. CAD12
The binarized image pattern created in 1 is input to the correction circuit 13. The correction circuit 13 adds a predetermined correction to the binarized image pattern sent from the CAD 12 and outputs it. The output from the correction circuit 13 is input to the external storage device 8 as master data MS, and the external storage device 8 stores this. At this time, the selector SL3 is connected to the correction circuit 13 side.

The external storage device 8 normally stores a plurality of types of master data MS corresponding to a plurality of types of wiring patterns, like the device according to the first embodiment. When the printed wiring board 2 having wiring patterns on both main surfaces is inspected, two specific types of master data MS required for inspection are selected from a plurality of types of master data MS, and the semiconductor memories are respectively selected. SM1 and semiconductor memory SM2
To the semiconductor memories SM1 and SM2 and rewrite the contents stored in the semiconductor memories SM1 and SM2 with new master data MS (step S
2, S4). At this time, the selector SL3 is connected to the selector SL4 side, and the selector SL4 is connected to the selector SL.
3 side is connected. Prior to outputting and storing the master data MS to the semiconductor memory SM1 (step S2), the selector SL5 is connected to the semiconductor memory SM1 side in advance (step S1).
Prior to outputting and storing the master data MS to 2 (step S4), the selector SL5 is connected to the semiconductor memory SM2 side in advance (step S3). The selectors SL3, SL4, SL5, and the external storage device 8 operate by operating the operation unit 9. The operation after step S5 is similar to that of the representative example 1. In steps after step S5, the selector SL4 is connected to the difference detection device 7 side.

[Third Embodiment] FIG. 8 is a flow chart showing a schematic procedure of an image pattern inspection method according to a third embodiment of the present invention. FIG. 9 is a schematic block diagram of an image pattern inspection apparatus that can implement the method shown in the flowchart of FIG. When a plurality of types of printed wiring boards 2 are mixedly flowing in the manufacturing line and a wiring pattern sampling inspection is performed, a plurality of types of master data MS corresponding to a plurality of types of wiring patterns are required. ..
For example, in the case where two types of printed wiring boards 2 having wiring patterns on both main surfaces are mixedly flowing in a manufacturing line and a wiring pattern sampling inspection is performed, four types of wiring patterns are supported. 4 types of master data MS
is necessary. The method and apparatus according to this embodiment can be used for such a purpose, and the apparatus is provided with four semiconductor memories, and accordingly the selector SL5 has four semiconductor memories SM1, SM2, SM3.
And SM4.

The process of creating the four types of master data MS corresponding to the four types of wiring patterns to be the reference and storing them in the semiconductor memory is performed in the same manner as in the first embodiment. That is, each time the reading device 3 sequentially reads the four types of wiring patterns to be the reference, the selector SL5 is sequentially switched from the semiconductor memory SM1 to the semiconductor memory SM4 (steps S11, S13, S15, and S17), and the semiconductor memory SM1. To the semiconductor memory SM4 are sequentially stored in the master data MS (steps S12 and S1).
4, S16, and S18).

Next, in step S19, a printed wiring board 2 having a wiring pattern to be inspected is prepared. That is, in the sampling inspection, the printed wiring board 2 to be inspected
Is removed from the production line. Then step S2
At 0, 1 (semiconductor memory according to the first selection) of the semiconductor memory that stores the master data MS corresponding to the wiring pattern to be inspected is selected from the four semiconductor memories SM1 to SM4. That is, by operating the operation unit 9, the selector SL5 is connected to 1 of the four semiconductor memories.

In step S21, an inspection is performed on one wiring pattern on the main surface of the printed wiring board 2 prepared in step S19. Step S21 is executed in the same manner as step S7 in the above embodiment. When the wiring pattern to be inspected and the master data MS stored in the semiconductor memory according to the first selection do not correspond to each other, the value "1" is output from the comparator 17 in the middle of this process, and the value is output to the controller 19. Is entered. Similar to step S7, when the input signal to the controller 19 becomes "1", the controller 19 drives the motor 20 to return the transport table 1 to the position immediately before the start of the inspection, and the controller 19 is in error. The display 21 is driven so as to emit light or sound for notifying. At the same time, the controller 19 operates to connect the selector SL5 to 1 (semiconductor memory according to the second selection) other than the semiconductor memory according to the first selection. After that, the master data MS stored in the semiconductor memory according to the second selection is used as reference data to be compared, and the printed wiring board 2 installed on the transport table 1 is left as it is, and the inspection is performed again from the beginning.

The master data MS stored in the semiconductor memory according to the second selection may not yet correspond to the wiring pattern to be inspected. In that case, the value "1" is again output from the comparator 17 and input to the controller 19 in the middle of the inspection. The controller 19 uses the motor 2
0, the display 21 is driven in the same manner as described above, and the selector SL5 is operated to select the third semiconductor memory different from both the first and the second. After that, the inspection is performed again from the beginning by using the master data MS stored in the semiconductor memory according to the third selection as reference data to be compared.

When the master data MS stored in the semiconductor memory according to the third selection does not correspond to the wiring pattern to be inspected yet, the comparator 1 is again in the middle of the inspection.
The value “1” is output from 7 and input to the controller 19. The controller 19 drives the motor 20 and the display 21 in the same manner as above, and operates the selector SL5 to select the fourth semiconductor memory different from any of the first, second and third semiconductor memories. Then, the inspection is performed again from the beginning by using the master data MS stored in the semiconductor memory according to the fourth selection as reference data to be compared. In this case, the main surface to be inspected and the master data MS to be the reference correspond to each other without any error, and the value "1" is not output from the comparator 17 in the middle of the inspection. Is ended (end of step 21).

The order of selection from the semiconductor memory according to the first selection to the semiconductor memory according to the fourth selection is an appropriate order in advance, for example, semiconductor memories SM1, SM2, S.
It is advisable to determine the order of M3, SM4, SM1 ... In this case, for example, if the semiconductor memory selected by the first selection is SM3, the semiconductor memory selected second is the semiconductor memory SM4, the semiconductor memory selected third is the semiconductor memory SM1, and so on. ..

Subsequently, in step S22, the master data MS to be compared with the wiring pattern of the main surface opposite to the main surface having the wiring pattern inspected in step S21.
1 of the semiconductor memory for storing is selected. That is, by operating the operation unit 9, the selector SL5 is connected to the newly selected semiconductor memory.

Next, in step S23, the printed wiring board 2 is used so that the reading device 3 can read the wiring pattern of the main surface different from the main surface to be inspected in step S21.
After the wafer is placed on the transport table 1, the wiring pattern is inspected. In step S23, the inspection is performed in the same procedure as in step S21.

In step S24, as in step S10, it is determined whether another printed wiring board 2 should be inspected. If another printed wiring board 2 should be inspected, the process proceeds to step S19 and a new inspection is performed. The printed wiring board 2 to be prepared is prepared. If it is determined in step S24 that it is not necessary to inspect another printed wiring board 2, the inspection is ended.

In this embodiment, as described above, each one of the two types of reference image patterns to be compared with the image patterns to be inspected on the front and back main surfaces of the two types of printed wiring boards 2 is stored in four semiconductor memories. Since a reference pattern to be stored in each 1 as a storage signal in advance and a reference pattern to be compared with the inspection target image pattern is selected by selecting 1 from the four semiconductor memories to detect a defect, a defect is detected on both main surfaces. The wiring patterns of the two types of printed wiring boards 2 having the wiring patterns can be efficiently inspected. In particular, even when the reference image pattern and the image pattern to be inspected do not correspond by mistake, the error is automatically detected in a short time and the semiconductor memory to be selected is switched, and the defect is automatically detected again. Therefore, the wiring pattern can be inspected more efficiently.

In general, a plurality of types of wiring patterns to be inspected on a plurality of types of printed wiring boards 2 can be inspected in the same manner as this embodiment. At this time, as many semiconductor memories as the number of types of wiring patterns to be inspected may be prepared. The selector SL5 may have a structure capable of being selectively connected to any of these semiconductor memories. The printed wiring board 2 may include the printed wiring board 2 having a wiring pattern on only one surface. [Fourth Embodiment] FIG. 10 is a schematic block diagram of an image pattern inspection apparatus according to a fourth embodiment of the present invention. This device is provided with a master data inspection device 22 in addition to the configuration shown in the schematic block diagram of FIG. Load the wiring pattern that should be the reference,
In the process of storing the master data MS in the semiconductor memory SM1 or SM2, the master data inspection device main body 22a connected to the selector SL5 inspects the master data MS by the feature extraction method. For example, if there is a defective portion of the wiring pattern that is narrower than the permissible range for the width of the wiring pattern, the master data inspection device body 22a displays the presence of the defect on the display 22b together with the position of the defect (for example, coordinate value). The master data MS stored in the semiconductor memory SM1 or SM2 is operated by operating the keyboard 22c after writing the master data MS into the semiconductor memory SM1 or SM2.
Is read out to the master data inspecting apparatus main body 22a, and the defective portion displayed on the display 22b in the read master data MS is corrected one by one by operating the keyboard 22c. Modified master data MS
Operating the keyboard 22c causes the master data inspection device main body 22a to move to the original semiconductor memory SM.
1 or SM2. When the master data MS is read from the semiconductor memory SM1 or SM2 to the master data inspection device main body 22a, and when the corrected master data MS is written from the master data inspection device main body 22a to the semiconductor memory SM1 or SM2, the master data inspection device main body 22a. Operates the selector SL5 to select the semiconductor memory SM1 or SM2. The display 22b is the display 11b.
The keyboard 22c may also serve as the keyboard 11c.

As described above, in this embodiment, the master data MS stored in the semiconductor memories SM1 and SM2 is
The printed wiring board 2 having a wiring pattern that is incomplete as a reference is selected for the creation of the master data MS, because it is inspected by the feature extraction method and the defective portion is corrected in advance based on the inspection. Even in such a case, the inspection of the defect of the wiring pattern to be inspected can be executed without error.

[Embodiment 5] In each of the above embodiments, the technique disclosed in Japanese Patent Application Laid-Open No. 62-140009 by the present applicant can be used for the technique of the difference detection device 7 and the determination circuit 10. .. That is, instead of the difference detection device 7 and the determination circuit 10, the comparison inspection unit 23 having the internal structure shown in the block diagram of FIG. 11 can be used.

The evaluation section setting unit 24 has the same structure as that of the evaluation section setting unit 14a described above.
The part corresponding to the evaluation section CR, that is, the evaluation object data OD is output to the comparison unit 25. The correction section setting unit 26 includes master data corresponding to a plurality of areas (correction sections HRi) obtained by displacing the evaluation section CR in the area (extended section SR) in which the evaluation section CR is expanded by a certain number of pixels. MS part (correction evaluation master data MD
i) is output to the comparison unit 25. Here, the symbol i is an index for identifying each one of the plurality of correction sections corresponding to one expansion section SR. Each 1 of the plurality of comparison units 25 has the same structure as the comparison unit 15 described above, and is exclusive for each pixel in the same position between the input evaluation object data OD and the corrected evaluation master data MDi. The logical OR is calculated, and the difference data DISi as the calculation result is determined by the determination circuit 27.
Output to. As a result, the difference data DISi becomes the evaluation object data OD and the correction evaluation master data MDi.
"1" is taken in the pixel corresponding to the non-coincidence portion, and "0" is taken in the pixel corresponding to the coincidence portion.

Each 1 of the judgment circuit 27 is the judgment circuit 10 described above.
It is the same structure as the above, and the presence or absence of a defect in each difference data DISi is determined using the pixel operator OP. Each 1 of the determination circuit 27 is "in the difference data DISi".
In the region D of pixels having 1 ", the pixel operator OP
If there is at least one part that coincides with or a part that can include the pixel operator OP, it is determined to be a defect candidate and the value "
1 "is output, and conversely, if there is no such part,
It is determined that it is not a defect candidate, and the value "0" is output.

The outputs of the respective judgment circuits 27 are input to the AND circuits 28, and it is judged that there is a defect in the evaluation section CR only when all the judgment circuits 27 output the value "1" which means a defect candidate. If the value "1" corresponding to the above is output and conversely the value "0" indicating that even one of the determination circuits 27 is not a defect candidate is output, the evaluation section C
Value "0" corresponding to judging that there is no defect in R
Is output.

By using the comparison inspection unit 23, it is possible to prevent an erroneous determination in the detection of a defect due to a positional deviation when the printed wiring board 2 is placed on the transport table 1 at a predetermined position.

The present invention shown in the above-described first to fifth embodiments is not limited to the wiring pattern of the printed wiring board 2 but also the lead frame pattern to be incorporated in the integrated circuit.
It can be generally carried out on an object to be inspected for defects by a method of comparing the binarized image patterns.

[0064]

According to the image pattern inspection method and the apparatus therefor of the present invention, a plurality of storage means, for example, a semiconductor memory capable of high-speed reading are prepared, and a plurality of standards to be compared with a plurality of types of image patterns to be inspected. Each one of the image patterns is previously stored in each one of the plurality of storage means as a storage signal, and the reference pattern to be compared with the image pattern to be inspected is read out by selecting one from the plurality of storage means. Since the defect is detected, the inspection of the wiring pattern of the printed wiring board having the wiring patterns on both main surfaces, the inspection of the wiring patterns of a plurality of types of printed wiring boards, etc. can be efficiently performed.
6).

When the inspection target image pattern is compared with the reference image pattern to detect the defect, when the number of defects is counted and the number of defects exceeds a predetermined reference value, The defect detection is interrupted, another 1 is selected from the plurality of storage means to read a new reference pattern, and the defect detection is performed again. Therefore, the type of the reference image pattern and the image pattern to be inspected are determined. Even when the type does not correspond by mistake, the error can be found in a short time and the defect can be detected again, and as a result, the inspection of the wiring pattern of the printed wiring board having the wiring patterns on both main surfaces can be performed.
Alternatively, it is possible to more efficiently inspect the wiring patterns of a plurality of types of printed wiring boards.
6).

In particular, the detection of defects and the counting of the number of defects are automatically performed, and when the number of defects exceeds a predetermined reference value and becomes large, another defect is automatically selected from a plurality of storage means. Since 1 is selected and a new reference pattern is read out,
Even when the type of the reference image pattern and the type of the image pattern to be inspected do not correspond by mistake, the inspection of the wiring pattern of the printed wiring board having the wiring patterns on both main surfaces,
Alternatively, it is possible to more efficiently inspect the wiring patterns of a plurality of types of printed wiring boards (claim 5,
6).

Further, defects are detected and the number of defects is automatically counted, and when the number of defects exceeds a predetermined reference value and becomes large, another defect is automatically selected from a plurality of storage means. 1 is selected and a new reference pattern is read out, and the defect detection is automatically restarted from the beginning. Therefore, it is possible to inspect a wiring pattern of a printed wiring board having wiring patterns on both main surfaces or to check a plurality of types of printed wiring boards. The inspection of the wiring pattern and the like can be executed more efficiently (claim 6).

[Brief description of drawings]

FIG. 1 is a flowchart showing a schematic procedure of an image pattern inspection method according to an embodiment of the present invention.

FIG. 2 is a schematic block diagram of an image pattern inspection apparatus for implementing the method shown in the flowchart of FIG. 1 according to an embodiment of the present invention.

FIG. 3 is a block diagram showing an internal structure of a difference detection device.

FIG. 4 is a schematic diagram illustrating an evaluation section.

FIG. 5 is a schematic diagram illustrating the operation of an operator.

FIG. 6 is an operation explanatory diagram of a transport table.

FIG. 7 is a schematic block diagram of an image pattern inspection device according to a second embodiment of the present invention.

FIG. 8 is a flowchart showing a schematic procedure of an image pattern inspection method according to a third embodiment of the present invention.

FIG. 9 is a schematic block diagram of an image pattern inspection device according to a third embodiment of the present invention.

FIG. 10 is a schematic block diagram of an image pattern inspection device according to a fourth embodiment of the present invention.

11 is a block diagram showing an internal structure of a comparison inspection unit 23. FIG.

FIG. 12 is a schematic block diagram of a conventional image pattern inspection device.

FIG. 13 is a schematic block diagram of another example of a conventional image pattern inspection device.

[Explanation of symbols]

 1 Transport Table 2 Printed Wiring Board 3 Reader 4 A / D Converter 5 Binarization Processor 7 Difference Detector 10 Judgment Circuit 12 CAD 13 Correction Circuit 15 Comparing Section 16 Counter 17 Comparator 18 Reference Value Setting Section 19 Controller 20 Motor SM1 to SM4 Semiconductor memory SL5 Selector

Claims (6)

[Claims] 1. An image pattern inspection method for detecting a defect by comparing an inspection target image pattern with a reference image pattern, comprising: (a) preparing a plurality of storage means; A step of storing each one of the reference image patterns in each one of the storage means in advance as a storage signal; and (c) selecting one from the plurality of storage means and reading out the storage signal, whereby the reference image An image pattern comprising: a step of obtaining a pattern; (d) a step of obtaining the inspection target image pattern; and (e) a step of comparing the inspection target image pattern with the reference image pattern to detect the defect. Inspection method. 2. The method further comprises (f) at least a step of setting a reference value before the step (e), wherein the step (e) includes (e-1) the inspection target image pattern and the reference image. Detecting the defect by comparing with a pattern; (e-2) counting the number of the defect in the process (e-1); (e-3) the process (e) In -2), if the number of counted defects is detected exceeding the reference value,
At that time, a step of interrupting the step (e-1), and (e-4) the step (e-) in the step (e-3).
If 1) is interrupted, one of the storage means not selected after the step (c) from the plurality of storage means.
To obtain another reference image pattern by reading the stored data. (E-5) the steps (e-1) to (e-4)
The method of inspecting an image pattern according to claim 1, wherein the steps of repeating up to are replaced with. 3. An image pattern inspection apparatus for detecting defects by comparing an inspection target image pattern with a reference image pattern, comprising: (a) a plurality of storage means; and (b) a plurality of the reference image patterns. A means for storing each 1 as a storage signal in advance in each of the storage means; and (c) means for obtaining the reference image pattern by selecting 1 from the plurality of storage means and reading the storage signal. An image pattern inspection apparatus comprising: (d) means for obtaining the inspection target image pattern; and (e) means for comparing the inspection target image pattern with the reference image pattern to detect the defect. 4. (f) means for setting a reference value; (g) means for counting the number of defects detected by the means (e); (h) the defects counted by the means (g). 4. The image pattern inspection apparatus according to claim 3, further comprising: a unit that compares the number of each of the numbers with the reference value set by the unit (f) and outputs the result as a signal. 5. (i) When the means (h) outputs a signal corresponding to the number of the defects exceeding the reference value, the means (c) newly creates a new one from the plurality of storage means. 5. The image pattern inspection device according to claim 4, further comprising means for operating the means (c) so as to obtain a new reference image pattern by selecting No. 6. (j) When the means (h) outputs a signal corresponding to the number of the defects exceeding the reference value, the operation of the means (e) is interrupted and the operation is started. 6. Further comprising means for controlling to perform from
The image pattern inspection device according to 1.