TW201834102A - External-appearance examination device - Google Patents

Abstract

Provided is an external-appearance examination device that can shorten the time required for examination in a state where a plurality of element chips having mutually different patterns are mixed together. Specifically, an external-appearance examination device 100 comprises: an image capture unit 40 that captures images of examination-target element chips 210; a storage unit 50 in which are pre-stored good-product images P serving as an examination reference for the element chips 210 having mutually different patterns A-D; and an examination unit 61 that identifies the type of the patterns A-D of the examination-target element chips 210 captured by the image capture unit 40, and that determines whether the examination-target element chips 210 are good products or not by comparing: the images of the examination-target element chips 210 captured by the image capture unit 40; and the good-product images P which correspond to the identified patterns of the examination-target element chips 210.

Description

Visual inspection device

The present invention relates to an appearance inspection device, and more particularly to an appearance inspection device including an inspection unit that determines whether or not an element wafer to be inspected is a good product by comparison with a good image.

In the past, there has been known an appearance inspection device including an inspection unit that determines whether or not the component wafer to be inspected is a good product by comparison with a good image (see, for example, Patent Document 1). Patent Document 1 discloses an appearance inspection method for finding a difference between a standard image (good image) and an inspection image, and inspecting a defect of the workpiece based on a difference between the standard image and the inspection image. In the inspection method, first, a large number of good workpieces are photographed during the teaching process, and an average value (standard image) of the gradation values of each pixel of the image is obtained. Next, during the inspection, the workpiece is photographed, and the presence or absence of the defect (whether it is good or not) is determined based on the comparison between the inspection image of the workpiece to be inspected and the standard image of the good workpiece. In addition, as a standard image of a good workpiece, only a standard image of one good workpiece is used. [Prior Art Document] [Patent Document] [Patent Document 1] Japanese Patent Laid-Open No. Hei 10-123064

[Problems to be Solved by the Invention] In the defect inspection method described in Patent Document 1, as a standard image of a good workpiece, only a standard image of one good workpiece is used, and thus the same pattern is set for all the workpieces. When the workpiece is a good one based on the standard image of one good workpiece. On the other hand, in a state in which a plurality of workpieces having mutually different patterns are mixed, it is necessary to prepare a standard image of a plurality of good workpieces having mutually different patterns. In this case, first, a plurality of workpieces are sequentially photographed in a state in which a standard image of one of the plurality of good workpieces has been prepared (in a state in which the memory is called). For example, imaging is performed by scanning the plurality of workpieces by the imaging unit. Next, the inspection images of the plurality of shots are sequentially compared with the standard image of the good workpiece, and it is determined whether each of the workpieces is a good one. Further, a standard image of a good workpiece of a type (pattern) different from the type (pattern) of the inspection is prepared, and a plurality of workpieces are photographed, and it is determined whether each workpiece is a good one. As described above, in the conventional defect inspection method described in Patent Document 1, the scanning of the imaging unit is performed plural times, and the number of times of scanning is the number of types of patterns. Therefore, there is a problem that it takes a relatively long time to perform inspection of all the workpieces (component wafers). The present invention has been made to solve the problems as described above, and an object of the present invention is to provide an appearance inspection capable of shortening the time required for inspection in a state in which a plurality of element wafers having mutually different patterns are mixed. Device. [Means for Solving the Problems] In order to achieve the above object, an aspect inspection apparatus according to an aspect of the present invention is characterized in that a plurality of component wafers are inspected in a state in which a plurality of component wafers having mutually different patterns are mixed, and each of them is provided. An imaging unit that captures an element wafer to be inspected; a memory unit that stores in advance a good image that is an inspection standard of the element wafer in a pattern different from each other; and an inspection unit that recognizes an inspection target imaged by the imaging unit The type of the pattern of the element wafer is compared with the image of the component wafer to be inspected by the imaging unit and the good image corresponding to the pattern of the identified component wafer, thereby determining whether the component wafer to be inspected is The discrimination of good products. As described above, the visual inspection device according to the present invention includes an inspection unit that recognizes the pattern type of the component wafer to be inspected by the imaging unit, and compares the image of the component wafer to be inspected by the imaging unit. A good image corresponding to the pattern of the component wafer of the identified inspection object is used to determine whether or not the component wafer to be inspected is good. In this way, since the inspection unit recognizes the type of the pattern of the component wafer to be inspected, it is possible to read from each of the component wafers to be inspected by the inspection unit and the component wafer to be inspected. The pattern corresponds to the good image. As a result, in a state in which a plurality of element wafers having mutually different patterns are mixed, it is not necessary to repeatedly photograph the plurality of element wafers by the imaging unit (scanning of the imaging unit), and the components can be scanned by one scan. Whether the wafer is a good product. Thereby, in a state in which a plurality of element wafers having mutually different patterns are mixed, the time required for inspection can be shortened. Preferably, in the visual inspection device of the above aspect, the plurality of component wafers are disposed on the substrate, and the wafer configuration information of the pattern of the component wafer disposed at any position on the substrate is previously stored in the memory portion. The inspection unit recognizes the pattern type of the component wafer for inspection by the imaging unit based on the wafer arrangement information stored in the memory unit. According to this configuration, since the memory portion pre-stores the wafer arrangement information of the pattern of the component wafer provided at any position on the substrate, the image is captured by image recognition (comparison of images). The time required for the inspection can be further shortened as compared with the case where the pattern of the component wafer for inspection corresponds to the image of the good one. In this case, it is preferable that a plurality of component wafer groups each including a plurality of component wafers each having a different pattern from each other are disposed on the substrate, and the component wafer groups are respectively formed with a plurality of component wafers having different patterns from each other. The arrangement position is the same in each of the component wafer groups, and the wafer arrangement information of a plurality of component wafers including a plurality of component wafer groups is previously stored in the memory section. According to this configuration, since the arrangement positions of the plurality of element wafers are the same in each of the element wafer groups, the same mask can be used to form the element wafers for each of the element wafer groups. Preferably, in the visual inspection device in which the plurality of component wafers are mounted on the substrate, each of the plurality of component wafers for inspection provided on the substrate is sequentially moved: the substrate and the imaging portion are relatively moved. In the state, the imaging unit captures the component wafer for inspection; the inspection unit recognizes the pattern type of the component wafer for inspection; and switches the good image to a pattern having a pattern corresponding to the identified component wafer for inspection. A good image; and a comparison between the image of the component wafer for inspection and the good image to determine whether the component wafer is a good product. According to this configuration, in a state in which a plurality of element wafers having mutually different patterns are mixed, continuous inspection of a plurality of element wafers can be performed smoothly. [Effects of the Invention] According to the present invention, as described above, in a state in which a plurality of element wafers having mutually different patterns are mixed, the time required for inspection can be shortened.

Hereinafter, embodiments of the present invention will be described based on the drawings. [Embodiment] (Structure of Appearance Inspection Apparatus) The structure of the appearance inspection apparatus 100 of the present embodiment will be described with reference to Figs. 1 to 7 . The visual inspection device 100 is configured to inspect a plurality of component wafers 210 in a state in which a plurality of component wafers 210 (see FIG. 4) having mutually different patterns are mixed. As shown in FIG. 1, the visual inspection device 100 includes a moving stage 10. The moving stage 10 includes an X-axis slider 11 and a Y-axis slider 12. The X-axis slider 11 is disposed on the base portion 20. Further, the Y-axis slider 12 is disposed on the X-axis slider 11. Moreover, the visual inspection device 100 is provided with the mounting platform 30. The mounting platform 30 is disposed on the Y-axis slider 12. Further, the mounting platform 30 is configured to move in the X direction and the Y direction by moving the stage 10. Moreover, the mounting platform 30 is configured to mount the wafer 220 (the component wafer 210 to be inspected, see FIG. 4). Further, the wafer 220 is an example of a "substrate" in the scope of the patent application. Moreover, the visual inspection device 100 is provided with the imaging unit 40. The imaging unit 40 is configured to capture an element wafer 210 to be inspected and a good element wafer 210 for imaging a good image P (an image of the good element wafer 210, see FIG. 3) to be used as an inspection standard. The imaging unit 40 includes a lens barrel 41 , a half mirror 42 , a counter lens 43 , and an imaging camera 44 . The imaging camera 44 includes a light receiving element 44a. Further, the imaging camera 44 is configured to output an image of the imaged element wafer 210 to a control unit 60, which will be described later. Moreover, as shown in FIG. 2, the imaging unit 40 is configured to sequentially capture a plurality of element wafers 210 that relatively move the imaging unit 40. Specifically, the element wafer 210 is relatively moved to the imaging unit 40 in the X direction or the Y direction by the moving stage 10 . Moreover, as shown in FIG. 1, the visual inspection apparatus 100 is provided with the memory part 50. As shown in FIG. 3, in the memory unit 50, a good image P which is a reference for inspection of the element wafer 210 in a pattern (patterns A to D) different from each other is stored in advance. In addition, "pre-" means before checking the component wafer 210 of the inspection object. Also, a plurality of good images P are memorized. For example, as shown in FIG. 3, the good image P includes: a good image P1 corresponding to the pattern A (see FIG. 3(a)), a good image P2 corresponding to the pattern B (see FIG. 3(b)), The good image P3 corresponding to the pattern C (see FIG. 3(c)) and the good image P4 corresponding to the pattern D (see FIG. 3(d)). Further, the good images P1 to P4 are individually stored in the storage unit 50. The good image P1 to P4 are images of the good element wafers 210a to 210d (see FIG. 4) which are formed so that the wiring patterns provided in the effective area 211 are different from each other. For example, the arrangement positions, sizes, and the like of the wiring patterns are different from each other. Further, in FIG. 4, the peripheral regions 212 surrounding the effective regions 211 of the element wafers 210a to 210d have the same pattern, and the patterns of the peripheral regions 212 of the element wafers 210a to 210d may be different from each other. Further, as shown in FIG. 5, a plurality of element wafers 210 are disposed on the wafer 220. The wafer 220 has a substantially circular shape in plan view. Further, a plurality of element wafers 210 are arranged in a matrix on the wafer 220. Further, in the present embodiment, as shown in FIG. 6, in the memory unit 50, the wafer layout information of the patterns A to D of the element wafer 210 provided at any position on the wafer 220 is previously stored. Specifically, the plurality of component wafers 210 that are arranged in a matrix on the wafer 220 correspond to the good image P of the good images P1 to P4 (having the same pattern A to D as the image of the good image P) The related configuration information is pre-memorized in the memory unit 50. Further, the wafer layout information is input by, for example, a user before the inspection of the component wafer 210 for inspection. In FIG. 6, the patterns A to D are described in a part of the element wafer 210, but the patterns A to D of all the element wafers 210 are actually stored in the memory unit 50 in advance. Further, in the present embodiment, as shown in FIG. 6, the wafer 220 is provided with a plurality of element wafers each including a plurality of element wafers 210 (inspection element wafers 210) each having a pattern different from each other. Group 230 (area surrounded by the square of the thick line of Figure 6). For example, as shown in FIG. 7, the one element wafer group 230 includes four element wafers 210a to 210d in which mutually different patterns are formed. Further, the arrangement positions of the plurality of element wafers 210a to 210d in which the element wafer groups 230 are formed with mutually different patterns are the same in each of the element wafer groups 230. For example, in one element wafer group 230, four element wafers 210a to 210d are arranged in two rows and two rows. Further, the element wafer 210a is placed on the upper left side, and the element wafer 210b is placed on the upper right side. Further, the element wafer 210c is placed on the lower left side, and the element wafer 210d is placed on the lower right side. This configuration location is the same in any of the component wafer groups 230. Further, as shown in FIG. 6, on the outer edge side of the wafer 220, since the wafer 220 has a substantially circular shape, the four element wafers 210a to 210d cannot be disposed. Therefore, in the outer edge side of the wafer 220, one of the four element wafers 210a to 210d (or a plurality of) is missing from the one element wafer group 230. The reason why the arrangement positions of the element wafers 210a to 210d are the same in each of the element wafer groups 230 is that when the element wafers 210a to 210d are formed on the wafer 220, they are formed using the same mask (not shown). The element wafers 210a to 210d are defective. Further, in the present embodiment, the wafer arrangement information of the plurality of element wafers 210 including the plurality of element wafer groups 230 is previously stored in the memory unit 50. That is, the wafer arrangement information as shown in FIG. 6 is memorized in advance in the memory unit 50. Moreover, as shown in FIG. 1, the visual inspection apparatus 100 is equipped with the inspection part 61. The inspection unit 61 is included in, for example, a control unit 60 configured by a CPU (Central Processing Unit) or the like. Further, the control unit 60 is configured to control the overall operation of the visual inspection device 100. In the present embodiment, the inspection unit 61 recognizes the types of the patterns A to D of the component wafer 210 to be inspected by the imaging unit 40. Next, the inspection unit 61 compares the image of the component wafer 210 to be inspected by the imaging unit 40 with the good image P corresponding to the patterns A to D of the identified component wafer 210 to be inspected. Whether or not the component wafer 210 is a good one is judged. Specifically, the inspection unit 61 is configured to recognize the types of the patterns A to D of the component wafer 210 for inspection by the imaging unit 40 based on the wafer placement information (see FIG. 6 ) stored in the storage unit 50 . (Operation of Appearance Inspection Device) Next, the operation of the appearance inspection device 100 will be described with reference to Figs. 8 to 11 . <Condition Setting> The operation (flow) of the condition setting will be described with reference to Fig. 8 . In addition, the registration described below is performed by, for example, displaying a screen for accepting information on a display unit (not shown) and inputting information by the user. Further, the information registered (input) is registered (memorized) in the storage unit 50. First, in step S1, the mapping information is registered. Specifically, the size of the wafer 220, the size of the element wafer 210, and the like are registered. Next, in step S2, registration of the pattern of the element wafer 210 is performed. Specifically, as shown in FIG. 6, the wafer layout information of the pattern of the component wafer 210 disposed at any position on the wafer 220 is registered. Next, in step S3, registration of the global alignment information of the component wafer 210 is performed. For example, information such as the angle or center position of the component wafer 210 is registered. Next, in step S4, the inspection condition is registered. Specifically, the optical condition when the imaging unit 40 performs imaging of the element wafer 210, the inspection area on the element wafer 210, and the like are registered. In addition, the inspection area is, for example, an area surrounded by a broken line on the element wafer 210 of FIG. Thereby, the condition setting operation ends. <Creation of Good Image> A creation (training) operation (flow) of the good image P will be described with reference to Fig. 9 . Further, the creation of the good image P is performed by the control unit 60. Further, the created good image P is registered in the storage unit 50. Further, the creation (training) of the good image P is performed in advance before the inspection of the component wafer 210 for inspection to be described later. First, in step S11, the inspection condition is read from the memory unit 50. The inspection condition is the registrant in the above step S4. Next, the wafer 220 is transferred in step S12. Specifically, the wafer 220 is placed on the moving stage 10 (the mounting platform 30). Further, the wafer 220 is disposed in a state in which a plurality of element wafers 210 having mutually different patterns are mixed. In addition, the plurality of component wafers 210 disposed on the wafer 220 may all be the good component wafer 210, or the defective component wafer 210 may be included in any of the plurality of component wafers 210. Further, the user (control unit 60) recognizes in advance which of the plurality of component wafers 210 is the good component wafer 210, and which of the plurality of component wafers 210 is the information of the defective component wafer 210. Next, in step S13, global alignment of the wafer 220 (element wafer 210) is performed. For example, the angle or center position of the component wafer 210 or the like is determined. In addition, the information of the global alignment is registered in the above step S3. Next, in step S14, the imaging unit 40 is relatively moved above the target element wafer 210. Specifically, by moving the wafer 220 on the moving stage 10, the target element wafer 210 is placed directly under the imaging unit 40. Which one of the plurality of element wafers 210 is the target element wafer 210 is registered in the memory unit 50 in advance. For example, if all of the plurality of component wafers 210 on the wafer 220 are good, then all of the component wafers 210 can be targeted. Further, if the plurality of element wafers 210 on the wafer 220 include defective products, only the good element wafer 210 may be the target element wafer 210. Further, it is also possible to target a part of the good component wafer 210 without targeting all of the good component wafers 210. Next, in step S15, the target element wafer 210 is imaged. The element wafer 210 is photographed one by one in accordance with the element wafer 210. Next, in step S16, the type of the pattern of the good element wafer 210 imaged by the imaging unit 40 is recognized. That is, it is recognized which one of the patterns A to D corresponds to the captured good element wafer 210. Further, the pattern of the plurality of element wafers 210 disposed on the wafer 220 corresponds to the position (coordinate) on the wafer 220 of the element wafer 210 corresponding to the pattern (A), and is previously stored in the memory unit 50. Next, based on the positional information (coordinates) of the wafer 220 by the imaging unit 40, it is recognized which one of the patterns A to D corresponds to the pattern of the element wafer 210 of the current imaging. Next, in step S17, alignment of the imaged element wafer 210 is performed. For example, based on the alignment marks previously provided on the element wafer 210, the effective area 211 of the element wafer 210 (the area where the element is formed, refer to FIG. 4) and the peripheral area 212 (the area of the active area 211 where the element is not formed) are paired. quasi. Next, in step S18, the image of the imaged good element wafer 210 (good image P) is assigned to each of the patterns A to D and stored in the memory unit 50. Next, in step S19, it is determined whether or not photographing of all of the good component wafers 210 of the target has ended. When it is determined that the shooting of all the good component chips 210 as the target is not completed, the process returns to step S14. When it is determined that the shooting of all the good component chips 210 as the target has ended, the process proceeds to step S20. The operations of the above-described steps S14 to S19 are continuously performed in a state in which the wafer 220 and the imaging unit 40 are relatively moved. For example, as shown by the path B in FIG. 6, the wafer 220 and the imaging unit 40 are relatively moved in such a manner that a plurality of element wafers 210 disposed on the wafer 220 are imaged in a stroke. Specifically, the wafer 220 relatively moves in the Y1 direction with respect to the imaging unit 40, and performs imaging (and identification, registration, alignment, registration) of a plurality of element wafers 210 arranged along the Y direction. Then, after the imaging of the element wafer 210 disposed at the end portion on the Y1 direction side is completed, the wafer 220 is relatively moved by the imaging unit 40 in the X1 direction by the size of one element wafer 210. Subsequently, the wafer 220 relatively moves in the Y2 direction with respect to the imaging unit 40, and performs imaging of a plurality of element wafers 210 arranged along the Y direction. Next, after the imaging of the element wafer 210 disposed at the end portion on the Y2 direction side is completed, the wafer 220 is relatively moved by the imaging unit 40 in the X1 direction by the size of one element wafer 210. Subsequently, the above actions are repeated. Next, in step S20, a good image P (training material) is generated. Specifically, each of the patterns A to D memorizes (saves) an image of a plurality of good component wafers 210. Next, the luminance values of the images of the good component wafer 210 are added to each pixel and averaged. This addition and averaging are performed individually for each of the patterns A to D. Thereby, the good image P (good images P1 to P4) is generated in the patterns A to D. Next, in step S21, the wafer 220 is stored at a specific position, and the generation operation of the good image P is completed. <Inspection of Element Wafer> An inspection operation (flow) of the element wafer 210 will be described with reference to FIGS. 10 and 11 . Further, the inspection of the element wafer 210 is performed by the inspection unit 61 (control unit 60). First, in step S31, the inspection condition is read from the memory unit 50. The inspection condition is the registrant in the above step S4. Next, the wafer 220 is transferred in step S32. Specifically, the wafer 220 is placed on the moving stage 10 (the mounting platform 30). Further, the wafer 220 is disposed in a state in which a plurality of element wafers 210 having mutually different patterns are mixed. In addition, the plurality of component wafers 210 disposed on the wafer 220 may be scribed or not scribed. Next, in step S33, the global alignment of the element wafer 210 of the wafer 220 (element wafer 210) is performed. For example, information such as the angle or center position of the component wafer 210 is determined. In addition, the global alignment information is registered in the above step S3. Next, in step S34, the imaging unit 40 is relatively moved above the element wafer 210 of the target (inspection target). Specifically, by moving the wafer 220 by the moving stage 10, the target element wafer 210 is placed directly under the imaging unit 40. Next, in step S35, the component wafer 210 of the target (inspection target) is imaged. The element wafer 210 is photographed one by one in accordance with the element wafer 210. Further, in a state in which the wafer 220 and the imaging unit 40 are relatively moved, a plurality of element wafers 210 are successively imaged by the element wafer 210 one by one. In the present embodiment, in step S36, the type (patterns A to D) of the pattern of the component wafer 210 to be inspected by the imaging unit 40 is recognized. The memory unit 50 preliminarily stores the wafer arrangement information of the patterns A to D of the element wafer 210 disposed at any position on the wafer 220. For example, the pattern of the component wafer 210 disposed at any position on the wafer 220 is stored in correspondence with the position (coordinate) of the component wafer 210 on the wafer 220. Next, the inspection unit 61 recognizes the type of the pattern of the component wafer 210 for inspection by the imaging unit 40 based on the wafer placement information stored in the storage unit 50. For example, based on the positional information (coordinates) of the wafer 220 by the imaging unit 40, it is recognized which one of the patterns A to D corresponds to the pattern of the element wafer 210 of the current imaging. Next, in step S37, alignment of the photographed component wafer 210 is performed. For example, the active area 211 (the area forming the element, refer to FIG. 4) and the peripheral area 212 (the area surrounding the unformed element surrounding the effective area 211) of the element wafer 210 are aligned based on the alignment marks previously provided on the element wafer 210. . Next, in step S38, the good image P having the pattern corresponding to the component wafer 210 to be inspected is read from the memory unit 50. For example, when the pattern of the component wafer 210 to be inspected is the pattern A, the good image P1 having the pattern A is read from the memory unit 50. In other words, the good image P is switched in accordance with the pattern of the component wafer 210 to be inspected by the imaging unit 40. Next, in the present embodiment, in the present embodiment, the image of the component wafer 210 to be inspected by the imaging unit 40 and the good image P corresponding to the pattern of the identified component wafer 210 are compared. Thereby, it is determined whether or not the component wafer 210 to be inspected is a good one. For example, an image of the component wafer 210 of the inspection object having the pattern A and a good image P1 having the pattern A are compared. Specifically, the luminance values of each of the two images are compared. Further, when the difference in the luminance values to be compared is relatively large, the image of the component wafer 210 to be inspected is different from the image of the good image P1. In this case, a defect occurs in a portion where the difference in luminance values of the element wafer 210 to be inspected is relatively large. For example, in the case of the element wafer 210 shown in FIG. 11, when the element wafer 210 has the defect 213, the difference from the luminance value of the good image P1 in the pixel corresponding to the defect 213 is increased. Therefore, when the difference in the luminance values to be compared is relatively large, it is judged that the component wafer 210 to be inspected is not a good product (defective product). In addition, the image of the inspection element wafer 210 that is determined to be good by the inspection unit 61 is deleted when the determination of whether or not the component wafer 210 for inspection is good is completed. Thereby, it is possible to suppress an increase in the data capacity of the element wafer 210 stored in the memory (not shown). Next, in step S40, it is judged whether or not the inspection of the component wafers 210 of all the inspection targets is completed. When it is determined that the inspection of the component wafer 210 of all the inspection targets is not completed, the process returns to step S34. The operations of the above-described steps S34 to S40 are continuously performed in a state in which the wafer 220 and the imaging unit 40 are relatively moved. For example, as shown by the path B in FIG. 6, the wafer 220 and the imaging unit 40 are relatively moved in such a manner that a plurality of element wafers 210 disposed on the wafer 220 are imaged in a stroke. Thereby, since the wafer 220 and the imaging unit 40 can be moved relative to each other without using the useless movement of the path, the time required for the imaging of all the element wafers 210 can be shortened. The operation of the relative movement of the wafer 220 and the imaging unit 40 is the same as the operation when the good image is created. As described above, in the present embodiment, each of the plurality of component wafers 210 to be inspected on the wafer 220 is sequentially placed in a state in which the wafer 220 and the imaging unit 40 are relatively moved. 40. The component wafer 210 for imaging inspection; the inspection unit 61 identifies the pattern type of the component wafer 210 for inspection; and the good image P is switched to have a pattern corresponding to the pattern of the identified component wafer 210 for inspection. The good image P; and the image of the component wafer 210 for inspection and the good image P are compared to determine whether the component wafer 210 is a good one. Moreover, in the case where it is determined in step S40 that the inspection of the component wafers 210 of all the inspection targets is completed, the process proceeds to step S41. Next, in step S41, the wafer 220 is stored in a specific position, and the inspection operation of the component wafer 210 to be inspected is completed. (Effects of the Present Embodiment) Next, effects of the present embodiment will be described. In the present embodiment, as described above, the inspection unit 61 is provided to recognize the types of the patterns A to D of the component wafer 210 to be inspected by the imaging unit 40, and compare the component wafers to be inspected by the imaging unit 40. The image of 210 and the good image P corresponding to the patterns (A to D) of the component wafer 210 of the identified inspection target are used to determine whether or not the component wafer 210 to be inspected is good. In this way, since the inspection unit 61 recognizes the pattern type of the component wafer 210 to be inspected, it is possible to read the component of the inspection target from the memory unit 50 for each of the component wafers 210 to be inspected. A good image P corresponding to the pattern of the wafer 210. As a result, in a state in which a plurality of element wafers 210 having mutually different patterns are mixed, it is not necessary to repeatedly image the plurality of element wafers 210 (scanning of the image pickup unit 40) by the image pickup unit 40, and the scanning can be performed once by one time. Whether or not the component wafer 210 is a good product is determined. Thereby, in a state in which a plurality of element wafers 210 having mutually different patterns are mixed, the time required for inspection can be shortened. Further, in the present embodiment, as described above, a plurality of component wafers 210 are disposed on the wafer 220, and the component wafer 210 having any position on the wafer 220 is previously stored in the memory portion 50. The inspection unit 61 recognizes the pattern type of the component wafer 210 for inspection by the imaging unit 40 based on the wafer placement information stored in the storage unit 50. Thereby, in the memory unit 50, the wafer arrangement information of the pattern of the element wafer 210 disposed at any position on the wafer 220 is previously stored, and thus the identification is performed by image recognition (comparison of images). The time required for the inspection can be further shortened as compared with the case where the pattern of the component wafer 210 for inspection is corresponding to the image of the good image P. Further, in the present embodiment, as described above, a plurality of element wafer groups 230 each including a plurality of element wafers 210 each having a pattern different from each other are formed on the wafer 220, and the element wafer groups 230 are formed separately. The arrangement positions of the plurality of component wafers 210 having mutually different patterns are the same in each of the component wafer groups 230, and the wafer configuration information of the plurality of component wafers 210 including the plurality of component wafer groups 230 is previously stored in the memory portion 50. . Thereby, since the arrangement positions of the plurality of element wafers 210 are the same in each of the element wafer groups 230, the element wafer 210 can be formed in each of the element wafer groups 230 using the same mask (not shown). Further, in the present embodiment, as described above, each of the plurality of component wafers 210 for inspection provided on the wafer 220 is sequentially moved in a state in which the wafer 220 and the imaging unit 40 are relatively moved. The component wafer 210 for inspection is imaged by the imaging unit 40, the pattern type of the component wafer 210 for inspection is detected by the inspection unit 61, and the good image P is switched to have the component wafer 210 for inspection and identification. The good image P of the pattern corresponding to the pattern; and the image of the component wafer 210 for inspection and the good image P are compared to determine whether the component wafer 210 is a good one. Thereby, in a state in which a plurality of element wafers 210 having mutually different patterns are mixed, the inspection of the plurality of element wafers 210 can be continuously and smoothly performed. [Modifications] It should be understood that the embodiments and examples of the present disclosure are illustrative and not restrictive. The scope of the present invention is defined by the scope of the claims and the description of the embodiments and the embodiments of the invention, and all modifications (variations) within the meaning and scope of the patent application. For example, in the above embodiment, the display inspection unit 61 is included in the control unit 60, but the present invention is not limited thereto. For example, the inspection unit 61 can be provided separately from the control unit 60. Further, in the above-described embodiment, the example in which the element wafers 210 of the four patterns different from each other are mixed is shown, but the present invention is not limited thereto. For example, the number of patterns of the component wafer 210 may be other than four. Further, in the above-described embodiment, the memory unit 50 displays an example in which the wafer arrangement information of the element wafer 210 provided at any position on the wafer 220 is stored in advance, but the present invention is not limited thereto. For example, each time the component wafer 210 is imaged, the image of the component wafer 210 for inspection and the plurality of good images P can be compared, and the pattern and the plurality of component wafers 210 for inspection can be identified. Which of the good images P has the same pattern. Further, in the above-described embodiment, the arrangement positions of the plurality of element wafers 210 in which the display element wafer group 230 are formed with mutually different patterns are the same in each of the element wafer groups 230, but the present invention is not limited thereto. this. For example, the arrangement positions of the plurality of element wafers 210 in which the element wafer groups 230 are formed with mutually different patterns may be different for each of the element wafer groups 230. Further, in the above embodiment, an example of inspecting the element wafer 210 provided on the wafer 220 is shown, but the present invention is not limited thereto. For example, the component wafer 210 that is not disposed on the wafer 220 can be inspected.

10‧‧‧Mobile stage

11‧‧‧X-axis slider

12‧‧‧Y-axis slider

20‧‧‧Base Department

30‧‧‧Loading platform

40‧‧‧Photography Department

41‧‧‧Mirror tube

42‧‧‧half mirror

43‧‧‧object lens

44‧‧‧ camera camera

44a‧‧‧Light-receiving components

50‧‧‧Memory Department

60‧‧‧Control Department

61‧‧‧Inspection Department

100‧‧‧ appearance inspection device

210‧‧‧Component chip

210a～210d‧‧‧Component chip

211‧‧‧effective area

212‧‧‧ Peripheral area

213‧‧‧ Defects

220‧‧‧ wafer (substrate)

230‧‧‧Component Wafer Group

A‧‧‧ pattern

B‧‧‧ pattern

B‧‧‧ Path

C‧‧‧ pattern

D‧‧‧ pattern

P‧‧‧good images

P1～P4‧‧‧ good images

S1～S4‧‧‧Steps

S11～S21‧‧‧Steps

S31～S41‧‧‧Steps

X‧‧‧ direction

X1‧‧‧ direction

X2‧‧‧ direction

Y‧‧‧ direction

Y1‧‧‧ direction

Y2‧‧‧ direction

Z‧‧‧ direction

Fig. 1 is a general view of an appearance inspection device according to an embodiment of the present invention. FIG. 2 is a view for explaining an operation of an imaging unit of the visual inspection device according to the embodiment of the present invention. 3(a) to 3(d) are diagrams showing a good image (an image of a component wafer of a good product). Fig. 4 is a view showing a component wafer for inspection. Figure 5 is a diagram showing a plurality of component wafers disposed on a wafer. Fig. 6 is a view showing a plurality of element wafers having different patterns arranged on a wafer. Fig. 7 is a view showing a position at which a plurality of element wafers of a component wafer group are arranged. Fig. 8 is a flow chart for explaining the operation of setting conditions of the visual inspection device according to the embodiment of the present invention. Fig. 9 is a flow chart for explaining an operation for generating a good image in the visual inspection device according to the embodiment of the present invention. Fig. 10 is a flow chart for explaining the operation of the inspection device wafer of the visual inspection device according to the embodiment of the present invention. Fig. 11 is a view showing a component wafer of a defective product.

Claims (4)

An appearance inspection device that inspects a plurality of component wafers in a state in which a plurality of component wafers having mutually different patterns are mixed, and includes: an imaging unit that images an element wafer to be inspected; and a memory unit Preliminarily storing a good image which is an inspection standard of the element wafer in a pattern different from each other; and an inspection unit that recognizes a pattern type of the element wafer to be inspected by the imaging unit, and compares and photographs by the imaging unit The image of the component wafer to be inspected and the good image corresponding to the pattern of the component wafer to be inspected by the object to be inspected are used to determine whether or not the component wafer to be inspected is good. The visual inspection device of claim 1, wherein the plurality of component wafers are disposed on the substrate, and the memory portion pre-stores, in the memory portion, a wafer arrangement information of a pattern of the component wafer disposed at any position on the substrate, and The inspection unit is configured to recognize a pattern type of the element wafer for inspection by the imaging unit based on the wafer arrangement information stored in the memory unit. The visual inspection device of claim 2, wherein the plurality of component wafer groups each including a plurality of the plurality of component wafers each having a pattern different from each other are disposed on the substrate, wherein the component wafer groups are formed differently from each other The arrangement positions of the plurality of element wafers in the pattern are the same in each of the element wafer groups, and the wafer arrangement information of the plurality of element wafers including the plurality of element chip groups is previously stored in the memory portion. The visual inspection device according to claim 2 or 3, wherein each of the plurality of inspection target wafers provided on the substrate is sequentially moved in a state in which the substrate and the imaging unit are relatively moved The image forming unit scans the component wafer for inspection; the inspection unit recognizes the pattern type of the component wafer for inspection, and switches the good image to have the component wafer for identification inspection The good image of the pattern corresponding to the pattern; and the image of the component wafer for inspection and the good image are used to determine whether the component wafer is a good product.