WO2018145335A1 - 阵列基板行驱动电路的检测装置及方法 - Google Patents

阵列基板行驱动电路的检测装置及方法 Download PDF

Info

Publication number
WO2018145335A1
WO2018145335A1 PCT/CN2017/075084 CN2017075084W WO2018145335A1 WO 2018145335 A1 WO2018145335 A1 WO 2018145335A1 CN 2017075084 W CN2017075084 W CN 2017075084W WO 2018145335 A1 WO2018145335 A1 WO 2018145335A1
Authority
WO
WIPO (PCT)
Prior art keywords
row driving
driving unit
unit
signal
driving circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2017/075084
Other languages
English (en)
French (fr)
Inventor
高天华
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuhan China Star Optoelectronics Technology Co Ltd
Original Assignee
Wuhan China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wuhan China Star Optoelectronics Technology Co Ltd filed Critical Wuhan China Star Optoelectronics Technology Co Ltd
Priority to US15/519,347 priority Critical patent/US20190385500A1/en
Publication of WO2018145335A1 publication Critical patent/WO2018145335A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/40—Testing power supplies
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2230/00—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays

Definitions

  • the present invention relates to the field of detection technologies for display panels, and in particular, to a detection device and method for an array substrate row driving circuit.
  • LTPS Low Temperature Poly-Silicon
  • the interception mechanism of the low-temperature polysilicon product process mainly includes electrical detection and optical detection.
  • Electrical detection includes array substrate inspection.
  • the main detection items of array substrate detection include: array substrate row driving circuit, gate line and data line of low temperature polysilicon product.
  • a defect of the detecting device of the array substrate row driving circuit in the prior art is that the detecting device can only reflect the abnormality of the entire array substrate driving circuit, and cannot further determine the row driving unit in which the abnormality occurs, thereby increasing the abnormality analysis. Difficulty.
  • the present invention provides a detecting device and method for an array substrate row driving circuit.
  • an apparatus for detecting an array substrate row driving circuit comprising:
  • An input module configured to input a test signal to the first-level row driving unit of the row driving circuit, where the row driving circuit includes a plurality of cascaded row driving units;
  • An acquisition module configured to acquire an output signal of each row driving unit
  • a detecting module configured to determine, according to an output signal of all the row driving units, a row driving unit that operates abnormally when it is determined that the row driving circuit is abnormal.
  • the detection module includes a plurality of conversion units
  • Each of the conversion units corresponds to the first-level row driving unit, and is configured to convert the output signal of the row-row driving unit into a pulse signal, and the pulse signals corresponding to the other row driving units do not overlap each other. ;
  • a superimposing unit configured to superimpose pulse signals output by all conversion units to obtain a superimposed signal
  • a determining unit configured to determine, according to the superimposed signal, a row driving unit that operates abnormally.
  • the conversion unit includes a NAND gate circuit for performing a NAND operation on a clock signal and an output signal of a row driving unit corresponding to the conversion unit to obtain the pulse signal.
  • the determining unit is specifically configured to: determine a missing waveform in the superimposed signal, and determine a row driving unit corresponding to the missing waveform as the abnormally operating row driving unit.
  • a display module is further included for displaying a waveform of the superimposed signal.
  • the detecting module further includes:
  • the determining unit is configured to determine an operating state of the row driving circuit according to an output signal of the last row driving unit.
  • a method for detecting an array substrate row driving circuit including:
  • the row driving circuit Inputting a test signal to a first stage row driving unit of the row driving circuit, the row driving circuit comprising a plurality of cascaded row driving units;
  • the row driving unit that operates abnormally is determined according to the output signals of all the row driving units.
  • the determining, according to an output signal of all the row driving units, determining a row driving unit that operates abnormally includes:
  • each row driving unit respectively, converting an output signal of the row driving unit into a pulse signal, and causing the pulse signal and the pulse signals corresponding to the other row driving units not to overlap each other;
  • a row driving unit that operates abnormally is determined.
  • the output signal of the row driving unit is converted into a pulse for each row driving unit, respectively. Punching the signal and making the pulse signal and the pulse signals corresponding to the other row driving units do not overlap each other, including:
  • a clock signal and an output signal corresponding to the row driving unit are NANDed to obtain the pulse signal.
  • determining, according to the superimposed signal, a row driving unit that operates abnormally includes:
  • the detecting method further includes displaying a waveform of the superimposed signal.
  • determining that the row driving circuit works abnormally includes:
  • the operating state of the row driving circuit is determined according to an output signal of the last-stage row driving unit.
  • the operating state of the row driving circuit includes two states in which the row driving circuit works normally and the row driving circuit operates abnormally.
  • the detecting device of the array substrate row driving circuit of the present invention determines the row driving unit that operates abnormally according to the output signal of each row driving unit obtained when the row driving circuit operates abnormally.
  • the present invention can determine abnormal operation when it is known that the row driving circuit is abnormal overall.
  • the position of the row driving unit is beneficial to improve the efficiency of line driving unit abnormality detection and analysis. It can be seen that the present invention can obtain more specific detection results, thereby facilitating the subsequent repair of the row driving circuit, and significantly shortening the troubleshooting and repair time of the row driving circuit defects.
  • FIG. 1 is a schematic structural view of a detecting device of a conventional array substrate row driving circuit
  • FIG. 2 is a schematic diagram showing an output waveform of a conventional array substrate row driving circuit
  • FIG. 3 is a schematic structural view of a detecting device of an array substrate row driving circuit according to a first embodiment of the present invention
  • FIG. 4 is a schematic structural diagram of a detecting module according to a second embodiment of the present invention.
  • FIG. 5 is a waveform diagram of a superimposed signal corresponding to a normal line driving circuit according to a second embodiment of the present invention, and A waveform diagram of a superimposed signal corresponding to an abnormal row driving circuit caused by a failure of the nth row driving unit;
  • FIG. 6 is a flow chart showing a method of detecting an array substrate row driving circuit according to a third embodiment of the present invention.
  • FIG. 7 is a flow chart showing a method of determining an abnormally operating row driving unit according to a fourth embodiment of the present invention.
  • FIG. 1 is a schematic structural view of a conventional detecting device for an array substrate row driving circuit.
  • the detecting device of the conventional array substrate row driving circuit includes an input module 101, an obtaining module 102, and a detecting module 103.
  • the input module 101 inputs a test signal for normally driving the row driving circuit 104 to the first-stage row driving unit of the array substrate row driving circuit 104 to enable the array substrate row driving circuit 104 to scan normally.
  • the acquisition module 102 acquires an output signal of the last stage row driving unit of the array substrate row driving circuit 104.
  • the detecting module 103 determines whether the structure of the entire array substrate row driving circuit 104 has a driving failure by detecting whether the waveform of the output signal of the last-stage row driving unit of the array substrate row driving circuit 104 is normal.
  • each row of row driving cells drives a gate line corresponding thereto, and a shift register is used to transfer the driving signals of the row driving cells of the first stage to the next row driving cells.
  • the left array substrate row driving circuit 104 and the right array substrate row driving circuit 104 are respectively disposed on both sides of the display region. That is, the row driving circuit 104 of the row driving unit including the odd rows is disposed on the left side of the display area, and the row driving circuit 104 of the row driving unit including the even rows is disposed on the right side of the display region.
  • the driving method of the interlaced scanning causes the left array substrate row driving circuit 104 and the right array substrate row driving circuit 104 to alternately output driving signals.
  • the detection method of the row driving circuit 104 in the prior art will be described below by taking the left array substrate row driving circuit 104 as an example.
  • the input module 101 is connected to the input terminal of the first-stage row driving unit of the row driving circuit 104 for inputting a test signal to the first-level row driving unit of the row driving circuit 104.
  • the row driving circuit 104 includes a plurality of cascaded row driving units, that is, a first-level row driving unit, a third-level row driving unit, a fifth-level row driving unit, ..., an n-th row driving unit, ..., 2N-1 row drive unit and 2N+1 row drive unit.
  • n represents the serial number of the row driving unit
  • n is an odd number in the interval [1, 2N+1]
  • 2N+1 represents the total number of row driving units that the row driving circuit 104 has.
  • FIG. 2 is a diagram showing the output waveform of the conventional array substrate row driving circuit 104.
  • U2D represents a forward scan signal
  • D2U represents a reverse scan signal
  • CK1 represents a first clock signal
  • CK3 represents a third clock signal
  • STV represents a frame start signal
  • GOA_OUT(1) represents a first stage row drive unit.
  • the output signal, GATE (1) represents the first row of gate signals
  • GOA_OUT (3) represents the output signal of the third-row row driver unit
  • GATE (3) represents the third row of gate signals
  • GOA_OUT (5) represents the fifth.
  • the output signal of the row row driving unit, GATE (5) represents the fifth row of gate signals.
  • the output signal of the last row driving unit of the side array substrate row driving circuit 104 is mainly subjected to waveform measurement to determine the side array substrate row driving circuit based on the measurement result. 104 working status. If the measurement result shows that there is no normal periodic square wave waveform (general frequency is 60 Hz) output, it is considered that the side array substrate row driving circuit 104 as a whole fails.
  • the method for detecting the right array substrate row driving circuit 104 is the same as the above detection method, and details are not described herein again.
  • the detection scheme of the array substrate row driving circuit 104 provided by the prior art generally only reflects the abnormality of the entire array substrate row driving circuit 104, and cannot determine the row driving unit in which the abnormality occurs, thereby increasing the abnormality analysis. Difficulty.
  • an embodiment of the present invention provides a detection apparatus and method for an array substrate row driving circuit.
  • the left array substrate row driver circuit and the right array substrate row driver circuit are separately detected.
  • the detection method used is the same. Therefore, the following description will be made by taking an example of detecting the left array substrate row driving circuit.
  • the detecting device mainly includes an input module 301, an obtaining module 302, and a detecting module 303.
  • the input module 301 is connected to the input terminal of the first-stage row driving unit of the row driving circuit 304 for inputting a test signal to the first-level row driving unit of the row driving circuit 304.
  • the row driving circuit 304 includes a plurality of cascaded row driving units, that is, a first-level row driving unit, a third-level row driving unit, a fifth-level row driving unit, ..., an n-th row driving unit, ..., 2N-1 row drive unit and 2N+1 row drive unit.
  • n represents the sequence number of the row drive unit
  • n is an odd number within the interval [1, 2N+1]
  • 2N+1 represents the total number of row drive units that the row drive circuit 304 has.
  • the acquisition module 302 is connected to the output terminals of the row driving units of the row driving circuit 304 for acquiring the output signals of the row driving units of each stage.
  • the detecting module 303 is connected to the obtaining module 302 for determining the row driving unit that operates abnormally according to the output signals of all the row driving units when determining that the traveling driving circuit 304 is abnormal.
  • the input module 301 inputs a test signal for normally driving the row driving circuit 304 to the first-stage row driving unit of the row driving unit 304 to enable the row driving circuit 304 to scan normally.
  • the test signal is a frame start signal.
  • the acquisition module 302 acquires an output signal of each row driving unit in the row driving circuit 304.
  • the detecting module 303 determines the row driving unit that operates abnormally in the row driving circuit 304 according to the output signals of all the row driving units in the row driving circuit 304.
  • the detecting module 303 may further include a determining unit 10 for determining an operating state of the row driving circuit 304 according to an output signal of the last row driving unit in the row driving circuit 304.
  • the operating state of the row driving circuit 304 refers to the overall operating state of the row driving circuit 304, which mainly reflects the normal operation or abnormal operation of the row driving circuit 304 as a whole.
  • the operational state of the row driver circuit 304 includes two states in which the row driver circuit 304 operates normally and the row driver circuit 304 operates abnormally.
  • the detection of the right array substrate row driving circuit 304 (not shown) is the same as the detection device and the detection method for detecting the left array substrate row driving circuit 304, and details are not described herein again.
  • the row driving unit of the abnormally operating row is determined according to the obtained output signal of each row driving unit.
  • the overall operation state of the row driving circuit 304 can be reflected only according to the output signal of the obtained last-level row driving unit.
  • This embodiment can further improve when the row driving circuit 304 is abnormal overall. Judging the position of the row driving unit that works abnormally is beneficial to improving the efficiency of abnormal detection and analysis of the row driving unit. It can be seen that the present embodiment can obtain more specific detection results, thereby facilitating the subsequent repair of the row driving circuit 304, and significantly shortening the troubleshooting and repair time of the row driving circuit 304.
  • the detecting device of the array substrate row driving circuit 304 of the present embodiment has practical guiding significance in the field of detecting technology of the display panel.
  • This embodiment further optimizes the structure of the detection module 303 in the first embodiment.
  • FIG. 4 is a schematic structural diagram of a detecting module 303 according to a second embodiment of the present invention.
  • the detecting module 303 of the present embodiment may include a superimposing unit 30, a determining unit 40, and a plurality of converting units 20.
  • Each of the conversion units 20 is connected to the acquisition module 302.
  • each of the conversion units 20 has a one-to-one correspondence with the first-level row driving unit, and is configured to convert the output signal of the row-row driving unit acquired by the obtaining module 302 into a pulse signal, and make the pulse signal correspond to the pulse of the other row driving unit.
  • the signals do not overlap each other.
  • the superimposing units 30 are respectively connected to the respective converting units 20 for superimposing the pulse signals output by all the converting units 20 to obtain superimposed signals.
  • the determining unit 40 is connected to the superimposing unit 30 for determining the row driving unit that operates abnormally according to the superimposed signal obtained by the superimposing unit 30.
  • the detecting device in this embodiment may further include a display module (not shown) for displaying the waveform of the superimposed signal, which is convenient for the worker to view.
  • the display module can intuitively display the waveform of the superimposed signal to the staff, so that the worker can quickly and intuitively know the row driving unit in which the abnormality occurs.
  • the method of the detection module 303 of the present embodiment for screening the abnormally operating row driving unit will be described in detail below.
  • each conversion unit 20 obtains an output signal of the corresponding row driving unit through the acquisition module 302.
  • the conversion unit 20 corresponding to the first-level row driving unit is configured to convert the output signal of the first-level row driving unit into a pulse signal.
  • the conversion unit 20 corresponding to the third-level row driving unit is configured to convert the output signal of the third-level row driving unit into a pulse signal.
  • the converting unit 20 corresponding to the 1919th row driving unit is configured to convert the output signal of the 1919th row driving unit into a pulse signal. Therefore, for the row driving circuit 304 of the present embodiment, a total of 960 pulse signals are obtained. And, importantly, these 960 pulse signals do not overlap each other.
  • the superimposing unit 30 superimposes the 960 non-overlapping pulse signals to obtain a superimposed signal.
  • the determining unit 40 determines the row driving unit that operates abnormally based on the obtained superimposed signal.
  • each conversion unit 20 includes a NAND gate circuit.
  • the NAND circuit is used for NANDing the clock signal and the output signal of the row driving unit each corresponding to the conversion unit 20 to obtain a pulse signal.
  • both the clock signal and the output signal correspond to a certain conversion unit 20. In this way, by the NAND operation here, it can be ensured that the pulse signals output by the respective conversion units 20 do not overlap each other, and the pulse signals output by the respective conversion units 20 are not overlapped.
  • the principle that the NAND circuit circuit obtains the pulse signals that do not overlap each other in this embodiment is: since the clock signals of the row driving units of the row driving circuit 304 in this embodiment do not overlap each other, the driving units of each row of the driving units are The pulse signals obtained by the NAND operation of the output signal through the NAND gate circuit and the corresponding clock signal also do not overlap each other.
  • the determining unit 40 is specifically configured to: determine a missing waveform in the superimposed signal, and determine the row driving unit corresponding to the missing waveform as the row driving unit that operates abnormally. The determination order will be specifically described below with reference to FIG. 5. The working principle of Yuan 40.
  • FIG. 5 is a waveform diagram showing a superimposed signal corresponding to the normal line driving circuit 304 of the second embodiment of the present invention, and a waveform diagram of a superimposed signal corresponding to the abnormal line driving circuit 304 due to the failure of the nth stage row driving unit.
  • the nth row driving unit operates abnormally, the nth row driving unit fails to output a corresponding output signal.
  • the row driving units are cascaded with each other, that is, the output signal of the upper row driving unit is used as the working trigger signal of the next row driving unit, the row driving unit after the nth stage (n+2 level)
  • the row driving unit to the 1919th row driving unit cannot output the corresponding output signals, which may cause the waveform corresponding to the nth row driving unit to the 1919th row driving unit to be missing.
  • the waveform corresponding to the nth row driving unit is missing, the waveform corresponding to the n+2th row driving unit is missing, and then the waveform corresponding to the n+4th row driving unit to the 1919th row driving unit is Missing.
  • the determining unit 40 can determine the row driving unit that operates abnormally based on the missing waveform in the superimposed signal. Referring to FIG. 5, since the waveform corresponding to the nth stage row driving unit to the 1999th row driving unit is missing in the superimposed signal, it can be determined that the superimposed signal is missing from the nth row driving unit, thereby The row drive unit that derives the abnormal operation is the nth row drive unit.
  • the output signals of the row driving units of each level are converted into pulse signals that do not overlap each other, and then superimposed according to the respective pulse signals.
  • the missing waveform in the superimposed signal is used to determine the row driver unit for abnormal operation. It can be seen that the structure of the detecting module 303 of the embodiment is simple, and provides intuitive and accurate data support for accurately and effectively determining the row driving unit that operates abnormally.
  • a method for detecting the array substrate row driving circuit 304 is further provided in the embodiment of the present invention.
  • the left array substrate row driving circuit 304 is taken as an example for description.
  • FIG. 6 is a flow chart showing a method of detecting an array substrate row driving circuit 304 according to a third embodiment of the present invention. As shown in FIG. 6, the detecting method may include the following steps S610, S620, and S630.
  • step S610 a test signal is input to the first stage row driving unit of the row driving circuit 304.
  • the row driving circuit 304 includes a plurality of cascaded row driving units.
  • step S620 output signals of the respective row driving units are acquired.
  • step S630 when it is determined that the line driving circuit 304 is operating abnormally, the row driving unit that operates abnormally is determined based on the output signals of all the row driving units.
  • step S630 further includes determining an operational state of row drive circuit 304 based on an output signal of the last stage row drive unit.
  • the detection method of the array substrate row driving circuit 304 of the embodiment of the present invention is used to determine the row driving unit that operates abnormally according to the output signal of each row driving unit obtained when the row driving circuit 304 operates abnormally.
  • the overall operation state of the row driving circuit 304 can be reflected only according to the output signal of the obtained last-level row driving unit.
  • This embodiment can further improve when the row driving circuit 304 is abnormal overall. Judging the position of the row driving unit that works abnormally is beneficial to improving the efficiency of abnormal detection and analysis of the row driving unit. It can be seen that the present embodiment can obtain more specific detection results, thereby facilitating the subsequent repair of the row driving circuit 304, and significantly shortening the troubleshooting and repair time of the row driving circuit 304.
  • This embodiment further optimizes step S630 in the third embodiment.
  • FIG. 7 is a flow chart showing a method of determining an abnormally operating row driving unit according to a fourth embodiment of the present invention.
  • the method is for determining a row driving unit that operates abnormally according to an output signal of all row driving units. As shown in FIG. 7, the method may include the following steps S710, S720, and S730.
  • step S710 for each row driving unit, the output signal of the row driving unit is converted into a pulse signal, and the pulse signals corresponding to the pulse driving signals and the other row driving units are not overlapped with each other.
  • step S710 includes: performing a NAND operation on the clock signal and the output signal corresponding to the row driving unit for each row driving unit, respectively, to obtain a pulse signal.
  • step S720 the pulse signals corresponding to all the row driving units are superimposed to obtain a superimposed signal.
  • step S730 based on the superimposed signal, the row driving unit that operates abnormally is determined.
  • step S730 includes: determining a missing waveform in the superimposed signal, and determining the row driving unit corresponding to the missing waveform as the row driving unit that operates abnormally.
  • step S730 further includes displaying a waveform of the superimposed signal for viewing by a worker.
  • the present embodiment can intuitively visualize the waveform of the superimposed signal to the worker, so that the worker can quickly and intuitively know the row driving unit in which the abnormality occurs.
  • modules or steps of the present invention described above can be implemented by a general-purpose computing device, which can be centralized on a single computing device or distributed over a network of multiple computing devices. Alternatively, they may be implemented by program code executable by the computing device, such that they may be stored in a storage device by a computing device, or they may be fabricated into individual integrated circuit modules, or many of them Modules or steps are made into a single integrated circuit module. Thus, the invention is not limited to any specific combination of hardware and software.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

一种阵列基板行驱动电路的检测装置及方法，该检测装置包括：输入模块，用于向行驱动电路第一级行驱动单元输入测试信号；获取模块，用于获取各行驱动单元的输出信号；检测模块，用于在判断出行驱动电路工作异常时，根据所有行驱动单元的输出信号确定异常工作的行驱动单元。本发明能判断出异常工作的行驱动单元。

Description

阵列基板行驱动电路的检测装置及方法
本申请要求享有2017年02月13日提交的名称为“阵列基板行驱动电路的检测装置及方法”的中国专利申请CN201710075519.X的优先权，其全部内容通过引用并入本文中。
技术领域
本发明涉及显示面板的检测技术领域，尤其涉及一种阵列基板行驱动电路的检测装置及方法。
背景技术
近年来，LTPS(Low Temperature Poly-Silicon，低温多晶硅)技术广泛应用于较高端的手机及平板电脑产品。由于具有低功耗、高反应速率、高开口率等优点，LTPS技术已成为研发高PPI(pixels per inch，每英寸所拥有的像素数目)产品过程中不可缺少的重要技术之一。为了提高生产效率及生产良率，对LTPS产品的制程及半成品的监控和检测是必不可少的。
目前，低温多晶硅产品制程的拦检机制主要包括电性检测和光学检测等等。电性检测包括阵列基板检测。阵列基板检测的主要检测项目包括：低温多晶硅产品的阵列基板行驱动电路、栅极线和数据线等。
现有技术中的阵列基板行驱动电路的检测装置的缺陷在于：该检测装置只能反映阵列基板行驱动电路整体的异常，而不能进一步确定发生异常的行驱动单元，从而加大了对异常解析的难度。
发明内容
为了解决上述技术问题，本发明提供了一种阵列基板行驱动电路的检测装置及方法。
根据本发明的一个方面，提供了一种阵列基板行驱动电路的检测装置，其包括：
输入模块，用于向所述行驱动电路的第一级行驱动单元输入测试信号，所述行驱动电路包括多个级联的行驱动单元；
获取模块，用于获取各个行驱动单元的输出信号；
检测模块，用于在判断出所述行驱动电路工作异常时，根据所有行驱动单元的输出信号，确定异常工作的行驱动单元。
在一个实施例中，所述检测模块包括多个转换单元；
其中，每个转换单元与一级行驱动单元相对应，用于将该级行驱动单元的输出信号转换成脉冲信号，并使所述脉冲信号与其它行驱动单元对应的脉冲信号互不交叠；
叠加单元，用于将所有转换单元输出的脉冲信号进行叠加，得到叠加信号；
确定单元，用于根据所述叠加信号，确定异常工作的行驱动单元。
在一个实施例中，所述转换单元包括与非门电路，所述与非门电路用于将所述转换单元对应的行驱动单元的时钟信号和输出信号进行与非运算，得到所述脉冲信号。
在一个实施例中，所述确定单元具体用于：确定所述叠加信号中的缺失波形，并将所述缺失波形对应的行驱动单元确定为所述异常工作的行驱动单元。
在一个实施例中，还包括显示模块，用于显示所述叠加信号的波形。
在一个实施例中，所述检测模块还包括：
判断单元，用于根据最后一级行驱动单元的输出信号，确定所述行驱动电路的工作状态。
根据本发明的另一方面，还提供了一种阵列基板行驱动电路的检测方法，其包括：
向所述行驱动电路的第一级行驱动单元输入测试信号，所述行驱动电路包括多个级联的行驱动单元；
获取各个行驱动单元的输出信号；
在判断出所述行驱动电路工作异常时，根据所有行驱动单元的输出信号，确定异常工作的行驱动单元。
在一个实施例中，所述根据所有行驱动单元的输出信号，确定异常工作的行驱动单元，包括：
分别对于每个行驱动单元，将所述行驱动单元的输出信号转换成脉冲信号，并使所述脉冲信号与其它行驱动单元对应的脉冲信号互不交叠；
将所有行驱动单元对应的脉冲信号进行叠加，得到叠加信号；
根据所述叠加信号，确定异常工作的行驱动单元。
在一个实施例中，分别对于每个行驱动单元，将所述行驱动单元的输出信号转换成脉 冲信号，并使所述脉冲信号与其它行驱动单元对应的脉冲信号互不交叠，包括：
分别对于每个行驱动单元，将均与所述行驱动单元对应的时钟信号和输出信号进行与非运算，得到所述脉冲信号。
在一个实施例中，根据所述叠加信号，确定异常工作的行驱动单元，包括：
确定所述叠加信号中的缺失波形，并将所述缺失波形对应的行驱动单元确定为所述异常工作的行驱动单元。
在一个实施例中，上述检测方法还包括显示所述叠加信号的波形。
在一个实施例中，判断所述行驱动电路工作异常，包括：
根据最后一级行驱动单元的输出信号，确定所述行驱动电路的工作状态。这里，行驱动电路的工作状态包括行驱动电路工作正常和行驱动电路工作异常两个状态。
与现有技术相比，本发明的一个或多个实施例可以具有如下优点：
应用本发明的阵列基板行驱动电路的检测装置，在行驱动电路工作异常时，根据获取的每一个行驱动单元的输出信号来确定异常工作的行驱动单元。相较于现有技术中只能根据获取的最后一级行驱动单元的输出信号来反映行驱动电路整体工作状态的方案来说，本发明在得知行驱动电路整体异常时，能够判断出异常工作的行驱动单元的位置，有利于提高行驱动单元异常检测与解析的效率。可见，本发明能够得到更为具体的检测结果，从而有利于后续对行驱动电路的修复，显著缩短了行驱动电路缺陷的排查及修复时间。
本发明的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本发明而了解。本发明的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
附图说明
附图用来提供对本发明的进一步理解，并且构成说明书的一部分，与本发明的实施例共同用于解释本发明，并不构成对本发明的限制。在附图中：
图1是现有的阵列基板行驱动电路的检测装置的结构示意图；
图2是现有的阵列基板行驱动电路的输出波形示意图；
图3是根据本发明第一实施例的阵列基板行驱动电路的检测装置的结构示意图；
图4是根据本发明第二实施例的检测模块的结构示意图；
图5是根据本发明第二实施例的正常行驱动电路对应的叠加信号的波形示意图，以及 由于第n级行驱动单元失效而导致的异常行驱动电路对应的叠加信号的波形示意图；
图6是根据本发明第三实施例的阵列基板行驱动电路的检测方法的流程示意图；
图7是根据本发明第四实施例的异常工作的行驱动单元的确定方法的流程示意图。
具体实施方式
以下将结合附图及实施例来详细说明本发明的实施方式，借此对本发明如何应用技术手段来解决技术问题，并达成技术效果的实现过程能充分理解并据以实施。需要说明的是，只要不构成冲突，本发明中的各个实施例以及各实施例中的各个特征可以相互结合，所形成的技术方案均在本发明的保护范围之内。
图1为现有的阵列基板行驱动电路的检测装置的结构示意图。如图1所示，现有的阵列基板行驱动电路的检测装置包括输入模块101、获取模块102和检测模块103。
具体地，输入模块101向阵列基板行驱动电路104的第一级行驱动单元输入用于正常驱动该行驱动电路104的测试信号，以使阵列基板行驱动电路104能够正常扫描。获取模块102获取阵列基板行驱动电路104的最后一级行驱动单元的输出信号。检测模块103通过检测阵列基板行驱动电路104的最后一级行驱动单元的输出信号的波形是否正常，来判断整个阵列基板行驱动电路104的结构是否存在驱动不良。
在现有的阵列基板行驱动电路104中，每级行驱动单元驱动与之对应的一条栅极线，并且采用移位寄存器将本级行驱动单元的驱动信号传递至下一级行驱动单元。一般来讲，将左侧阵列基板行驱动电路104和右侧阵列基板行驱动电路104分别设置在显示区域的两侧。即，将包括奇数行的行驱动单元的行驱动电路104设置在显示区域的左侧，将包括偶数行的行驱动单元的行驱动电路104设置在显示区域的右侧。采用隔行扫描的驱动方式，使左侧阵列基板行驱动电路104和右侧阵列基板行驱动电路104交替输出驱动信号。
下面以左侧阵列基板行驱动电路104为例，来说明现有技术中行驱动电路104的检测方法。
具体地，输入模块101与行驱动电路104的第一级行驱动单元的输入端相连，用于向行驱动电路104的第一级行驱动单元输入测试信号。这里，行驱动电路104包括多个级联的行驱动单元，即第一级行驱动单元、第三级行驱动单元、第五级行驱动单元、…、第n级行驱动单元、…、第2N-1级行驱动单元、第2N+1级行驱动单元。其中n表示行驱动单元的序号，n为区间[1,2N+1]内的奇数，2N+1表示该行驱动电路104具有的行驱动单元的总数。
图2示出了现有的阵列基板行驱动电路104的输出波形示意图。在图2中，U2D表示正向扫描信号，D2U表示反向扫描信号，CK1表示第一时钟信号、CK3表示第三时钟信号，STV表示帧开始信号，GOA_OUT(1)表示第一级行驱动单元的输出信号，GATE(1)表示第一行栅极信号，GOA_OUT(3)表示第三级行驱动单元的输出信号，GATE(3)表示第三行栅极信号，GOA_OUT(5)表示第五级行驱动单元的输出信号，GATE(5)表示第五行栅极信号。在对左侧阵列基板行驱动电路104进行检测时，主要对该侧阵列基板行驱动电路104的最后一级行驱动单元的输出信号进行波形测量，以基于测量结果确定该侧阵列基板行驱动电路104的工作状态。若测量结果显示没有正常的周期方波波形(一般频率为60Hz)输出，则认为该侧阵列基板行驱动电路104整体失效。
对右侧阵列基板行驱动电路104进行检测的方法与上述检测方法雷同，在此不再赘述。
可见，现有技术提供的阵列基板行驱动电路104的检测方案一般只能反映出阵列基板行驱动电路104整体的异常，而不能确定具体发生异常的行驱动单元，从而加大了对异常解析的难度。
为了解决上述技术问题，本发明实施例提供了一种阵列基板行驱动电路的检测装置及方法。
第一实施例
一般来说，左侧阵列基板行驱动电路和右侧阵列基板行驱动电路是分开检测的。所用的检测方法相同。因此，下面以检测左侧阵列基板行驱动电路为例进行说明。
图3为根据本发明第一实施例的阵列基板行驱动电路(这里，为左侧阵列基板行驱动电路，简称行驱动电路)的检测装置的结构示意图。如图3所示，检测装置主要包括输入模块301、获取模块302和检测模块303。
具体地，输入模块301与行驱动电路304的第一级行驱动单元的输入端相连，用于向行驱动电路304的第一级行驱动单元输入测试信号。这里，行驱动电路304包括多个级联的行驱动单元，即第一级行驱动单元、第三级行驱动单元、第五级行驱动单元、…、第n级行驱动单元、…、第2N-1级行驱动单元、第2N+1级行驱动单元。其中n表示行驱动单元的序号，n为区间[1,2N+1]内的奇数，2N+1表示该行驱动电路304具有的行驱动单元的总数。
获取模块302与行驱动电路304的各级行驱动单元的输出端相连，用于获取各级行驱动单元的输出信号。
检测模块303与获取模块302相连，用于在判断出行驱动电路304工作异常时，根据所有级行驱动单元的输出信号，确定异常工作的行驱动单元。
以下详细说明本实施例的阵列基板行驱动电路304的检测装置的检测原理。首先，输入模块301向行驱动单元304的第一级行驱动单元输入用于正常驱动该行驱动电路304的测试信号，以使行驱动电路304能够正常扫描。这里，测试信号为帧开始信号。获取模块302获取行驱动电路304中各个行驱动单元的输出信号。检测模块303在判断出行驱动电路304工作异常时，根据该行驱动电路304中所有级行驱动单元的输出信号，确定该行驱动电路304中异常工作的行驱动单元。
在一个优选的实施例中，检测模块303还可以包括判断单元10，其用于根据行驱动电路304中最后一级行驱动单元的输出信号来确定该行驱动电路304的工作状态。这里，行驱动电路304的工作状态指的是行驱动电路304整体的工作状态，其主要反映行驱动电路304整体正常工作或异常工作。换句话说，行驱动电路304的工作状态包括行驱动电路304工作正常和行驱动电路304工作异常两个状态。
检测右侧阵列基板行驱动电路304(图中未显出)与检测左侧阵列基板行驱动电路304的检测装置及检测方法相同，这里不再赘述。
应用本实施例的阵列基板行驱动电路304的检测装置，在行驱动电路304工作异常时，根据获取的每一个行驱动单元的输出信号来确定异常工作的行驱动单元。相较于现有技术中只能根据获取的最后一级行驱动单元的输出信号来反映行驱动电路304整体工作状态的方案来说，本实施例在得知行驱动电路304整体异常时，能够进一步判断出异常工作的行驱动单元的位置，有利于提高行驱动单元异常检测与解析的效率。可见，本实施例能够得到更为具体的检测结果，从而有利于后续对行驱动电路304的修复，显著缩短了行驱动电路304缺陷的排查及修复时间。
综上所述，本实施例的阵列基板行驱动电路304的检测装置，在显示面板的检测技术领域中具有实际的指导意义。
第二实施例
本实施例对实施例一中的检测模块303的结构做了进一步优化。
图4为根据本发明第二实施例的检测模块303的结构示意图。如图4所示，本实施例的检测模块303可以包括叠加单元30、确定单元40和多个转换单元20。其中，每个转换单元20都与获取模块302相连。并且，每个转换单元20与一级行驱动单元一一对应，用于将获取模块302获取的该级行驱动单元的输出信号转换成脉冲信号，并使脉冲信号与其它行驱动单元对应的脉冲信号互不交叠。叠加单元30分别与各个转换单元20相连，用于将所有转换单元20输出的脉冲信号进行叠加，得到叠加信号。确定单元40与叠加单元30相连，用于根据叠加单元30得到的叠加信号，确定异常工作的行驱动单元。
本实施例中的检测装置还可以包括显示模块(图中未示出)，用于显示叠加信号的波形，便于工作人员查看。这里，显示模块能够直观地向工作人员展现叠加信号的波形，以方便工作人员快速直观地知晓出现异常的行驱动单元。
下面详细说明本实施例的检测模块303筛查异常工作的行驱动单元的方法。
如图4所示，每个转换单元20通过获取模块302得到相应行驱动单元的输出信号。具体地，在第一扫描周期内，第一级行驱动单元对应的转换单元20，用于将第一级行驱动单元的输出信号转换成一个脉冲信号。在第三扫描周期内，第三级行驱动单元对应的转换单元20，用于将第三级行驱动单元的输出信号转换成一个脉冲信号。假设一共有1920级行驱动单元，依此类推，第1919级行驱动单元对应的转换单元20，用于将第1919级行驱动单元的输出信号转换成一个脉冲信号。因此，对于本实施例的行驱动电路304来说，一共得到960个脉冲信号。并且，重要地，这960个脉冲信号互不交叠。叠加单元30将这960个互不交叠的脉冲信号进行叠加，得到一个叠加信号。确定单元40根据得到的该叠加信号确定异常工作的行驱动单元。
在一个优选的实施例中，每个转换单元20包括与非门电路。与非门电路用于将均与该转换单元20相对应的行驱动单元的时钟信号和输出信号进行与非运算，得到脉冲信号。此处，时钟信号和输出信号均与某一个转换单元20相对应。这样，通过此处的与非运算，可保证各个转换单元20输出的脉冲信号彼此无交集，即可保证各个转换单元20输出的脉冲信号互不交叠。
本实施例采用与非门电路得到互不交叠的脉冲信号的原理是：由于本实施例行驱动电路304中的各级行驱动单元的时钟信号互不交叠，因此各级行驱动单元的输出信号通过与非门电路和对应的时钟信号进行与非运算后得到的脉冲信号也互不交叠。
在一个优选的实施例中，确定单元40具体用于：确定叠加信号中的缺失波形，并将缺失波形对应的行驱动单元确定为异常工作的行驱动单元。下面参照图5具体说明确定单 元40的工作原理。
图5示出了本发明第二实施例的正常行驱动电路304对应的叠加信号的波形示意图，以及由于第n级行驱动单元失效而导致的异常行驱动电路304对应的叠加信号的波形示意图。当第n级行驱动单元工作异常时，该第n级行驱动单元未能输出相应的输出信号。由于行驱动单元彼此之间都是级联的，即上一级行驱动单元的输出信号作为下一级行驱动单元的工作触发信号，因此第n级之后的行驱动单元(第n+2级行驱动单元至第1919级行驱动单元)均无法输出相应的输出信号，从而会导致第n级行驱动单元至第1919级行驱动单元对应的波形的缺失。如图5所示，第n级行驱动单元对应的波形缺失，第n+2级行驱动单元对应的波形缺失，之后第n+4级行驱动单元至第1919级行驱动单元对应的波形均缺失。由于脉冲信号互不交叠，因此能够直观地从叠加信号中确定缺失波形及其相对应的行驱动单元。这样，确定单元40可以根据叠加信号中的缺失波形来确定工作异常的行驱动单元。参照图5，由于在叠加信号中，与第n级行驱动单元至第1999级行驱动单元对应的波形都缺失，因此可以确定叠加信号是从第n级行驱动单元处开始缺失的，从而可以推导出异常工作的行驱动单元为第n级行驱动单元。
应用本实施例的检测模块303，巧妙地利用时钟信号及与非门电路的特点，将各级行驱动单元的输出信号转换成互不交叠的脉冲信号，然后再根据由各个脉冲信号叠加而成的叠加信号中的缺失波形，来确定异常工作的行驱动单元。可见，本实施例检测模块303的结构简单，为准确有效地确定异常工作的行驱动单元提供了直观精确的数据支持。
第三实施例
基于同一发明构思，本发明实施例中还提供了一种阵列基板行驱动电路304的检测方法。同样地，本实施例仍以左侧阵列基板行驱动电路304为例进行说明。
图6为根据本发明第三实施例的阵列基板行驱动电路304的检测方法的流程示意图。如图6所示，该检测方法可以包括如下步骤S610、步骤S620和步骤S630。
在步骤S610中，向行驱动电路304的第一级行驱动单元输入测试信号。这里，行驱动电路304包括多个级联的行驱动单元。
在步骤S620中，获取各个行驱动单元的输出信号。
在步骤S630中，在判断出行驱动电路304工作异常时，根据所有行驱动单元的输出信号，确定异常工作的行驱动单元。
在一个优选的实施例中，步骤S630还包括根据最后一级行驱动单元的输出信号，确定行驱动电路304的工作状态。
应用本发明实施例的阵列基板行驱动电路304的检测方法，在行驱动电路304工作异常时，根据获取的每一个行驱动单元的输出信号来确定异常工作的行驱动单元。相较于现有技术中只能根据获取的最后一级行驱动单元的输出信号来反映行驱动电路304整体工作状态的方案来说，本实施例在得知行驱动电路304整体异常时，能够进一步判断出异常工作的行驱动单元的位置，有利于提高行驱动单元异常检测与解析的效率。可见，本实施例能够得到更为具体的检测结果，从而有利于后续对行驱动电路304的修复，显著缩短了行驱动电路304缺陷的排查及修复时间。
第四实施例
本实施例对第三实施例中步骤S630做的进一步优化。
图7为根据本发明第四实施例的异常工作的行驱动单元的确定方法的流程示意图。该方法用于根据所有行驱动单元的输出信号，确定异常工作的行驱动单元。如图7所示，该方法可以包括如下步骤S710、步骤S720和步骤S730。
在步骤S710中，分别对于每个行驱动单元，将行驱动单元的输出信号转换成脉冲信号，并使脉冲信号与其它行驱动单元对应的脉冲信号互不交叠。
具体地，步骤S710包括：分别对于每个行驱动单元，将均与行驱动单元对应的时钟信号和输出信号进行与非运算，得到脉冲信号。
在步骤S720中，将所有行驱动单元对应的脉冲信号进行叠加，得到叠加信号。
在步骤S730中，根据叠加信号，确定异常工作的行驱动单元。
具体地，步骤S730包括：确定叠加信号中的缺失波形，并将缺失波形对应的行驱动单元确定为异常工作的行驱动单元。
在一个优选的实施例中，步骤S730还包括显示叠加信号的波形，以便于工作人员查看。这里，本实施例能够直观地向工作人员显现叠加信号的波形，以方便工作人员快速直观地知晓出现异常的行驱动单元。
应用本实施例的确定异常工作的行驱动单元的方法，巧妙地利用时钟信号及与非门电路的特点，将各级行驱动单元的输出信号转换成互不交叠的脉冲信号，然后再根据由各个脉冲信号叠加而成的叠加信号中的缺失波形，来确定异常工作的行驱动单元。可见，本实 施例的方法简单，为准确有效地确定异常工作的行驱动单元提供了直观精确的数据支持。
上述各步骤中的具体细化，可参见上面结合图1至图5对本发明检测装置的说明，在此不再详细赘述。
本领域的技术人员应该明白，上述的本发明的各模块或各步骤可以用通用的计算装置来实现，它们可以集中在单个的计算装置上，或者分布在多个计算装置所组成的网络上，可选地，它们可以用计算装置可执行的程序代码来实现，从而，可以将它们存储在存储装置中由计算装置来执行，或者将它们分别制作成各个集成电路模块，或者将它们中的多个模块或步骤制作成单个集成电路模块来实现。这样，本发明不限制于任何特定的硬件和软件结合。
以上所述，仅为本发明的具体实施案例，本发明的保护范围并不局限于此，任何熟悉本技术的技术人员在本发明所述的技术规范内，对本发明的修改或替换，都应在本发明的保护范围之内。

Claims (20)

  1. 一种阵列基板行驱动电路的检测装置，包括：
    输入模块，用于向所述行驱动电路的第一级行驱动单元输入测试信号，所述行驱动电路包括多个级联的行驱动单元；
    获取模块，用于获取各个行驱动单元的输出信号；
    检测模块，用于在判断出所述行驱动电路工作异常时，根据所有行驱动单元的输出信号，确定异常工作的行驱动单元。
  2. 根据权利要求1所述的检测装置，其中，所述检测模块包括：
    多个转换单元，其中，每个转换单元与一级行驱动单元相对应，用于将该级行驱动单元的输出信号转换成脉冲信号，并使所述脉冲信号与其它行驱动单元对应的脉冲信号互不交叠；
    叠加单元，用于将所有转换单元输出的脉冲信号进行叠加，得到叠加信号；
    确定单元，用于根据所述叠加信号，确定异常工作的行驱动单元。
  3. 根据权利要求2所述的检测装置，其中，所述转换单元包括与非门电路，所述与非门电路用于将所述转换单元对应的行驱动单元的时钟信号和输出信号进行与非运算，得到所述脉冲信号。
  4. 根据权利要求2所述的检测装置，其中，所述确定单元具体用于：确定所述叠加信号中的缺失波形，并将所述缺失波形对应的行驱动单元确定为所述异常工作的行驱动单元。
  5. 根据权利要求3所述的检测装置，其中，所述确定单元具体用于：确定所述叠加信号中的缺失波形，并将所述缺失波形对应的行驱动单元确定为所述异常工作的行驱动单元。
  6. 根据权利要求2所述的检测装置，其中，还包括显示模块，用于显示所述叠加信号的波形。
  7. 根据权利要求3所述的检测装置，其中，还包括显示模块，用于显示所述叠加信号的波形。
  8. 根据权利要求4所述的检测装置，其中，还包括显示模块，用于显示所述叠加信号的波形。
  9. 根据权利要求5所述的检测装置，其中，还包括显示模块，用于显示所述叠加信号的波形。
  10. 根据权利要求2所述的检测装置，其中，所述检测模块还包括：
    判断单元，用于根据最后一级行驱动单元的输出信号，确定所述行驱动电路的工作状态。
  11. 根据权利要求3所述的检测装置，其中，所述检测模块还包括：
    判断单元，用于根据最后一级行驱动单元的输出信号，确定所述行驱动电路的工作状态。
  12. 根据权利要求4所述的检测装置，其中，所述检测模块还包括：
    判断单元，用于根据最后一级行驱动单元的输出信号，确定所述行驱动电路的工作状态。
  13. 根据权利要求5所述的检测装置，其中，所述检测模块还包括：
    判断单元，用于根据最后一级行驱动单元的输出信号，确定所述行驱动电路的工作状态。
  14. 根据权利要求6所述的检测装置，其中，所述检测模块还包括：
    判断单元，用于根据最后一级行驱动单元的输出信号，确定所述行驱动电路的工作状态。
  15. 根据权利要求7所述的检测装置，其中，所述检测模块还包括：
    判断单元，用于根据最后一级行驱动单元的输出信号，确定所述行驱动电路的工作状态。
  16. 一种阵列基板行驱动电路的检测方法，包括：
    向所述行驱动电路的第一级行驱动单元输入测试信号，所述行驱动电路包括多个级联的行驱动单元；
    获取各个行驱动单元的输出信号；
    在判断出所述行驱动电路工作异常时，根据所有行驱动单元的输出信号，确定异常工作的行驱动单元。
  17. 根据权利要求16所述的检测方法，其中，所述根据所有行驱动单元的输出信号，确定异常工作的行驱动单元，包括：
    分别对于每个行驱动单元，将所述行驱动单元的输出信号转换成脉冲信号，并使所述脉冲信号与其它行驱动单元对应的脉冲信号互不交叠；
    将所有行驱动单元对应的脉冲信号进行叠加，得到叠加信号；
    根据所述叠加信号，确定异常工作的行驱动单元。
  18. 根据权利要求17所述的检测方法，其中，分别对于每个行驱动单元，将所述行驱动单元的输出信号转换成脉冲信号，并使所述脉冲信号与其它行驱动单元对应的脉冲信号互不交叠，包括：
    分别对于每个行驱动单元，将均与所述行驱动单元对应的时钟信号和输出信号进行与非运算，得到所述脉冲信号。
  19. 根据权利要求17所述的检测方法，其中，根据所述叠加信号，确定异常工作的行驱动单元，包括：
    确定所述叠加信号中的缺失波形，并将所述缺失波形对应的行驱动单元确定为所述异常工作的行驱动单元。
  20. 根据权利要求18所述的检测方法，其中，根据所述叠加信号，确定异常工作的行驱动单元，包括：
    确定所述叠加信号中的缺失波形，并将所述缺失波形对应的行驱动单元确定为所述异常工作的行驱动单元。
PCT/CN2017/075084 2017-02-13 2017-02-28 阵列基板行驱动电路的检测装置及方法 Ceased WO2018145335A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/519,347 US20190385500A1 (en) 2017-02-13 2017-02-28 Detection device and method for array substrate row drive circuit

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201710075519.XA CN106782252B (zh) 2017-02-13 2017-02-13 阵列基板行驱动电路的检测装置及方法
CN201710075519.X 2017-02-13

Publications (1)

Publication Number Publication Date
WO2018145335A1 true WO2018145335A1 (zh) 2018-08-16

Family

ID=58955847

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/075084 Ceased WO2018145335A1 (zh) 2017-02-13 2017-02-28 阵列基板行驱动电路的检测装置及方法

Country Status (3)

Country Link
US (1) US20190385500A1 (zh)
CN (1) CN106782252B (zh)
WO (1) WO2018145335A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020160104A (ja) * 2019-03-25 2020-10-01 セイコーエプソン株式会社 駆動回路、電気光学装置、電気光学装置を備える電子機器、及び電子機器を備える移動体

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111724724A (zh) * 2020-07-23 2020-09-29 谊美吉斯光电科技（福建）有限公司 一种led显示屏故障监测模块、检测系统及检测方法
CN117746771A (zh) * 2024-01-29 2024-03-22 厦门天马微电子有限公司 显示面板、其控制方法及显示装置

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1505289A (zh) * 2002-12-03 2004-06-16 深圳市中兴通讯股份有限公司 一种数据信号检测装置
US20040119824A1 (en) * 2002-12-18 2004-06-24 Semiconductor Energy Laboratory Co., Ltd. Image display device and testing method of the same
CN1681234A (zh) * 2004-04-10 2005-10-12 鸿富锦精密工业（深圳）有限公司 数据传输的正确性检查系统及方法
CN1764845A (zh) * 2003-03-25 2006-04-26 株式会社半导体能源研究所 半导体装置和检查电路及检查方法
CN1801264A (zh) * 2004-12-06 2006-07-12 株式会社半导体能源研究所 测试电路及具有该测试电路的显示装置
CN101038315A (zh) * 2006-03-16 2007-09-19 统宝光电股份有限公司 平面显示器的扫描检测装置与方法
CN102930808A (zh) * 2011-08-08 2013-02-13 联咏科技股份有限公司 显示面板驱动装置与其操作方法以及其源极驱动器

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6462433B1 (en) * 1998-08-13 2002-10-08 Toshiba Tec Kabushiki Kaisha Capacitive load driving unit and method and apparatus for inspecting the same
US9391528B2 (en) * 2012-12-27 2016-07-12 Fairchild (Taiwan) Corporation Active clamp circuits for flyback power converters
CN203325416U (zh) * 2013-07-03 2013-12-04 深圳市华星光电技术有限公司 阵列基板行驱动电路
CN103310755B (zh) * 2013-07-03 2016-01-13 深圳市华星光电技术有限公司 阵列基板行驱动电路
CN103745706B (zh) * 2013-12-31 2016-01-06 深圳市华星光电技术有限公司 三阶驱动的阵列基板行驱动电路
CN104680963A (zh) * 2015-03-26 2015-06-03 京东方科技集团股份有限公司 一种显示面板goa电路的检测装置和检测方法
CN105321453A (zh) * 2015-12-01 2016-02-10 武汉华星光电技术有限公司 显示面板以及显示装置
CN106297641A (zh) * 2016-10-18 2017-01-04 深圳市华星光电技术有限公司 一种阵列基板行驱动电路及显示面板

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1505289A (zh) * 2002-12-03 2004-06-16 深圳市中兴通讯股份有限公司 一种数据信号检测装置
US20040119824A1 (en) * 2002-12-18 2004-06-24 Semiconductor Energy Laboratory Co., Ltd. Image display device and testing method of the same
CN1764845A (zh) * 2003-03-25 2006-04-26 株式会社半导体能源研究所 半导体装置和检查电路及检查方法
CN1681234A (zh) * 2004-04-10 2005-10-12 鸿富锦精密工业（深圳）有限公司 数据传输的正确性检查系统及方法
CN1801264A (zh) * 2004-12-06 2006-07-12 株式会社半导体能源研究所 测试电路及具有该测试电路的显示装置
CN101038315A (zh) * 2006-03-16 2007-09-19 统宝光电股份有限公司 平面显示器的扫描检测装置与方法
CN102930808A (zh) * 2011-08-08 2013-02-13 联咏科技股份有限公司 显示面板驱动装置与其操作方法以及其源极驱动器

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020160104A (ja) * 2019-03-25 2020-10-01 セイコーエプソン株式会社 駆動回路、電気光学装置、電気光学装置を備える電子機器、及び電子機器を備える移動体
CN111739454A (zh) * 2019-03-25 2020-10-02 精工爱普生株式会社 驱动电路、电光装置、电子设备以及移动体
JP7268436B2 (ja) 2019-03-25 2023-05-08 セイコーエプソン株式会社 駆動回路、電気光学装置、電気光学装置を備える電子機器、及び電子機器を備える移動体

Also Published As

Publication number Publication date
CN106782252B (zh) 2019-11-26
CN106782252A (zh) 2017-05-31
US20190385500A1 (en) 2019-12-19

Similar Documents

Publication Publication Date Title
CN109243347B (zh) 栅极驱动器的检测电路及显示装置
CN105590607B (zh) 栅极驱动电路及其检测方法、阵列基板、显示装置
CN110299110B (zh) 栅极驱动电路的驱动方法及栅极驱动电路、显示装置
CN104183225B (zh) 一种驱动装置、阵列基板和显示装置
US10916170B2 (en) Gate driving circuit for detecting scanning signal abnormalities and driving method thereof
CN106448522A (zh) 检测电路、栅极驱动电路及显示面板
WO2019242514A1 (zh) 栅极驱动信号检测电路、方法和显示装置
CN105575301A (zh) 阵列基板、信号线检测方法、显示面板及显示装置
CN107065247A (zh) 一种显示面板检测方法、装置及系统
WO2017118212A1 (zh) 显示面板测试方法及测试装置
WO2018145335A1 (zh) 阵列基板行驱动电路的检测装置及方法
CN104700762A (zh) 阵列基板、显示面板、弯曲程度检测方法
WO2015027604A1 (zh) 液晶面板的亮点检测方法
CN104680963A (zh) 一种显示面板goa电路的检测装置和检测方法
EA032445B1 (ru) Дисплейная панель
CN109036236A (zh) 阵列基板检测方法及检测装置
CN106200181A (zh) 一种液晶显示面板测试线路及液晶显示面板
CN108877610A (zh) 阵列基板及其检测方法和显示装置
CN105047115B (zh) 检测驱动电路、检测驱动装置及检测方法
CN100517432C (zh) 测试电路及具有该测试电路的显示装置
US9778527B2 (en) Array substrate and method for detecting the same
JP4624109B2 (ja) 半導体装置の検査回路
CN120853484B (zh) 栅极驱动电路、显示面板和异常检测方法
WO2014176816A1 (zh) 一种异物不良点监控方法及监控装置
CN119046709B (zh) 一种有机电致发光驱动电路故障诊断优化方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17896302

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 17896302

Country of ref document: EP

Kind code of ref document: A1