WO2018126336A1 - 一种封装芯片的基板结构 - Google Patents

一种封装芯片的基板结构 Download PDF

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Publication number
WO2018126336A1
WO2018126336A1 PCT/CN2017/000030 CN2017000030W WO2018126336A1 WO 2018126336 A1 WO2018126336 A1 WO 2018126336A1 CN 2017000030 W CN2017000030 W CN 2017000030W WO 2018126336 A1 WO2018126336 A1 WO 2018126336A1
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WO
WIPO (PCT)
Prior art keywords
substrate
groove
feature point
present application
packaged chip
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PCT/CN2017/000030
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English (en)
French (fr)
Inventor
杨科
刘凯
曾珊珊
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深圳市汇顶科技股份有限公司
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Application filed by 深圳市汇顶科技股份有限公司 filed Critical 深圳市汇顶科技股份有限公司
Priority to PCT/CN2017/000030 priority Critical patent/WO2018126336A1/zh
Priority to EP17889948.0A priority patent/EP3419052A4/en
Priority to CN201780005332.0A priority patent/CN108886032A/zh
Publication of WO2018126336A1 publication Critical patent/WO2018126336A1/zh
Priority to US16/131,149 priority patent/US20190013253A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H01L2223/54486—Located on package parts, e.g. encapsulation, leads, package substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49894—Materials of the insulating layers or coatings

Definitions

  • the present application relates to the field of chip packaging technologies, and in particular, to a substrate structure of a packaged chip.
  • the packaging material such as a small amount of overflow of the epoxy resin (EMC, Epoxy Molding Compound) near the die vent.
  • EMC Epoxy Molding Compound
  • overflow phenomenon presents an uncontrollable irregular flow state of the encapsulating material such as epoxy molding compound, which affects the appearance of the substrate and covers the relevant substrate feature points of the plasticized substrate.
  • the upper surface of the substrate substrate 11 of the substrate, the portion not covered by the green lacquer 13 has at least one substrate feature point 12, and typically the thickness of the substrate pad 12 is about 10-20 um.
  • the green lacquer 13 on the upper surface of the substrate substrate 11 is thicker than the substrate feature point because the thickness of the copper foil (Cu Foil) is to be covered. If the venting groove 14 is present around the substrate feature point 12, when the epoxy molding compound is overflowed near the venting groove 14, it is highly prone to overflow of the epoxy molding compound flowing over the substrate feature point 12 to cause clogging.
  • the present application provides a substrate structure for packaging a chip, which can avoid covering the substrate feature points due to irregular flow of the package material without redesigning different mold and substrate feature points.
  • the present invention provides a substrate structure of a packaged chip, the upper surface of the substrate substrate of the substrate, the portion not covered by the green paint has at least one substrate feature point, and the upper surface of the substrate substrate of the substrate has at least one groove.
  • the recess is used to guide the irregularly flowing packaging material during the chip packaging process.
  • the present application provides at least one groove on the upper surface of the substrate substrate of the substrate.
  • the irregularly flowing encapsulating material during the chip packaging process can be conducted to the grooves so that the encapsulating material is not randomly distributed, thereby affecting the normal appearance of the substrate and covering the substrate feature points.
  • the present application does not require redesigning different mold and substrate feature points without increasing product cost.
  • 1 is a schematic structural view of a substrate of a packaged chip
  • FIG. 2 is a schematic view showing some embodiments of a substrate structure of a packaged chip of the present application
  • FIG. 3 is a schematic view showing another embodiment of a substrate structure of a packaged chip of the present application.
  • 4a and 4b are schematic diagrams showing still further embodiments of the substrate structure of the packaged chip of the present application.
  • the application provides at least one groove on the upper surface of the substrate substrate of the substrate.
  • the irregularly flowing encapsulating material during the chip packaging process can be conducted to the grooves so that the encapsulating material is not randomly distributed, thereby affecting the normal appearance of the substrate and covering the substrate feature points.
  • the present application does not require redesigning different mold and substrate feature points without increasing product cost.
  • an embodiment of the present application provides a substrate structure of a packaged chip.
  • the upper surface of the substrate substrate 11 of the substrate, the portion not covered by the green paint 13 has at least one substrate feature point 12.
  • the upper surface of the substrate substrate 11 of the substrate has at least one groove 15 for guiding the irregularly flowing packaging material during the chip packaging process.
  • the substrate feature point 12 is an optical positioning point.
  • At least one groove 15 is disposed on the upper surface of the substrate substrate 11 of the substrate.
  • the irregularly flowing encapsulating material during the chip packaging process can be conducted to the recess 15 so that the encapsulating material is not randomly distributed, thereby affecting the normal appearance of the substrate and covering the substrate feature points.
  • the present application does not require redesigning different mold and substrate feature points without increasing product cost.
  • another embodiment of the present application provides a substrate structure of a packaged chip.
  • the upper surface of the substrate substrate 11 of the substrate, the portion not covered by the green paint 13 has at least one substrate feature point 12, the green paint.
  • the upper surface of the 13 has at least one venting groove 14.
  • the upper surface of the substrate substrate 11 of the substrate has at least one groove 15 for guiding the epoxy molding compound overflowing the venting groove 14.
  • the substrate feature point 12 is an optical positioning point.
  • At least one groove 15 is disposed on the upper surface of the substrate substrate 11 of the substrate.
  • the epoxy molding compound overflowing from the exhaust groove 14 during the chip packaging process can be conducted to the groove 15 so that the epoxy molding compound is not randomly distributed, thereby affecting the normal appearance of the substrate, and covering the substrate characteristics. point.
  • the present application does not require redesigning different mold and substrate feature points without increasing product cost.
  • the distance of the groove 15 from the exhaust groove 14 is greater than or equal to 50 um.
  • a groove 15 is provided in the vicinity of the exhaust groove 14 to function as a guide groove.
  • the overflowing encapsulating material can flow in the shape of the groove 15 at different pressures around the groove 15 and in the groove 15, thereby avoiding the influence of the overflowing encapsulating material on the appearance of the substrate.
  • the distance of the groove 15 from the substrate feature point 12 is greater than or equal to 100 um.
  • a groove 15 is provided in the vicinity of the substrate feature point 12 to function as a flow guiding groove.
  • the overflowing encapsulating material can flow in the shape of the groove 15 at different pressures around the groove 15 and in the groove 15, thereby avoiding the influence of the overflowing encapsulating material on the appearance of the substrate.
  • the recess 15 is shaped to surround the substrate feature points 12 to further prevent spilled packaging material from covering the substrate feature points 12.
  • the shape specification of the groove 15 is designed according to the space of the location. Therefore, the present application can set the shape of the groove 15 according to the space of the substrate substrate 11 and the substrate feature points 12 and the exhaust grooves 14.
  • the depth of the groove 15 is determined according to the thickness of the green paint 13 and the copper foil. That is, if the thickness of the green paint 13 and the copper foil is small, the depth of the groove 15 is small, and if the thickness of the green paint 13 and the copper foil is large, the depth of the groove 15 is large.
  • the shape specification of the substrate feature point 12 varies according to the size of the groove 15.
  • the shape specification of the substrate feature point 12 is not fixed, and the upper surface of the substrate substrate 11 is changed according to the size of the groove 15, so as to avoid being covered by the encapsulating material.

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Led Device Packages (AREA)

Abstract

一种封装芯片的基板结构，所述基板的基板底材（11）上表面，未被绿漆（13）覆盖的部分具有至少一基板特征点（12），所述基板的基板底材（11）上表面具有至少一凹槽（15），所述凹槽（15）用于导流芯片封装过程中无规则流动的封装材料。该基板结构无需重新设计不同的模具和基板特征点（12），即可避免因封装材料无规则流动而覆盖基板特征点（12）。

Description

一种封装芯片的基板结构 技术领域
本申请涉及芯片封装技术领域，尤其涉及一种封装芯片的基板结构。
背景技术
芯片封装的制程工艺中，因为模压的作用，都会存在封装材料的溢出现象，比如环氧树脂模塑料(EMC，Epoxy Molding Compound)在模具排气槽附近的少量溢出现象。此类溢出现象呈现环氧树脂模塑料等封装材料不可控制的无规则流动状态，会影响基板的外观，并覆盖塑封基板的相关基板特征点。参见图1，所述基板的基板底材11上表面，未被绿漆13覆盖的部分具有至少一基板特征点12，通常基板特征点12(Cu pad)的厚度约10-20um。基板底材11上表面的绿漆13因为要覆盖铜箔(Cu Foil)厚度会比基板特征点高。如果基板特征点12周围存在排气槽14，当排气槽14附近环氧树脂模塑料溢出时，极容易出现溢出的环氧树脂模塑料流至基板特征点12上方造成遮盖。
这类覆盖严重影响之后各段工艺生产精度和效率，如果依据不同产品设计不同的模具和基板特征点，则会增加产品成本。
发明内容
有鉴于此，本申请提供一种封装芯片的基板结构，其无需重新设计不同的模具和基板特征点，即可避免因封装材料无规则流动而覆盖基板特征点。
本申请提供一种封装芯片的基板结构，所述基板的基板底材上表面，未被绿漆覆盖的部分具有至少一基板特征点，所述基板的基板底材上表面具有至少一凹槽，所述凹槽用于导流芯片封装过程中无规则流动的封装材料。
由以上技术方案可见，本申请在所述基板的基板底材上表面设置至少一凹槽。芯片封装过程中无规则流动的封装材料即可导流至所述凹槽，使得封装材料不会随机分布，从而影响基板的正常外观，以及覆盖所述基板特征点。并且，本申请无需重新设计不同的模具和基板特征点，不会增加产品成本。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请中记载的一些实施例，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。
图1是封装芯片的基板结构示意图；
图2是本申请封装芯片的基板结构一些实施例示意图；
图3是本申请封装芯片的基板结构另一些实施例示意图；
图4a以及图4b是本申请封装芯片的基板结构再一些实施例示意图。
具体实施方式
本申请在所述基板的基板底材上表面设置至少一凹槽。芯片封装过程中无规则流动的封装材料即可导流至所述凹槽，使得封装材料不会随机分布，从而影响基板的正常外观，以及覆盖所述基板特征点。并且，本申请无需重新设计不同的模具和基板特征点，不会增加产品成本。
当然，实施本申请的任一技术方案必不一定需要同时达到以上的所有优点。
为了使本领域的人员更好地理解本申请中的技术方案，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员所获得的所有其他实施例，都应当属于本申请保护的范围。
下面结合本申请附图进一步说明本申请具体实现。
参见图2，本申请一实施例提供一种封装芯片的基板结构，所述基板的基板底材11上表面，未被绿漆13覆盖的部分具有至少一基板特征点12。所述基板的基板底材11上表面具有至少一凹槽15，所述凹槽15用于导流芯片封装过程中无规则流动的封装材料。
具体地，所述基板特征点12为光学定位点。
本申请在所述基板的基板底材11上表面设置至少一凹槽15。芯片封装过程中无规则流动的封装材料即可导流至所述凹槽15，使得封装材料不会随机分布，从而影响基板的正常外观，以及覆盖所述基板特征点。并且，本申请无需重新设计不同的模具和基板特征点，不会增加产品成本。
参见图3，本申请另一实施例提供一种封装芯片的基板结构，所述基板的基板底材11上表面，未被绿漆13覆盖的部分具有至少一基板特征点12，所述绿漆13的上表面具有至少一排气槽14。所述基板的基板底材11上表面具有至少一凹槽15，所述凹槽15用于导流排气槽14溢出的环氧树脂模塑料。
具体地，所述基板特征点12为光学定位点。
本申请在所述基板的基板底材11上表面设置至少一凹槽15。芯片封装过程中排气槽14溢出的环氧树脂模塑料即可导流至所述凹槽15，使得环氧树脂模塑料不会随机分布，从而影响基板的正常外观，以及覆盖所述基板特征点。并且，本申请无需重新设计不同的模具和基板特征点，不会增加产品成本。
在本申请一具体实现中，参见图4a以及图4b，所述凹槽15距离所述排气槽14的距离大于或者等于50um。
本申请在排气槽14附近设置凹槽15，起到导流槽的作用。当存在封装材料溢出时，在凹槽15周围和凹槽15内的不同的压强下，可以让溢出的封装材料按照凹槽15的形状流动，从而避免溢出的封装材料对基板外观的影响。
在本申请另一具体实现中，参见图4a以及图4b，所述凹槽15距离所述基板特征点12的距离大于或者等于100um。
本申请在基板特征点12附近设置凹槽15，起到导流槽的作用。当存在封装材料溢出时，在凹槽15周围和凹槽15内的不同的压强下，可以让溢出的封装材料按照凹槽15的形状流动，从而避免溢出的封装材料对基板外观的影响。
所述凹槽15的形状为环绕所述基板特征点12，从而进一步避免溢出的封装材料覆盖所述基板特征点12。
在本申请再一具体实现中，所述凹槽15的形状规格根据所在位置的空间进行设计。因此，本申请可以根据所述基板底材11以及基板特征点12、排气槽14的空间情况，设置所述凹槽15的形状。
在本申请再一具体实现中，所述凹槽15深度为根据所述绿漆13和铜箔的厚度确定。即，如果所述绿漆13和铜箔的厚度小，则所述凹槽15深度较小，如果所述绿漆13和铜箔的厚度大，则所述凹槽15深度较大。
在本申请再一具体实现中，所述基板特征点12的形状规格根据所述凹槽15的尺寸进行变化。所述基板特征点12的形状规格并不固定，在所述基板底材11上表面根据所述凹槽15的尺寸进行变化，从而避免被封装材料覆盖。
尽管已描述了本申请的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本申请范围的所有变更和修改。显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的精神和范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (9)

  1. 一种封装芯片的基板结构，所述基板的基板底材上表面，未被绿漆覆盖的部分具有至少一基板特征点，其特征在于，所述基板的基板底材上表面具有至少一凹槽，所述凹槽用于导流芯片封装过程中无规则流动的封装材料。
  2. 根据权利要求1所述的封装芯片的基板结构，其特征在于，所述绿漆的上表面具有至少一排气槽，所述凹槽用于导流排气槽溢出的环氧树脂模塑料。
  3. 根据权利要求2所述的压力检测结构，其特征在于，所述凹槽距离所述排气槽的距离大于或者等于50um。
  4. 根据权利要求1所述的封装芯片的基板结构，其特征在于，所述凹槽距离所述基板特征点的距离大于或者等于100um。
  5. 根据权利要求4所述的封装芯片的基板结构，其特征在于，所述凹槽的形状为环绕所述基板特征点。
  6. 根据权利要求1所述的封装芯片的基板结构，其特征在于，所述凹槽的形状规格根据所在位置的空间进行设计。
  7. 根据权利要求1所述的封装芯片的基板结构，其特征在于，所述凹槽深度为根据绿漆和铜箔的厚度确定。
  8. 根据权利要求1所述的封装芯片的基板结构，其特征在于，所述基板特征点的形状规格根据所述凹槽的尺寸进行变化。
  9. 根据权利要求1-8中任一项所述的封装芯片的基板结构，其特征在于，所述基板特征点为光学定位点。
PCT/CN2017/000030 2017-01-03 2017-01-03 一种封装芯片的基板结构 WO2018126336A1 (zh)

Priority Applications (4)

Application Number Priority Date Filing Date Title
PCT/CN2017/000030 WO2018126336A1 (zh) 2017-01-03 2017-01-03 一种封装芯片的基板结构
EP17889948.0A EP3419052A4 (en) 2017-01-03 2017-01-03 SUBSTRATE STRUCTURE FOR PACKING SCHIP
CN201780005332.0A CN108886032A (zh) 2017-01-03 2017-01-03 一种封装芯片的基板结构
US16/131,149 US20190013253A1 (en) 2017-01-03 2018-09-14 Substrate for chip package

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US20190013253A1 (en) 2019-01-10
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CN108886032A (zh) 2018-11-23

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