WO2018120289A1 - 扫描驱动电路及显示面板 - Google Patents

扫描驱动电路及显示面板 Download PDF

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Publication number
WO2018120289A1
WO2018120289A1 PCT/CN2017/070620 CN2017070620W WO2018120289A1 WO 2018120289 A1 WO2018120289 A1 WO 2018120289A1 CN 2017070620 W CN2017070620 W CN 2017070620W WO 2018120289 A1 WO2018120289 A1 WO 2018120289A1
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WIPO (PCT)
Prior art keywords
controllable switch
control
controllable
receives
switch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2017/070620
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English (en)
French (fr)
Inventor
石龙强
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TCL China Star Optoelectronics Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Technology Co Ltd
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Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to US15/325,149 priority Critical patent/US10204562B2/en
Publication of WO2018120289A1 publication Critical patent/WO2018120289A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a scan driving circuit and a display panel.
  • GOA Gate Driver on Array technology is widely used and researched because it facilitates the narrow frame design and cost reduction of the display.
  • IGZO indium gallium zinc Oxide, indium gallium zinc oxide
  • IGZO thin film transistor has high mobility and good device stability, which can reduce the complexity of GOA circuit, making The size of the thin film transistor in the GOA circuit can be made smaller than that of the a-Si, which is advantageous for the fabrication of the narrow bezel display, and can also reduce the number of power supply and thin film transistors used to stabilize the performance of the thin film transistor, thereby making the circuit simple and reducing Power consumption.
  • the existing IGZO-based GOA circuits are few, the circuit design is not simple enough, the number of power supplies is large, the power consumption is greatly increased, and the advantages of IGZO are not carried forward.
  • the technical problem to be solved by the present invention is to provide a scan driving circuit and a display panel, which are simple in circuit and low in power consumption by reducing the number of power sources and thin film transistors.
  • a technical solution adopted by the present invention is to provide a scan driving circuit, and the scan driving circuit includes:
  • a pull-up control circuit for pulling up a potential of the pull-up control signal point to a high level or pulling the potential of the pull-up control signal point to a low level
  • a pull-down control circuit connected to the pull-up control circuit for pulling up a potential of a pull-down control signal point to a high level or pulling a potential of the pull-down control signal point to a low level;
  • a scan output circuit connected to the pull-up control circuit and the pull-down control circuit, for outputting a high-level scan driving signal or low power according to a potential of the pull-up control signal point and a potential of the pull-down control signal point Flat scan drive signal;
  • the pull-up control circuit includes first and second controllable switches, the control end of the first controllable switch receives a signal transmitted by the upper stage, and the first end of the first controllable switch receives an open voltage, the first a second end of the controllable switch is connected to the first end of the second controllable switch, the pull-down control circuit and the scan output circuit, and the control end of the second controllable switch is connected to the pull-down control circuit and The scan output circuit, the second end of the second controllable switch is connected to the pull-down control circuit and the scan output circuit, and receives a turn-off voltage.
  • the pull-down control circuit includes third to ninth controllable switches, and the control end of the third controllable switch receives a lower-level scan signal, and the first end of the third controllable switch is connected to the sixth and eighth Controlling the first end of the switch, and receiving the turn-on voltage, the second end of the third controllable switch is connected to the first end of the fourth controllable switch, the first end of the fifth controllable switch, The second end of the seventh and ninth controllable switches and the control end of the second controllable switch, the control end of the fourth controllable switch is connected to the second end of the first controllable switch a second end of the fourth controllable switch is connected to the second end of the fifth controllable switch, the second end of the second controllable switch, and the scan output circuit, and receives the turn-off voltage, the fifth The control end of the controllable switch receives the upper scan signal, the control end of the sixth controllable switch receives the first clock signal, and the second end of the sixth controllable switch is connected to the
  • the scan output circuit includes tenth to thirteenth controllable switches and a capacitor, and a control end of the tenth controllable switch is connected to the second end of the first controllable switch and the second controllable switch a first end of the eleventh controllable switch is connected to the first end of the eleventh controllable switch, and receives the fourth clock signal,
  • the second end of the tenth controllable switch receives the signal transmitted by the first stage, and the second end of the eleventh controllable switch is connected to the scan signal output end and the first end of the thirteenth controllable switch,
  • the control end of the thirteenth controllable switch receives the second clock signal, and the second end of the thirteenth controllable switch is connected to the second end of the twelfth controllable switch, the second controllable switch a second end, a second end of the fifth controllable switch, a second end of the fourth controllable switch, and receiving the shutdown voltage, the control end of the twelfth controllable switch being connected to
  • the first to thirteenth controllable switches are all N-type indium gallium zinc oxide thin film transistors, and the control ends, the first ends and the second ends of the first to thirteenth controllable switches respectively correspond to N-type indium The gate, drain and source of the gallium zinc oxide thin film transistor.
  • the second clock signal is opposite to the potential of the fourth clock signal, the first clock signal is opposite to the potential of the third clock signal; the duty ratio of the first to fourth clock signals is 50%, phase
  • the overlap time between two adjacent clock signals is half of the width of the clock signal; the voltages of the first to fourth clock signals are -8V-28V; the turn-on voltage is 28V, and the turn-off voltage is -6V.
  • a technical solution adopted by the present invention is to provide a scan driving circuit, including:
  • a pull-up control circuit for pulling up a potential of the pull-up control signal point to a high level or pulling the potential of the pull-up control signal point to a low level
  • a pull-down control circuit connected to the pull-up control circuit for pulling up a potential of a pull-down control signal point to a high level or pulling a potential of the pull-down control signal point to a low level;
  • a scan output circuit connected to the pull-up control circuit and the pull-down control circuit, for outputting a high-level scan driving signal or low power according to a potential of the pull-up control signal point and a potential of the pull-down control signal point Flat scan drive signal.
  • the pull-up control circuit includes first and second controllable switches, and the control end of the first controllable switch receives a signal transmitted by the upper stage, and the first end of the first controllable switch receives the turn-on voltage.
  • the second end of the first controllable switch is connected to the first end of the second controllable switch, the pull-down control circuit and the scan output circuit, and the control end of the second controllable switch is connected to the pull-down control And a circuit and the scan output circuit, the second end of the second controllable switch is connected to the pull-down control circuit and the scan output circuit, and receives a turn-off voltage.
  • the pull-down control circuit includes third to ninth controllable switches, and the control end of the third controllable switch receives a lower-level scan signal, and the first end of the third controllable switch is connected to the sixth and the third a first end of the eight controllable switch, and receiving the turn-on voltage, the second end of the third controllable switch is connected to the first end of the fourth controllable switch, and the first end of the fifth controllable switch a second end of the seventh and ninth controllable switches and a control end of the second controllable switch, and a control end of the fourth controllable switch is connected to the second end of the first controllable switch a second end of the fourth controllable switch is coupled to the second end of the fifth controllable switch, the second end of the second controllable switch, and the scan output circuit, and receives the shutdown voltage,
  • the control end of the fifth controllable switch receives the upper scan signal
  • the control end of the sixth controllable switch receives the first clock signal
  • the scan output circuit includes a tenth to thirteenth controllable switch and a capacitor, and a control end of the tenth controllable switch is connected to the second end of the first controllable switch, and the second controllable switch
  • the first end of the eleventh controllable switch, the first end of the tenth controllable switch is connected to the first end of the eleventh controllable switch, and receives the fourth clock signal
  • the second end of the tenth controllable switch receives the signal transmitted by the first stage, and the second end of the eleventh controllable switch is connected to the scan signal output end and the first end of the thirteenth controllable switch.
  • the control end of the thirteenth controllable switch receives the second clock signal, and the second end of the thirteenth controllable switch is connected to the second end of the twelfth controllable switch, the second Controlling a second end of the switch, a second end of the fifth controllable switch, and a second end of the fourth controllable switch, and receiving the shutdown voltage, wherein the control end of the twelfth controllable switch is connected to the second a control end of the controllable switch, the first end of the twelfth controllable switch being connected to the second end of the eleventh controllable switch a first end of the thirteenth controllable switch and the scan signal output end, the capacitor is connected between the control end of the tenth controllable switch and the first end of the twelfth controllable switch .
  • the first to thirteenth controllable switches are all N-type indium gallium zinc oxide thin film transistors, and the control ends, the first ends and the second ends of the first to thirteenth controllable switches respectively correspond to N The gate, drain and source of the indium gallium zinc oxide thin film transistor.
  • the second clock signal is opposite to the potential of the fourth clock signal
  • the first clock signal is opposite to the potential of the third clock signal
  • the duty ratio of the first to fourth clock signals is 50%
  • the overlap time between two adjacent clock signals is half of the width of the clock signal
  • the voltages of the first to fourth clock signals are -8V-28V
  • the turn-on voltage is 28V
  • the turn-off voltage is -6V.
  • the pull-down control circuit includes third to ninth controllable switches, and the control end of the third controllable switch receives a lower-level scan signal, and the first end of the third controllable switch is connected to the sixth and the third a first end of the eight controllable switch, and receiving the turn-on voltage, the second end of the third controllable switch is connected to the first end of the fourth controllable switch, and the first end of the fifth controllable switch a second end of the seventh and ninth controllable switches and a control end of the second controllable switch, and a control end of the fourth controllable switch is connected to the second end of the first controllable switch a second end of the fourth controllable switch is coupled to the second end of the fifth controllable switch, the second end of the second controllable switch, and the scan output circuit, and receives the shutdown voltage,
  • the control end of the fifth controllable switch receives the upper scan signal
  • the control end of the sixth controllable switch receives the second clock signal
  • the scan output circuit includes tenth to thirteenth controllable switches and a capacitor, and a control end of the tenth controllable switch is connected to the second end of the first controllable switch and the second controllable switch a first end of the eleventh controllable switch, the first end of the eleventh controllable switch is connected to the first end of the eleventh controllable switch, and receives the first clock signal,
  • the second end of the tenth controllable switch receives the signal transmitted by the first stage, and the second end of the eleventh controllable switch is connected to the scan signal output end and the first end of the thirteenth controllable switch,
  • the control end of the thirteenth controllable switch receives the third clock signal, and the second end of the thirteenth controllable switch is connected to the second end of the twelfth controllable switch, the second controllable switch a second end, a second end of the fifth controllable switch, a second end of the fourth controllable switch, and receiving the shutdown voltage, the control end of the
  • the pull-down control circuit includes third to ninth controllable switches, and the control end of the third controllable switch receives a lower-level scan signal, and the first end of the third controllable switch is connected to the sixth and the third a first end of the eight controllable switch, and receiving the turn-on voltage, the second end of the third controllable switch is connected to the first end of the fourth controllable switch, and the first end of the fifth controllable switch a second end of the seventh and ninth controllable switches and a control end of the second controllable switch, and a control end of the fourth controllable switch is connected to the second end of the first controllable switch a second end of the fourth controllable switch is coupled to the second end of the fifth controllable switch, the second end of the second controllable switch, and the scan output circuit, and receives the shutdown voltage,
  • the control end of the fifth controllable switch receives the upper scan signal
  • the control end of the sixth controllable switch receives the third clock signal
  • the scan output circuit includes tenth to thirteenth controllable switches and a capacitor, and a control end of the tenth controllable switch is connected to the second end of the first controllable switch and the second controllable switch a first end of the eleventh controllable switch connected to the first end of the eleventh controllable switch, and receiving the second clock signal,
  • the second end of the tenth controllable switch receives the signal transmitted by the first stage, and the second end of the eleventh controllable switch is connected to the scan signal output end and the first end of the thirteenth controllable switch,
  • the control end of the thirteenth controllable switch receives the fourth clock signal, and the second end of the thirteenth controllable switch is connected to the second end of the twelfth controllable switch, the second controllable switch a second end, a second end of the fifth controllable switch, a second end of the fourth controllable switch, and receiving the shutdown voltage, the control end of the twelfth controllable switch being connected to the second
  • the pull-down control circuit includes third to ninth controllable switches, and the control end of the third controllable switch receives a lower-level scan signal, and the first end of the third controllable switch is connected to the sixth and the third a first end of the eight controllable switch, and receiving the turn-on voltage, the second end of the third controllable switch is connected to the first end of the fourth controllable switch, and the first end of the fifth controllable switch a second end of the seventh and ninth controllable switches and a control end of the second controllable switch, and a control end of the fourth controllable switch is connected to the second end of the first controllable switch a second end of the fourth controllable switch is coupled to the second end of the fifth controllable switch, the second end of the second controllable switch, and the scan output circuit, and receives the shutdown voltage,
  • the control end of the fifth controllable switch receives the upper scan signal
  • the control end of the sixth controllable switch receives the fourth clock signal
  • the scan output circuit includes tenth to thirteenth controllable switches and a capacitor, and a control end of the tenth controllable switch is connected to the second end of the first controllable switch and the second controllable switch a first end of the eleventh controllable switch connected to the first end of the eleventh controllable switch, and receiving the third clock signal,
  • the second end of the tenth controllable switch receives the signal transmitted by the first stage, and the second end of the eleventh controllable switch is connected to the scan signal output end and the first end of the thirteenth controllable switch,
  • the control end of the thirteenth controllable switch receives the first clock signal, and the second end of the thirteenth controllable switch is connected to the second end of the twelfth controllable switch, the second controllable switch a second end, a second end of the fifth controllable switch, a second end of the fourth controllable switch, and receiving the shutdown voltage, the control end of the twelfth controllable switch being connected to the second
  • the present invention adopts a technical solution to provide a display panel, the display panel includes a scan driving circuit, and the scan driving circuit includes:
  • a pull-up control circuit for pulling up a potential of the pull-up control signal point to a high level or pulling the potential of the pull-up control signal point to a low level
  • a pull-down control circuit connected to the pull-up control circuit for pulling up a potential of a pull-down control signal point to a high level or pulling a potential of the pull-down control signal point to a low level;
  • a scan output circuit connected to the pull-up control circuit and the pull-down control circuit, for outputting a high-level scan driving signal or low power according to a potential of the pull-up control signal point and a potential of the pull-down control signal point Flat scan drive signal.
  • the pull-up control circuit includes first and second controllable switches, and the control end of the first controllable switch receives a signal transmitted by the upper stage, and the first end of the first controllable switch receives the turn-on voltage.
  • the second end of the first controllable switch is connected to the first end of the second controllable switch, the pull-down control circuit and the scan output circuit, and the control end of the second controllable switch is connected to the pull-down control And a circuit and the scan output circuit, the second end of the second controllable switch is connected to the pull-down control circuit and the scan output circuit, and receives a turn-off voltage.
  • the pull-down control circuit includes third to ninth controllable switches, and the control end of the third controllable switch receives a lower-level scan signal, and the first end of the third controllable switch is connected to the sixth and the third a first end of the eight controllable switch, and receiving the turn-on voltage, the second end of the third controllable switch is connected to the first end of the fourth controllable switch, and the first end of the fifth controllable switch a second end of the seventh and ninth controllable switches and a control end of the second controllable switch, and a control end of the fourth controllable switch is connected to the second end of the first controllable switch a second end of the fourth controllable switch is coupled to the second end of the fifth controllable switch, the second end of the second controllable switch, and the scan output circuit, and receives the shutdown voltage,
  • the control end of the fifth controllable switch receives the upper scan signal
  • the control end of the sixth controllable switch receives the first clock signal
  • the scan output circuit includes a tenth to thirteenth controllable switch and a capacitor, and a control end of the tenth controllable switch is connected to the second end of the first controllable switch, and the second controllable switch
  • the first end of the eleventh controllable switch, the first end of the tenth controllable switch is connected to the first end of the eleventh controllable switch, and receives the fourth clock signal
  • the second end of the tenth controllable switch receives the signal transmitted by the first stage, and the second end of the eleventh controllable switch is connected to the scan signal output end and the first end of the thirteenth controllable switch.
  • the control end of the thirteenth controllable switch receives the second clock signal, and the second end of the thirteenth controllable switch is connected to the second end of the twelfth controllable switch, the second Controlling a second end of the switch, a second end of the fifth controllable switch, and a second end of the fourth controllable switch, and receiving the shutdown voltage, wherein the control end of the twelfth controllable switch is connected to the second a control end of the controllable switch, the first end of the twelfth controllable switch being connected to the second end of the eleventh controllable switch a first end of the thirteenth controllable switch and the scan signal output end, the capacitor is connected between the control end of the tenth controllable switch and the first end of the twelfth controllable switch .
  • the first to thirteenth controllable switches are all N-type indium gallium zinc oxide thin film transistors, and the control ends, the first ends and the second ends of the first to thirteenth controllable switches respectively correspond to N The gate, drain and source of the indium gallium zinc oxide thin film transistor.
  • the second clock signal is opposite to the potential of the fourth clock signal
  • the first clock signal is opposite to the potential of the third clock signal
  • the duty ratio of the first to fourth clock signals is 50%
  • the overlap time between two adjacent clock signals is half of the width of the clock signal
  • the voltages of the first to fourth clock signals are -8V-28V
  • the turn-on voltage is 28V
  • the turn-off voltage is -6V.
  • the pull-down control circuit includes third to ninth controllable switches, and the control end of the third controllable switch receives a lower-level scan signal, and the first end of the third controllable switch is connected to the sixth and the third a first end of the eight controllable switch, and receiving the turn-on voltage, the second end of the third controllable switch is connected to the first end of the fourth controllable switch, and the first end of the fifth controllable switch a second end of the seventh and ninth controllable switches and a control end of the second controllable switch, and a control end of the fourth controllable switch is connected to the second end of the first controllable switch a second end of the fourth controllable switch is coupled to the second end of the fifth controllable switch, the second end of the second controllable switch, and the scan output circuit, and receives the shutdown voltage,
  • the control end of the fifth controllable switch receives the upper scan signal
  • the control end of the sixth controllable switch receives the second clock signal
  • the scan output circuit includes tenth to thirteenth controllable switches and a capacitor, and a control end of the tenth controllable switch is connected to the second end of the first controllable switch and the second controllable switch a first end of the eleventh controllable switch, the first end of the eleventh controllable switch is connected to the first end of the eleventh controllable switch, and receives the first clock signal,
  • the second end of the tenth controllable switch receives the signal transmitted by the first stage, and the second end of the eleventh controllable switch is connected to the scan signal output end and the first end of the thirteenth controllable switch,
  • the control end of the thirteenth controllable switch receives the third clock signal, and the second end of the thirteenth controllable switch is connected to the second end of the twelfth controllable switch, the second controllable switch a second end, a second end of the fifth controllable switch, a second end of the fourth controllable switch, and receiving the shutdown voltage, the control end of the
  • the pull-down control circuit includes third to ninth controllable switches, and the control end of the third controllable switch receives a lower-level scan signal, and the first end of the third controllable switch is connected to the sixth and the third a first end of the eight controllable switch, and receiving the turn-on voltage, the second end of the third controllable switch is connected to the first end of the fourth controllable switch, and the first end of the fifth controllable switch a second end of the seventh and ninth controllable switches and a control end of the second controllable switch, and a control end of the fourth controllable switch is connected to the second end of the first controllable switch a second end of the fourth controllable switch is coupled to the second end of the fifth controllable switch, the second end of the second controllable switch, and the scan output circuit, and receives the shutdown voltage,
  • the control end of the fifth controllable switch receives the upper scan signal
  • the control end of the sixth controllable switch receives the third clock signal
  • the scan output circuit includes tenth to thirteenth controllable switches and a capacitor, and a control end of the tenth controllable switch is connected to the second end of the first controllable switch and the second controllable switch a first end of the eleventh controllable switch connected to the first end of the eleventh controllable switch, and receiving the second clock signal,
  • the second end of the tenth controllable switch receives the signal transmitted by the first stage, and the second end of the eleventh controllable switch is connected to the scan signal output end and the first end of the thirteenth controllable switch,
  • the control end of the thirteenth controllable switch receives the fourth clock signal, and the second end of the thirteenth controllable switch is connected to the second end of the twelfth controllable switch, the second controllable switch a second end, a second end of the fifth controllable switch, a second end of the fourth controllable switch, and receiving the shutdown voltage, the control end of the twelfth controllable switch being connected to the second
  • the pull-down control circuit includes third to ninth controllable switches, and the control end of the third controllable switch receives a lower-level scan signal, and the first end of the third controllable switch is connected to the sixth and the third a first end of the eight controllable switch, and receiving the turn-on voltage, the second end of the third controllable switch is connected to the first end of the fourth controllable switch, and the first end of the fifth controllable switch a second end of the seventh and ninth controllable switches and a control end of the second controllable switch, and a control end of the fourth controllable switch is connected to the second end of the first controllable switch a second end of the fourth controllable switch is coupled to the second end of the fifth controllable switch, the second end of the second controllable switch, and the scan output circuit, and receives the shutdown voltage,
  • the control end of the fifth controllable switch receives the upper scan signal
  • the control end of the sixth controllable switch receives the fourth clock signal
  • the scan output circuit includes tenth to thirteenth controllable switches and a capacitor, and a control end of the tenth controllable switch is connected to the second end of the first controllable switch and the second controllable switch a first end of the eleventh controllable switch connected to the first end of the eleventh controllable switch, and receiving the third clock signal,
  • the second end of the tenth controllable switch receives the signal transmitted by the first stage, and the second end of the eleventh controllable switch is connected to the scan signal output end and the first end of the thirteenth controllable switch,
  • the control end of the thirteenth controllable switch receives the first clock signal, and the second end of the thirteenth controllable switch is connected to the second end of the twelfth controllable switch, the second controllable switch a second end, a second end of the fifth controllable switch, a second end of the fourth controllable switch, and receiving the shutdown voltage, the control end of the twelfth controllable switch being connected to the second
  • the invention has the beneficial effects that the scan driving circuit and the display panel of the present invention are provided with IGZO thin film transistors in the pull-up control circuit, the pull-down control circuit and the scan output circuit, thereby reducing the difference from the prior art.
  • the number of power sources and thin film transistors in the scan driving circuit makes the circuit simple and low in power consumption.
  • FIG. 1 is a circuit diagram of a first embodiment of a scan driving circuit of the present invention
  • Figure 2 is a waveform diagram of a scan driving circuit of the present invention
  • Figure 3 is a circuit diagram of a second embodiment of the scan driving circuit of the present invention.
  • Figure 4 is a circuit diagram of a third embodiment of the scan driving circuit of the present invention.
  • Figure 5 is a circuit diagram of a fourth embodiment of the scan driving circuit of the present invention.
  • Fig. 6 is a schematic structural view of a display panel of the present invention.
  • the scan driving circuit includes a pull-up control circuit 10 for pulling up a potential of the pull-up control signal point to a high level or pulling a potential of the pull-up control signal point to a low level; the pull-down control circuit 20 Connecting the pull-up control circuit 10, for pulling up the potential of the pull-down control signal point to a high level or pulling the potential of the pull-down control signal point to a low level; scanning the output circuit 30, connecting the The pull-up control circuit 10 and the pull-down control circuit 20 are configured to output a high-level scan driving signal or a low-level scan driving signal according to the potential of the pull-up control signal point and the potential of the pull-down control signal point. .
  • the pull-up control circuit 10 includes first and second controllable switches T1 and T2, and the control end of the first controllable switch T1 receives a higher-level transmission signal, and the first controllable switch T1 Receiving a turn-on voltage VGH at one end, the second end of the first controllable switch T1 is connected to the first end of the second controllable switch T2, the pull-down control circuit 20, and the scan output circuit 30, The control terminal of the second controllable switch T2 is connected to the pull-down control circuit 20 and the scan output circuit 30, and the second end of the second controllable switch T2 is connected to the pull-down control circuit 20 and the scan output circuit 30, And receives the shutdown voltage VSS.
  • the pull-down control circuit 20 includes third to ninth controllable switches T3-T9, the control end of the third controllable switch T3 receives a lower-level scan signal, and the first end of the third controllable switch T3 is connected to the a first end of the sixth controllable switch T6 and a first end of the eighth controllable switch T8, and receiving the turn-on voltage VGH, the second end of the third controllable switch T3 is connected to the fourth controllable switch a first end of T4, a first end of the fifth controllable switch T5, a second end of the seventh and ninth controllable switches T7, T9, and a control end of the second controllable switch T2
  • the control end of the fourth controllable switch T4 is connected to the second end of the first controllable switch T1, and the second end of the fourth controllable switch T4 is connected to the second end of the fifth controllable switch T5,
  • the second end of the second controllable switch T2 and the scan output circuit 30 receive the turn-off voltage
  • the scan output circuit 30 includes tenth to thirteenth controllable switches T10-T13 and a capacitor C1, and a control end of the tenth controllable switch T10 is connected to the second end of the first controllable switch T1, a first end of the second controllable switch T1 and a first end of the eleventh controllable switch T11, the first end of the tenth controllable switch T10 is connected to the first end of the eleventh controllable switch T11 And receiving the fourth clock signal CK1, the second end of the tenth controllable switch T10 receives the signal transmitted by the level, and the second end of the eleventh controllable switch T11 is connected to the scan signal output end for Outputting the scan signal of the current stage and the first end of the thirteenth controllable switch T13, the control end of the thirteenth controllable switch T13 receives the second clock signal CK3, the thirteenth controllable switch T13 The second end is connected to the second end of the twelfth controllable switch T12, the second end of
  • the first to thirteenth controllable switches T1-T13 are N-type indium gallium zinc oxide thin film transistors, and the control ends of the first to thirteenth controllable switches T1-T13, The first end and the second end respectively correspond to a gate, a drain and a source of the N-type indium gallium zinc oxide thin film transistor.
  • other types of switches may be employed as long as the objectives of the present invention are achieved.
  • the second clock signal CK2 is opposite in potential to the fourth clock signal CK4, and the first clock signal CK1 is opposite in potential to the third clock signal CK3.
  • the duty ratio of the first to fourth clock signals CK1-CK4 is 50%.
  • the overlap time between two adjacent clock signals is half of the width of the clock signal.
  • the voltages of the first to fourth clock signals CK1-CK4 are -8V-28V.
  • the turn-on voltage VGH is 28V
  • the turn-off voltage VSS is -6V.
  • the upper level transmission signal is ST(N-2), the current level transmission signal is ST(N), the current level scanning signal is G(N), and the upper level scanning signal is G(N).
  • the lower-level scan signal is G(N+2), the first clock signal is CK2, the second clock signal is CK3, the third clock signal is CK4, and the fourth clock signal is For CK1, the turn-on voltage is VGH, and the turn-off voltage is VSS.
  • the working principle of the scan driving circuit is as follows, and the output scan signal G(5) is taken as an example for detailed description.
  • the scanning signal G(N) G(5) of the current level
  • the signal ST(N-2) ST(3) of the superior stage
  • the signal ST(N) ST(3) of the current stage
  • the upper scanning signal G(N-1) G(4)
  • lower-level scan signal G(N+2) G(7)
  • pull-up control signal point Q(N) Q(5)
  • pull-down control signal point P(N) P(5).
  • the first controllable switch T1 When the upper stage signal ST(3) is at a high level, the first controllable switch T1 is turned on, the pull-up control signal point Q(5) is a high level, and the tenth controllable switch T10 and the eleventh controllable switch T11 are both turned on.
  • the fourth clock signal CK1 is at a high level, so the current scanning signal G(5) and the local level transmission signal ST(5) are both Is high, because the fourth controllable switch T4 is turned on, so turning off the voltage VSS will pull the pull-down control signal P(5) is pulled low to a low level, and the second controllable switch T2 and the twelfth controllable switch T12 are both turned off, and the current scanning signal G(5) is at a high level.
  • the first controllable switch T1 When the upper stage signal ST(3) is at a low level, the first controllable switch T1 is turned off, and the pull-up control signal point Q(5) is subjected to a coupling effect of a capacitor, and its high level becomes Higher, the tenth controllable switch T10 and the eleventh controllable switch T11 are both turned on.
  • the fourth clock signal CK1 is at a high level, so the current scanning signal G(5) and The stage-level signal ST(5) is high level because the fourth controllable switch T4 is turned on, so the turn-off control signal point is turned off by the voltage VSS.
  • the second controllable switch T2 and the twelfth controllable switch T12 are both turned off, so the potential of the pull-up control signal point Q(5) is not affected.
  • the fifth controllable switch T5 is turned on, and the turn-off voltage VSS causes the low potential of the pull-down control signal point P(5) to be kept better.
  • the second controllable switch T2 and the twelfth controllable switch T12 are both turned off, and the current scanning signal G(5) is at a high level.
  • the third controllable switch T3 is turned on, and the turn-on voltage VGH causes the pull-down control signal point P (5) Is a high level, the second controllable switch T2 and the twelfth controllable switch T12 are both turned on, the turn-off voltage VSS will be the pull-up control signal point Q (5) and the current level
  • the scan signal G(5) is pulled low to low level.
  • the sixth controllable switch T6 is controlled by the first clock signal CK2
  • the seventh controllable switch T7 is controlled by the second clock signal CK3
  • the eighth controllable switch T8 is subjected to the third
  • the clock signal CK4 is controlled
  • the ninth controllable switch T9 is controlled by the fourth clock signal CK1, thereby ensuring that the pull-down control signal point P(5) is high level within one frame, thereby ensuring the The low level of the scanning signal G(5) of this stage.
  • the control end of the thirteenth controllable switch T13 receives the second clock signal CK3 opposite to the potential of the fourth clock signal CK1, so that the periodic opening of the second clock signal CK3 further ensures the present The low level of the level scan signal G(5).
  • FIG. 3 is a circuit diagram of a second embodiment of the scan driving circuit 1 of the present invention.
  • the second embodiment of the scan driving circuit is different from the first embodiment described above in that the control terminal of the sixth controllable switch T6 in the pull-down control circuit 20 receives the second clock signal CK3,
  • the control end of the seventh controllable switch T7 receives the third clock signal CK1, the control end of the eighth controllable switch T8 receives the fourth clock signal CK1, and the control end of the ninth controllable switch T9 receives the first clock signal CK2;
  • the first end of the tenth controllable switch T10 in the scan output circuit 30 is connected to the first end of the eleventh controllable switch T11, and receives the first clock signal CK2, the thirteenth The control terminal of the controllable switch T13 receives the third clock signal CK4.
  • FIG. 4 is a circuit diagram of a third embodiment of the scan driving circuit 1 of the present invention.
  • the third embodiment of the scan driving circuit is different from the first embodiment in that the control terminal of the sixth controllable switch T6 in the pull-down control circuit 20 receives the third clock signal CK4,
  • the control end of the seventh controllable switch T7 receives the fourth clock signal CK1, the control end of the eighth controllable switch T8 receives the first clock signal CK2, and the control end of the ninth controllable switch T9 receives the second clock signal CK3;
  • the first end of the tenth controllable switch T10 in the scan output circuit 30 is connected to the first end of the eleventh controllable switch T11, and receives the second clock signal CK3, the thirteenth The control terminal of the controllable switch receives the fourth clock signal CK1.
  • FIG. 5 is a circuit diagram of a second embodiment of the scan driving circuit 1 of the present invention.
  • the second embodiment of the scan driving circuit is different from the first embodiment described above in that the control terminal of the sixth controllable switch T6 in the pull-down control circuit 20 receives the fourth clock signal CK1,
  • the control end of the seventh controllable switch T7 receives the first clock signal CK2, the control end of the eighth controllable switch T8 receives the second clock signal CK3, and the control end of the ninth controllable switch T9 receives the third clock signal CK4;
  • the first end of the tenth controllable switch T10 in the scan output circuit 30 is connected to the first end of the eleventh controllable switch T11, and receives the third clock signal CK4, the thirteenth The control terminal of the controllable switch receives the first clock signal CK2.
  • FIG. 6 is a schematic structural diagram of a display panel 2 according to the present invention.
  • the display panel 2 includes the foregoing scan driving circuit 1.
  • the other devices and functions in the display panel 2 are the same as those of the existing display panel, and are not described herein again.
  • the display panel 2 is an LCD or an OLED.
  • the scan driving circuit and the display panel reduce the number of power sources and thin film transistors in the scan driving circuit by setting an IGZO thin film transistor in the pull-up control circuit, the pull-down control circuit, and the scan output circuit, thereby making the circuit Simple and low power consumption.

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Abstract

一种扫描驱动电路（1）及显示面板（2）；扫描驱动电路（1）包括上拉控制电路（10），将上拉控制信号点（Q(N)）的电位上拉至高电平或者将上拉控制信号点（Q(N)）的电位下拉至低电平；下拉控制电路（20），将下拉控制信号点（P(N)）的电位上拉至高电平或者将下拉控制信号点（P(N)）的电位下拉至低电平；扫描输出电路（30），根据上拉控制信号点（Q(N)）的电位及下拉控制信号点（P(N)）的电位输出高电平的扫描驱动信号（G(N)）或者低电平的扫描驱动信号（G(N)）。

Description

扫描驱动电路及显示面板
【技术领域】
本发明涉及显示技术领域，特别是涉及一种扫描驱动电路及显示面板。
【背景技术】
GOA(Gate Driver on Array)技术有利于显示屏的窄边框设计和成本的降低，因此得到广泛地应用和研究。IGZO（indium gallium zinc oxide，铟镓锌氧化物）作为现今非常热门的薄膜晶体管有源层，得到广泛关注.，IGZO薄膜晶体管具有高的迁移率和良好的器件稳定性，其可减少GOA电路的复杂程度，使得 GOA电路中薄膜晶体管的尺寸相对a-Si可以做的更小，有利于窄边框显示器的制作，也可以减少用来稳定薄膜晶体管的性能的电源和薄膜晶体管的数量，从而使得电路简单，并且降低功耗。然而，现有的基于IGZO的GOA电路很少，电路设计不够简洁，电源数量较多，大大增加了功耗，没有将IGZO的优点发扬光大。
【发明内容】
本发明主要解决的技术问题是提供一种扫描驱动电路及显示面板，通过减少电源及薄膜晶体管数量以使电路简单且功耗低。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种扫描驱动电路，所述扫描驱动电路包括：
上拉控制电路，用于将上拉控制信号点的电位上拉至高电平或者将所述上拉控制信号点的电位下拉至低电平；
下拉控制电路，连接所述上拉控制电路，用于将下拉控制信号点的电位上拉至高电平或者将所述下拉控制信号点的电位下拉至低电平；及
扫描输出电路，连接所述上拉控制电路及所述下拉控制电路，用于根据所述上拉控制信号点的电位及所述下拉控制信号点的电位输出高电平的扫描驱动信号或者低电平的扫描驱动信号；
所述上拉控制电路包括第一及第二可控开关，所述第一可控开关的控制端接收上级级传信号，所述第一可控开关的第一端接收开启电压，所述第一可控开关的第二端连接所述第二可控开关的第一端、所述下拉控制电路及所述扫描输出电路，所述第二可控开关的控制端连接所述下拉控制电路及所述扫描输出电路，所述第二可控开关的第二端连接所述下拉控制电路及所述扫描输出电路，并接收关闭电压。
所述下拉控制电路包括第三至第九可控开关，所述第三可控开关的控制端接收下级扫描信号，所述第三可控开关的第一端连接所述第六及第八可控开关的第一端，并接收所述开启电压，所述第三可控开关的第二端连接所述第四可控开关的第一端、所述第五可控开关的第一端、所述第七及第九可控开关的第二端及所述第二可控开关的控制端，所述第四可控开关的控制端连接所述第一可控开关的第二端，所述第四可控开关的第二端连接所述第五可控开关的第二端、第二可控开关的第二端及所述扫描输出电路，并接收所述关闭电压，所述第五可控开关的控制端接收上级扫描信号，所述第六可控开关的控制端接收第一时钟信号，所述第六可控开关的第二端连接所述第七可控开关的第一端，所述第七可控开关的控制端接收第二时钟信号，所述第八可控开关的控制端接收第三时钟信号，所述第八可控开关的第二端连接所述第九可控开关的第一端，所述第九可控开关的控制端接收第四时钟信号。
所述扫描输出电路包括第十至第十三可控开关及电容，所述第十可控开关的控制端连接所述第一可控开关的第二端、所述第二可控开关的第一端及所述第十一可控开关的控制端，所述第十可控开关的第一端连接所述第十一可控开关的第一端，并接收所述第四时钟信号，所述第十可控开关的第二端接收本级级传信号，所述第十一可控开关的第二端连接扫描信号输出端及所述第十三可控开关的第一端，所述第十三可控开关的控制端接收所述第二时钟信号，所述第十三可控开关的第二端连接所述第十二可控开关的第二端、所述第二可控开关的第二端、第五可控开关的第二端、第四可控开关的第二端，并接收所述关闭电压，所述第十二可控开关的控制端连接所述第二可控开关的控制端，所述第十二可控开关的第一端连接所述第十一可控开关的第二端、所述第十三可控开关的第一端及所述扫描信号输出端，所述电容连接在所述第十可控开关的控制端与所述第十二可控开关的第一端之间。
所述第一至第十三可控开关均为N型铟镓锌氧化物薄膜晶体管，所述第一至第十三可控开关的控制端、第一端及第二端分别对应N型铟镓锌氧化物薄膜晶体管的栅极、漏极及源极。
所述第二时钟信号与所述第四时钟信号电位相反，所述第一时钟信号与所述第三时钟信号电位相反；所述第一至第四时钟信号的占空比为50%，相邻两个时钟信号之间重叠时间为时钟信号宽度的一半；所述第一至第四时钟信号的电压为-8V-28V；开启电压为28V，关闭电压为-6V。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种扫描驱动电路，包括：
上拉控制电路，用于将上拉控制信号点的电位上拉至高电平或者将所述上拉控制信号点的电位下拉至低电平；
下拉控制电路，连接所述上拉控制电路，用于将下拉控制信号点的电位上拉至高电平或者将所述下拉控制信号点的电位下拉至低电平；及
扫描输出电路，连接所述上拉控制电路及所述下拉控制电路，用于根据所述上拉控制信号点的电位及所述下拉控制信号点的电位输出高电平的扫描驱动信号或者低电平的扫描驱动信号。
其中，所述上拉控制电路包括第一及第二可控开关，所述第一可控开关的控制端接收上级级传信号，所述第一可控开关的第一端接收开启电压，所述第一可控开关的第二端连接所述第二可控开关的第一端、所述下拉控制电路及所述扫描输出电路，所述第二可控开关的控制端连接所述下拉控制电路及所述扫描输出电路，所述第二可控开关的第二端连接所述下拉控制电路及所述扫描输出电路，并接收关闭电压。
其中，所述下拉控制电路包括第三至第九可控开关，所述第三可控开关的控制端接收下级扫描信号，所述第三可控开关的第一端连接所述第六及第八可控开关的第一端，并接收所述开启电压，所述第三可控开关的第二端连接所述第四可控开关的第一端、所述第五可控开关的第一端、所述第七及第九可控开关的第二端及所述第二可控开关的控制端，所述第四可控开关的控制端连接所述第一可控开关的第二端，所述第四可控开关的第二端连接所述第五可控开关的第二端、第二可控开关的第二端及所述扫描输出电路，并接收所述关闭电压，所述第五可控开关的控制端接收上级扫描信号，所述第六可控开关的控制端接收第一时钟信号，所述第六可控开关的第二端连接所述第七可控开关的第一端，所述第七可控开关的控制端接收第二时钟信号，所述第八可控开关的控制端接收第三时钟信号，所述第八可控开关的第二端连接所述第九可控开关的第一端，所述第九可控开关的控制端接收第四时钟信号。
其中，所述扫描输出电路包括第十至第十三可控开关及电容，所述第十可控开关的控制端连接所述第一可控开关的第二端、所述第二可控开关的第一端及所述第十一可控开关的控制端，所述第十可控开关的第一端连接所述第十一可控开关的第一端，并接收所述第四时钟信号，所述第十可控开关的第二端接收本级级传信号，所述第十一可控开关的第二端连接扫描信号输出端及所述第十三可控开关的第一端，所述第十三可控开关的控制端接收所述第二时钟信号，所述第十三可控开关的第二端连接所述第十二可控开关的第二端、所述第二可控开关的第二端、第五可控开关的第二端、第四可控开关的第二端，并接收所述关闭电压，所述第十二可控开关的控制端连接所述第二可控开关的控制端，所述第十二可控开关的第一端连接所述第十一可控开关的第二端、所述第十三可控开关的第一端及所述扫描信号输出端，所述电容连接在所述第十可控开关的控制端与所述第十二可控开关的第一端之间。
其中，所述第一至第十三可控开关均为N型铟镓锌氧化物薄膜晶体管，所述第一至第十三可控开关的控制端、第一端及第二端分别对应N型铟镓锌氧化物薄膜晶体管的栅极、漏极及源极。
其中，所述第二时钟信号与所述第四时钟信号电位相反，所述第一时钟信号与所述第三时钟信号电位相反；所述第一至第四时钟信号的占空比为50%，相邻两个时钟信号之间重叠时间为时钟信号宽度的一半；所述第一至第四时钟信号的电压为-8V-28V；开启电压为28V，关闭电压为-6V。
其中，所述下拉控制电路包括第三至第九可控开关，所述第三可控开关的控制端接收下级扫描信号，所述第三可控开关的第一端连接所述第六及第八可控开关的第一端，并接收所述开启电压，所述第三可控开关的第二端连接所述第四可控开关的第一端、所述第五可控开关的第一端、所述第七及第九可控开关的第二端及所述第二可控开关的控制端，所述第四可控开关的控制端连接所述第一可控开关的第二端，所述第四可控开关的第二端连接所述第五可控开关的第二端、第二可控开关的第二端及所述扫描输出电路，并接收所述关闭电压，所述第五可控开关的控制端接收上级扫描信号，所述第六可控开关的控制端接收第二时钟信号，所述第六可控开关的第二端连接所述第七可控开关的第一端，所述第七可控开关的控制端接收第三时钟信号，所述第八可控开关的控制端接收第四时钟信号，所述第八可控开关的第二端连接所述第九可控开关的第一端，所述第九可控开关的控制端接收第一时钟信号；
所述扫描输出电路包括第十至第十三可控开关及电容，所述第十可控开关的控制端连接所述第一可控开关的第二端、所述第二可控开关的第一端及所述第十一可控开关的控制端，所述第十可控开关的第一端连接所述第十一可控开关的第一端，并接收所述第一时钟信号，所述第十可控开关的第二端接收本级级传信号，所述第十一可控开关的第二端连接扫描信号输出端及所述第十三可控开关的第一端，所述第十三可控开关的控制端接收所述第三时钟信号，所述第十三可控开关的第二端连接所述第十二可控开关的第二端、所述第二可控开关的第二端、第五可控开关的第二端、第四可控开关的第二端，并接收所述关闭电压，所述第十二可控开关的控制端连接所述第二可控开关的控制端，所述第十二可控开关的第一端连接所述第十一可控开关的第二端、所述第十三可控开关的第一端及所述扫描信号输出端，所述电容连接在所述第十可控开关的控制端与所述第十二可控开关的第一端之间。
其中，所述下拉控制电路包括第三至第九可控开关，所述第三可控开关的控制端接收下级扫描信号，所述第三可控开关的第一端连接所述第六及第八可控开关的第一端，并接收所述开启电压，所述第三可控开关的第二端连接所述第四可控开关的第一端、所述第五可控开关的第一端、所述第七及第九可控开关的第二端及所述第二可控开关的控制端，所述第四可控开关的控制端连接所述第一可控开关的第二端，所述第四可控开关的第二端连接所述第五可控开关的第二端、第二可控开关的第二端及所述扫描输出电路，并接收所述关闭电压，所述第五可控开关的控制端接收上级扫描信号，所述第六可控开关的控制端接收第三时钟信号，所述第六可控开关的第二端连接所述第七可控开关的第一端，所述第七可控开关的控制端接收第四时钟信号，所述第八可控开关的控制端接收第一时钟信号，所述第八可控开关的第二端连接所述第九可控开关的第一端，所述第九可控开关的控制端接收第二时钟信号；
所述扫描输出电路包括第十至第十三可控开关及电容，所述第十可控开关的控制端连接所述第一可控开关的第二端、所述第二可控开关的第一端及所述第十一可控开关的控制端，所述第十可控开关的第一端连接所述第十一可控开关的第一端，并接收所述第二时钟信号，所述第十可控开关的第二端接收本级级传信号，所述第十一可控开关的第二端连接扫描信号输出端及所述第十三可控开关的第一端，所述第十三可控开关的控制端接收所述第四时钟信号，所述第十三可控开关的第二端连接所述第十二可控开关的第二端、所述第二可控开关的第二端、第五可控开关的第二端、第四可控开关的第二端，并接收所述关闭电压，所述第十二可控开关的控制端连接所述第二可控开关的控制端，所述第十二可控开关的第一端连接所述第十一可控开关的第二端、所述第十三可控开关的第一端及所述扫描信号输出端，所述电容连接在所述第十可控开关的控制端与所述第十二可控开关的第一端之间。
其中，所述下拉控制电路包括第三至第九可控开关，所述第三可控开关的控制端接收下级扫描信号，所述第三可控开关的第一端连接所述第六及第八可控开关的第一端，并接收所述开启电压，所述第三可控开关的第二端连接所述第四可控开关的第一端、所述第五可控开关的第一端、所述第七及第九可控开关的第二端及所述第二可控开关的控制端，所述第四可控开关的控制端连接所述第一可控开关的第二端，所述第四可控开关的第二端连接所述第五可控开关的第二端、第二可控开关的第二端及所述扫描输出电路，并接收所述关闭电压，所述第五可控开关的控制端接收上级扫描信号，所述第六可控开关的控制端接收第四时钟信号，所述第六可控开关的第二端连接所述第七可控开关的第一端，所述第七可控开关的控制端接收第一时钟信号，所述第八可控开关的控制端接收第二时钟信号，所述第八可控开关的第二端连接所述第九可控开关的第一端，所述第九可控开关的控制端接收第三时钟信号；
所述扫描输出电路包括第十至第十三可控开关及电容，所述第十可控开关的控制端连接所述第一可控开关的第二端、所述第二可控开关的第一端及所述第十一可控开关的控制端，所述第十可控开关的第一端连接所述第十一可控开关的第一端，并接收所述第三时钟信号，所述第十可控开关的第二端接收本级级传信号，所述第十一可控开关的第二端连接扫描信号输出端及所述第十三可控开关的第一端，所述第十三可控开关的控制端接收所述第一时钟信号，所述第十三可控开关的第二端连接所述第十二可控开关的第二端、所述第二可控开关的第二端、第五可控开关的第二端、第四可控开关的第二端，并接收所述关闭电压，所述第十二可控开关的控制端连接所述第二可控开关的控制端，所述第十二可控开关的第一端连接所述第十一可控开关的第二端、所述第十三可控开关的第一端及所述扫描信号输出端，所述电容连接在所述第十可控开关的控制端与所述第十二可控开关的第一端之间。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种显示面板，所述显示面板包括扫描驱动电路，所述扫描驱动电路包括：
上拉控制电路，用于将上拉控制信号点的电位上拉至高电平或者将所述上拉控制信号点的电位下拉至低电平；
下拉控制电路，连接所述上拉控制电路，用于将下拉控制信号点的电位上拉至高电平或者将所述下拉控制信号点的电位下拉至低电平；及
扫描输出电路，连接所述上拉控制电路及所述下拉控制电路，用于根据所述上拉控制信号点的电位及所述下拉控制信号点的电位输出高电平的扫描驱动信号或者低电平的扫描驱动信号。
其中，所述上拉控制电路包括第一及第二可控开关，所述第一可控开关的控制端接收上级级传信号，所述第一可控开关的第一端接收开启电压，所述第一可控开关的第二端连接所述第二可控开关的第一端、所述下拉控制电路及所述扫描输出电路，所述第二可控开关的控制端连接所述下拉控制电路及所述扫描输出电路，所述第二可控开关的第二端连接所述下拉控制电路及所述扫描输出电路，并接收关闭电压。
其中，所述下拉控制电路包括第三至第九可控开关，所述第三可控开关的控制端接收下级扫描信号，所述第三可控开关的第一端连接所述第六及第八可控开关的第一端，并接收所述开启电压，所述第三可控开关的第二端连接所述第四可控开关的第一端、所述第五可控开关的第一端、所述第七及第九可控开关的第二端及所述第二可控开关的控制端，所述第四可控开关的控制端连接所述第一可控开关的第二端，所述第四可控开关的第二端连接所述第五可控开关的第二端、第二可控开关的第二端及所述扫描输出电路，并接收所述关闭电压，所述第五可控开关的控制端接收上级扫描信号，所述第六可控开关的控制端接收第一时钟信号，所述第六可控开关的第二端连接所述第七可控开关的第一端，所述第七可控开关的控制端接收第二时钟信号，所述第八可控开关的控制端接收第三时钟信号，所述第八可控开关的第二端连接所述第九可控开关的第一端，所述第九可控开关的控制端接收第四时钟信号。
其中，所述扫描输出电路包括第十至第十三可控开关及电容，所述第十可控开关的控制端连接所述第一可控开关的第二端、所述第二可控开关的第一端及所述第十一可控开关的控制端，所述第十可控开关的第一端连接所述第十一可控开关的第一端，并接收所述第四时钟信号，所述第十可控开关的第二端接收本级级传信号，所述第十一可控开关的第二端连接扫描信号输出端及所述第十三可控开关的第一端，所述第十三可控开关的控制端接收所述第二时钟信号，所述第十三可控开关的第二端连接所述第十二可控开关的第二端、所述第二可控开关的第二端、第五可控开关的第二端、第四可控开关的第二端，并接收所述关闭电压，所述第十二可控开关的控制端连接所述第二可控开关的控制端，所述第十二可控开关的第一端连接所述第十一可控开关的第二端、所述第十三可控开关的第一端及所述扫描信号输出端，所述电容连接在所述第十可控开关的控制端与所述第十二可控开关的第一端之间。
其中，所述第一至第十三可控开关均为N型铟镓锌氧化物薄膜晶体管，所述第一至第十三可控开关的控制端、第一端及第二端分别对应N型铟镓锌氧化物薄膜晶体管的栅极、漏极及源极。
其中，所述第二时钟信号与所述第四时钟信号电位相反，所述第一时钟信号与所述第三时钟信号电位相反；所述第一至第四时钟信号的占空比为50%，相邻两个时钟信号之间重叠时间为时钟信号宽度的一半；所述第一至第四时钟信号的电压为-8V-28V；开启电压为28V，关闭电压为-6V。
其中，所述下拉控制电路包括第三至第九可控开关，所述第三可控开关的控制端接收下级扫描信号，所述第三可控开关的第一端连接所述第六及第八可控开关的第一端，并接收所述开启电压，所述第三可控开关的第二端连接所述第四可控开关的第一端、所述第五可控开关的第一端、所述第七及第九可控开关的第二端及所述第二可控开关的控制端，所述第四可控开关的控制端连接所述第一可控开关的第二端，所述第四可控开关的第二端连接所述第五可控开关的第二端、第二可控开关的第二端及所述扫描输出电路，并接收所述关闭电压，所述第五可控开关的控制端接收上级扫描信号，所述第六可控开关的控制端接收第二时钟信号，所述第六可控开关的第二端连接所述第七可控开关的第一端，所述第七可控开关的控制端接收第三时钟信号，所述第八可控开关的控制端接收第四时钟信号，所述第八可控开关的第二端连接所述第九可控开关的第一端，所述第九可控开关的控制端接收第一时钟信号；
所述扫描输出电路包括第十至第十三可控开关及电容，所述第十可控开关的控制端连接所述第一可控开关的第二端、所述第二可控开关的第一端及所述第十一可控开关的控制端，所述第十可控开关的第一端连接所述第十一可控开关的第一端，并接收所述第一时钟信号，所述第十可控开关的第二端接收本级级传信号，所述第十一可控开关的第二端连接扫描信号输出端及所述第十三可控开关的第一端，所述第十三可控开关的控制端接收所述第三时钟信号，所述第十三可控开关的第二端连接所述第十二可控开关的第二端、所述第二可控开关的第二端、第五可控开关的第二端、第四可控开关的第二端，并接收所述关闭电压，所述第十二可控开关的控制端连接所述第二可控开关的控制端，所述第十二可控开关的第一端连接所述第十一可控开关的第二端、所述第十三可控开关的第一端及所述扫描信号输出端，所述电容连接在所述第十可控开关的控制端与所述第十二可控开关的第一端之间。
其中，所述下拉控制电路包括第三至第九可控开关，所述第三可控开关的控制端接收下级扫描信号，所述第三可控开关的第一端连接所述第六及第八可控开关的第一端，并接收所述开启电压，所述第三可控开关的第二端连接所述第四可控开关的第一端、所述第五可控开关的第一端、所述第七及第九可控开关的第二端及所述第二可控开关的控制端，所述第四可控开关的控制端连接所述第一可控开关的第二端，所述第四可控开关的第二端连接所述第五可控开关的第二端、第二可控开关的第二端及所述扫描输出电路，并接收所述关闭电压，所述第五可控开关的控制端接收上级扫描信号，所述第六可控开关的控制端接收第三时钟信号，所述第六可控开关的第二端连接所述第七可控开关的第一端，所述第七可控开关的控制端接收第四时钟信号，所述第八可控开关的控制端接收第一时钟信号，所述第八可控开关的第二端连接所述第九可控开关的第一端，所述第九可控开关的控制端接收第二时钟信号；
所述扫描输出电路包括第十至第十三可控开关及电容，所述第十可控开关的控制端连接所述第一可控开关的第二端、所述第二可控开关的第一端及所述第十一可控开关的控制端，所述第十可控开关的第一端连接所述第十一可控开关的第一端，并接收所述第二时钟信号，所述第十可控开关的第二端接收本级级传信号，所述第十一可控开关的第二端连接扫描信号输出端及所述第十三可控开关的第一端，所述第十三可控开关的控制端接收所述第四时钟信号，所述第十三可控开关的第二端连接所述第十二可控开关的第二端、所述第二可控开关的第二端、第五可控开关的第二端、第四可控开关的第二端，并接收所述关闭电压，所述第十二可控开关的控制端连接所述第二可控开关的控制端，所述第十二可控开关的第一端连接所述第十一可控开关的第二端、所述第十三可控开关的第一端及所述扫描信号输出端，所述电容连接在所述第十可控开关的控制端与所述第十二可控开关的第一端之间。
其中，所述下拉控制电路包括第三至第九可控开关，所述第三可控开关的控制端接收下级扫描信号，所述第三可控开关的第一端连接所述第六及第八可控开关的第一端，并接收所述开启电压，所述第三可控开关的第二端连接所述第四可控开关的第一端、所述第五可控开关的第一端、所述第七及第九可控开关的第二端及所述第二可控开关的控制端，所述第四可控开关的控制端连接所述第一可控开关的第二端，所述第四可控开关的第二端连接所述第五可控开关的第二端、第二可控开关的第二端及所述扫描输出电路，并接收所述关闭电压，所述第五可控开关的控制端接收上级扫描信号，所述第六可控开关的控制端接收第四时钟信号，所述第六可控开关的第二端连接所述第七可控开关的第一端，所述第七可控开关的控制端接收第一时钟信号，所述第八可控开关的控制端接收第二时钟信号，所述第八可控开关的第二端连接所述第九可控开关的第一端，所述第九可控开关的控制端接收第三时钟信号；
所述扫描输出电路包括第十至第十三可控开关及电容，所述第十可控开关的控制端连接所述第一可控开关的第二端、所述第二可控开关的第一端及所述第十一可控开关的控制端，所述第十可控开关的第一端连接所述第十一可控开关的第一端，并接收所述第三时钟信号，所述第十可控开关的第二端接收本级级传信号，所述第十一可控开关的第二端连接扫描信号输出端及所述第十三可控开关的第一端，所述第十三可控开关的控制端接收所述第一时钟信号，所述第十三可控开关的第二端连接所述第十二可控开关的第二端、所述第二可控开关的第二端、第五可控开关的第二端、第四可控开关的第二端，并接收所述关闭电压，所述第十二可控开关的控制端连接所述第二可控开关的控制端，所述第十二可控开关的第一端连接所述第十一可控开关的第二端、所述第十三可控开关的第一端及所述扫描信号输出端，所述电容连接在所述第十可控开关的控制端与所述第十二可控开关的第一端之间。
本发明的有益效果是：区别于现有技术的情况，本发明的所述扫描驱动电路及显示面板通过在所述上拉控制电路、下拉控制电路及扫描输出电路中设置IGZO薄膜晶体管，从而减少了所述扫描驱动电路中电源及薄膜晶体管的数量，以此使得电路简单且功耗低。
【附图说明】
图1是本发明的扫描驱动电路的第一实施例的电路图；
图2是本发明的扫描驱动电路的波形图；
图3是本发明的扫描驱动电路的第二实施例的电路图；
图4是本发明的扫描驱动电路的第三实施例的电路图；
图5是本发明的扫描驱动电路的第四实施例的电路图；
图6是本发明的显示面板的结构示意图。
【具体实施方式】
请参阅图1及图2，是本发明的扫描驱动电路1的第一实施例的电路图。所述扫描驱动电路包括上拉控制电路10，用于将所述上拉控制信号点的电位上拉至高电平或者将所述上拉控制信号点的电位下拉至低电平；下拉控制电路20，连接所述上拉控制电路10，用于将所述下拉控制信号点的电位上拉至高电平或者将所述下拉控制信号点的电位下拉至低电平；扫描输出电路30，连接所述上拉控制电路10及所述下拉控制电路20，用于根据所述上拉控制信号点的电位及所述下拉控制信号点的电位输出高电平的扫描驱动信号或者低电平的扫描驱动信号。
具体地，所述上拉控制电路10包括第一及第二可控开关T1、T2，所述第一可控开关T1的控制端接收上级级传信号，所述第一可控开关T1的第一端接收开启电压VGH，所述第一可控开关T1的第二端连接所述第二可控开关T2的第一端、所述下拉控制电路20及所述扫描输出电路30，所述第二可控开关T2的控制端连接所述下拉控制电路20及所述扫描输出电路30，所述第二可控开关T2的第二端连接所述下拉控制电路20及所述扫描输出电路30，并接收关闭电压VSS。
所述下拉控制电路20包括第三至第九可控开关T3-T9，所述第三可控开关T3的控制端接收下级扫描信号，所述第三可控开关T3的第一端连接所述第六可控开关T6的第一端及第八可控开关T8的第一端，并接收所述开启电压VGH，所述第三可控开关T3的第二端连接所述第四可控开关T4的第一端、所述第五可控开关T5的第一端、所述第七及第九可控开关T7、T9的第二端及所述第二可控开关T2的控制端，所述第四可控开关T4的控制端连接所述第一可控开关T1的第二端，所述第四可控开关T4的第二端连接所述第五可控开关T5的第二端、第二可控开关T2的第二端及所述扫描输出电路30，并接收所述关闭电压VSS，所述第五可控开关T5的控制端接收上级扫描信号，所述第六可控开关T6的控制端接收第一时钟信号CK2，所述第六可控开关T6的第二端连接所述第七可控开关T7的第一端，所述第七可控开关T7的控制端接收第二时钟信号CK3，所述第八可控开关T8的控制端接收第三时钟信号CK4，所述第八可控开关T8的第二端连接所述第九可控开关T9的第一端，所述第九可控开关T9的控制端接收第四时钟信号CK1。
所述扫描输出电路30包括第十至第十三可控开关T10-T13及电容C1，所述第十可控开关T10的控制端连接所述第一可控开关T1的第二端、所述第二可控开关T2的第一端及所述第十一可控开关T11的控制端，所述第十可控开关T10的第一端连接所述第十一可控开关T11的第一端，并接收所述第四时钟信号CK1，所述第十可控开关T10的第二端接收本级级传信号，所述第十一可控开关T11的第二端连接扫描信号输出端用于输出本级扫描信号及所述第十三可控开关T13的第一端，所述第十三可控开关T13的控制端接收所述第二时钟信号CK3，所述第十三可控开关T13的第二端连接所述第十二可控开关T12的第二端、所述第二可控开关T2的第二端、第五可控开关T5的第二端、第四可控开关T4的第二端，并接收所述关闭电压VSS，所述第十二可控开关T12的控制端连接所述第二可控开关T2的控制端，所述第十二可控开关T12的第一端连接所述第十一可控开关T11的第二端、所述第十三可控开关T13的第一端及所述扫描信号输出端，所述电容C1连接在所述第十可控开关T10的控制端与所述第十二可控开关T12的第一端之间。
在本实施例中，所述第一至第十三可控开关T1-T13均为N型铟镓锌氧化物薄膜晶体管，所述第一至第十三可控开关T1-T13的控制端、第一端及第二端分别对应N型铟镓锌氧化物薄膜晶体管的栅极、漏极及源极。在其他实施例中，也可以采用其他类型的开关，只要能实现本发明的目的即可。
在本实施例中，所述第二时钟信号CK2与所述第四时钟信号CK4电位相反，所述第一时钟信号CK1与所述第三时钟信号CK3电位相反。所述第一至第四时钟信号CK1-CK4的占空比为50%。相邻两个时钟信号之间重叠时间为时钟信号宽度的一半。所述第一至第四时钟信号CK1-CK4的电压为-8V-28V。开启电压VGH为28V，关闭电压VSS为-6V。
其中，所述上级级传信号为ST（N-2），所述本级级传信号为ST（N），所述本级扫描信号为G（N），所述上级扫描信号为G（N-1），所述下级扫描信号为G（N+2），所述第一时钟信号为CK2，所述第二时钟信号为CK3，所述第三时钟信号为CK4，所述第四时钟信号为CK1，所述开启电压为VGH，所述关闭电压为VSS。
所述扫描驱动电路的工作原理如下所述，其中以输出扫描信号G（5）为例进行详细说明。
其中，本级扫描信号G(N)=G(5)，上级级传信号ST(N-2)=ST(3)，本级级传信号ST(N)=ST(3)，上级扫描信号G(N-1)=G(4)，下级扫描信号G(N+2)=G(7)，上拉控制信号点Q(N)=Q(5)，下拉控制信号点P(N)=P(5)。
当所述上级级传信号ST(3)为高电平时，所述第一可控开关T1导通，所述上拉控制信号点Q(5)为高电平，所述第十可控开关T10及所述第十一可控开关T11均导通，此时，所述第四时钟信号CK1为高电平，因此本级扫描信号G(5)和本级级传信号ST(5)均为高电平，因为所述第四可控开关T4导通，因此关闭电压VSS将所述下拉控制信号点 P(5)拉低为低电平，所述第二可控开关T2及所述第十二可控开关T12均截止，此时所述本级扫描信号G(5)为高电平。
当所述上级级传信号ST(3)为低电平时，所述第一可控开关T1截止，所述上拉控制信号点Q(5)由于受到电容的耦合效应，其高电平变得更高，所述第十可控开关T10及所述第十一可控开关T11均导通，此时，所述第四时钟信号CK1为高电平，因此本级扫描信号G(5)和本级级传信号ST(5)均为高电平，因为所述第四可控开关T4导通，因此关闭电压VSS将所述下拉控制信号点 P(5)拉低为低电平，此时所述第二可控开关T2及所述第十二可控开关T12均截止，因此不影响所述上拉控制信号点Q（5）的电位，此外，由于上级扫描信号G(4)为高电平，因此所述第五可控开关T5导通，所述关闭电压VSS会使得下拉控制信号点P(5)的低电位保持的更好, 所述第二可控开关T2及所述第十二可控开关T12均截止，此时所述本级扫描信号G(5)为高电平。
当所述第四时钟信号CK1为低电平时，所述第二时钟信号CK3为高电平，所述第十三可控开关T13导通，所述关闭电压VSS将本级扫描信号G(5)拉低为低电平，同时，由于下级扫描信号G(7)为高电平，因此所述第三可控开关T3导通，所述开启电压VGH使得所述下拉控制信号点P(5)为高电平，所述第二可控开关T2及所述第十二可控开关T12均导通，所述关闭电压VSS将所述上拉控制信号点Q(5)及所述本级扫描信号G(5)均拉低至低电平。
因为所述第六可控开关T6受到所述第一时钟信号CK2控制，所述第七可控开关T7受到所述第二时钟信号CK3控制，所述第八可控开关T8受到所述第三时钟信号CK4控制，所述第九可控开关T9受到所述第四时钟信号CK1控制，因此保证了一帧之内所述下拉控制信号点P(5)为高电平，从而保证了所述本级扫描信号G(5)的低电位。
其中，所述第十三可控开关T13的控制端接收与所述第四时钟信号CK1电位相反的第二时钟信号CK3，使得所述第二时钟信号CK3周期性的打开更加保证了所述本级扫描信号G(5)的低电位。
请参阅图3，是本发明的扫描驱动电路1的第二实施例的电路图。所述扫描驱动电路的第二实施例与上述第一实施例的区别之处在于：所述下拉控制电路20中的所述第六可控开关T6的控制端接收第二时钟信号CK3，所述第七可控开关T7的控制端接收第三时钟信号CK4，所述第八可控开关T8的控制端接收第四时钟信号CK1，所述第九可控开关T9的控制端接收第一时钟信号CK2；
所述扫描输出电路30中的所述第十可控开关T10的第一端连接所述第十一可控开关T11的第一端，并接收所述第一时钟信号CK2，所述第十三可控开关T13的控制端接收所述第三时钟信号CK4。
请参阅图4，是本发明的扫描驱动电路1的第三实施例的电路图。所述扫描驱动电路的第三实施例与上述第一实施例的区别之处在于：所述下拉控制电路20中的所述第六可控开关T6的控制端接收第三时钟信号CK4，所述第七可控开关T7的控制端接收第四时钟信号CK1，所述第八可控开关T8的控制端接收第一时钟信号CK2，所述第九可控开关T9的控制端接收第二时钟信号CK3；
所述扫描输出电路30中的所述第十可控开关T10的第一端连接所述第十一可控开关T11的第一端，并接收所述第二时钟信号CK3，所述第十三可控开关的控制端接收所述第四时钟信号CK1。
请参阅图5，是本发明的扫描驱动电路1的第二实施例的电路图。所述扫描驱动电路的第二实施例与上述第一实施例的区别之处在于：所述下拉控制电路20中的所述第六可控开关T6的控制端接收第四时钟信号CK1，所述第七可控开关T7的控制端接收第一时钟信号CK2，所述第八可控开关T8的控制端接收第二时钟信号CK3，所述第九可控开关T9的控制端接收第三时钟信号CK4；
所述扫描输出电路30中的所述第十可控开关T10的第一端连接所述第十一可控开关T11的第一端，并接收所述第三时钟信号CK4，所述第十三可控开关的控制端接收所述第一时钟信号CK2。
其中，所述扫描驱动电路的第二至第四实施例的工作原理与上述所述扫描驱动电路的第一实施例的工作原理相同，在此不再赘述。
请参阅图6，为本发明一种显示面板2的结构示意图。所述显示面板2包括前述的扫描驱动电路1，所述显示面板2中的其他器件及功能与现有显示面板的器件及功能相同，在此不再赘述。所述显示面板2为LCD或OLED。
所述扫描驱动电路及显示面板通过在所述上拉控制电路、下拉控制电路及扫描输出电路中设置IGZO薄膜晶体管，从而减少了所述扫描驱动电路中电源及薄膜晶体管的数量，以此使得电路简单且功耗低。
以上仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (19)

  1. 一种扫描驱动电路，其中，所述扫描驱动电路包括：
    上拉控制电路，用于将上拉控制信号点的电位上拉至高电平或者将所述上拉控制信号点的电位下拉至低电平；
    下拉控制电路，连接所述上拉控制电路，用于将下拉控制信号点的电位上拉至高电平或者将所述下拉控制信号点的电位下拉至低电平；及
    扫描输出电路，连接所述上拉控制电路及所述下拉控制电路，用于根据所述上拉控制信号点的电位及所述下拉控制信号点的电位输出高电平的扫描驱动信号或者低电平的扫描驱动信号；
    所述上拉控制电路包括第一及第二可控开关，所述第一可控开关的控制端接收上级级传信号，所述第一可控开关的第一端接收开启电压，所述第一可控开关的第二端连接所述第二可控开关的第一端、所述下拉控制电路及所述扫描输出电路，所述第二可控开关的控制端连接所述下拉控制电路及所述扫描输出电路，所述第二可控开关的第二端连接所述下拉控制电路及所述扫描输出电路，并接收关闭电压。
    所述下拉控制电路包括第三至第九可控开关，所述第三可控开关的控制端接收下级扫描信号，所述第三可控开关的第一端连接所述第六及第八可控开关的第一端，并接收所述开启电压，所述第三可控开关的第二端连接所述第四可控开关的第一端、所述第五可控开关的第一端、所述第七及第九可控开关的第二端及所述第二可控开关的控制端，所述第四可控开关的控制端连接所述第一可控开关的第二端，所述第四可控开关的第二端连接所述第五可控开关的第二端、第二可控开关的第二端及所述扫描输出电路，并接收所述关闭电压，所述第五可控开关的控制端接收上级扫描信号，所述第六可控开关的控制端接收第一时钟信号，所述第六可控开关的第二端连接所述第七可控开关的第一端，所述第七可控开关的控制端接收第二时钟信号，所述第八可控开关的控制端接收第三时钟信号，所述第八可控开关的第二端连接所述第九可控开关的第一端，所述第九可控开关的控制端接收第四时钟信号。
    所述扫描输出电路包括第十至第十三可控开关及电容，所述第十可控开关的控制端连接所述第一可控开关的第二端、所述第二可控开关的第一端及所述第十一可控开关的控制端，所述第十可控开关的第一端连接所述第十一可控开关的第一端，并接收所述第四时钟信号，所述第十可控开关的第二端接收本级级传信号，所述第十一可控开关的第二端连接扫描信号输出端及所述第十三可控开关的第一端，所述第十三可控开关的控制端接收所述第二时钟信号，所述第十三可控开关的第二端连接所述第十二可控开关的第二端、所述第二可控开关的第二端、第五可控开关的第二端、第四可控开关的第二端，并接收所述关闭电压，所述第十二可控开关的控制端连接所述第二可控开关的控制端，所述第十二可控开关的第一端连接所述第十一可控开关的第二端、所述第十三可控开关的第一端及所述扫描信号输出端，所述电容连接在所述第十可控开关的控制端与所述第十二可控开关的第一端之间。
    所述第一至第十三可控开关均为N型铟镓锌氧化物薄膜晶体管，所述第一至第十三可控开关的控制端、第一端及第二端分别对应N型铟镓锌氧化物薄膜晶体管的栅极、漏极及源极。
    所述第二时钟信号与所述第四时钟信号电位相反，所述第一时钟信号与所述第三时钟信号电位相反；所述第一至第四时钟信号的占空比为50%，相邻两个时钟信号之间重叠时间为时钟信号宽度的一半；所述第一至第四时钟信号的电压为-8V-28V；开启电压为28V，关闭电压为-6V。
  2. 一种扫描驱动电路，其中，所述扫描驱动电路包括：
    上拉控制电路，用于将上拉控制信号点的电位上拉至高电平或者将所述上拉控制信号点的电位下拉至低电平；
    下拉控制电路，连接所述上拉控制电路，用于将下拉控制信号点的电位上拉至高电平或者将所述下拉控制信号点的电位下拉至低电平；及
    扫描输出电路，连接所述上拉控制电路及所述下拉控制电路，用于根据所述上拉控制信号点的电位及所述下拉控制信号点的电位输出高电平的扫描驱动信号或者低电平的扫描驱动信号。
  3. 根据权利要求2所述的扫描驱动电路，其中，所述上拉控制电路包括第一及第二可控开关，所述第一可控开关的控制端接收上级级传信号，所述第一可控开关的第一端接收开启电压，所述第一可控开关的第二端连接所述第二可控开关的第一端、所述下拉控制电路及所述扫描输出电路，所述第二可控开关的控制端连接所述下拉控制电路及所述扫描输出电路，所述第二可控开关的第二端连接所述下拉控制电路及所述扫描输出电路，并接收关闭电压。
  4. 根据权利要求3所述的扫描驱动电路，其中，所述下拉控制电路包括第三至第九可控开关，所述第三可控开关的控制端接收下级扫描信号，所述第三可控开关的第一端连接所述第六及第八可控开关的第一端，并接收所述开启电压，所述第三可控开关的第二端连接所述第四可控开关的第一端、所述第五可控开关的第一端、所述第七及第九可控开关的第二端及所述第二可控开关的控制端，所述第四可控开关的控制端连接所述第一可控开关的第二端，所述第四可控开关的第二端连接所述第五可控开关的第二端、第二可控开关的第二端及所述扫描输出电路，并接收所述关闭电压，所述第五可控开关的控制端接收上级扫描信号，所述第六可控开关的控制端接收第一时钟信号，所述第六可控开关的第二端连接所述第七可控开关的第一端，所述第七可控开关的控制端接收第二时钟信号，所述第八可控开关的控制端接收第三时钟信号，所述第八可控开关的第二端连接所述第九可控开关的第一端，所述第九可控开关的控制端接收第四时钟信号。
  5. 根据权利要求4所述的扫描驱动电路，其中，所述扫描输出电路包括第十至第十三可控开关及电容，所述第十可控开关的控制端连接所述第一可控开关的第二端、所述第二可控开关的第一端及所述第十一可控开关的控制端，所述第十可控开关的第一端连接所述第十一可控开关的第一端，并接收所述第四时钟信号，所述第十可控开关的第二端接收本级级传信号，所述第十一可控开关的第二端连接扫描信号输出端及所述第十三可控开关的第一端，所述第十三可控开关的控制端接收所述第二时钟信号，所述第十三可控开关的第二端连接所述第十二可控开关的第二端、所述第二可控开关的第二端、第五可控开关的第二端、第四可控开关的第二端，并接收所述关闭电压，所述第十二可控开关的控制端连接所述第二可控开关的控制端，所述第十二可控开关的第一端连接所述第十一可控开关的第二端、所述第十三可控开关的第一端及所述扫描信号输出端，所述电容连接在所述第十可控开关的控制端与所述第十二可控开关的第一端之间。
  6. 根据权利要求5所述的扫描驱动电路，其中，所述第一至第十三可控开关均为N型铟镓锌氧化物薄膜晶体管，所述第一至第十三可控开关的控制端、第一端及第二端分别对应N型铟镓锌氧化物薄膜晶体管的栅极、漏极及源极。
  7. 根据权要求5所述的扫描驱动电路，其中，所述第二时钟信号与所述第四时钟信号电位相反，所述第一时钟信号与所述第三时钟信号电位相反；所述第一至第四时钟信号的占空比为50%，相邻两个时钟信号之间重叠时间为时钟信号宽度的一半；所述第一至第四时钟信号的电压为-8V-28V；开启电压为28V，关闭电压为-6V。
  8. 根据权要求3所述的扫描驱动电路，其中，所述下拉控制电路包括第三至第九可控开关，所述第三可控开关的控制端接收下级扫描信号，所述第三可控开关的第一端连接所述第六及第八可控开关的第一端，并接收所述开启电压，所述第三可控开关的第二端连接所述第四可控开关的第一端、所述第五可控开关的第一端、所述第七及第九可控开关的第二端及所述第二可控开关的控制端，所述第四可控开关的控制端连接所述第一可控开关的第二端，所述第四可控开关的第二端连接所述第五可控开关的第二端、第二可控开关的第二端及所述扫描输出电路，并接收所述关闭电压，所述第五可控开关的控制端接收上级扫描信号，所述第六可控开关的控制端接收第二时钟信号，所述第六可控开关的第二端连接所述第七可控开关的第一端，所述第七可控开关的控制端接收第三时钟信号，所述第八可控开关的控制端接收第四时钟信号，所述第八可控开关的第二端连接所述第九可控开关的第一端，所述第九可控开关的控制端接收第一时钟信号；
    所述扫描输出电路包括第十至第十三可控开关及电容，所述第十可控开关的控制端连接所述第一可控开关的第二端、所述第二可控开关的第一端及所述第十一可控开关的控制端，所述第十可控开关的第一端连接所述第十一可控开关的第一端，并接收所述第一时钟信号，所述第十可控开关的第二端接收本级级传信号，所述第十一可控开关的第二端连接扫描信号输出端及所述第十三可控开关的第一端，所述第十三可控开关的控制端接收所述第三时钟信号，所述第十三可控开关的第二端连接所述第十二可控开关的第二端、所述第二可控开关的第二端、第五可控开关的第二端、第四可控开关的第二端，并接收所述关闭电压，所述第十二可控开关的控制端连接所述第二可控开关的控制端，所述第十二可控开关的第一端连接所述第十一可控开关的第二端、所述第十三可控开关的第一端及所述扫描信号输出端，所述电容连接在所述第十可控开关的控制端与所述第十二可控开关的第一端之间。
  9. 根据权要求2所述的扫描驱动电路，其中，所述下拉控制电路包括第三至第九可控开关，所述第三可控开关的控制端接收下级扫描信号，所述第三可控开关的第一端连接所述第六及第八可控开关的第一端，并接收所述开启电压，所述第三可控开关的第二端连接所述第四可控开关的第一端、所述第五可控开关的第一端、所述第七及第九可控开关的第二端及所述第二可控开关的控制端，所述第四可控开关的控制端连接所述第一可控开关的第二端，所述第四可控开关的第二端连接所述第五可控开关的第二端、第二可控开关的第二端及所述扫描输出电路，并接收所述关闭电压，所述第五可控开关的控制端接收上级扫描信号，所述第六可控开关的控制端接收第三时钟信号，所述第六可控开关的第二端连接所述第七可控开关的第一端，所述第七可控开关的控制端接收第四时钟信号，所述第八可控开关的控制端接收第一时钟信号，所述第八可控开关的第二端连接所述第九可控开关的第一端，所述第九可控开关的控制端接收第二时钟信号；
    所述扫描输出电路包括第十至第十三可控开关及电容，所述第十可控开关的控制端连接所述第一可控开关的第二端、所述第二可控开关的第一端及所述第十一可控开关的控制端，所述第十可控开关的第一端连接所述第十一可控开关的第一端，并接收所述第二时钟信号，所述第十可控开关的第二端接收本级级传信号，所述第十一可控开关的第二端连接扫描信号输出端及所述第十三可控开关的第一端，所述第十三可控开关的控制端接收所述第四时钟信号，所述第十三可控开关的第二端连接所述第十二可控开关的第二端、所述第二可控开关的第二端、第五可控开关的第二端、第四可控开关的第二端，并接收所述关闭电压，所述第十二可控开关的控制端连接所述第二可控开关的控制端，所述第十二可控开关的第一端连接所述第十一可控开关的第二端、所述第十三可控开关的第一端及所述扫描信号输出端，所述电容连接在所述第十可控开关的控制端与所述第十二可控开关的第一端之间。
  10. 根据权要求3所述的扫描驱动电路，其中，所述下拉控制电路包括第三至第九可控开关，所述第三可控开关的控制端接收下级扫描信号，所述第三可控开关的第一端连接所述第六及第八可控开关的第一端，并接收所述开启电压，所述第三可控开关的第二端连接所述第四可控开关的第一端、所述第五可控开关的第一端、所述第七及第九可控开关的第二端及所述第二可控开关的控制端，所述第四可控开关的控制端连接所述第一可控开关的第二端，所述第四可控开关的第二端连接所述第五可控开关的第二端、第二可控开关的第二端及所述扫描输出电路，并接收所述关闭电压，所述第五可控开关的控制端接收上级扫描信号，所述第六可控开关的控制端接收第四时钟信号，所述第六可控开关的第二端连接所述第七可控开关的第一端，所述第七可控开关的控制端接收第一时钟信号，所述第八可控开关的控制端接收第二时钟信号，所述第八可控开关的第二端连接所述第九可控开关的第一端，所述第九可控开关的控制端接收第三时钟信号；
    所述扫描输出电路包括第十至第十三可控开关及电容，所述第十可控开关的控制端连接所述第一可控开关的第二端、所述第二可控开关的第一端及所述第十一可控开关的控制端，所述第十可控开关的第一端连接所述第十一可控开关的第一端，并接收所述第三时钟信号，所述第十可控开关的第二端接收本级级传信号，所述第十一可控开关的第二端连接扫描信号输出端及所述第十三可控开关的第一端，所述第十三可控开关的控制端接收所述第一时钟信号，所述第十三可控开关的第二端连接所述第十二可控开关的第二端、所述第二可控开关的第二端、第五可控开关的第二端、第四可控开关的第二端，并接收所述关闭电压，所述第十二可控开关的控制端连接所述第二可控开关的控制端，所述第十二可控开关的第一端连接所述第十一可控开关的第二端、所述第十三可控开关的第一端及所述扫描信号输出端，所述电容连接在所述第十可控开关的控制端与所述第十二可控开关的第一端之间。
  11. 一种显示面板，其中，所述显示面板包括扫描驱动电路，所述扫描驱动电路包括：
    上拉控制电路，用于将上拉控制信号点的电位上拉至高电平或者将所述上拉控制信号点的电位下拉至低电平；
    下拉控制电路，连接所述上拉控制电路，用于将下拉控制信号点的电位上拉至高电平或者将所述下拉控制信号点的电位下拉至低电平；及
    扫描输出电路，连接所述上拉控制电路及所述下拉控制电路，用于根据所述上拉控制信号点的电位及所述下拉控制信号点的电位输出高电平的扫描驱动信号或者低电平的扫描驱动信号。
  12. 根据权利要求11所述的显示面板，其中，所述上拉控制电路包括第一及第二可控开关，所述第一可控开关的控制端接收上级级传信号，所述第一可控开关的第一端接收开启电压，所述第一可控开关的第二端连接所述第二可控开关的第一端、所述下拉控制电路及所述扫描输出电路，所述第二可控开关的控制端连接所述下拉控制电路及所述扫描输出电路，所述第二可控开关的第二端连接所述下拉控制电路及所述扫描输出电路，并接收关闭电压。
  13. 根据权利要求12所述的显示面板，其中，所述下拉控制电路包括第三至第九可控开关，所述第三可控开关的控制端接收下级扫描信号，所述第三可控开关的第一端连接所述第六及第八可控开关的第一端，并接收所述开启电压，所述第三可控开关的第二端连接所述第四可控开关的第一端、所述第五可控开关的第一端、所述第七及第九可控开关的第二端及所述第二可控开关的控制端，所述第四可控开关的控制端连接所述第一可控开关的第二端，所述第四可控开关的第二端连接所述第五可控开关的第二端、第二可控开关的第二端及所述扫描输出电路，并接收所述关闭电压，所述第五可控开关的控制端接收上级扫描信号，所述第六可控开关的控制端接收第一时钟信号，所述第六可控开关的第二端连接所述第七可控开关的第一端，所述第七可控开关的控制端接收第二时钟信号，所述第八可控开关的控制端接收第三时钟信号，所述第八可控开关的第二端连接所述第九可控开关的第一端，所述第九可控开关的控制端接收第四时钟信号。
  14. 根据权利要求13所述的显示面板，其中，所述扫描输出电路包括第十至第十三可控开关及电容，所述第十可控开关的控制端连接所述第一可控开关的第二端、所述第二可控开关的第一端及所述第十一可控开关的控制端，所述第十可控开关的第一端连接所述第十一可控开关的第一端，并接收所述第四时钟信号，所述第十可控开关的第二端接收本级级传信号，所述第十一可控开关的第二端连接扫描信号输出端及所述第十三可控开关的第一端，所述第十三可控开关的控制端接收所述第二时钟信号，所述第十三可控开关的第二端连接所述第十二可控开关的第二端、所述第二可控开关的第二端、第五可控开关的第二端、第四可控开关的第二端，并接收所述关闭电压，所述第十二可控开关的控制端连接所述第二可控开关的控制端，所述第十二可控开关的第一端连接所述第十一可控开关的第二端、所述第十三可控开关的第一端及所述扫描信号输出端，所述电容连接在所述第十可控开关的控制端与所述第十二可控开关的第一端之间。
  15. 根据权利要求14所述的显示面板，其中，所述第一至第十三可控开关均为N型铟镓锌氧化物薄膜晶体管，所述第一至第十三可控开关的控制端、第一端及第二端分别对应N型铟镓锌氧化物薄膜晶体管的栅极、漏极及源极。
  16. 根据权要求14所述的显示面板，其中，所述第二时钟信号与所述第四时钟信号电位相反，所述第一时钟信号与所述第三时钟信号电位相反；所述第一至第四时钟信号的占空比为50%，相邻两个时钟信号之间重叠时间为时钟信号宽度的一半；所述第一至第四时钟信号的电压为-8V-28V；开启电压为28V，关闭电压为-6V。
  17. 根据权要求12所述的显示面板，其中，所述下拉控制电路包括第三至第九可控开关，所述第三可控开关的控制端接收下级扫描信号，所述第三可控开关的第一端连接所述第六及第八可控开关的第一端，并接收所述开启电压，所述第三可控开关的第二端连接所述第四可控开关的第一端、所述第五可控开关的第一端、所述第七及第九可控开关的第二端及所述第二可控开关的控制端，所述第四可控开关的控制端连接所述第一可控开关的第二端，所述第四可控开关的第二端连接所述第五可控开关的第二端、第二可控开关的第二端及所述扫描输出电路，并接收所述关闭电压，所述第五可控开关的控制端接收上级扫描信号，所述第六可控开关的控制端接收第二时钟信号，所述第六可控开关的第二端连接所述第七可控开关的第一端，所述第七可控开关的控制端接收第三时钟信号，所述第八可控开关的控制端接收第四时钟信号，所述第八可控开关的第二端连接所述第九可控开关的第一端，所述第九可控开关的控制端接收第一时钟信号；
    所述扫描输出电路包括第十至第十三可控开关及电容，所述第十可控开关的控制端连接所述第一可控开关的第二端、所述第二可控开关的第一端及所述第十一可控开关的控制端，所述第十可控开关的第一端连接所述第十一可控开关的第一端，并接收所述第一时钟信号，所述第十可控开关的第二端接收本级级传信号，所述第十一可控开关的第二端连接扫描信号输出端及所述第十三可控开关的第一端，所述第十三可控开关的控制端接收所述第三时钟信号，所述第十三可控开关的第二端连接所述第十二可控开关的第二端、所述第二可控开关的第二端、第五可控开关的第二端、第四可控开关的第二端，并接收所述关闭电压，所述第十二可控开关的控制端连接所述第二可控开关的控制端，所述第十二可控开关的第一端连接所述第十一可控开关的第二端、所述第十三可控开关的第一端及所述扫描信号输出端，所述电容连接在所述第十可控开关的控制端与所述第十二可控开关的第一端之间。
  18. 根据权要求12所述的显示面板，其中，所述下拉控制电路包括第三至第九可控开关，所述第三可控开关的控制端接收下级扫描信号，所述第三可控开关的第一端连接所述第六及第八可控开关的第一端，并接收所述开启电压，所述第三可控开关的第二端连接所述第四可控开关的第一端、所述第五可控开关的第一端、所述第七及第九可控开关的第二端及所述第二可控开关的控制端，所述第四可控开关的控制端连接所述第一可控开关的第二端，所述第四可控开关的第二端连接所述第五可控开关的第二端、第二可控开关的第二端及所述扫描输出电路，并接收所述关闭电压，所述第五可控开关的控制端接收上级扫描信号，所述第六可控开关的控制端接收第三时钟信号，所述第六可控开关的第二端连接所述第七可控开关的第一端，所述第七可控开关的控制端接收第四时钟信号，所述第八可控开关的控制端接收第一时钟信号，所述第八可控开关的第二端连接所述第九可控开关的第一端，所述第九可控开关的控制端接收第二时钟信号；
    所述扫描输出电路包括第十至第十三可控开关及电容，所述第十可控开关的控制端连接所述第一可控开关的第二端、所述第二可控开关的第一端及所述第十一可控开关的控制端，所述第十可控开关的第一端连接所述第十一可控开关的第一端，并接收所述第二时钟信号，所述第十可控开关的第二端接收本级级传信号，所述第十一可控开关的第二端连接扫描信号输出端及所述第十三可控开关的第一端，所述第十三可控开关的控制端接收所述第四时钟信号，所述第十三可控开关的第二端连接所述第十二可控开关的第二端、所述第二可控开关的第二端、第五可控开关的第二端、第四可控开关的第二端，并接收所述关闭电压，所述第十二可控开关的控制端连接所述第二可控开关的控制端，所述第十二可控开关的第一端连接所述第十一可控开关的第二端、所述第十三可控开关的第一端及所述扫描信号输出端，所述电容连接在所述第十可控开关的控制端与所述第十二可控开关的第一端之间。
  19. 根据权要求12所述的显示面板，其中，所述下拉控制电路包括第三至第九可控开关，所述第三可控开关的控制端接收下级扫描信号，所述第三可控开关的第一端连接所述第六及第八可控开关的第一端，并接收所述开启电压，所述第三可控开关的第二端连接所述第四可控开关的第一端、所述第五可控开关的第一端、所述第七及第九可控开关的第二端及所述第二可控开关的控制端，所述第四可控开关的控制端连接所述第一可控开关的第二端，所述第四可控开关的第二端连接所述第五可控开关的第二端、第二可控开关的第二端及所述扫描输出电路，并接收所述关闭电压，所述第五可控开关的控制端接收上级扫描信号，所述第六可控开关的控制端接收第四时钟信号，所述第六可控开关的第二端连接所述第七可控开关的第一端，所述第七可控开关的控制端接收第一时钟信号，所述第八可控开关的控制端接收第二时钟信号，所述第八可控开关的第二端连接所述第九可控开关的第一端，所述第九可控开关的控制端接收第三时钟信号；
    所述扫描输出电路包括第十至第十三可控开关及电容，所述第十可控开关的控制端连接所述第一可控开关的第二端、所述第二可控开关的第一端及所述第十一可控开关的控制端，所述第十可控开关的第一端连接所述第十一可控开关的第一端，并接收所述第三时钟信号，所述第十可控开关的第二端接收本级级传信号，所述第十一可控开关的第二端连接扫描信号输出端及所述第十三可控开关的第一端，所述第十三可控开关的控制端接收所述第一时钟信号，所述第十三可控开关的第二端连接所述第十二可控开关的第二端、所述第二可控开关的第二端、第五可控开关的第二端、第四可控开关的第二端，并接收所述关闭电压，所述第十二可控开关的控制端连接所述第二可控开关的控制端，所述第十二可控开关的第一端连接所述第十一可控开关的第二端、所述第十三可控开关的第一端及所述扫描信号输出端，所述电容连接在所述第十可控开关的控制端与所述第十二可控开关的第一端之间。
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CN104766586A (zh) * 2015-04-29 2015-07-08 合肥京东方光电科技有限公司 移位寄存器单元、其驱动方法、栅极驱动电路及显示装置

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