WO2018120076A1 - 薄膜晶体管、显示器设备及薄膜晶体管的制备方法 - Google Patents

薄膜晶体管、显示器设备及薄膜晶体管的制备方法 Download PDF

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Publication number
WO2018120076A1
WO2018120076A1 PCT/CN2016/113641 CN2016113641W WO2018120076A1 WO 2018120076 A1 WO2018120076 A1 WO 2018120076A1 CN 2016113641 W CN2016113641 W CN 2016113641W WO 2018120076 A1 WO2018120076 A1 WO 2018120076A1
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miscellaneous
film transistor
semiconductor layer
region
thin film
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PCT/CN2016/113641
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English (en)
French (fr)
Inventor
陈小明
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深圳市柔宇科技有限公司
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Priority to CN201680049277.0A priority Critical patent/CN108064416B/zh
Priority to PCT/CN2016/113641 priority patent/WO2018120076A1/zh
Priority to EP16925756.5A priority patent/EP3565007A1/en
Priority to US16/340,422 priority patent/US20190237587A1/en
Priority to KR1020197022079A priority patent/KR20190099511A/ko
Priority to JP2019534933A priority patent/JP2020515041A/ja
Publication of WO2018120076A1 publication Critical patent/WO2018120076A1/zh

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    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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    • H01L29/66409—Unipolar field-effect transistors
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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Definitions

  • the present invention relates to the field of display technologies, and in particular, to a thin film transistor, a display device using the same, and a method of fabricating the same.
  • TFTs Thin film transistors
  • MEMS microelectromechanical systems
  • planar X-ray sources etc.
  • the application prospect is broad.
  • the offset drain is a basic structure on the TFT, as shown in FIG. 1, in which the substrate 1 is provided with a semiconductor layer, and the impurity region 2 is disposed at a corresponding position of the semiconductor layer, and the impurity region 2 is respectively The source 3 and the drain 4 are disposed, and the insulating layer 6 is disposed between the gate 5 and the semiconductor layer 1.
  • the gate 5 and the drain 4 have a certain offset (ie, the distance between the gate 5 and the drain 4 is relatively long).
  • the distance between the gate 5 and the source 3 is far, as shown in FIG. 1, the offset distance L) between the gate 5 and the drain 4 is such that the semiconductor layer 1 between the two forms an offset region, so that the drain 4 is
  • the high voltage mainly falls on the offset region, thereby increasing the breakdown voltage of the TFT.
  • the offset region has a significant effect on the breakdown voltage of the shifted drain TFT.
  • the problem of this structure is that the resistance of the semiconductor layer 1 in the offset region is very high, and the off-state current of the offset drain TFT is several orders of magnitude smaller than that of a commonly used thin film transistor, which affects its current driving capability. . technical problem
  • An object of the present invention is to provide a thin film transistor, a display device using the same, and a method for fabricating the thin film transistor, which are intended to solve the current driving of the thin film transistor after the offset region is set in the prior art. The problem of capacity being affected.
  • the technical solution of the present invention is to provide a thin film transistor including a substrate, a semiconductor layer, an insulating layer, a source, a drain, and a gate.
  • the semiconductor layer is disposed on the substrate, and the semiconductor layer is A first miscellaneous region is formed on each of the two ends, and the source and the drain are respectively disposed on the two first miscellaneous regions, and the two first miscellaneous regions of the semiconductor layer are separated by a plurality of second exotic regions.
  • the gate is disposed between the source and the drain, and the distance between the gate and the drain is farther than the distance between the gate and the source, so that the semiconductor layer between the gate and the drain forms an offset region, and multiple
  • the second impurity region is located in the offset region;
  • the thin film transistor further includes a plurality of floating electrodes, and the insulating layer covers the region where the plurality of second miscellaneous regions are not formed in the offset region, and the plurality of floating electrodes are correspondingly disposed on the insulating layer
  • the horizontal cross-sectional width of the plurality of second miscellaneous regions is sequentially reduced in the direction from the source to the drain.
  • the number of second miscellaneous regions is one of three, four or five.
  • the dose of the catastrophic substance in the first miscellaneous region is greater than the dose of the filthy substance in the second miscellaneous region.
  • the impurity in the first miscellaneous region is the same as the impurity in the second miscellaneous region, and the impurity is phosphorus ion or boron ion.
  • the first miscellaneous region and the second miscellaneous region are both formed by catastrophic ions on the semiconductor layer.
  • the number of ions in the first miscellaneous area is 1x10 16 /cm 2
  • the number of ions in the second miscellaneous area is 5x10 15 /cm 2 .
  • a display device comprising the above-described thin film transistor.
  • a method for fabricating a thin film transistor comprising the steps of: providing a substrate, and forming a semiconductor layer on the substrate; forming an insulating layer on a side of the semiconductor layer away from the substrate, and correspondingly providing a gate on the insulating layer; a plurality of suspended electrodes are disposed between the gate and the suspended electrodes and between the adjacent two suspended electrodes; the ends of the semiconductor layer are subjected to a cumbersome treatment to form a first miscellaneous region, respectively
  • the semiconductor layer covered by the pole and the plurality of floating electrodes is subjected to a cumbersome process to form a plurality of second miscellaneous regions; the source and the drain are respectively disposed on the two first miscellaneous regions.
  • the insulating material layer and the metal layer are sequentially formed on the semiconductor layer, and the insulating material layer and the metal layer are patterned together, and the insulating material layer forms insulation.
  • the layer, the metal layer forms a gate and a plurality of floating electrodes.
  • the first impurity region and the second impurity region are formed by using ion implantation on the semiconductor layer, and the number of ions in the first miscellaneous region is 1 ⁇ 10 16 /cm 2 The number of ions in the second miscellaneous area is 5x10 15 /cm 2 .
  • a plurality of second impurity regions are disposed in the offset region of the thin film transistor, and the resistance of the second impurity region is lower than that of the semiconductor layer at the same position of the thin film transistor of the prior art.
  • the added TFT of the second impurity region has a higher output current, thereby enhancing the current driving capability of the thin film transistor.
  • FIG. 1 is a cross-sectional structural view of a thin film transistor in the prior art
  • FIG. 2 is a cross-sectional structural view showing an embodiment of a thin film transistor of the present invention
  • FIG. 3 is a flow chart showing the steps of preparing a thin film transistor of the present invention.
  • the drain; 40 an insulating layer
  • the thin film transistor of the present embodiment includes a substrate 101 and a semiconductor layer 10.
  • the material for preparing the semiconductor layer 10 is not limited to a polysilicon material, that is, the semiconductor layer 10 is formed, and an oxide semiconductor layer may be formed.
  • an IGZO material that is, an indium gallium zinc oxide, a source 20, a drain 30, a gate 50, an insulating layer 40, and a plurality of floating electrodes 60
  • the semiconductor layer 10 is disposed on the substrate 101, and the two ends of the semiconductor layer 10 are respectively A first impurity region 11 is formed, and a source electrode 20 and a drain electrode 30 are respectively disposed on the first impurity regions 11 on both end sides of the semiconductor layer 10, and the gate electrode 50 is disposed between the source electrode 20 and the drain electrode 30.
  • the semiconductor layer 10 corresponding to the gate 50 is not formed with a miscellaneous region, and the semiconductor layer 10 between the gate 50 and the drain 30 forms an offset region, and the offset region is provided with a plurality of second miscellaneous spaces.
  • the insulating layer 40 is covered on the semiconductor layer 10 in which the impurity regions are not formed, and the gate electrode 50 and the plurality of flying electrodes 60 are spaced apart from each other on the insulating layer 40.
  • the plurality of floating electrodes 60 are located between the gate 50 and the drain 30, and are spaced apart from each other.
  • the gate 50 and the plurality of floating electrodes 60 define a plurality of second miscellaneous regions 12, each of which The second miscellaneous region 12 is located between two adjacent flying electrodes 60 or gates 50 and an adjacent one of the floating electrodes 60.
  • the second impurity region 12 is added in the offset region, and the resistance of the second impurity region 12 is higher than that of the thin film transistor in the prior art.
  • the resistance of the layer is low, so that the thin film transistor in which the second impurity region 12 is added has a higher output current, so that the thin film transistor has a higher breakdown voltage and enhances the current driving capability.
  • a floating electrode 60 is disposed on the offset region to define a second impurity region 12 together with the gate 50, and the second impurity region 12 optimizes the electric field distribution of the offset region, and the floating electrode 60 and the The gate electrode 50 can be used as a mask in the formation of the second impurity region 12, thereby achieving self-alignment, which eliminates the influence of the alignment deviation problem in forming the second impurity region 12 ⁇ on the electrical characteristics of the thin film transistor.
  • the insulating layer 40 is divided into a plurality of insulating layer units (not shown), wherein an insulating layer unit is disposed between the semiconductor layer 10 and the gate 50 to electrically insulate the two
  • the remaining insulating layer units are disposed one by one on the semiconductor layer 10 between the adjacent two second miscellaneous regions 12.
  • the gate electrode 50 is disposed on the insulating layer unit adjacent to the source electrode 20, and the plurality of flying electrodes 60 are disposed correspondingly on a single unit of the remaining insulating layer, and the floating electrode 60 and the semiconductor are correspondingly corresponding to the single unit of the insulating layer.
  • the layers 10 are insulated from each other.
  • the thin film transistor in the offset region is provided, and the intensity of the electric field gradually becomes weaker in the direction from the source 20 to the drain 30.
  • the horizontal cross-sectional width of the plurality of flying electrodes 60 is along the source 20 to the drain 3
  • the direction of 0 is sequentially reduced, so that the horizontal cross-sectional widths of the plurality of second miscellaneous regions 12 are sequentially reduced in the same direction.
  • the plurality of second miscellaneous regions 12 of the structure facilitates smoothing of the electric field from the source 20 to the drain 30, further optimizing the electric field distribution of the offset region.
  • the thin film transistor of the embodiment is provided with three second impurity regions 12, and the widths of the three second impurity regions 12 are gradually reduced in the direction from the source 20 to the drain 30.
  • the number of the plurality of second miscellaneous areas 12 may be set according to actual requirements, for example, 4, 5, etc. may also be set. It should be noted that the second miscellaneous area 12 The more the number, the more favorable to the optimization of the electric field, but the number of the second miscellaneous area 12 is mostly, which increases the difficulty of the process, so the number of the second miscellaneous area 12 needs to be based on actual demand or process conditions. set up.
  • the dose of the catastrophic substance in the first miscellaneous region 11 is greater than the dose of the toxic substance in the second miscellaneous region 12, and the first miscellaneous region 11 is a heavily miscellaneous region, the first The second miscellaneous area 12 is a light and miscellaneous area.
  • the filthy substance is phosphorus ion or boron ion, and the resistance of the heavy and miscellaneous area is low.
  • phosphorus ions or boron ions may be mixed on the semiconductor layer 10 by ion implantation to form the first impurity region 11 and the second impurity region 12, respectively.
  • the miscellaneous dose of the first miscellaneous area 11 may be 1 x 10 16 / cm 2
  • the second dose of the second miscellaneous area 12 may be 5 x 10 15 / cm 2 , or may be adjusted according to actual needs, Make specific limits.
  • 5x10 is /cm 2 is the dose of ion implantation, which means 5x10 15 phosphorus ions or boron ions per square centimeter.
  • the breakdown voltage of the offset region of the present embodiment is high.
  • a plurality of second miscellaneous regions 12 are disposed in the offset region to connect the electric field of the region. Optimized to make the current drive capability of the offset region stronger.
  • a display device (not shown) is provided.
  • the display device includes the aforementioned thin film transistor, and the display device further includes a control module, and the thin film transistor is electrically connected to the control module.
  • the control module changes the electric drive capability of the output of the thin film transistor by controlling the voltage signal of the thin film transistor.
  • the display device is a liquid crystal display device (LCD) or an organic electroluminescence display device (OLED).
  • the thin film transistor outputs a display driving force to achieve driving capability of liquid crystal molecules in different regions of the liquid crystal panel in the display device, thereby realizing a high-resolution imaging function.
  • the control module adopts the prior art IC control module or other electrical control unit in the prior art that can meet the control requirements.
  • FIG. 3 a process for preparing the foregoing thin film transistor is provided. The process includes the following steps:
  • Step S10 providing a substrate 101, and forming a semiconductor layer 10 on the substrate 101;
  • Step S20 forming an insulating layer 40 on a side of the semiconductor layer 10 away from the substrate 101, and correspondingly disposed on the insulating layer 40 with a gate 50 and a plurality of flying electrodes 60, between the gate 50 and the floating electrode 60 And two adjacent floating electrodes 60 are spaced apart from each other.
  • an integral insulating material layer and a metal layer are sequentially formed on the semiconductor layer 10, and then the insulating material layer and the metal layer are sequentially patterned to form the insulating material layer.
  • the insulating layer 40 forms the gate electrode 50 and the plurality of flying electrodes 60 (or the insulating material layer and the metal layer may be patterned together).
  • the above patterning treatment can be performed by chemical etching.
  • the gate electrode 50 is formed in the same metal layer as the plurality of flying electrodes 60 (i.e., the metal layer formed on the insulating material layer), and the additional floating process is not required to form the floating electrode 60, which is advantageous for simplifying the molding process.
  • Step S30 performing cumbersome processing on both ends of the semiconductor layer 10 to form the first impurity regions 11 respectively, and performing cumbersome processing on the semiconductor layer 10 not covered by the gate electrode 50 and the plurality of floating electrodes 60.
  • a plurality of second miscellaneous regions 12 are formed. Among them, the order of forming the first miscellaneous area 11 and the second miscellaneous area 12 may be interchanged, and the first miscellaneous area 11 may be formed first, and then the second miscellaneous area 12 may be formed, and vice versa.
  • Step S40 The source 20 and the drain 30 are respectively disposed on the two first miscellaneous regions 11 respectively.
  • the gate 50 and the plurality of flying electrodes 60 together serve as a mask to be opposite to the gate 50.
  • the semiconductor layer 10 covered by the plurality of flying electrodes 60 is subjected to a cumbersome process to form a plurality of second miscellaneous regions 12 such that the preparation process of the second miscellaneous regions 12 in the offset regions is not affected by the alignment deviation.
  • the design structure of the thin film transistor By applying the design structure of the thin film transistor, self-alignment of the impurity process in the offset region of the thin film transistor can be realized, so that the thin film transistor is not affected by the alignment deviation, and compared with the related art thin film transistor,
  • the presence of the offset region makes the breakdown voltage of the thin film transistor higher, improves the electrical characteristics of the thin film transistor, and enhances the current driving capability of the offset region by providing the second impurity region 12.

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Abstract

一种薄膜晶体管、其制作方法及显示器设备。薄膜晶体管包括基底（101）、半导体层（10）、源极（20）、漏极（30）和栅极（50）、绝缘层（40）和多个悬空电极（60）。半导体层（10）形成在基底（101）上，半导体层（10）的两端分别形成有第一掺杂区域（11），源极（20）与漏极（30）分别对应设置在第一掺杂区（11）域上，栅极（50）设置在源极（20）与漏极（30）之间。栅极（50）与漏极（30）之间的半导体层（10）形成偏移区域，偏移区域上间隔地形成有多个第二掺杂区域（12）。绝缘层（40）遮盖在偏移区域未形成有第二掺杂区域（12）的区域，多个悬空电极（60）对应设置于绝缘层（40）。第二掺杂区域的设置，有利于改善薄膜晶体管的电流驱动能力。

Description

薄膜晶体管、 显示器设备及薄膜晶体管的制备方法 技术领域
[0001] 本发明涉及显示器技术领域， 具体地， 涉及一种薄膜晶体管、 使用该薄膜晶体 管的显示器设备以及该薄膜晶体管的制备方法。
背景技术
[0002] 薄膜晶体管 （TFT) 可应用于显示器设备、 打印机、 扫描设备、 微机电系统 （ MEMS) 、 平面型 X射线源等等， 尤其在显示器设备、 微机电系统、 平面型 X射 线源中的应用前景广阔。 偏移漏极是 TFT上的基本结构， 如图 1所示， 在该结构 中， 基底 1设置了半导体层 ， 并在半导体层 的相应位置上设置的惨杂区域 2， 惨杂区域 2上分别设置源极 3和漏极 4， 栅极 5与半导体层 1之间设置了绝缘层 6 ， 栅极 5和漏极 4之间有一定偏移量 （即栅极 5与漏极 4的距离较栅极 5与源极 3的 距离远， 如图 1， 栅极 5和漏极 4之间具有偏移距离 L) 而使得两者之间的半导体 层 1形成偏移区域， 使得漏极 4上的高电压主要落在偏移区域上， 从而提高 TFT的 击穿电压。 偏移区域对偏移的漏极的 TFT的击穿电压有显著影响。 该结构所存在 的问题在于： 偏移区域的半导体层 1的电阻很高， 与一般常用的薄膜晶体管相比 较， 偏移的漏极的 TFT的幵态电流小若干数量级， 会影响其电流驱动能力。 技术问题
[0003] 本发明的目的在于提供一种薄膜晶体管、 使用该薄膜晶体管的显示器设备以及 该薄膜晶体管的制备方法， 旨在解决现有技术中薄膜晶体管在设置偏移区域之 后， 薄膜晶体管的电流驱动能力受到影响的问题。
问题的解决方案
技术解决方案
[0004] 为解决上述技术问题， 本发明的技术方案是： 提供 一种薄膜晶体管， 包括基 底、 半导体层、 绝缘层、 源极、 漏极和栅极， 半导体层设置在基底上， 半导体 层的两端分别形成有一第一惨杂区域， 源极与漏极分别对应设置在两个第一惨 杂区域上， 半导体层的两个第一惨杂区域之间具有间隔设置的多个第二惨杂区 域； 栅极设置在源极与漏极之间， 且栅极与漏极的距离较栅极与源极的距离远 ， 从而栅极与漏极之间的半导体层形成偏移区域， 多个第二惨杂区域位于偏移 区域； 所薄膜晶体管还包括多个悬空电极， 绝缘层遮盖在偏移区域未形成有多 个第二惨杂区域的区域， 多个悬空电极对应设置于该绝缘层上， 栅极与相邻的 一悬空电极之间具有一个第二惨杂区域， 剩余的悬空电极中的每相邻两个之间 具有一个第二惨杂区域。
[0005] 优选地， 沿源极向漏极的方向， 多个第二惨杂区域的水平横截宽度依次缩小。
[0006] 优选地， 第二惨杂区域的数量为三个、 四个或五个中之一。
[0007] 优选地， 第一惨杂区域中所惨杂物质的剂量大于第二惨杂区域中所惨杂物质的 剂量。
[0008] 优选地， 第一惨杂区域中所惨杂物质与第二惨杂区域中所惨杂物质相同， 所惨 杂物质为磷离子或硼离子。
[0009] 优选地， 第一惨杂区域和第二惨杂区域均为通过在半导体层上惨杂离子而形成
， 第一惨杂区域惨杂的离子个数为是 1x10 16个 /cm 2， 第二惨杂区域惨杂的离子个 数为是 5x10 15个 /cm 2。
[0010] 一种显示器设备， 包括上述的薄膜晶体管。
[0011] 一种薄膜晶体管的制备方法， 包括以下步骤： 提供基底， 并在基底上形成半导 体层； 在半导体层远离基底的一侧形成绝缘层， 并在绝缘层上对应地设置一个 栅极及多个悬空电极， 栅极与悬空电极之间以及相邻两个悬空电极之间均间隔 设置； 对半导体层的两端进行惨杂处理以分别形成一第一惨杂区域， 并对未被 栅极和多个悬空电极遮盖的半导体层进行惨杂处理以形成多个第二惨杂区域； 在两个第一惨杂区域上分别相应地设置源极和漏极。
[0012] 优选地， 在形成绝缘层、 栅极和多个悬空电极过程中， 在半导体层上依次形成 绝缘材料层及金属层， 同吋图案化绝缘材料层及金属层， 绝缘材料层形成绝缘 层， 金属层形成栅极和多个悬空电极。
[0013] 优选地， 第一惨杂区域和第二惨杂区域均为通过在半导体层上采用离子注入的 方式而形成， 第一惨杂区域惨杂的离子个数为 1x10 16个 /cm 2， 第二惨杂区域惨杂 的离子个数为 5x10 15个 /cm 2。 发明的有益效果
有益效果
[0014] 本发明中， 在薄膜晶体管的偏移区域设置有多个第二惨杂区域， 第二惨杂区域 的电阻较现有技术的薄膜晶体管的形同位置的半导体层的电阻低， 因而相对于 现有技术的偏移的漏极的 TFT而言， 增设的第二惨杂区域的 TFT具有较高的输出 电流， 从而增强了薄膜晶体管的电流驱动能力。
对附图的简要说明
附图说明
[0015] 图 1是现有技术中薄膜晶体管的剖视结构示意图；
[0016] 图 2是本发明的薄膜晶体管的实施例的剖视结构示意图；
[0017] 图 3是本发明的制备薄膜晶体管的步骤流程图。
[0018] 在附图中：
[0019] 10、 半导体层； 11、 第一惨杂区域；
[0020] 12、 第二惨杂区域； 20、 源极；
[0021] 30、 漏极； 40、 绝缘层；
[0022] 50、 栅极； 60、 悬空电极；
[0023] 101、 基底。
本发明的实施方式
[0024] 为了使本发明的目的、 技术方案及优点更加清楚明白， 以下结合附图及实施例 ， 对本发明进行进一步详细说明。 应当理解， 此处所描述的具体实施例仅仅用 以解释本发明， 并不用于限定本发明。
[0025] 需要说明的是， 当元件被称为 "固定于"或"设置于"另一个元件， 它可以直接在 另一个元件上或者间接在该另一个元件上。 当一个元件被称为"连接于 "另一个元 件， 它可以是直接连接到另一个元件或者间接连接至该另一个元件上。
[0026] 还需要说明的是， 本实施例中的左、 右、 上、 下等方位用语， 仅是互为相对概 念或是以产品的正常使用状态为参考的， 而不应该认为是具有限制性的。 [0027] 如图 2所示， 本实施例的薄膜晶体管包括基底 101、 半导体层 10 (半导体层 10的 制备材料并不仅限于多晶硅材料， 即形成该半导体层 10， 也可以是氧化物半导 体层， 如 IGZO材料， 即铟镓锌氧化物） 、 源极 20、 漏极 30、 栅极 50、 绝缘层 40 以及多个悬空电极 60， 半导体层 10设置在基底 101上， 半导体层 10的两端分别形 成有第一惨杂区域 11， 源极 20与漏极 30分别设置在半导体层 10的两端侧的第一 惨杂区域 11上， 栅极 50设置在源极 20与漏极 30之间， 该栅极 50对应的半导体层 1 0未形成有惨杂区域， 栅极 50与漏极 30之间的半导体层 10形成偏移区域， 该偏移 区域上间隔地设有多个第二惨杂区域 12， 绝缘层 40覆盖在未形成有惨杂区域的 半导体层 10上， 栅极 50及多个悬空电极 60分别间隔地设置在绝缘层 40上。 该多 个悬空电极 60位于该栅极 50与该漏极 30之间， 并间隔设置， 由该栅极 50及一该 多个悬空电极 60介定出多个第二惨杂区域 12， 每一第二惨杂区域 12位于相邻的 两个悬空电极 60或栅极 50与相邻的一个悬空电极 60之间。
[0028] 本实施方式的薄膜晶体管结构， 因在偏移区域增设了第二惨杂区域 12， 该第二 惨杂区域 12的电阻较现有技术中的薄膜晶体管的未进行惨杂物质的半导体层的 电阻低， 因而增设了第二惨杂区域 12的薄膜晶体管具有较高的输出电流， 使得 薄膜晶体管具有更高的击穿电压的同吋， 增强了电流驱动能力。 此外， 在偏移 区域上设置悬空电极 60从而与该栅极 50共同介定出第二惨杂区域 12， 第二惨杂 区域 12优化了偏移区域的电场分布， 并且该悬空电极 60与该栅极 50在形成第二 惨杂区域 12吋可以共同作为掩膜， 而实现自对准， 消除了因在形成第二惨杂区 域 12吋的对准偏差问题而影响薄膜晶体管的电气特性。
[0029] 在本实施例中， 绝缘层 40被分割成多个绝缘层单元 （未图示） ， 其中一绝缘层 单元设置于半导体层 10和栅极 50之间， 以使二者相互电绝缘， 其余的绝缘层单 元一一对应地设置在相邻两个第二惨杂区域 12之间的半导体层 10上。 栅极 50设 置在靠近源极 20的绝缘层单元上， 多个悬空电极 60—一对应地设置在其余的绝 缘层的单个单元上， 通过绝缘层的单个单元相对应的使悬空电极 60与半导体层 1 0之间相互绝缘。
[0030] 容易理解， 设置偏移区域的薄膜晶体管， 沿源极 20向漏极 30的方向， 电场的强 度逐渐变弱。 本实施方式中， 多个悬空电极 60的水平横截宽度沿源极 20向漏极 3 0的方向， 依次缩小， 使得该多个第二惨杂区域 12的水平横截宽度沿同一方向， 依次缩小。 此结构的多个第二惨杂区域 12有利于使从源极 20向漏极 30方向的电 场平缓化， 进一步优化了偏移区域的电场分布。 在偏移区域中， 本实施例的薄 膜晶体管增设了 3个第二惨杂区域 12， 在沿源极 20至漏极 30的方向上， 该 3个第 二惨杂区域 12的宽度逐渐变小。 在其余可行的实施方式中， 该多个第二惨杂区 域 12设置的个数可以根据实际需求设定， 例如还可以设置 4、 5个等， 需要说明 的是， 该第二惨杂区域 12的个数越多， 越有利于电场的优化， 但是该第二惨杂 区域 12的个数大多， 造成工艺难度增加， 因而该第二惨杂区域 12的个数需根据 实际需求或工艺条件进行设定。
[0031] 本发明中， 第一惨杂区域 11中所惨杂物质的剂量大于第二惨杂区域 12中所惨杂 物质的剂量， 该第一惨杂区域 11为重惨杂区域， 该第二惨杂区域 12为轻惨杂区 域， 惨杂的物质为磷离子或硼离子， 重惨杂区域的电阻较轻惨杂区域的电阻低 。 具体， 可通过离子注入的方式， 在半导体层 10上惨杂磷离子或硼离子从而分 别形成第一惨杂区域 11及第二惨杂区域 12。 第一惨杂区域 11的惨杂剂量可以是 1 xlO 16个 /cm 2， 第二惨杂区域 12的惨杂剂量可以是 5x10 15个 /cm 2， 也可以根据实 际需求进行调整， 在此不做具体限定。 其中， 5x10 is个 /cm 2是离子注入的剂量， 意思是每平方厘米 5x10 15个磷离子或硼离子。
[0032] 如图 2所示， 本实施例的偏离区域的击穿电压高， 为了优化偏离区域的电场分 布， 通过在偏离区域中设置多个第二惨杂区域 12对该区域的电场进行衔接优化 ， 使得该偏移区域的电流驱动能力更强。
[0033] 根据本发明的另一方面， 提供了一种显示器设备 （未图示） 。 该显示器设备包 括前述的薄膜晶体管， 并且该显示器设备还包括控制模块， 薄膜晶体管与控制 模块电连接。 控制模块通过控制该薄膜晶体管的电压信号， 从而改变薄膜晶体 管输出的电力驱动能力。 其中， 该显示器设备为液晶显示设备 （LCD) 或有机 电致发光显示设备 （OLED) 。 在液晶显示设备中， 该薄膜晶体管输出显示驱动 力， 以达到对显示器设备中的液晶面板中不同区域的液晶分子的驱动能力， 实 现高分辨率的显像功能。 其中， 控制模块采用现有技术的 IC控制模块或者现有 技术中其他的能够满足控制需求的电气控制单元。 [0034] 根据本发明的又一方面， 如图 3所示， 提供了一种制备前述的薄膜晶体管的工 艺方法。 该工艺方法包括以下步骤：
[0035] 步骤 S10: 提供一基底 101， 并在该基底 101上形成半导体层 10;
[0036] 步骤 S20: 在半导体层 10远离基底 101的一侧形成绝缘层 40， 并在绝缘层 40上对 应地设置一个栅极 50及多个悬空电极 60， 栅极 50与悬空电极 60之间以及相邻两 个悬空电极 60之间均间隔设置。 在实施步骤 S20的过程中， 首先在半导体层 10上 依次形成一层整体的绝缘材料层及金属层， 再对该绝缘材料层及该金属层先后 进行图案化处理， 使该绝缘材料层形成该绝缘层 40， 该金属层形成该栅极 50及 该多个悬空电极 60 (或者， 也可以是绝缘材料层和金属层同吋进行图案化处理 ) 。 可通过化学刻蚀的方式进行上述图案化处理。 该栅极 50与该多个悬空电极 6 0属于同一金属层 （即在绝缘材料层上形成的金属层） 中同吋形成， 无需额外增 加工艺来形成该悬空电极 60， 有利于简化成型工艺。
[0037] 步骤 S30: 对半导体层 10的两端进行惨杂处理以分别形成第一惨杂区域 11， 以 及对未被栅极 50和多个悬空电极 60遮盖的半导体层 10进行惨杂处理以形成多个 第二惨杂区域 12。 其中， 形成第一惨杂区域 11及第二惨杂区域 12的顺序可互换 ， 既可先形成第一惨杂区域 11， 再形成第二惨杂区域 12， 反之亦然。
[0038] 步骤 S40: 在该二第一惨杂区域 11上分别相应地设置源极 20和漏极 30。
[0039] 在对该薄膜晶体管进行加工的过程中， 在进行第二惨杂区域 12制备过程中， 该 栅极 50与该多个悬空电极 60共同作为掩膜， 以对未被该栅极 50、 该多个悬空电 极 60遮盖的半导体层 10进行惨杂处理来形成多个第二惨杂区域 12， 使得偏移区 域中的第二惨杂区域 12的制备过程不受对准偏差的影响。 通过应用该薄膜晶体 管的设计结构， 能够实现薄膜晶体管的偏移区域中进行惨杂工艺的自对准， 使 得薄膜晶体管不受对准偏差的影响， 并且与现有技术的薄膜晶体管相比较， 由 于存在偏移区域使得薄膜晶体管的击穿电压较高， 改善了薄膜晶体管的电学特 性， 并且通过设置第二惨杂区域 12从而增强了偏移区域的电流驱动能力。
[0040] 以上仅为本发明的较佳实施例而已， 并不用以限制本发明， 凡在本发明的精神 和原则之内所作的任何修改、 等同替换和改进等， 均应包含在本发明的保护范 围之内。

Claims

权利要求书
[权利要求 1] 一种薄膜晶体管， 包括基底 （101) 、 半导体层 （10) 、 绝缘层 （40
) 、 源极 （20) 、 漏极 （30) 和栅极 （50) ， 所述半导体层 （10) 设 置在所述基底 （101) 上， 其特征在于，
所述半导体层 （10) 的两端分别形成有一第一惨杂区域 （11) ， 所述 源极 （20) 与所述漏极 （30) 分别对应设置在两个所述第一惨杂区域 (11) 上， 所述半导体层 （10) 的两个所述第一惨杂区域 （11) 之间 具有间隔设置的多个第二惨杂区域 （12) ；
所述栅极 （50) 设置在所述源极 （20) 与所述漏极 （30) 之间， 且所 述栅极 （50) 与所述漏极 （30) 的距离较所述栅极 （50) 与所述源极 (20) 的距离远， 从而所述栅极 （50) 与所述漏极 （30) 之间的半导 体层 （10) 形成偏移区域， 所述多个第二惨杂区域 （12) 位于所述偏 移区域；
所薄膜晶体管还包括多个悬空电极 （60) ， 所述绝缘层 （40) 遮盖在 所述偏移区域未形成有所述多个第二惨杂区域 （12) 的区域， 所述多 个悬空电极 （60) 对应设置于该绝缘层 （40) 上， 所述栅极 （50) 与 相邻的一所述悬空电极 （60) 之间具有一个所述第二惨杂区域 （12) ， 剩余的所述悬空电极 （60) 中的每相邻两个之间具有一个所述第二 惨杂区域 (12) 。
[权利要求 2] 如权利要求 1所述的薄膜晶体管， 其特征在于， 沿所述源极 （20) 向 所述漏极 （30) 的方向， 多个所述第二惨杂区域 （12) 的水平横截宽 度依次缩小。
[权利要求 3] 如权利要求 1所述的薄膜晶体管， 其特征在于， 所述第二惨杂区域 （1
2) 的数量为三个、 四个或五个中之一。
[权利要求 4] 如权利要求 1至 3中任一项所述的薄膜晶体管， 其特征在于， 所述第一 惨杂区域 （11) 中所惨杂物质的剂量大于所述第二惨杂区域 （12) 中 所惨杂物质的剂量。
[权利要求 5] 如权利要求 4所述的薄膜晶体管， 其特征在于， 所述第一惨杂区域 （1 1) 中所惨杂物质与所述第二惨杂区域 （12) 中所惨杂物质相同， 所 惨杂物质为磷离子或硼离子。
如权利要求 5所述的薄膜晶体管， 其特征在于， 所述第一惨杂区域 （1 1) 和第二惨杂区域 （12) 均为通过在所述半导体层 （10) 上惨杂离 子而形成， 所述第一惨杂区域 （11) 惨杂的离子个数为是 1x10 16 个 /cm 2， 第二惨杂区域 （12) 惨杂的离子个数为是 5x10 15个 /cm 2。 一种显示器设备， 其特征在于， 该显示器设备包括权利要求 1至 6中任 一项所述的薄膜晶体管。
一种薄膜晶体管的制备方法， 其特征在于， 包括以下步骤： 提供基底 （101) ， 并在基底 （101) 上形成半导体层 （10) ； 在所述半导体层 （10) 远离所述基底 （101) 的一侧形成绝缘层 （40
) ， 并在所述绝缘层 （40) 上对应地设置一个栅极 （50) 及多个悬空 电极 （60) ， 所述栅极 （50) 与所述悬空电极 （60) 之间以及相邻两 个所述悬空电极 （60) 之间均间隔设置；
对所述半导体层 （10) 的两端进行惨杂处理以分别形成一第一惨杂区 域 （11) ， 并对未被所述栅极 （50) 和所述多个悬空电极 （60) 遮盖 的半导体层 （10) 进行惨杂处理以形成多个第二惨杂区域 （12) ； 在两个所述第一惨杂区域 （11) 上分别相应地设置源极 （20) 和漏极 (30) 。
如权利要求 8所述的薄膜晶体管的制备方法， 其特征在于， 在形成所 述绝缘层 （40) 、 所述栅极 （50) 和所述多个悬空电极 （60) 过程中 ， 在所述半导体层 （10) 上依次形成绝缘材料层及金属层， 同吋图案 化所述绝缘材料层及所述金属层， 所述绝缘材料层形成绝缘层 （40) ， 所述金属层形成栅极 （50) 和多个悬空电极 （60) 。
如权利要求 8所述的薄膜晶体管的制备方法， 其特征在于， 所述第一 惨杂区域 （11) 和所述第二惨杂区域 （12) 均为通过在所述半导体层 ( 10) 上采用注入离子的方式而形成， 所述第一惨杂区域 （11) 惨杂 的离子个数为 1x10 16个 /cm 2， 所述第二惨杂区域 （12) 惨杂的离子个 数为 5x10 15个 /cm 2。
PCT/CN2016/113641 2016-12-30 2016-12-30 薄膜晶体管、显示器设备及薄膜晶体管的制备方法 WO2018120076A1 (zh)

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