CN108064416A - 薄膜晶体管、显示器设备及薄膜晶体管的制备方法 - Google Patents

薄膜晶体管、显示器设备及薄膜晶体管的制备方法 Download PDF

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CN108064416A
CN108064416A CN201680049277.0A CN201680049277A CN108064416A CN 108064416 A CN108064416 A CN 108064416A CN 201680049277 A CN201680049277 A CN 201680049277A CN 108064416 A CN108064416 A CN 108064416A
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doped region
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陈小明
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Shenzhen Royole Technologies Co Ltd
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Abstract

提供一种薄膜晶体管、其制作方法及显示器设备。薄膜晶体管包括基底(101)、半导体层(10)、源极(20)、漏极(30)和栅极(50)、绝缘层(40)和多个悬空电极(60)。半导体层(10)形成在基底(101)上，半导体层(10)的两端分别形成有第一掺杂区域(11)，源极(20)与漏极(30)分别对应设置在第一掺杂区(11)域上，栅极(50)设置在源极(20)与漏极(30)之间。栅极(50)与漏极(30)之间的半导体层(10)形成偏移区域，偏移区域上间隔地形成有多个第二掺杂区域(12)。绝缘层(40)遮盖在偏移区域未形成有第二掺杂区域(12)的区域，多个悬空电极(60)对应设置于绝缘层(40)。第二掺杂区域的设置，有利于改善薄膜晶体管的电流驱动能力。

Description

薄膜晶体管、显示器设备及薄膜晶体管的制备方法
技术领域
本发明涉及显示器技术领域，具体地，涉及一种薄膜晶体管、使用该薄膜晶体管的显示器设备以及该薄膜晶体管的制备方法。
背景技术
薄膜晶体管(TFT)可应用于显示器设备、打印机、扫描设备、微机电系统(MEMS)、平面型X射线源等等，尤其在显示器设备、微机电系统、平面型X射线源中的应用前景广阔。偏移漏极是TFT上的基本结构，如图1所示，在该结构中，基底1设置了半导体层1＇，并在半导体层1＇的相应位置上设置的掺杂区域2，掺杂区域2上分别设置源极3和漏极4，栅极5与半导体层1之间设置了绝缘层6，栅极5和漏极4之间有一定偏移量(即栅极5与漏极4的距离较栅极5与源极3的距离远，如图1，栅极5和漏极4之间具有偏移距离L)而使得两者之间的半导体层1形成偏移区域，使得漏极4上的高电压主要落在偏移区域上，从而提高TFT的击穿电压。偏移区域对偏移的漏极的TFT的击穿电压有显著影响。该结构所存在的问题在于：偏移区域的半导体层1的电阻很高，与一般常用的薄膜晶体管相比较，偏移的漏极的TFT的开态电流小若干数量级，会影响其电流驱动能力。
发明内容
本发明的目的在于提供一种薄膜晶体管、使用该薄膜晶体管的显示器设备以及该薄膜晶体管的制备方法，旨在解决现有技术中薄膜晶体管在设置偏移区域之后，薄膜晶体管的电流驱动能力受到影响的问题。
为解决上述技术问题，本发明的技术方案是：提供一种薄膜晶体管，包括基底、半导体层、绝缘层、源极、漏极和栅极，半导体层设置在基底上，半导体层的两端分别形成有一第一掺杂区域，源极与漏极分别对应设置在两个第一掺杂区域上，半导体层的两个第一掺杂区域之间具有间隔设置的多个第二掺杂区域；栅极设置在源极与漏极之间，且栅极与漏极的距离较栅极与源极的距离远，从而栅极与漏极之间的半导体层形成偏移区域，多个第二掺杂区域位于偏移区域；所薄膜晶体管还包括多个悬空电极，绝缘层遮盖在偏移区域未形成有多个第二掺杂区域的区域，多个悬空电极对应设置于该绝缘层上，栅极与相邻的一悬空电极之间具有一个第二掺杂区域，剩余的悬空电极中的每相邻两个之间具有一个第二掺杂区域。
优选地，沿源极向漏极的方向，多个第二掺杂区域的水平横截宽度依次缩小。
优选地，第二掺杂区域的数量为三个、四个或五个中之一。
优选地，第一掺杂区域中所掺杂物质的剂量大于第二掺杂区域中所掺杂物质的剂量。
优选地，第一掺杂区域中所掺杂物质与第二掺杂区域中所掺杂物质相同，所掺杂物质为磷离子或硼离子。
优选地，第一掺杂区域和第二掺杂区域均为通过在半导体层上掺杂离子而形成，第一掺杂区域掺杂的离子个数为是1×1016个/cm2，第二掺杂区域掺杂的离子个数为是5×1015个/cm2。
一种显示器设备，包括上述的薄膜晶体管。
一种薄膜晶体管的制备方法，包括以下步骤：提供基底，并在基底上形成半导体层；在半导体层远离基底的一侧形成绝缘层，并在绝缘层上对应地设置一个栅极及多个悬空电极，栅极与悬空电极之间以及相邻两个悬空电极之间均间隔设置；对半导体层的两端进行掺杂处理以分别形成一第一掺杂区域，并对未被栅极和多个悬空电极遮盖的半导体层进行掺杂处理以形成多个第二掺杂区域；在两个第一掺杂区域上分别相应地设置源极和漏极。
优选地，在形成绝缘层、栅极和多个悬空电极过程中，在半导体层上依次形成绝缘材料层及金属层，同时图案化绝缘材料层及金属层，绝缘材料层形成绝缘层，金属层形成栅极和多个悬空电极。
优选地，第一掺杂区域和第二掺杂区域均为通过在半导体层上采用离子注入的方式而形成，第一掺杂区域掺杂的离子个数为1×1016个/cm2，第二掺杂区域掺杂的离子个数为5×1015个/cm2。
本发明中，在薄膜晶体管的偏移区域设置有多个第二掺杂区域，第二掺杂区域的电阻较现有技术的薄膜晶体管的形同位置的半导体层的电阻低，因而相对于现有技术的偏移的漏极的TFT而言，增设的第二掺杂区域的TFT具有较高的输出电流，从而增强了薄膜晶体管的电流驱动能力。
附图说明
图1是现有技术中薄膜晶体管的剖视结构示意图；
图2是本发明的薄膜晶体管的实施例的剖视结构示意图；
图3是本发明的制备薄膜晶体管的步骤流程图。
在附图中：
10、半导体层； 11、第一掺杂区域；
12、第二掺杂区域； 20、源极；
30、漏极； 40、绝缘层；
50、栅极； 60、悬空电极；
101、基底。
具体实施方式
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
需要说明的是，当元件被称为“固定于”或“设置于”另一个元件，它可以直接在另一个元件上或者间接在该另一个元件上。当一个元件被称为“连接于”另一个元件，它可以是直接连接到另一个元件或者间接连接至该另一个元件上。
还需要说明的是，本实施例中的左、右、上、下等方位用语，仅是互为相对概念或是以产品的正常使用状态为参考的，而不应该认为是具有限制性的。
如图2所示，本实施例的薄膜晶体管包括基底101、半导体层10(半导体层10的制备材料并不仅限于多晶硅材料，即形成该半导体层10，也可以是氧化物半导体层，如IGZO材料，即铟镓锌氧化物)、源极20、漏极30、栅极50、绝缘层40以及多个悬空电极60，半导体层10设置在基底101上，半导体层10的两端分别形成有第一掺杂区域11，源极20与漏极30分别设置在半导体层10的两端侧的第一掺杂区域11上，栅极50设置在源极20与漏极30之间，该栅极50对应的半导体层10未形成有掺杂区域，栅极50与漏极30之间的半导体层10形成偏移区域，该偏移区域上间隔地设有多个第二掺杂区域12，绝缘层40覆盖在未形成有掺杂区域的半导体层10上，栅极50及多个悬空电极60分别间隔地设置在绝缘层40上。该多个悬空电极60位于该栅极50与该漏极30之间，并间隔设置，由该栅极50及一该多个悬空电极60介定出多个第二掺杂区域12，每一第二掺杂区域12位于相邻的两个悬空电极60或栅极50与相邻的一个悬空电极60之间。
本实施方式的薄膜晶体管结构，因在偏移区域增设了第二掺杂区域12，该第二掺杂区域12的电阻较现有技术中的薄膜晶体管的未进行掺杂物质的半导体层的电阻低，因而增设了第二掺杂区域12的薄膜晶体管具有较高的输出电流，使得薄膜晶体管具有更高的击穿电压的同时，增强了电流驱动能力。此外，在偏移区域上设置悬空电极60从而与该栅极50共同介定出第二掺杂区域12，第二掺杂区域12优化了偏移区域的电场分布，并且该悬空电极60与该栅极50在形成第二掺杂区域12时可以共同作为掩膜，而实现自对准，消除了因在形成第二掺杂区域12时的对准偏差问题而影响薄膜晶体管的电气特性。
在本实施例中，绝缘层40被分割成多个绝缘层单元(未图示)，其中一绝缘层单元设置于半导体层10和栅极50之间，以使二者相互电绝缘，其余的绝缘层单元一一对应地设置在相邻两个第二掺杂区域12之间的半导体层10上。栅极50设置在靠近源极20的绝缘层单元上，多个悬空电极60一一对应地设置在其余的绝缘层的单个单元上，通过绝缘层的单个单元相对应的使悬空电极60与半导体层10之间相互绝缘。
容易理解，设置偏移区域的薄膜晶体管，沿源极20向漏极30的方向，电场的强度逐渐变弱。本实施方式中，多个悬空电极60的水平横截宽度沿源极20向漏极30的方向，依次缩小，使得该多个第二掺杂区域12的水平横截宽度沿同一方向，依次缩小。此结构的多个第二掺杂区域12有利于使从源极20向漏极30方向的电场平缓化，进一步优化了偏移区域的电场分布。在偏移区域中，本实施例的薄膜晶体管增设了3个第二掺杂区域12，在沿源极20至漏极30的方向上，该3个第二掺杂区域12的宽度逐渐变小。在其余可行的实施方式中，该多个第二掺杂区域12设置的个数可以根据实际需求设定，例如还可以设置4、5个等，需要说明的是，该第二掺杂区域12的个数越多，越有利于电场的优化，但是该第二掺杂区域12的个数大多，造成工艺难度增加，因而该第二掺杂区域12的个数需根据实际需求或工艺条件进行设定。
本发明中，第一掺杂区域11中所掺杂物质的剂量大于第二掺杂区域12中所掺杂物质的剂量，该第一掺杂区域11为重掺杂区域，该第二掺杂区域12为轻掺杂区域，掺杂的物质为磷离子或硼离子，重掺杂区域的电阻较轻掺杂区域的电阻低。具体，可通过离子注入的方式，在半导体层10上掺杂磷离子或硼离子从而分别形成第一掺杂区域11及第二掺杂区域12。第一掺杂区域11的掺杂剂量可以是1×1016个/cm2，第二掺杂区域12的掺杂剂量可以是5×1015个/cm2，也可以根据实际需求进行调整，在此不做具体限定。其中，5×1015个/cm2是离子注入的剂量，意思是每平方厘米5×1015个磷离子或硼离子。
如图2所示，本实施例的偏离区域的击穿电压高，为了优化偏离区域的电场分布，通过在偏离区域中设置多个第二掺杂区域12对该区域的电场进行衔接优化，使得该偏移区域的电流驱动能力更强。
根据本发明的另一方面，提供了一种显示器设备(未图示)。该显示器设备包括前述的薄膜晶体管，并且该显示器设备还包括控制模块，薄膜晶体管与控制模块电连接。控制模块通过控制该薄膜晶体管的电压信号，从而改变薄膜晶体管输出的电力驱动能力。其中，该显示器设备为液晶显示设备(LCD)或有机电致发光显示设备(OLED)。在液晶显示设备中，该薄膜晶体管输出显示驱动力，以达到对显示器设备中的液晶面板中不同区域的液晶分子的驱动能力，实现高分辨率的显像功能。其中，控制模块采用现有技术的IC控制模块或者现有技术中其他的能够满足控制需求的电气控制单元。
根据本发明的又一方面，如图3所示，提供了一种制备前述的薄膜晶体管的工艺方法。该工艺方法包括以下步骤：
步骤S10：提供一基底101，并在该基底101上形成半导体层10；
步骤S20：在半导体层10远离基底101的一侧形成绝缘层40，并在绝缘层40上对应地设置一个栅极50及多个悬空电极60，栅极50与悬空电极60之间以及相邻两个悬空电极60之间均间隔设置。在实施步骤S20的过程中，首先在半导体层10上依次形成一层整体的绝缘材料层及金属层，再对该绝缘材料层及该金属层先后进行图案化处理，使该绝缘材料层形成该绝缘层40，该金属层形成该栅极50及该多个悬空电极60(或者，也可以是绝缘材料层和金属层同时进行图案化处理)。可通过化学刻蚀的方式进行上述图案化处理。该栅极50与该多个悬空电极60属于同一金属层(即在绝缘材料层上形成的金属层)中同时形成，无需额外增加工艺来形成该悬空电极60，有利于简化成型工艺。
步骤S30：对半导体层10的两端进行掺杂处理以分别形成第一掺杂区域11，以及对未被栅极50和多个悬空电极60遮盖的半导体层10进行掺杂处理以形成多个第二掺杂区域12。其中，形成第一掺杂区域11及第二掺杂区域12的顺序可互换，既可先形成第一掺杂区域11，再形成第二掺杂区域12，反之亦然。
步骤S40：在该二第一掺杂区域11上分别相应地设置源极20和漏极30。
在对该薄膜晶体管进行加工的过程中，在进行第二掺杂区域12制备过程中，该栅极50与该多个悬空电极60共同作为掩膜，以对未被该栅极50、该多个悬空电极60遮盖的半导体层10进行掺杂处理来形成多个第二掺杂区域12，使得偏移区域中的第二掺杂区域12的制备过程不受对准偏差的影响。通过应用该薄膜晶体管的设计结构，能够实现薄膜晶体管的偏移区域中进行掺杂工艺的自对准，使得薄膜晶体管不受对准偏差的影响，并且与现有技术的薄膜晶体管相比较，由于存在偏移区域使得薄膜晶体管的击穿电压较高，改善了薄膜晶体管的电学特性，并且通过设置第二掺杂区域12从而增强了偏移区域的电流驱动能力。
以上仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。

Claims (10)

1.一种薄膜晶体管，包括基底(101)、半导体层(10)、绝缘层(40)、源极(20)、漏极(30)和栅极(50)，所述半导体层(10)设置在所述基底(101)上，其特征在于，
所述半导体层(10)的两端分别形成有一第一掺杂区域(11)，所述源极(20)与所述漏极(30)分别对应设置在两个所述第一掺杂区域(11)上，所述半导体层(10)的两个所述第一掺杂区域(11)之间具有间隔设置的多个第二掺杂区域(12)；
所述栅极(50)设置在所述源极(20)与所述漏极(30)之间，且所述栅极(50)与所述漏极(30)的距离较所述栅极(50)与所述源极(20)的距离远，从而所述栅极(50)与所述漏极(30)之间的半导体层(10)形成偏移区域，所述多个第二掺杂区域(12)位于所述偏移区域；
所薄膜晶体管还包括多个悬空电极(60)，所述绝缘层(40)遮盖在所述偏移区域未形成有所述多个第二掺杂区域(12)的区域，所述多个悬空电极(60)对应设置于该绝缘层(40)上，所述栅极(50)与相邻的一所述悬空电极(60)之间具有一个所述第二掺杂区域(12)，剩余的所述悬空电极(60)中的每相邻两个之间具有一个所述第二掺杂区域(12)。
2.如权利要求1所述的薄膜晶体管，其特征在于，沿所述源极(20)向所述漏极(30)的方向，多个所述第二掺杂区域(12)的水平横截宽度依次缩小。
3.如权利要求1所述的薄膜晶体管，其特征在于，所述第二掺杂区域(12)的数量为三个、四个或五个中之一。
4.如权利要求1至3中任一项所述的薄膜晶体管，其特征在于，所述第一掺杂区域(11)中所掺杂物质的剂量大于所述第二掺杂区域(12)中所掺杂物质的剂量。
5.如权利要求4所述的薄膜晶体管，其特征在于，所述第一掺杂区域(11)中所掺杂物质与所述第二掺杂区域(12)中所掺杂物质相同，所掺杂物质为磷离子或硼离子。
6.如权利要求5所述的薄膜晶体管，其特征在于，所述第一掺杂区域(11)和第二掺杂区域(12)均为通过在所述半导体层(10)上掺杂离子而形成，所述第一掺杂区域(11)掺杂的离子个数为是1×1016个/cm2，第二掺杂区域(12)掺杂的离子个数为是5×1015个/cm2。
7.一种显示器设备，其特征在于，该显示器设备包括权利要求1至6中任一项所述的薄膜晶体管。
8.一种薄膜晶体管的制备方法，其特征在于，包括以下步骤：
提供基底(101)，并在基底(101)上形成半导体层(10)；
在所述半导体层(10)远离所述基底(101)的一侧形成绝缘层(40)，并在所述绝缘层(40)上对应地设置一个栅极(50)及多个悬空电极(60)，所述栅极(50)与所述悬空电极(60)之间以及相邻两个所述悬空电极(60)之间均间隔设置；
对所述半导体层(10)的两端进行掺杂处理以分别形成一第一掺杂区域(11)，并对未被所述栅极(50)和所述多个悬空电极(60)遮盖的半导体层(10)进行掺杂处理以形成多个第二掺杂区域(12)；
在两个所述第一掺杂区域(11)上分别相应地设置源极(20)和漏极(30)。
9.如权利要求8所述的薄膜晶体管的制备方法，其特征在于，在形成所述绝缘层(40)、所述栅极(50)和所述多个悬空电极(60)过程中，在所述半导体层(10)上依次形成绝缘材料层及金属层，同时图案化所述绝缘材料层及所述金属层，所述绝缘材料层形成绝缘层(40)，所述金属层形成栅极(50)和多个悬空电极(60)。
10.如权利要求8所述的薄膜晶体管的制备方法，其特征在于，所述第一掺杂区域(11)和所述第二掺杂区域(12)均为通过在所述半导体层(10)上采用注入离子的方式而形成，所述第一掺杂区域(11)掺杂的离子个数为1×1016个/cm2，所述第二掺杂区域(12)掺杂的离子个数为5×1015个/cm2。
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