CN204758983U - 一种阵列基板、液晶面板及液晶显示装置 - Google Patents
一种阵列基板、液晶面板及液晶显示装置 Download PDFInfo
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Abstract
本实用新型公开一种阵列基板、液晶面板及液晶显示装置,涉及显示技术领域,用于增大液晶显示装置的视角。阵列基板包括呈阵列状排列的多个像素单元,至少一个像素单元包括第一像素电极和第二像素电极,第一像素电极连接有第一薄膜晶体管,第二像素电极连接有第二薄膜晶体管;其中,第一薄膜晶体管中的源极和漏极之间设有沟道,第一像素电极在沟道所在平面上的投影覆盖至少部分沟道,第一像素电极以及第一薄膜晶体管中的源极和漏极构成顶栅薄膜晶体管。所述液晶面板包括上述技术方案所提供的阵列基板。所述液晶显示装置包括上述技术方案所提供的液晶面板。本实用新型提供的阵列基板、液晶面板及液晶显示装置用于液晶显示设备中。
Description
技术领域
本实用新型涉及显示技术领域,尤其涉及一种阵列基板、液晶面板及液晶显示装置。
背景技术
液晶显示装置具有功耗低、无辐射等特点,现已占据了平面显示领域的主导地位。
现有的液晶显示装置中的液晶面板通常包括相对设置的阵列基板和彩膜基板,以及填充在阵列基板和彩膜基板之间的液晶层,其中,阵列基板上设有呈阵列状排列的多个像素单元,像素单元中设有像素电极,对应该像素电极,在彩膜基板上设有公共电极,通过像素电极和公共电极之间形成的电场,控制像素单元对应的液晶区域内的液晶分子的偏转角度,进而实现液晶显示功能。
然而,在现有的阵列基板中,每个像素单元通常仅包括一个像素电极,在该像素电极和公共电极形成的电场的作用下,单个像素单元对应的液晶区域内的液晶分子均具有相同的偏转角度,导致现有技术中液晶显示装置的视角较小。
实用新型内容
本实用新型的目的在于提供一种阵列基板及显示装置,用于增大液晶显示装置的视角。
为了实现上述目的,本实用新型提供如下技术方案:
一方面,本实用新型提供了一种阵列基板,包括呈阵列状排列的多个像素单元,至少一个所述像素单元包括第一像素电极和第二像素电极,所述第一像素电极连接有第一薄膜晶体管,所述第二像素电极连接有第二薄膜晶体管;其中,
所述第一薄膜晶体管中的源极和漏极之间设有沟道,所述第一像素电极在所述沟道所在平面上的投影覆盖至少部分所述沟道,所述第一像素电极以及所述第一薄膜晶体管中的源极和漏极构成顶栅薄膜晶体管。
在本实用新型提供的阵列基板中,多个像素单元中至少有一个像素单元包括由第一薄膜晶体管驱动的第一像素电极以及由第二薄膜晶体管驱动的第二像素电极,其中,第一薄膜晶体管中的源极和漏极之间设有沟道,第一像素电极在沟道平面上的投影覆盖至少部分该沟道,第一像素电极以及第一薄膜晶体管中的源极和漏极共同构成顶栅薄膜晶体管,在顶栅薄膜晶体管中,以第一像素电极作为栅极,以第一薄膜晶体管的漏极作为源极,以第一薄膜晶体管的源极作为漏极;并且,第一像素电极与顶栅薄膜晶体管的源极(即第一薄膜晶体管的漏极)电连接。当第一像素电极放电时,顶栅薄膜晶体管的栅极(即第一像素电极)内产生载流子迁移,使得顶栅薄膜晶体管中的源极和漏极之间的沟道导通,即顶栅薄膜晶体管处于开态,从而第一像素电极能够通过顶栅薄膜晶体管释放部分电压。因此,当第一像素电极和第二像素电极放电时,在同一像素单元中,第一像素电极的电压低于第二像素电极的电压,从而第一像素电极对应的液晶区域内的液晶分子的偏转角度小于第二像素电极对应的液晶区域内的液晶分子的偏转角度,即同一像素单元对应的液晶区域内的液晶分子具有不同的偏转角度;因此,与现有技术中同一像素单元对应的液晶区域内的液晶分子的偏转角度相同相比,本实用新型提供的阵列基板中,同一像素单元对应的液晶区域内的液晶分子至少具有两种偏转角度,从而明显提高了液晶显示装置的视角。
第二方面,本实用新型还提供了一种液晶面板,所述液晶面板包括上述技术方案所提供的阵列基板。
相对于现有技术,本实用新型提供的液晶面板具有的优势与上述阵列基板相对于现有技术所具有的优势相同,在此不再赘述。
第三方面,本实用新型还提供了一种液晶显示装置,所述液晶显示装置包括上述技术方案所提供的液晶面板。
相对于现有技术,本实用新型提供的液晶显示装置具有的优势与上述液晶面板相对于现有技术所具有的优势相同,在此不再赘述。
附图说明
此处所说明的附图用来提供对本实用新型的进一步理解,构成本实用新型的一部分,本实用新型的示意性实施例及其说明用于解释本实用新型,并不构成对本实用新型的不当限定。在附图中:
图1为本实用新型实施例的阵列基板中像素单元的结构示意图;
图2为本实用新型实施例的阵列基板中另一种像素单元的结构示意图。
附图标记:
1-液晶面板,2-背光源,
21-凹部,100-第一像素电极,
110-第一薄膜晶体管,111-第一薄膜晶体管的源极,
112-第一薄膜晶体管的漏极,113-第一过孔,
200-第二像素电极,210-第二薄膜晶体管,
211-第二薄膜晶体管的源极,212-第二薄膜晶体管的漏极,
213-第二过孔,300-公共电极,
310-屏蔽电极。
具体实施方式
为了进一步说明本实用新型实施例提供的阵列基板及显示装置,下面结合说明书附图进行详细描述。
请参阅图1,本实用新型实施例提供了一种阵列基板,包括呈阵列状排列的多个像素单元,其中至少一个像素单元包括第一像素电极100和第二像素电极200,第一像素电极100连接有第一薄膜晶体管110,第二像素电极200连接有第二薄膜晶体管210;其中,第一薄膜晶体管110中的源极111和漏极112之间设有沟道,第一像素电极100在该沟道所在平面上的投影覆盖至少部分该沟道,第一像素电极100以及第一薄膜晶体管110中的源极111和漏极112构成顶栅薄膜晶体管。
具体实施时,阵列基板包括衬底基板,以及在衬底基板上呈阵列状排列的多个像素单元,在至少一个像素单元中,第一像素电极100和第二像素电极200位于该像素单元的顶部,且以第一像素电极100作为顶栅薄膜晶体管的栅极,以第一薄膜晶体管110中的漏极112作为顶栅薄膜晶体管的源极,以第一薄膜晶体管110中的源极113作为顶栅薄膜晶体管的漏极,且第一像素电极与顶栅薄膜晶体管的源极(即漏极113)连接。
通过上述设置,在像素电极放电时,顶栅薄膜晶体管的栅极(即第一像素电极100)中存在载流子的迁移,使得顶栅薄膜晶体管的中的源极和漏极之间的沟道导通,即顶栅薄膜晶体管处于开态,从而第一像素电极100能够通过顶栅薄膜晶体管向数据线2释放部分电压,使得在同一像素单元中,第一像素电极100的放电速率高于第二像素电极200的放电速率,从而使得第一像素电极100的电压低于第二像素电极200的电压,进而使得第一像素电极100与彩膜基板上的公共电极所形成的电场的场强低于第二像素电极200与彩膜基板上的公共电极所形成的电场的场强;将同一像素单元对应的液晶区域大致分为第一像素电极100对应的低压畴区和第二像素电极200对应的高压畴区,则在上述场强不同的电场的作用下,低压畴区内的液晶分子所受的电场力小于高压畴区内的液晶分子所受的电场力,从而使得低压畴区内的液晶分子的偏转角度小于高压畴区内的液晶分子的偏转角度,即同一像素单元对应的液晶区域内的液晶分子具有不同的偏转角度;因此,与现有技术中同一像素单元对应的液晶区域内的液晶分子的偏转角度相同相比,本实用新型提供的阵列基板中,同一像素单元对应的液晶区域内的液晶分子至少具有两种偏转角度,从而明显提高了液晶显示装置的视角。
在本实用新型实施例中,第一像素电极100在第一薄膜晶体管110中源极111和漏极112之间的沟道所在平面上的投影,可如图1所示,覆盖第一薄膜晶体管110中源极111和漏极112之间的整个沟道,也可如图2所示,覆盖第一薄膜晶体管110中源极111和漏极112之间的部分沟道,由于在通常情况下,第一像素电极100通过顶栅薄膜晶体管的放电速率,与上述第一像素电极100在第一薄膜晶体管110中源极111和漏极112之间的沟道所在平面上的投影对该沟道的覆盖面积正相关,因此,在具体实施时,本领域技术人员可根据第一像素电极100通过顶栅薄膜晶体管放电的速率以及阵列基板上的布线空间大小,合理调整上述第一像素电极100的投影覆盖沟道的面积。
进一步地,在同一像素单元中可设置至少两个第一像素电极100,每个第一像素电极100由对应的第一薄膜晶体管110驱动,每个第一薄膜晶体管110中的源极111和漏极112之间存在沟道,与第一薄膜晶体管110对应的第一像素电极100在该第一薄膜晶体管110中的沟道所在平面上的投影至少部分覆盖该沟道,且对于每个第一薄膜晶体管110,其沟道被第一像素电极100所覆盖部分的面积大小不等,使得对应每个第一像素电极100构成不同的顶栅薄膜晶体管。通过上述手段,在同一像素单元中,当第一像素电极100和第二像素电极200放电时,使各第一像素电极100通过对应的顶栅薄膜晶体管释放电压的速率不同,从而使得各第一像素电极100所具有的电压不同,该不同的电压使得各低压畴区内的液晶分子具有不同的偏转角度,加之高压畴区内的液晶分子的偏转角度也不同于与各低压畴区内的液晶分子的偏转角度,因此,在本实用新型实施例中,同一像素单元对应的液晶区域内的液晶分子至少具有三个不同的偏转角度,与现有技术中同一像素单元对应的液晶区域内的液晶分子只有一种偏转角度相比,明显增大了液晶显示装置的视角。
请参阅图1,对于上述技术方案而言,阵列基板还包括横纵交叉设置的多条数据线和多条栅线,第二薄膜晶体管210包括异层设置的源极211和栅极;其中,源极211由数据线2与栅线1交叉区域的一段数据线构成,该栅极由栅线1与数据线2交叉区域的一段栅线构成。具体地,栅线1位于像素单元中的栅极层,数据线2位于像素单元中源极111、源极211及漏极112、漏极212所在的源漏金属层,在进行栅极层和源漏金属层的构图工艺时,直接使数据线2与栅线1交叉区域的一段数据线2充当源极211,并使该区域内的栅线1充当栅极,从而无需在衬底基板上另外布置源极211、栅极以及将源极211和栅极分别连接至信号线的线路,这样既能够简化栅极层和源漏金属层的构图工艺,又能够降低阵列基板上的线路总面积,提高基板的开口率,从而获得更好的显示效果。此外,本实用新型实施例优选同一像素单元中的第一像素电极100和第二像素电极200分别位于信号线的两侧,并进一步优选同一像素单元中的第一像素电极100和第二像素电极200分别位于栅线1的两侧,从而能够使第一像素电极100和第二像素电极200均接近栅线1,减少将第二像素电极200连接至第二薄膜晶体管210的线路长度、以及将第一像素电极100连接至第一薄膜晶体管110的线路长度,从而进一步简化栅极层和源漏金属层的构图工艺,并降低阵列基板上的线路总面积,提高基板的开口率,从而获得更好的显示效果。
请参阅图1,进一步地,将第二薄膜晶体管210的源极211的形状设置为圆弧状,与I形的源极相比,圆弧状的源极211使位于源极211和漏极212之间的沟道的长度增加,进而增加该沟道的平均宽长比W/L(其中,宽W为沟道的长度,L为沟道横截面的宽度,在该实施例中,宽W与圆弧状的部分数据线2的长度成正比),由于当第二薄膜晶体管210处于开态时,其充电电流Ion与沟道的宽长比W/L之间存在如下关系式:
其中,Vgs为栅极和源极间的电位差,Vth为电荷对有源层导带的起始受激电压,即阈值电压。Cox=ε0εox/dox,式中Cox为栅极绝缘层单位面积的电容,ε0为真空介电常数、εox为栅绝缘层介电常数、dox为栅绝缘层的厚度。μn为有源层的电子载流子迁移率。
由上述关系式可知,第二薄膜晶体管210的充电电流大小与其沟道的宽长比成正比。基于上述原因,将第二薄膜晶体管210的源极211设置为圆弧状,使得第二薄膜晶体管中源极211和漏极212之间的沟道变长,从而提高第二薄膜晶体管200中沟道的宽长比,进而提高第二薄膜晶体管210的充电电流,进一步提高第二像素电极200在充电时所获得的电压,以进一步增大同一像素单元中第一像素电极100的电压和第二像素电极200的电压的差值,进而进一步增大低压畴区内的液晶分子的偏转角度和高压畴区内的液晶分子的偏转角度的差值,使得低压畴区内的液晶分子的偏转角度与高压畴区内的液晶分子的偏转角度的夹角更大,从而进一步扩大液晶显示装置的视角。
请参阅图2,通常情况下,第一像素电极100或第二像素电极200具有的电压越高,其产生的电磁场对周围元器件内通过的信号的干扰越大,因此,与第一像素电极100相比,第二像素电极200所产生的电磁场对周围元器件内通过的信号的干扰较为明显。为了减轻此现象,作为上述技术方案的一个改进方案,在第一像素电极100和第二像素电极200之间还设有公共电极300,公共电极300上设有伸向第二像素电极200且位于相邻两个第二像素电极200之间的屏蔽电极310。通过上述设置,使相邻的两个第二像素电极200被屏蔽电极310隔开,并通过屏蔽电极310对第二像素电极200产生的电磁场进行屏蔽,减轻第二像素电极200所产生的电磁场对相邻像素单元中的元器件内通过的信号的干扰。此外,屏蔽电极310形状可为图2中所示的长条状,本实用新型实施例优选音叉状的屏蔽电极310,这是由于,音叉状的屏蔽电极具有两个平行排列的叉臂,两个叉臂共同对第二像素电极200的电磁场进行屏蔽,从而能够更好地减弱该电磁场对周围元器件的影响,进一步提高屏蔽电极310对第二像素电极200所产生的电场和磁场的屏蔽效果。
请参阅图2,进一步地,屏蔽电极310位于相邻的两条数据线2之间,在屏蔽电极310两侧,数据线2与每个第二像素电极200对应的部分具有向该第二像素电极200内凹的凹部21。具体地,数据线2位于源极111、211和漏极112、212所在的源漏金属层上,在进行源漏金属层的构图工艺时,在数据线2上,对应各个与其相邻的第二像素电极200,数据线2上的一段数据线向第二像素电极200凸起以形成上述凹部21,凹部21可呈矩形的凹坑状。通过上述设置,使得第二像素电极200附近的部分数据线2与屏蔽电极310之间存在适当的间隔,从而能够避免该部分数据线2与屏蔽电极310构成寄生电容,对数据线2内通过的信号产生干扰。
请参阅图2,对于上述改进方案而言,第一薄膜晶体管110的漏极111和第一像素电极100之间设有钝化层,第一薄膜晶体管110的漏极111通过设于钝化层上的第一过孔113与第一像素电极100电连接;且第一过孔113在公共电极300所在平面上的投影位于公共电极300内。具体地,使第一像素电极100和公共电极300在第一过孔113处存在一定的正对面积,从而使得第一像素电极100与公共电极在第一过孔113处形成一个较小的补偿电容(第一像素电极100和公共电极300分别作为补偿电容的两个电极),该补偿电容能够在第一像素电极100充电时存储一定的电量,并在第一像素电极100放电时对其电压进行适度的补偿,以避免第一像素电极100放电过快。由于第一像素电极100放电过快将导致其放电过程不能维持至下次充电过程开始,则低压畴区内的液晶分子无法在第一像素电极100的一次充放电循环中保持偏转,导致在第一像素电极100的一次充放电循环中,低压畴区无法持续使光线透过,最终造成该像素单元对应的画面上的像素点产生闪烁。因此,本实用新型实施例通过将第一过孔113设置在公共电极300正上方,以避免第一像素电极放电过快所造成的画面上的像素点产生闪烁。
请参阅图2,对于上述改进方案而言,第二薄膜晶体管210的漏极211和第二像素电极200之间设有钝化层,第二薄膜晶体管210的漏极211通过设于钝化层上的第二过孔213与第二像素电极200电连接;且第二过孔213在公共电极300所在平面上的投影位于公共电极300内。具体地,使第二像素电极200和公共电极300在第二过孔213处存在一定的正对面积,从而使得第二像素电极200和公共电极300在第二过孔213处形成一个较小的补偿电容,该补偿电容能够在第二像素电极200充电时存储一定的电量,并在第二像素电极200放电时对第二像素电极200的电压进行一定程度的补偿,从而进一步降低第二像素电极200的放电速率,使得同一像素单元中第二像素电极200的电压高于第一像素电极100的电压,从而确保低压畴区内的液晶分子的偏转角度和高压畴区内的液晶分子的偏转角度的差值,进而确保液晶显示装置的视角。
本实用新型实施例还提供了一种液晶面板,包括上述任一项技术方案所述的阵列基板。
在本实用新型提供的液晶面板包括的阵列基板上,设有呈阵列状排列的多个像素单元,其中至少有一个像素单元包括由第一薄膜晶体管驱动的第一像素电极以及由第二薄膜晶体管驱动的第二像素电极,其中,第一薄膜晶体管中的源极和漏极之间设有沟道,第一像素电极在沟道平面上的投影覆盖至少部分该沟道,第一像素电极以及第一薄膜晶体管中的源极和漏极共同构成顶栅薄膜晶体管,在顶栅薄膜晶体管中,以第一像素电极作为栅极,以第一薄膜晶体管的漏极作为源极,以第一薄膜晶体管的源极作为漏极;并且,第一像素电极与顶栅薄膜晶体管的源极(即第一薄膜晶体管的漏极)电连接。当第一像素电极放电时,顶栅薄膜晶体管的栅极(即第一像素电极)内产生载流子迁移,使得顶栅薄膜晶体管中的源极和漏极之间的沟道导通,即顶栅薄膜晶体管处于开态,从而第一像素电极能够通过顶栅薄膜晶体管释放部分电压。因此,当第一像素电极和第二像素电极放电时,在同一像素单元中,第一像素电极的电压低于第二像素电极的电压,从而第一像素电极对应的液晶区域内的液晶分子的偏转角度小于第二像素电极对应的液晶区域内的液晶分子的偏转角度,即同一像素单元对应的液晶区域内的液晶分子具有不同的偏转角度;因此,与现有技术中同一像素单元对应的液晶区域内的液晶分子的偏转角度相同相比,本实用新型所提供的液晶面板所采用的阵列基板中,同一像素单元对应的液晶区域内的液晶分子至少具有两种偏转角度,从而明显提高了液晶显示装置的视角。
本实用新型实施例还提供了一种液晶显示装置,包括上述技术方案所述的液晶面板。
在本实用新型提供的液晶显示装置中包括液晶面板,液晶面板包括阵列基板,阵列基板上设有呈阵列状排列的多个像素单元,其中至少有一个像素单元包括由第一薄膜晶体管驱动的第一像素电极以及由第二薄膜晶体管驱动的第二像素电极,其中,第一薄膜晶体管中的源极和漏极之间设有沟道,第一像素电极在沟道平面上的投影覆盖至少部分该沟道,第一像素电极以及第一薄膜晶体管中的源极和漏极共同构成顶栅薄膜晶体管,在顶栅薄膜晶体管中,以第一像素电极作为栅极,以第一薄膜晶体管的漏极作为源极,以第一薄膜晶体管的源极作为漏极;并且,第一像素电极与顶栅薄膜晶体管的源极(即第一薄膜晶体管的漏极)电连接。当第一像素电极放电时,顶栅薄膜晶体管的栅极(即第一像素电极)内产生载流子迁移,使得顶栅薄膜晶体管中的源极和漏极之间的沟道导通,即顶栅薄膜晶体管处于开态,从而第一像素电极能够通过顶栅薄膜晶体管释放部分电压。因此,当第一像素电极和第二像素电极放电时,在同一像素单元中,第一像素电极的电压低于第二像素电极的电压,从而第一像素电极对应的液晶区域内的液晶分子的偏转角度小于第二像素电极对应的液晶区域内的液晶分子的偏转角度,即同一像素单元对应的液晶区域内的液晶分子具有不同的偏转角度;因此,与现有技术中同一像素单元对应的液晶区域内的液晶分子的偏转角度相同相比,本实用新型提供的阵列基板所采用的液晶面板中,阵列基板上的同一像素单元对应的液晶区域内的液晶分子至少具有两种偏转角度,从而显著增大了液晶显示装置的视角。
在上述实施方式的描述中,具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上,仅为本实用新型的具体实施方式,但本实用新型的保护范围并不局限于此,任何熟悉本技术领域的技术人员在本实用新型揭露的技术范围内,可轻易想到变化或替换,都应涵盖在本实用新型的保护范围之内。因此,本实用新型的保护范围应以权利要求的保护范围为准。
Claims (9)
1.一种阵列基板,包括呈阵列状排列的多个像素单元,其特征在于,至少一个所述像素单元包括第一像素电极和第二像素电极,所述第一像素电极连接有第一薄膜晶体管,所述第二像素电极连接有第二薄膜晶体管;其中,
所述第一薄膜晶体管中的源极和漏极之间设有沟道,所述第一像素电极在所述沟道所在平面上的投影覆盖至少部分所述沟道,所述第一像素电极以及所述第一薄膜晶体管中的源极和漏极构成顶栅薄膜晶体管。
2.根据权利要求1所述的阵列基板,其特征在于,所述阵列基板还包括横纵交叉设置的多条数据线和多条栅线;所述第二薄膜晶体管包括异层设置的源极和栅极;其中,所述源极由所述数据线与所述栅线交叉区域的一段数据线构成,所述栅极由所述栅线与所述数据线交叉区域的一段栅线构成。
3.根据权利要求2所述的阵列基板,其特征在于,所述第二薄膜晶体管的源极的形状为圆弧状。
4.根据权利要求1或2所述的阵列基板,其特征在于,在所述第一像素电极和所述第二像素电极之间还设有公共电极,所述公共电极上设有伸向所述第二像素电极且位于相邻两个所述第二像素电极之间的屏蔽电极。
5.根据权利要求4所述的阵列基板,其特征在于,所述阵列基板还包括多条数据线,所述屏蔽电极位于相邻的两条所述数据线之间,在所述屏蔽电极的两侧,所述数据线与每个所述第二像素电极对应的部分具有向该所述第二像素电极内凹的凹部。
6.根据权利要求4所述的阵列基板,其特征在于,所述第一薄膜晶体管的漏极和所述第一像素电极之间设有钝化层,所述第一薄膜晶体管的漏极通过设于所述钝化层上的第一过孔与所述第一像素电极电连接;且所述第一过孔在所述公共电极所在平面上的投影位于所述公共电极内。
7.根据权利要求4所述的阵列基板,其特征在于,所述第二薄膜晶体管的漏极和所述第二像素电极之间设有钝化层,所述第二薄膜晶体管的漏极通过设于所述钝化层上的第二过孔与所述第二像素电极电连接;且所述第二过孔在所述公共电极所在平面上的投影位于所述公共电极内。
8.一种液晶面板,其特征在于,包括权利要求1-7中任一项所述的阵列基板。
9.一种液晶显示装置,其特征在于,包括权利要求8所述的液晶面板。
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US15/038,147 US20170115533A1 (en) | 2015-05-26 | 2015-11-20 | Array substrate, liquid crystal display panel and liquid crystal display device |
EP15860011.4A EP3306385B1 (en) | 2015-05-26 | 2015-11-20 | Array substrate, liquid crystal display panel and liquid crystal display device |
JP2016567905A JP6629240B2 (ja) | 2015-05-26 | 2015-11-20 | アレイ基板、液晶表示パネル及び液晶表示装置 |
KR1020177000631A KR101964750B1 (ko) | 2015-05-26 | 2015-11-20 | 어레이 기판, 액정 디스플레이 패널 및 액정 디스플레이 디바이스 |
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MX2017000370A MX360795B (es) | 2015-05-26 | 2015-11-20 | Sustrato de matriz, panel visualizador de cristal liquido y dispositivo visualizador de cristal liquido. |
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WO2016188062A1 (zh) * | 2015-05-26 | 2016-12-01 | 京东方科技集团股份有限公司 | 一种阵列基板、液晶显示面板及液晶显示装置 |
US10754216B2 (en) | 2015-05-26 | 2020-08-25 | Boe Technology Group Co., Ltd. | Array substrate and driving method thereof, liquid crystal display panel, and liquid crystal display device |
WO2017041441A1 (zh) * | 2015-09-09 | 2017-03-16 | 京东方科技集团股份有限公司 | 阵列基板及其制造方法、显示装置 |
US10490575B2 (en) | 2015-09-09 | 2019-11-26 | Boe Technology Group Co., Ltd. | Array substrate and display device |
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