CN105652542B - 阵列基板、液晶显示面板及液晶显示装置 - Google Patents
阵列基板、液晶显示面板及液晶显示装置 Download PDFInfo
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Abstract
本发明的阵列基板、液晶显示面板及液晶显示装置,设计由多晶硅半导体层和第一金属层以及两者之间的绝缘层,或者多晶硅半导体层和第二金属层以及两者之间的绝缘层形成MIS存储电容,当第一金属层或第二金属层一侧接收负性灰阶电压时,多晶硅半导体层中的P‑Si会聚集形成空穴,当接收正性灰阶电压时,在P‑Si的上层会形成耗尽层,降低MIS存储电容的电容量,从而降低MIS存储电容在正负性灰阶电压时的电容量差值,改善闪烁现象的发生,确保显示效果。
Description
技术领域
本发明涉及液晶显示技术领域,具体而言涉及一种阵列基板、液晶显示面板及液晶显示装置。
背景技术
LCD(Liquid Crystal Display,液晶显示器)产生闪烁(Flicker)现象的原因有多种,最主要的原因是TFT(Thin Film Transistor,薄膜晶体管)漏电的差异,即TFT在施加负性灰阶电压时的漏电大于施加正性灰阶电压时的漏电,导致阵列基板的存储电容在正负性灰阶电压时的电容量存在差值。随着LCD广泛应用于各个显示领域,并且为了降低功耗,LCD往往被施加较低的source(源极)驱动电压,导致相邻灰阶的灰阶电压之差变小,更容易加剧闪烁现象的发生,影响显示效果。
发明内容
有鉴于此,本发明提供一种阵列基板、液晶显示面板及液晶显示装置,能够改善闪烁现象的发生,确保显示效果。
本发明提供的一种阵列基板,包括衬底基材以及形成于衬底基材上的第一金属层、绝缘层、多晶硅半导体层以及第二金属层,第一金属层包括间隔设置的第一区域和第二区域,第一区域的第一金属层为阵列基板的TFT的栅极,第二金属层包括间隔设置的第三区域和第四区域,第三区域和第四区域的第二金属层分别为TFT的源极和漏极,其中,多晶硅半导体层和第二区域的第一金属层通过夹持于两者之间的绝缘层绝缘重叠,或者,多晶硅半导体层和第四区域的第二金属层通过夹持于两者之间的绝缘层绝缘重叠,以形成阵列基板的MIS存储电容。
其中,TFT的栅极位于多晶硅半导体层的上方,阵列基板还包括形成于衬底基材上的遮光金属层、设置于遮光金属层和多晶硅半导体层之间的缓冲层,遮光金属层位于第一区域的下方。
其中,阵列基板还包括形成于第一金属层和第二金属层之间的介质隔离层,多晶硅半导体层连接阵列基板的导电金属层,介质隔离层形成有第一接触孔,第二区域的第一金属层通过第一接触孔与第四区域的第二金属层连接,使得多晶硅半导体层和第二区域的第一金属层以及两者之间的绝缘层形成MIS存储电容。
其中,多晶硅半导体层连接阵列基板的导电金属层,第四区域的第二金属层的一部分直接设置于绝缘层上,使得多晶硅半导体层和第四区域的第二金属层以及两者之间的绝缘层形成MIS存储电容。
其中,遮光金属层包括间隔设置的第五区域和第六区域,第五区域位于第一区域的下方,阵列基板的导电金属层包括第六区域的遮光金属层,缓冲层形成有第二接触孔,多晶硅半导体层通过第二接触孔与第六区域的遮光金属层连接。
其中,第六区域的遮光金属层横跨阵列基板的有效显示区域,阵列基板还包括设置于衬底基材上的公共电极,第六区域的遮光金属层在有效显示区域的外围与公共电极连接。
其中,多晶硅半导体层包括重掺杂处理后的多晶硅层。
其中,重掺杂处理包括对多晶硅层重掺杂铍Be。
本发明提供的一种液晶显示面板,包括上述阵列基板。
本发明提供的一种液晶显示装置,包括液晶显示面板和为液晶显示面板提供光线的光源模组,所述液晶显示面板为上述液晶显示面板。
本发明的阵列基板、液晶显示面板及液晶显示装置,设计由多晶硅半导体层和第一金属层以及两者之间的绝缘层或者多晶硅半导体层和第二金属层以及两者之间的绝缘层形成MIS存储电容,当第一金属层或第二金属层一侧接收负性灰阶电压时,多晶硅半导体层中的P-Si会聚集形成空穴,当接收正性灰阶电压时,在P-Si的上层会形成耗尽层,降低MIS存储电容的电容量,从而降低MIS存储电容在正负性灰阶电压时的电容量差值,改善闪烁现象的发生,确保显示效果。
附图说明
图1是本发明一实施例的液晶显示面板的结构剖视图;
图2是图1所示液晶显示面板一实施例的像素结构示意图;
图3是图2所示的像素结构的等效电路图;
图4是图3所示的存储电容的结构剖视图;
图5是图3所示的存储电容的C-V曲线图;
图6是本发明第一实施例的像素区域的结构示意图;
图7是图6所示像素区域沿A-A线的结构剖视图;
图8是本发明第二实施例的像素区域的结构剖视图;
图9是本发明第三实施例的像素区域的结构示意图;
图10是图9所示像素区域沿B-B线的结构剖视图;
图11是本发明一实施例的液晶显示装置的结构剖视图。
具体实施方式
图1是本发明一实施例的液晶显示面板的结构剖视图。如图1所示,本实施例的液晶显示面板10包括相对间隔设置的彩膜基板(Color Filter Substrate,简称CF基板,又称彩色滤光片基板)11和阵列基板(Thin Film Transistor Substrate,简称TFT基板,又称薄膜晶体管基板或Array基板)12以及填充于两基板之间的液晶(液晶分子)13,该液晶13位于阵列基板12和彩膜基板11叠加形成的液晶盒内。
结合图2所示液晶显示面板10的像素结构示意图,阵列基板12包括沿列方向设置的多条据线D、沿行方向设置的多条扫描线G以及由扫描线G和数据线D定义的多个像素区域P。其中,每一像素区域P连接对应的一条数据线D和一条扫描线G,各条扫描线G连接于栅极驱动器21以对各像素区域P提供扫描电压,各条数据线D连接于源极驱动器22以对各像素区域P提供灰阶电压。进一步结合图3所示的像素结构的等效电路图,阵列基板12包括薄膜晶体管T、存储电容Cst以及液晶电容Clc,液晶电容Clc由位于像素区域P的像素电极、液晶显示面板10的公共电极以及位于两者之间的液晶13形成。
根据液晶显示面板10的显示原理,通过为扫描线G输入扫描电压,位于同一行的薄膜晶体管T被同时打开,且在一定时间后下一行的薄膜晶体管T被同时打开,依次类推。由于每一行薄膜晶体管T打开的时间比较短,液晶电容Clc充电控制液晶13偏转的时间较短,很难达到液晶13的响应时间,存储电容Cst便可以用于在薄膜晶体管T关闭后维持像素区域P的电压,从而为液晶13响应提供时间。
与现有技术不同的是,本发明实施例的存储电容Cst为MIS(MetalInsulatorSemiconductor,金属-绝缘体-半导体)存储电容,如图4所示,该MIS存储电容Cst由金属层41和多晶硅(polycrystalline silicon,P-Si)半导体层42通过夹持于两者之间的绝缘层43绝缘重叠形成。其中,对应位于MIS存储电容Cst区域的多晶硅半导体层42为重掺杂处理后的多晶硅层,优选在多晶硅层中重掺杂Be(铍)。
当金属层41一侧接收正负性灰阶电压时,多晶硅半导体层42中的P-Si会聚集形成空穴421,当金属层41接收的灰阶电压由正性变为负性时,空穴421所在区域会形成耗尽层422,即在P-Si的上层会形成耗尽层422,该耗尽层422能够降低MIS存储电容Cst的电容量。也就是说,本实施例的MIS存储电容Cst相当于一个可变电容器,进一步结合图5所示的C-V(电容量-灰阶电压)曲线,当灰阶电压为负性时,MIS存储电容Cst的电容量为C1,当灰阶电压为正性时,MIS存储电容Cst的电容量为C2=C1*C0/(C1+C0),其中C0为耗尽层422与金属层41之间的电容量,可知C1>C2,即MIS存储电容Cst在接收负性灰阶电压时的电容量大于接收正性灰阶电压时的电容量。由于灰阶电压为负性时薄膜晶体管T的漏电较大,本发明实施例增加MIS存储电容Cst的电容量,则会降低薄膜晶体管T的漏电,从而改善TFT漏电的影响,即降低MIS存储电容Cst在接收正负性灰阶电压时的电容量差值,以此改善闪烁现象的发生,确保液晶显示面板10的显示效果。
在不同的像素结构设计中,MIS存储电容Cst的金属层41以及绝缘层43具体为液晶显示面板10的不同结构。下面结合附图6~10,对本发明实施例的技术方案进行清楚、完整地描述。
图6是本发明第一实施例的像素区域P的结构示意图,图7是图6所示像素区域P沿A-A线的结构剖视图。结合图6和图7所示,阵列基板12包括衬底基材121以及依次形成于衬底基材121上的十一层结构:遮光金属层M0、缓冲层122、多晶硅半导体层123、绝缘层(GateInsulation Layer,GI,又称栅极绝缘层)124、第一金属层Ml、介质隔离层(Interlayerdielectric isolation,ILD,又称层间介质隔离)125、第二金属层M2、平坦钝化层126、公共电极127、PV(Passivation,钝化)层128以及像素电极129。其中,多晶硅半导体层123、第一区域Zl的第一金属层Ml、第三区域Z3和第四区域Z4的第二金属层M2以及相互之间所夹持的绝缘层124、介质隔离层125形成阵列基板12的薄膜晶体管T,其他各层结构之间的连接可参阅现有技术,此处不予以赘述。
第一金属层Ml包括间隔设置的第一区域Zl和第二区域Z2,第一区域Zl的第一金属层Ml为薄膜晶体管T的栅极;第二金属层M2包括间隔设置的第三区域Z3和第四区域Z4,第三区域Z3和第四区域Z4的第二金属层M2分别为薄膜晶体管T的源极和漏极;遮光金属层M0位于第一区域Z1的下方。鉴于薄膜晶体管T的栅极位于多晶硅半导体层123的上方,本实施例的像素区域P可视为顶栅型像素设计。
在本实施例中,介质隔离层125形成有第一接触孔Ol,第二区域Z2的第一金属层Ml通过第一接触孔Ol与第四区域Z4的第二金属层M2连接,以从第四区域Z4的第二金属层M2接收灰阶电压;多晶硅半导体层123连接阵列基板12的导电金属层以从导电金属层接收电压;多晶硅半导体层123和第二区域Z2的第一金属层Ml通过夹持于两者之间的绝缘层124绝缘重叠设置,以形成阵列基板12的MIS存储电容Cst。也就是说,本实施例的第二区域Z2的第一金属层Ml形成图4所示的MIS存储电容Cst的金属层41、绝缘层124形成图4所示的绝缘层43。
其中,与多晶硅半导体层123连接的导电金属层可以为公共电极127,该公共电极127横跨阵列基板12的有效显示区域(Active Area,AA),并在有效显示区域的外围与多晶硅半导体层123连接。
当然,该导电金属层也可以为与图7所示遮光金属层M0间隔设置的遮光金属层,请参阅图8所示的本发明第二实施例的像素区域P的结构剖视图。为便于描述与上述实施例的不同之处,对于其中相同结构元件进行相同标号。如图8所示,遮光金属层M0包括间隔设置的第五区域Z5和第六区域Z6,第五区域Z5位于第一区域Z1的下方,第六区域Z6位于第二区域Z2的下方;缓冲层122形成有第二接触孔O2,多晶硅半导体层123通过第二接触孔O2与第六区域Z6的遮光金属层M0连接,第六区域Z6的遮光金属层M0横跨阵列基板12的有效显示区域,并在有效显示区域的外围与公共电极127连接以接收电压。
本发明实施例全文描述中,对应位于薄膜晶体管T区域的多晶硅半导体层123包括未经重掺杂处理的多晶硅层P-Si,即,本发明实施例的多晶硅半导体层123包括间隔设置的两个区域,一个区域包括未经重掺杂处理的多晶硅层P-Si,另一个区域为重掺杂处理后的多晶硅层,该另一个区域的多晶硅半导体层123和第二区域Z2的第一金属层Ml以及两者之间的绝缘层124形成阵列基板12的MIS存储电容Cst。
图9是本发明第三实施例的像素区域P的结构示意图,图10是图9所示像素区域P沿B-B线的结构剖视图。为便于描述与上述实施例的不同之处,对于其中相同结构元件进行相同标号。结合图9和图10所示,在图6~图8所示实施例的描述基础上但不同的是,本实施例并未设置第二区域Z2的第一金属层Ml,而是将第四区域Z4的第二金属层M2的一部分直接设置于绝缘层124上,使得多晶硅半导体层123和第四区域Z4的第二金属层M2以及两者之间的绝缘层124形成MIS存储电容Cst,无需在介质隔离层125上形成有第一接触孔Ol。
综上所述,本发明实施例的目的是设计由多晶硅半导体层和第一金属层以及两者之间的绝缘层或者多晶硅半导体层和第二金属层以及两者之间的绝缘层形成MIS存储电容,当第一金属层或第二金属层一侧接收负性灰阶电压时,多晶硅半导体层中的P-Si会聚集形成空穴,当接收正性灰阶电压时,在P-Si的上层会形成耗尽层,降低MIS存储电容的电容量,从而降低MIS存储电容在正负性灰阶电压时的电容量差值,以此改善闪烁现象的发生,确保显示效果。
本发明实施例还提供一种如图11所示的液晶显示装置110,该液晶显示装置110包括上述液晶显示面板10以及为液晶显示面板10提供光线的光源模组111,该液晶显示面板10可以采用FFS(Fringe Field Switching,边缘场开关)技术。由于该液晶显示装置110也具有阵列基板12的上述设计,因此亦具有相同的有益效果。
应理解,以上所述仅为本发明的实施例,并非因此限制本发明的专利范围,凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换,例如各实施例之间技术特征的相互结合,或直接或间接运用在其他相关的技术领域,均同理包括在本发明的专利保护范围内。
Claims (8)
1.一种阵列基板,其特征在于,包括衬底基材以及形成于所述衬底基材上的第一金属层、绝缘层、多晶硅半导体层以及第二金属层,所述第一金属层包括间隔设置的第一区域和第二区域,所述第一区域的第一金属层为所述阵列基板的TFT的栅极,所述第二金属层包括间隔设置的第三区域和第四区域,所述第三区域和所述第四区域的第二金属层分别为所述TFT的源极和漏极,其中,所述多晶硅半导体层和所述第二区域的第一金属层通过夹持于两者之间的所述绝缘层绝缘重叠,或者,所述多晶硅半导体层和所述第四区域的第二金属层通过夹持于两者之间的所述绝缘层绝缘重叠,以形成所述阵列基板的MIS存储电容;
其中,当所述第一金属层或所述第二金属层一侧接收负性灰阶电压时,所述多晶硅半导体层中形成空穴,当接收正性灰阶电压时,在所述空穴所在区域会形成耗尽层,能够降低所述MIS存储电容的电容量,从而降低所述MIS存储电容在正负性灰阶电压时的电容量差值;
所述TFT的栅极位于所述多晶硅半导体层的上方,所述阵列基板还包括形成于所述衬底基材上的遮光金属层、设置于所述遮光金属层和所述多晶硅半导体层之间的缓冲层,所述遮光金属层位于所述第一区域的下方;
所述阵列基板还包括形成于所述第一金属层和所述第二金属层之间的介质隔离层,所述多晶硅半导体层连接所述阵列基板的导电金属层,所述介质隔离层形成有第一接触孔,所述第二区域的第一金属层通过所述第一接触孔与所述第四区域的第二金属层连接,使得所述多晶硅半导体层和所述第二区域的第一金属层以及两者之间的绝缘层形成所述MIS存储电容。
2.根据权利要求1所述的阵列基板,其特征在于,所述多晶硅半导体层连接所述阵列基板的导电金属层,所述第四区域的第二金属层的一部分直接设置于所述绝缘层上,使得所述多晶硅半导体层和所述第四区域的第二金属层以及两者之间的绝缘层形成所述MIS存储电容。
3.根据权利要求2所述的阵列基板,其特征在于,所述遮光金属层包括间隔设置的第五区域和第六区域,所述第五区域位于所述第一区域的下方,所述阵列基板的导电金属层包括所述第六区域的遮光金属层,所述缓冲层形成有第二接触孔,所述多晶硅半导体层通过所述第二接触孔与所述第六区域的遮光金属层连接。
4.根据权利要求3所述的阵列基板,其特征在于,所述第六区域的遮光金属层横跨所述阵列基板的有效显示区域,所述阵列基板还包括设置于所述衬底基材上的公共电极,所述第六区域的遮光金属层在所述有效显示区域的外围与所述公共电极连接。
5.根据权利要求1所述的阵列基板,其特征在于,所述多晶硅半导体层包括重掺杂处理后的多晶硅层。
6.根据权利要求5所述的阵列基板,其特征在于,所述重掺杂处理包括对所述多晶硅层重掺杂铍Be。
7.一种液晶显示面板,其特征在于,所述液晶显示面板包括权利要求1-6任意一项所述的阵列基板。
8.一种液晶显示装置,其特征在于,所述液晶显示装置包括液晶显示面板和为所述液晶显示面板提供光线的光源模组,其特征在于,所述液晶显示面板为权利要求7所述的液晶显示面板。
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