CN106783884B - 一种显示面板及制程 - Google Patents

一种显示面板及制程 Download PDF

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CN106783884B
CN106783884B CN201611261789.1A CN201611261789A CN106783884B CN 106783884 B CN106783884 B CN 106783884B CN 201611261789 A CN201611261789 A CN 201611261789A CN 106783884 B CN106783884 B CN 106783884B
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dielectric constant
amorphous silicon
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CN106783884A (zh
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卓恩宗
樊堃
田轶群
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HKC Co Ltd
Chongqing HKC Optoelectronics Technology Co Ltd
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HKC Co Ltd
Chongqing HKC Optoelectronics Technology Co Ltd
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Priority to PCT/CN2017/084128 priority patent/WO2018120584A1/zh
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Abstract

本发明公开一种显示面板及制程，显示面板包括：基板；多个主动开关，设置在基板上；低介电常数保护层，所述低介电常数保护层形成在所述多个主动开关上，所述低介电常数保护层的相对介电常数小于氮化硅的相对介电常数。采用低介电常数保护层取代主动开关上的保护层材料氮化硅，低介电常数保护层比一般氧化硅的相对介电常数更低，保护层采用低介电常数保护层可以提高主动开关性能，改善信号串扰问题和RC电路延时问题。

Description

一种显示面板及制程
技术领域
本发明涉及显示技术领域，更具体的说，涉及一种显示面板及制程。
背景技术
显示器具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。现有市场上的显示器大部分为背光型显示器，其包括显示面板及背光模组(backlight module)。显示面板的工作原理是在两片平行的基板当中放置液晶分子，并在两片基板上施加驱动电压来控制液晶分子的旋转方向，以将背光模组的光线折射出来产生画面。
其中，薄膜晶体管显示器(Thin Film Transistor-Liquid Crystal Display，TFT-LCD)由于具有低的功耗、优异的画面品质以及较高的生产良率等性能，目前已经逐渐占据了显示领域的主导地位。同样，薄膜晶体管显示器包含显示面板和背光模组，显示面板包括彩膜基板(Color Filter Substrate，CF Substrate，也称彩色滤光片基板)和薄膜晶体管阵列基板(Thin Film Transistor Substrate，TFT Substrate)，上述基板的相对内侧存在透明电极。两片基板之间夹一层液晶分子(Liquid Crystal，LC)。显示面板是通过电场对液晶分子取向的控制，改变光的偏振状态，并藉由偏光板实现光路的穿透与阻挡，实现显示的目的。
制备高性能的TFT器件是高品质LCD的基础，目前薄膜晶体管(TFT)的保护层通常使用氮化硅材料。保护层具有相对较小的相对介电常数，而氮化硅的相对介电常数较高，电容大，容易造成信号的串扰。
发明内容
本发明所要解决的技术问题是提供一种主动开关上保护层的相对介电常数低的一种显示面板。
此外，本发明还提供一种采用所述显示面板的制程。
本发明的目的是通过以下技术方案来实现的：
一种显示面板，包括：
基板；
多个主动开关，设置在基板上；
低介电常数保护层，所述低介电常数保护层形成在所述多个主动开关上，所述低介电常数保护层的相对介电常数小于氮化硅的相对介电常数。
其中，所述低介电常数保护层包括介孔氧化硅。
介孔氧化硅的相对介电常数εr＝1.4～2.4，低介电常数保护层采用介孔氧化硅取代5-mask与4-mask工艺TFT器件中的保护层材料SiNx(相对介电常数εr＝7～8)，介孔氧化硅比一般氧化硅(相对介电常数εr＝3.9～4.1)的εr更低，可以提高TFT器件性能，改善信号串扰问题和RC电路延时问题，减小低介电常数保护层的厚度，当然低介电常数保护层也可以采用其他低介电常数的材料，如纳米多孔硅等。
其中，所述介孔氧化硅包括多个彼此连接的空心柱状的子部件，所述子部件切面为六边形，所述子部件中间具有圆形通孔。
子部件通孔大小均匀，子部件切面为六边形，方便多个子部件拼接排列。
其中，所述介孔氧化硅包括多个子单元，所述子单元包括成三行排列的子部件，所述子单元的中间一行包括并排的三个子部件，所述子单元的第一行和第三行分别包括并排的两个子部件，所述第一行和第三行的两个子部件分别设置在中间一行三个子部件的任意两个子部件之间。
子单元具有排列规则有序的子部件，具有较高的比表面积，较好的热稳定性和水热稳定性。
其中，所述基板上设有若干条第一层导线，所述第一层导线上设有绝缘介质层，所述绝缘介质层上对应第一层导线的栅极导线段设有非晶硅层，所述非晶硅层上设有与非晶硅层对应的欧姆接触层，所述欧姆接触层上设有分隔的源极导线段和漏极导线段，所述源极导线段和漏极导线段之间设有沟道，所述沟道穿过欧姆接触层，所述沟道底部为非晶硅层，所述源极导线段和漏极导线段的宽度大于非晶硅层的宽度，所述源极导线段和漏极导线段上设有低介电常数保护层，所述低介电常数保护层上设有像素电极层，所述低介电常数保护层对应漏极导线段设有过孔，所述像素电极层通过过孔与漏极导线段连接。
可以获取更好性能的主动开关(例如薄膜晶体管TFT)。
其中，所述源极导线段超出非晶硅层部分一侧直接连接绝缘介质层另一侧直接连接低介电常数保护层，所述绝缘介质层对应过孔部分与漏极导线段之间连接。
使用5Mask获取的主动开关(例如薄膜晶体管TFT)。
其中，所述基板上设有若干条第一层导线，所述第一层导线上设有绝缘介质层，所述绝缘介质层上对应第一层导线的栅极导线段设有非晶硅层，所述非晶硅层上设有与非晶硅层对应的欧姆接触层，所述欧姆接触层上设有分隔的源极导线段和漏极导线段，所述源极导线段和漏极导线段之间设有沟道，所述沟道穿过欧姆接触层，所述沟道底部为非晶硅层，所述源极导线段和漏极导线段宽度大于非晶硅层的宽度，所述源极导线段和漏极导线段上设有低介电常数保护层，所述低介电常数保护层上设有像素电极层，所述低介电常数保护层对应漏极导线段设有过孔，所述像素电极层通过过孔与漏极导线段连接。
可以获取更好性能的主动开关(例如薄膜晶体管TFT)。
其中，所述源极导线段外侧的低介电常数保护层直接与绝缘介质层连接，所述绝缘介质层对应过孔上方依次设有非晶硅层、欧姆接触层和漏极导线段。
使用4道光刻(Mask)制程获取的主动开关(例如薄膜晶体管TFT)。
根据本发明的另一个方面，本发明还公开了一种显示面板制程，包括步骤：
在基板上设置多个主动开关；
在多个主动开关上形成相对介电常数小于氮化硅的低介电常数保护层。
在主动开关上用低介电常数保护层取代采用材料SiNx(相对介电常数εr＝7～8)的保护层，低介电常数保护层比一般氧化硅(相对介电常数εr＝3.9～4.1)的εr更低，主动开关例如薄膜晶体管TFT器件上的保护层采用低介电常数保护层可以提高TFT器件性能，改善信号串扰问题和RC电路延时问题。
其中，在多个主动开关上形成相对介电常数小于氮化硅的低介电常数保护层包括：
将胶束形成胶束棒；
将胶束棒按六角形排列形成六角形胶束棒；
将六角形胶束棒根据有机分子模板自组装机制形成氧化硅模板中间组；
将氧化硅模板中间组培烧去除模板形成介孔氧化硅；
将介孔氧化硅形成低介电常数保护层。
介孔氧化硅的相对介电常数εr＝1.4～2.4，低介电常数保护层采用介孔氧化硅取代5-mask与4-mask工艺薄膜晶体管TFT器件中的保护层材料SiNx(相对介电常数εr＝7～8)，介孔氧化硅比一般氧化硅(相对介电常数εr＝3.9～4.1)的εr更低，提高TFT器件性能，改善信号串扰问题和RC电路延时问题，减小低介电常数保护层的厚度。
与现有技术相比，本发明的技术效果是：
采用低介电常数保护层取代主动开关上的保护层材料氮化硅(SiNx相对介电常数εr＝7～8)，低介电常数保护层比一般氧化硅(相对介电常数εr＝3.9～4.1)的相对介电常数更低，主动开关上的保护层采用低介电常数保护层可以提高主动开关性能，改善信号串扰问题和RC电路延时问题。
附图说明
所包括的附图用来提供对本申请实施例的进一步的理解，其构成了说明书的一部分，用于例示本申请的实施方式，并与文字描述一起来阐释本申请的原理。显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。在附图中：
图1是本发明实施例一种5Mask倒置错排型TFT器件结构示意图；
图2是本发明实施例一种4Mask倒置错排型TFT器件结构示意图；
图3是本发明实施例一种5Mask倒置错排型TFT器件结构另一示意图；
图4是本发明实施例一种4Mask倒置错排型TFT器件结构另一示意图；
图5是本发明实施例介孔氧化硅示意图；
图6是本发明实施例一种显示面板制程示意图；
图7是本发明实施例一种显示面板制程的另一示意图；
图8是本发明实施例有机分子模板自组装法制备介孔氧化硅工艺示意图；
图9是本发明实施例介电常数测试示意图。
其中：10、基板，21、第一层导线，211、栅极导线段，22、绝缘介质层，23、非晶硅层，24、欧姆接触层，25、源极导线段，26、漏极导线段，27、沟道，28、过孔，30保护层，40、低介电常数保护层，42、子部件，43、子单元，50、像素电极层。
具体实施方式
这里所公开的具体结构和功能细节仅仅是代表性的，并且是用于描述本发明的示例性实施例的目的。但是本发明可以通过许多替换形式来具体实现，并且不应当被解释成仅仅受限于这里所阐述的实施例。
在本发明的描述中，需要理解的是，术语“中心”、“横向”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本发明的描述中，除非另有说明，“多个”的含义是两个或两个以上。另外，术语“包括”及其任何变形，意图在于覆盖不排他的包含。
在本发明的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本发明中的具体含义。
这里所使用的术语仅仅是为了描述具体实施例而不意图限制示例性实施例。除非上下文明确地另有所指，否则这里所使用的单数形式“一个”、“一项”还意图包括复数。还应当理解的是，这里所使用的术语“包括”和/或“包含”规定所陈述的特征、整数、步骤、操作、单元和/或组件的存在，而不排除存在或添加一个或更多其他特征、整数、步骤、操作、单元、组件和/或其组合。
下面结合附图和较佳的实施例对本发明作进一步说明。
下面参考图1至图8描述本发明实施例的显示面板及制程。
如图1所示，在图1的实施例中显示面板包括基板10，设置在所述基板10上的多个主动开关；形成在所述多个主动开关上的保护层30。所述保护层30采用氮化硅。其中，所述基板10上设有若干条第一层导线21，所述第一层导线21上设有绝缘介质层22，所述绝缘介质层22上对应第一层导线21的栅极导线段211设有非晶硅层23，所述非晶硅层23上设有与非晶硅层23对应的欧姆接触层24，所述欧姆接触层24上设有分隔的源极导线段25和漏极导线段26，所述源极导线段25和漏极导线段26之间设有沟道27，所述沟道27穿过欧姆接触层24，所述沟道27底部为非晶硅层23，所述源极导线段25和漏极导线段26的宽度大于非晶硅层23的宽度，所述源极导线段25和漏极导线段26上设有保护层30，所述保护层30上设有像素电极层50，所述保护层30对应漏极导线段26设有过孔28，所述像素电极层50通过过孔28与漏极导线段26连接。其中，所述源极导线段25超出非晶硅层23部分一侧直接连接绝缘介质层22另一侧直接连接保护层30，所述绝缘介质层22对应过孔28部分与漏极导线段26之间连接。使用5Mask获取的主动开关(例如薄膜晶体管TFT)具有较好的性能。
如图2所示，在图2的实施例中显示面板包括基板10，设置在所述基板10上的多个主动开关；形成在所述多个主动开关上的保护层30。所述保护层30采用氮化硅。其中，所述基板10上设有若干条第一层导线21，所述第一层导线21上设有绝缘介质层22，所述绝缘介质层22上对应第一层导线21的栅极导线段211设有非晶硅层23，所述非晶硅层23上设有与非晶硅层23对应的欧姆接触层24，所述欧姆接触层24上设有分隔的源极导线段25和漏极导线段26，所述源极导线段25和漏极导线段26之间设有沟道27，所述沟道27穿过欧姆接触层24，所述沟道27底部为非晶硅层23，所述源极导线段25和漏极导线段26宽度大于非晶硅层23的宽度，所述源极导线段25和漏极导线段26上设有保护层30，所述保护层30上设有像素电极层50，所述保护层30对应漏极导线段26设有过孔28，所述像素电极层50通过过孔28与漏极导线段26连接。其中，所述源极导线段25外侧的保护层30直接与绝缘介质层22连接，所述绝缘介质层22对应过孔28上方依次设有非晶硅层23、欧姆接触层24和漏极导线段26。使用4Mask获取的主动开关(例如薄膜晶体管TFT)具有较好的性能，而且可以节省一步光刻(Mask)工艺。
制备高性能的主动开关(例如薄膜晶体管TFT)是高品质LCD的基础，5-mask和4-mask倒置错排型TFT器件结构如图1和图2所示。薄膜晶体管TFT的保护层通常使用SiNx材料(相对介电常数εr＝7～8)，与栅绝缘层一样。相比于栅绝缘层希望保护层具有相对较小的εr，而SiNx的εr较高，电容大，容易造成信号的串扰、限制膜层厚度进一步减小等问题，不利于大世代面板的发展。
如图3和图5所示，在图3和图5的实施例中显示面板包括基板10，设置在所述基板10上的多个主动开关(例如薄膜晶体管)；形成在所述多个主动开关上的低介电常数保护层40，所述低介电常数保护层40的相对介电常数小于氮化硅的相对介电常数。采用低介电常数保护层40取代主动开关(例如薄膜晶体管)的保护层30材料SiNx(相对介电常数εr＝7～8)，低介电常数保护层40比一般氧化硅(相对介电常数εr＝3.9～4.1)的εr更低，保护层30采用低介电常数保护层40可以提高主动开关(例如薄膜晶体管)性能，改善信号串扰问题和RC电路延时问题。
其中，所述低介电常数保护层40包括介孔氧化硅。介孔氧化硅的相对介电常数εr＝1.4～2.4，低介电常数保护层40采用介孔氧化硅取代5-mask与4-mask工艺TFT器件中的保护层30材料SiNx(相对介电常数εr＝7～8)，介孔氧化硅比一般氧化硅(相对介电常数εr＝3.9～4.1)的εr更低，可以提高TFT器件性能，改善信号串扰问题和RC电路延时问题，减小低介电常数保护层40的厚度，当然低介电常数保护层40也可以采用其他低介电常数的材料，如纳米多孔硅等。
其中，所述介孔氧化硅包括多个彼此连接的空心柱状的子部件42，所述子部件42切面为六边形，所述子部件42中间具有圆形通孔。子部件42通孔大小均匀，子部件42切面为六边形，方便多个子部件42拼接排列。
其中，所述介孔氧化硅包括多个子单元43，所述子单元43包括成三行排列的子部件42，所述子单元43的中间一行包括并排的三个子部件42，所述子单元43的第一行和第三行分别包括并排的两个子部件42，所述第一行和第三行的两个子部件42分别设置在中间一行三个子部件42的任意两个子部件42之间。子单元43具有排列规则有序的子部件42，具有较高的比表面积，较好的热稳定性和水热稳定性。
其中，所述基板10上设有若干条第一层导线21，所述第一层导线21上设有绝缘介质层22，所述绝缘介质层22上对应第一层导线21的栅极导线段211设有非晶硅层23，所述非晶硅层23上设有与非晶硅层23对应的欧姆接触层24，所述欧姆接触层24上设有分隔的源极导线段25和漏极导线段26，所述源极导线段25和漏极导线段26之间设有沟道27，所述沟道27穿过欧姆接触层24，所述沟道27底部为非晶硅层23，所述源极导线段25和漏极导线段26的宽度大于非晶硅层23的宽度，所述源极导线段25和漏极导线段26上设有低介电常数保护层40，所述低介电常数保护层40上设有像素电极层50，所述低介电常数保护层40对应漏极导线段26设有过孔28，所述像素电极层50通过过孔28与漏极导线段26连接。其中，所述源极导线段25超出非晶硅层23部分一侧直接连接绝缘介质层22另一侧直接连接低介电常数保护层40，所述绝缘介质层22对应过孔28部分与漏极导线段26之间连接。使用5Mask获取的主动开关(例如薄膜晶体管TFT)可以获取更好性能。
如图4和图5所示，在图4和图5的实施例中显示面板包括基板10，设置在所述基板10上的多个主动开关；形成在所述多个主动开关上的低介电常数保护层40，所述低介电常数保护层40的相对介电常数小于氮化硅的相对介电常数。采用低介电常数保护层40取代主动开关(例如薄膜晶体管TFT)上的保护层30材料SiNx(相对介电常数εr＝7～8)，低介电常数保护层40比一般氧化硅(相对介电常数εr＝3.9～4.1)的εr更低，主动开关(例如薄膜晶体管TFT)上的保护层30采用低介电常数保护层40可以提高TFT器件性能，改善信号串扰问题和RC电路延时问题。
其中，所述低介电常数保护层40包括介孔氧化硅。介孔氧化硅的相对介电常数εr＝1.4～2.4，低介电常数保护层40采用介孔氧化硅取代5-mask与4-mask工艺TFT器件中的保护层30材料SiNx(相对介电常数εr＝7～8)，介孔氧化硅比一般氧化硅(相对介电常数εr＝3.9～4.1)的εr更低，可以提高TFT器件性能，改善信号串扰问题和RC电路延时问题，减小低介电常数保护层40的厚度，当然低介电常数保护层40也可以采用其他低介电常数的材料，如纳米多孔硅等。
其中，所述介孔氧化硅包括多个彼此连接的空心柱状的子部件42，所述子部件42切面为六边形，所述子部件42中间具有圆形通孔。子部件42通孔大小均匀，子部件42切面为六边形，方便多个子部件42拼接排列。
其中，所述基板10上设有若干条第一层导线21，所述第一层导线21上设有绝缘介质层22，所述绝缘介质层22上对应第一层导线21的栅极导线段211设有非晶硅层23，所述非晶硅层23上设有与非晶硅层23对应的欧姆接触层24，所述欧姆接触层24上设有分隔的源极导线段25和漏极导线段26，所述源极导线段25和漏极导线段26之间设有沟道27，所述沟道27穿过欧姆接触层24，所述沟道27底部为非晶硅层23，所述源极导线段25和漏极导线段26宽度大于非晶硅层23的宽度，所述源极导线段25和漏极导线段26上设有低介电常数保护层40，所述低介电常数保护层40上设有像素电极层50，所述低介电常数保护层40对应漏极导线段26设有过孔28，所述像素电极层50通过过孔28与漏极导线段26连接。
其中，所述源极导线段25外侧的低介电常数保护层40直接与绝缘介质层22连接，所述绝缘介质层22对应过孔28上方依次设有非晶硅层23、欧姆接触层24和漏极导线段26。
获取的主动开关(例如薄膜晶体管TFT)可以获取更好性能，而且可以节省一步Mask工艺，简约时间和成本。
根据本发明的另一个方面，如图6所示，本发明还公开了一种显示面板制程，包括步骤：
在基板上设置多个主动开关；
在多个主动开关上形成相对介电常数小于氮化硅的低介电常数保护层。
在主动开关(例如薄膜晶体管TFT)上用低介电常数保护层取代采用材料SiNx(相对介电常数εr＝7～8)的保护层，低介电常数保护层比一般氧化硅(相对介电常数εr＝3.9～4.1)的εr更低，保护层采用低介电常数保护层可以提高主动开关(例如薄膜晶体管TFT)性能，改善信号串扰问题和RC电路延时问题。
其中，如图7和图8所示，在主动开关(例如薄膜晶体管TFT)上设置相对介电常数小于氮化硅的低介电常数保护层包括：
将胶束形成胶束棒；
将胶束棒按六角形排列形成六角形胶束棒；
将六角形胶束棒根据有机分子模板自组装机制形成氧化硅模板中间组；
将氧化硅模板中间组培烧去除模板形成介孔氧化硅；
将介孔氧化硅形成低介电常数保护层。
介孔氧化硅的相对介电常数εr＝1.4～2.4，低介电常数保护层采用介孔氧化硅取代5-mask与4-mask工艺主动开关(例如薄膜晶体管TFT)上的保护层材料SiNx(相对介电常数εr＝7～8)，介孔氧化硅比一般氧化硅(相对介电常数εr＝3.9～4.1)的εr更低，提高主动开关(例如薄膜晶体管TFT)性能，改善信号串扰问题和RC电路延时问题，减小低介电常数保护层的厚度。
如图9所示，在图9所示的介电常数测试示意图中显示，介孔氧化硅的介电常数较低而且稳定，随着时间的增加变化很小。
在上述实施例中，非晶硅层采用a-Si材料，当然也可以采用其他半导体层材料。
在上述实施例中，所述基板的材料可以选用玻璃、塑料等。
在上述实施例中，显示面板包括液晶面板、等离子面板等，以液晶面板为例，液晶面板包括阵列基板和彩膜基板(CF)，所述阵列基板与彩膜基板相对设置，所述阵列基板与彩膜基板之间设有液晶和间隔单元(photo spacer，PS)，所述阵列基板上设有薄膜晶体管(TFT)，彩膜基板上设有彩色滤光层。
在上述实施例中，彩膜基板可包括TFT阵列，彩膜及TFT阵列可形成于同一基板上，阵列基本可包括彩色滤光层。
在上述实施例中，本发明的显示面板可为曲面型面板。
以上内容是结合具体的优选实施方式对本发明所作的进一步详细说明，不能认定本发明的具体实施只局限于这些说明。对于本发明所属技术领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本发明的保护范围。

Claims (8)

1.一种显示面板，其特征在于，包括：
基板；
多个主动开关，设置在基板上；
低介电常数保护层，所述低介电常数保护层形成在所述多个主动开关上，所述低介电常数保护层的相对介电常数小于氮化硅的相对介电常数；
所述低介电常数保护层包括介孔氧化硅；
所述介孔氧化硅的相对介电常数为1.4～2.4；
所述介孔氧化硅包括多个彼此连接的空心柱状的子部件，所述子部件切面为六边形，所述子部件中间具有圆形通孔。
2.如权利要求1所述的一种显示面板，其特征在于，所述介孔氧化硅包括多个子单元，所述子单元包括成三行排列的子部件，所述子单元的中间一行包括并排的三个子部件，所述子单元的第一行和第三行分别包括并排的两个子部件，所述第一行和第三行的两个子部件分别设置在中间一行三个子部件的任意两个子部件之间。
3.如权利要求1所述的一种显示面板，其特征在于，所述基板上设有若干条第一层导线，所述第一层导线上设有绝缘介质层，所述绝缘介质层上对应第一层导线的栅极导线段设有非晶硅层，所述非晶硅层上设有与非晶硅层对应的欧姆接触层，所述欧姆接触层上设有分隔的源极导线段和漏极导线段，所述源极导线段和漏极导线段之间设有沟道，所述沟道穿过欧姆接触层，所述沟道底部为非晶硅层，所述源极导线段和漏极导线段的宽度大于非晶硅层的宽度，所述源极导线段和漏极导线段上设有低介电常数保护层，所述低介电常数保护层上设有像素电极层，所述低介电常数保护层对应漏极导线段设有过孔，所述像素电极层通过过孔与漏极导线段连接。
4.如权利要求3所述的一种显示面板，其特征在于，所述源极导线段超出非晶硅层部分一侧直接连接绝缘介质层另一侧直接连接低介电常数保护层，所述绝缘介质层对应过孔部分与漏极导线段之间连接。
5.如权利要求1所述的一种显示面板，其特征在于，所述基板上设有若干条第一层导线，所述第一层导线上设有绝缘介质层，所述绝缘介质层上对应第一层导线的栅极导线段设有非晶硅层，所述非晶硅层上设有与非晶硅层对应的欧姆接触层，所述欧姆接触层上设有分隔的源极导线段和漏极导线段，所述源极导线段和漏极导线段之间设有沟道，所述沟道穿过欧姆接触层，所述沟道底部为非晶硅层，所述源极导线段和漏极导线段宽度等于非晶硅层的宽度，所述源极导线段和漏极导线段上设有低介电常数保护层，所述低介电常数保护层上设有像素电极层，所述低介电常数保护层对应漏极导线段设有过孔，所述像素电极层通过过孔与漏极导线段连接。
6.如权利要求5所述的一种显示面板，其特征在于，所述源极导线段外侧的低介电常数保护层直接与绝缘介质层连接，所述绝缘介质层对应过孔上方依次设有非晶硅层、欧姆接触层和漏极导线段。
7.一种显示面板制程，其特征在于，包括步骤：
在基板上设置多个主动开关；
在多个主动开关上形成相对介电常数小于氮化硅的低介电常数保护层；
其中，所述低介电常数保护层包括介孔氧化硅；所述介孔氧化硅的相对介电常数为1.4～2.4，所述介孔氧化硅包括多个彼此连接的空心柱状的子部件，所述子部件切面为六边形，所述子部件中间具有圆形通孔。
8.如权利要求7所述的一种显示面板制程，其特征在于，在多个主动开关上形成相对介电常数小于氮化硅的低介电常数保护层包括：
将胶束形成胶束棒；
将胶束棒按六角形排列形成六角形胶束棒；
将六角形胶束棒根据有机分子模板自组装机制形成氧化硅模板中间组；
将氧化硅模板中间组培烧去除模板形成介孔氧化硅；
将介孔氧化硅形成低介电常数保护层。
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Publication number Priority date Publication date Assignee Title
CN108022976B (zh) * 2017-11-03 2020-12-25 惠科股份有限公司 晶体管和晶体管制造方法
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1646726A (zh) * 2002-05-17 2005-07-27 三星电子株式会社 低电介绝缘层的汽相淀积方法、利用该低电介绝缘层的薄膜晶体管及其制造方法
CN1783357A (zh) * 2004-11-30 2006-06-07 财团法人工业技术研究院 改质介孔二氧化硅粉体、生成低介电环氧树脂与低介电聚亚酰胺树脂的前驱溶液、低介电常数基板及其形成方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6479391B2 (en) * 2000-12-22 2002-11-12 Intel Corporation Method for making a dual damascene interconnect using a multilayer hard mask
US7473933B2 (en) * 2004-10-29 2009-01-06 Ledengin, Inc. (Cayman) High power LED package with universal bonding pads and interconnect arrangement
TWI418890B (zh) * 2010-03-04 2013-12-11 Au Optronics Corp 觸控反射式顯示面及其製造方法
CN102280408A (zh) * 2011-06-28 2011-12-14 深圳市华星光电技术有限公司 薄膜晶体管矩阵基板及显示面板的制造方法
CN103121856B (zh) * 2011-07-25 2014-08-13 重庆文理学院 一种介孔氧化硅薄膜材料的制备方法
JP2015036797A (ja) * 2013-08-15 2015-02-23 ソニー株式会社 表示装置および電子機器

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1646726A (zh) * 2002-05-17 2005-07-27 三星电子株式会社 低电介绝缘层的汽相淀积方法、利用该低电介绝缘层的薄膜晶体管及其制造方法
CN1783357A (zh) * 2004-11-30 2006-06-07 财团法人工业技术研究院 改质介孔二氧化硅粉体、生成低介电环氧树脂与低介电聚亚酰胺树脂的前驱溶液、低介电常数基板及其形成方法

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