WO2018119964A1 - Goa电路 - Google Patents

Goa电路 Download PDF

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Publication number
WO2018119964A1
WO2018119964A1 PCT/CN2016/113319 CN2016113319W WO2018119964A1 WO 2018119964 A1 WO2018119964 A1 WO 2018119964A1 CN 2016113319 W CN2016113319 W CN 2016113319W WO 2018119964 A1 WO2018119964 A1 WO 2018119964A1
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Prior art keywords
goa circuit
node
thin film
film transistor
gate
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Ceased
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PCT/CN2016/113319
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English (en)
French (fr)
Inventor
李亚锋
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to US15/506,241 priority Critical patent/US10249243B2/en
Publication of WO2018119964A1 publication Critical patent/WO2018119964A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/067—Special waveforms for scanning, where no circuit details of the gate driver are given
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0219—Reducing feedthrough effects in active matrix panels, i.e. voltage changes on the scan electrode influencing the pixel voltage due to capacitive coupling

Definitions

  • the present invention relates to the field of liquid crystal displays, and more particularly to a GOA circuit.
  • the Gate Driver On Array (GOA) technology utilizes an existing thin film transistor liquid crystal display array (Array) process to fabricate a gate scan driving signal circuit on an array substrate to realize gate-by-row operation.
  • Array thin film transistor liquid crystal display array
  • the existing GOA circuit includes a plurality of cascaded GOA circuit units, wherein the nth stage GOA circuit unit that outputs the nth horizontal scan signal includes: a thin film transistor T1 whose gate is connected to a signal of the n-2th stage GOA circuit unit The output point Gn-2, the source and the drain are respectively connected to the node Hn and the input forward scan control signal U2D; the thin film transistor T2 has a gate connected to the node Qn, and the source and the drain are respectively connected to the signal of the nth stage GOA circuit unit The output point Gn and the input clock signal CKV2; the thin film transistor T3 whose gate is connected to the signal output point Gn+2 of the n+2th GOA circuit unit, and the source and the drain are respectively connected to the node Hn and the input reverse scan control signal D2U
  • the thin film transistor T4 has a gate connection node Pn, a source and a drain connected to
  • the node Qn is a point for controlling the gate drive signal output; the node Pn is a stable point for maintaining the low level of the Qn point and the Gn point.
  • 1 shows the structure of a GOA circuit unit with an nth-level GOA circuit unit corresponding to the Gn-level output, and the adjacent n+1-th GOA circuit unit structure corresponding to the Gn+1-level output is shown in FIG. The same, only different clock signals are used in operation, and the structure of the n+1th GOA circuit unit will not be described here.
  • FIG. 2 it is a schematic diagram of the forward scanning timing of the GOA circuit of FIG. 1.
  • FIG. 1 the specific working process (forward scanning) of the circuit is introduced as follows:
  • Phase 1 pre-charge: Gn-2 and U2D are simultaneously high, T1 is on, and Hn is pre-charged Electricity.
  • T5 is in an on state and the Qn point is precharged.
  • T7 is in the on state, and the Pn point is pulled down;
  • Gn outputs a high level: in phase 1, the Qn point is precharged, C1 has a certain holding effect on the charge, T2 is in an on state, and a high level of CKV2 is output to the Gn terminal;
  • stage 3 Gn outputs a low level: C1 has a holding effect on the high level of the Qn point, and at this time, the low level of CKV2 pulls the Gn point low;
  • Phase 5 Qn point and Gn point low level maintenance phase: When Qn point becomes low level, T7 is in the off state. When CKV4 jumps to high level, T8 turns on, Pn point is charged, then T4 and T6 Both are in the on state, which can ensure the stability of the low level of the Qn point and the Gn point, and the C2 has a certain holding effect on the high level of the Pn point.
  • the clock signals used are CKV1 and CKV3, and the working process can be obtained in conjunction with FIG.
  • FIG. 3 is a schematic diagram of the reverse scan timing of the GOA circuit of FIG. 1, the specific working process (reverse scan) of the circuit is described below with reference to FIG.
  • Phase 1 pre-charge: Gn+2 and D2U are simultaneously high, T3 is on, and Hn is pre-charged.
  • T3 is on
  • Hn is pre-charged.
  • T5 is in an on state
  • the Qn point is precharged.
  • T7 is in the on state, and the Pn point is pulled down;
  • Gn outputs a high level: in phase 1, the Qn point is precharged, C1 has a certain holding effect on the charge, T2 is in an on state, and a high level of CKV2 is output to the Gn terminal;
  • stage 3 Gn outputs a low level: C1 has a holding effect on the high level of the Qn point, and at this time, the low level of CKV2 pulls the Gn point low;
  • Phase 5 Qn point and Gn point low level maintenance phase: When Qn point becomes low level, T7 is in the off state. When CKV4 jumps to high level, T8 turns on, Pn point is charged, then T4 and T6 Both are in the on state, which can ensure the stability of the low level of the Qn point and the Gn point, and the C2 has a certain holding effect on the high level of the Pn point.
  • the clock signals used are CKV1 and CKV3, and the working process can be obtained in conjunction with FIG.
  • the high and low levels of the output of the existing GOA circuit Gn are VGH and VGL, respectively, and are two-order driving.
  • the corresponding feedthrough voltage of the gate driving method is large, and thus
  • the optimized common voltage (Vcom) corresponding to different areas of the panel is inconsistent, that is to say, the two-stage driving is likely to cause poor uniformity of the Vcom of the panel, which affects the quality of the display.
  • MLG multi-level gate
  • the present invention provides a GOA circuit comprising a plurality of cascaded GOA circuit units, wherein n is a natural number greater than 0, and the nth-level GOA circuit unit comprises:
  • a first thin film transistor having a source and a drain connected to the first node and an input forward scan control signal, respectively.
  • the gate is connected to the signal output of the n-2th GOA circuit unit. Point, otherwise its gate inputs the first start signal;
  • a third thin film transistor having a source and a drain connected to the first node and an input reverse scan control signal, respectively.
  • the gate is connected to the signal output of the n+2th GOA circuit unit. Point, otherwise its gate inputs a second start signal;
  • a seventh thin film transistor having a gate connected to the first node, a source and a drain connected to the fourth node and a constant voltage low potential;
  • a sixth thin film transistor having a gate connected to the fourth node, the source and the drain being respectively connected to the first node and a constant voltage low potential;
  • a fifth thin film transistor having a gate connected to a first constant voltage high potential, and a source and a drain connected to the first node and the second node, respectively;
  • An eighth thin film transistor having a gate inputting a first clock signal, a source and a drain respectively connected to the fourth node and a first constant voltage high potential;
  • a ninth thin film transistor having a gate inputting a first control signal, a source and a drain respectively connected to the third node and inputting the second clock signal;
  • a tenth thin film transistor having a second control signal input to the gate thereof, the source and the drain being respectively connected to the third node and the second constant voltage high potential;
  • a second thin film transistor having a gate connected to the second node, the source and the drain being respectively connected to the signal output point of the nth stage GOA circuit unit and the third node;
  • a fourth thin film transistor having a gate connected to the fourth node, wherein the source and the drain are respectively connected to the signal output point of the nth stage GOA circuit unit and the constant voltage low potential;
  • the second control signal When the first control signal is high, the second control signal is low; when the first control signal When the number is high, the second control signal is low.
  • the voltage of the second constant voltage high potential is lower than the voltage of the first constant voltage high potential.
  • the off-angle voltage is adjusted by adjusting the voltage corresponding to the second constant voltage high potential.
  • the off-angle time is adjusted by adjusting a time relationship corresponding to the first control signal and the second control signal.
  • the first clock signal and the second clock signal are rectangular waves with a duty ratio of 0.25, and the phases of the first clock signal and the second clock signal are different by a quarter cycle.
  • the gate of the first thin film transistor inputs a high level signal as the first start signal.
  • the gate of the third thin film transistor inputs a high level signal as the second start signal.
  • the present invention also provides a GOA circuit comprising a plurality of cascaded GOA circuit units, wherein n is a natural number greater than 0, and the nth-level GOA circuit unit comprises:
  • a first thin film transistor having a source and a drain connected to the first node and an input forward scan control signal, respectively.
  • the gate is connected to the signal output of the n-2th GOA circuit unit. Point, otherwise its gate inputs the first start signal;
  • a third thin film transistor having a source and a drain connected to the first node and an input reverse scan control signal, respectively.
  • the gate is connected to the signal output of the n+2th GOA circuit unit. Point, otherwise its gate inputs a second start signal;
  • a seventh thin film transistor having a gate connected to the first node, a source and a drain connected to the fourth node and a constant voltage low potential;
  • a sixth thin film transistor having a gate connected to the fourth node, the source and the drain being respectively connected to the first node and a constant voltage low potential;
  • a fifth thin film transistor having a gate connected to a first constant voltage high potential, and a source and a drain connected to the first node and the second node, respectively;
  • An eighth thin film transistor having a gate inputting a first clock signal, a source and a drain respectively connected to the fourth node and a first constant voltage high potential;
  • a ninth thin film transistor having a gate inputting a first control signal, a source and a drain respectively connected to the third node and inputting the second clock signal;
  • a tenth thin film transistor having a second control signal input to the gate thereof, the source and the drain being respectively connected to the third node and the second constant voltage high potential;
  • a second thin film transistor having a gate connected to the second node and a source and a drain connected to the nth stage a signal output point of the GOA circuit unit and a third node;
  • a fourth thin film transistor having a gate connected to the fourth node, wherein the source and the drain are respectively connected to the signal output point of the nth stage GOA circuit unit and the constant voltage low potential;
  • the second control signal when the first control signal is high level, the second control signal is low level; when the first control signal is high level, the second control signal is low level;
  • the voltage of the second constant voltage high potential is lower than the voltage of the first constant voltage high potential
  • the first clock signal and the second clock signal are rectangular waves with a duty ratio of 0.25, and the phases of the first clock signal and the second clock signal are different by a quarter cycle.
  • the present invention proposes a new GOA circuit, which has an MLG function, can effectively reduce feedthrough, improve in-plane Vcom uniformity, and improve picture display quality.
  • 1 is a schematic diagram of a conventional GOA circuit
  • FIG. 2 is a schematic diagram of a forward scan timing of the GOA circuit of FIG. 1;
  • FIG. 3 is a schematic diagram of a reverse scan timing of the GOA circuit of FIG. 1;
  • FIG. 4 is a schematic diagram of a GOA circuit of the present invention.
  • FIG. 5 is a schematic diagram of a forward scan timing of the GOA circuit of FIG. 4;
  • FIG. 6 is a schematic diagram showing the reverse scan timing of the GOA circuit of FIG. 4.
  • the GOA circuit of the present invention comprises a plurality of cascaded GOA circuit units, wherein n is a natural number greater than 0, and the nth stage GOA circuit unit outputting the nth horizontal scanning signal comprises: a thin film transistor T1, when the nth level is non- When the first end is two stages, its gate is connected to the signal output point Gn-2 of the n-2th GOA circuit unit, the source and the drain are respectively connected to the node Hn and the input forward scanning control signal U2D; the thin film transistor T2 is gated The pole connection node Qn, the source and the drain are respectively connected to the signal output point Gn and the node Mn of the nth stage GOA circuit unit; and the thin film transistor T3, when the nth stage is not the end two stages, the gate is connected to the n+2 The signal output point Gn+2 of the stage GOA circuit unit, the source and the drain are respectively connected to the n+2 The signal output point Gn+2 of the stage GOA circuit unit, the source
  • FIG. 4 shows the structure of the GOA circuit unit of the present invention by taking the nth-level GOA circuit unit corresponding to the Gn-level output as an example. Those skilled in the art can understand that the adjacent n+1th level corresponding to the Gn+1-level output.
  • the structure of the GOA circuit unit is the same as that shown in FIG. 4, and only different clock signals are used in operation, and the structure of the n+1th stage GOA circuit unit will not be described herein.
  • FIG. 5 it is a schematic diagram of the forward scan timing of the GOA circuit of FIG.
  • the specific working process of the circuit is as follows:
  • Phase 1 pre-charge: Gn-2 and U2D are simultaneously high, T1 is on, and Hn is pre-charged.
  • T1 is on
  • Hn is pre-charged.
  • T5 is in an on state
  • the Qn point is precharged.
  • T7 is in the on state, and the Pn point is pulled down;
  • Gn outputs a high level: in phase 1, the Qn point is precharged, C1 has a certain holding effect on the charge, and T2 is in an on state: when CKV2 and Select1 are simultaneously at a high level, the high voltage corresponding to CKV2 The output is flat to the Mn point, and at this time, T2 is in the on state, so the high level of the Mn point is output to the Gn point; when the Select2 is high level, the high level corresponding to Vgh1 is output to the Mn point, and at this time, the T2 is at In the on state, the high level corresponding to Mn is again output to the Gn point, and Vgh1 ⁇ VGH, so that the Gn point output realizes the MLG function.
  • the magnitude of the aberying voltage that is, the voltage at which the Gn point is outputted from the high level VGH
  • the voltage corresponding to Vgh1 can be realized by adjusting the voltage corresponding to Vgh1; and the length of the erasing time, that is, the Gn point output is high.
  • the time VGH is reduced to the time of outputting Vgh1, which can be achieved by adjusting the time relationship between Select1 and Select2.
  • Gn outputs a low level: C1 has a holding effect on the high level of the Qn point, and at this time, Select1 is a high level, and a low level of CKV2 pulls the Gn point low;
  • Phase 5 Qn point and Gn point low level maintenance phase: When Qn point becomes low level, T7 is in the off state. When CKV4 jumps to high level, T8 turns on, Pn point is charged, then T4 and T6 Both are in the on state, which can ensure the stability of the low level of the Qn point and the Gn point, and the C2 has a certain holding effect on the high level of the Pn point.
  • the gate of the thin film transistor T1 needs to input a high level signal as a start signal.
  • the input signal can be used instead of the missing signal input.
  • the n+1th GOA circuit unit corresponding to the Gn+1 level output, that is, the Gn+1 stage, the clock signals used in the forward scanning are CKV1 and CKV3, and the working process can also be obtained in conjunction with FIG.
  • FIG. 6 is a schematic diagram of the reverse scan timing of the GOA circuit of FIG.
  • Reverse scan the specific working process of the circuit (reverse scan) is introduced as follows:
  • Phase 1 pre-charge: Gn+2 and D2U are simultaneously high, T3 is on, and Hn is pre-charged.
  • T3 is on
  • Hn is pre-charged.
  • T5 is in an on state
  • the Qn point is precharged.
  • T7 is in the on state, and the Pn point is pulled down;
  • Gn outputs a high level: in phase 1, the Qn point is precharged, C1 has a certain holding effect on the charge, and T2 is in an on state: when CKV2 and Select1 are simultaneously at a high level, the high voltage corresponding to CKV2 The output is flat to the Mn point, and at this time, T2 is in the on state, so the high level of the Mn point is output to the Gn point; when the Select2 is high level, the high level corresponding to Vgh1 is output to the Mn point, and at this time, the T2 is at In the on state, the high level corresponding to Mn is again output to the Gn point, and Vgh1 ⁇ VGH, so that the Gn point output realizes the MLG function.
  • the elimination voltage can be realized by adjusting the voltage corresponding to Vgh1, and the elimination time can be realized by adjusting the time relationship between Select1 and Select2.
  • Gn outputs a low level: C1 has a holding effect on the high level of the Qn point, and at this time, Select1 is a low level of CKV2, which lowers the Gn point;
  • Qn point and Gn point low level maintenance phase When Qn point becomes low level, T7 is in the off state. When CKV4 jumps to high level, T8 turns on, Pn point is charged, then T4 and T6 All are in the on state, which can ensure the stability of the low level of Qn point and Gn point, and C2 It has a certain holding effect on the high level of the Pn point.
  • the thin film transistor T3 needs to input a high level signal as an enable signal.
  • the input signal can be used instead of the missing signal input.
  • the n+1th GOA circuit unit corresponding to the Gn+1 stage output, that is, the Gn+1 stage, the clock signals used in the reverse scan are CKV1 and CKV3, and the working process can also be obtained in conjunction with FIG.
  • the clock signals CKV1 to 4 are rectangular waves having a duty ratio of 0.25, and the phases of the clock signal CKV4 and the clock signal CKV2 are different by a quarter cycle, and the phases of the clock signal CKV3 and the clock signal CKV1 are different. One quarter cycle.
  • the present invention introduces two control signals, Select1, Select2, based on the existing GOA circuit.
  • Select1 When the Qn point is bootstrapped to a high level:
  • Select2 When Select2 is high, the high level corresponding to Vgh1 is output to the Gn point, and Vgh1 corresponds to The high level is less than VGH, that is, Vgh1 ⁇ VGH.
  • Vgh1 Vgh1 ⁇ VGH.
  • the Gn point output implements the 3rd order MLG function. It can effectively reduce feedthrough, improve in-plane Vcom uniformity, and improve the quality of picture display.
  • the elimination voltage can be realized by adjusting the voltage corresponding to Vgh1, and the elimination time can be realized by adjusting the time relationship between Select1 and Select2.
  • the known and potential technology/product application fields of the GOA circuit of the present invention and their application modes are as follows: 1. A liquid crystal display (Gate) driving circuit integrated on an array substrate; 2. A grid applied to a mobile phone, a display, and a television Extreme drive field; 3, can cover the advanced technology of LCD and OLED industry; 4, the stability of this circuit is suitable for high-resolution panel design.
  • Gate liquid crystal display
  • the present invention proposes a new GOA circuit, which has an MLG function, can effectively reduce feedthrough, improve in-plane Vcom uniformity, and improve picture display quality.

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Abstract

公开了一种GOA电路，该GOA电路包括级联的多个GOA电路单元，其中，设n为大于0的自然数，第n级GOA电路单元包括：第一薄膜晶体管（TI），第二薄膜晶体管（T2），第三薄膜晶体管（T3），第四薄膜晶体管（T4），第五薄膜晶体管（TS），第六薄膜晶体管（T6），第七薄膜晶体管（T7），第八薄膜晶体管（TS），第九薄膜晶体管（Tg），第十薄膜晶体管（T10），第一电容（CI）及第二电容（C2），还在现有的GOA电路的基础上引入两个控制信号（Select1、Select2）。该GOA电路具有MLG功能，可以有效的降低馈通，改善面板内Vcom均一性，提高画面显示的品质。

Description

GOA电路 技术领域
本发明涉及液晶显示器领域，尤其涉及一种GOA电路。
背景技术
阵列基板行驱动(Gate Driver On Array，简称GOA)技术是利用现有薄膜晶体管液晶显示器阵列(Array)制程将栅极(Gate)行扫描驱动信号电路制作在阵列基板上，实现对栅极逐行扫描的驱动方式的一项技术。
参见图1，其为现有的GOA电路示意图。现有的GOA电路包括级联的多个GOA电路单元，其中输出第n级水平扫描信号的第n级GOA电路单元包括：薄膜晶体管T1，其栅极连接第n-2级GOA电路单元的信号输出点Gn-2，源极和漏极分别连接节点Hn和输入正向扫描控制信号U2D；薄膜晶体管T2，其栅极连接节点Qn，源极和漏极分别连接第n级GOA电路单元的信号输出点Gn和输入时钟信号CKV2；薄膜晶体管T3，其栅极连接第n+2级GOA电路单元的信号输出点Gn+2，源极和漏极分别连接节点Hn和输入反向扫描控制信号D2U；薄膜晶体管T4，其栅极连接节点Pn，源极和漏极分别连接信号输出点Gn和恒压低电位VGL；薄膜晶体管T5，其栅极连接恒压高电位VGH，源极和漏极分别连接节点Hn和节点Qn；薄膜晶体管T6，其栅极连接节点Pn，源极和漏极分别连接节点Hn和恒压低电位VGL；薄膜晶体管T7，其栅极连接节点Hn，源极和漏极分别连接节点Pn和恒压低电位VGL；薄膜晶体管T8，其栅极输入时钟信号CKV4，源极和漏极分别连接节点Pn和恒压高电位VGH；电容C1，其两端分别连接节点Qn和信号输出点Gn；电容C2，其两端分别连接节点Pn和恒压低电位VGL。节点Qn为用于控制栅极驱动信号输出的点；节点Pn为用于维持Qn点及Gn点低电平的稳定点。图1以对应于Gn级输出的第n级GOA电路单元为例绘示GOA电路单元的结构，相邻的对应于Gn+1级输出的第n+1级GOA电路单元结构与图1所示相同，仅是在工作时采用不同的时钟信号，在此不再赘述第n+1级GOA电路单元的结构。
参见图2，其为图1的GOA电路正向扫描时序示意图，现结合图1，对电路的具体工作过程(正向扫描)介绍如下：
以Gn级输出为例；正向扫描时：U2D为高电平，D2U为低电平；
阶段1，预充电：Gn-2与U2D同时为高电平，T1导通，Hn点被预充 电。当Hn点为高电平时，T5处于导通状态，Qn点被预充电。当Hn点为高电平时，T7处于导通状态，Pn点被拉低；
阶段2，Gn输出高电平：在阶段1中，Qn点被预充电，C1对电荷具有一定的保持作用，T2处于导通状态，CKV2的高电平输出到Gn端；
阶段3，Gn输出低电平：C1对Qn点的高电平具有保持作用，而此时CKV2的低电平将Gn点拉低；
阶段4，Qn点拉低到VGL：当Gn+2为高电平，此时D2U为低电平，T3处于导通的状态，那么Qn点被拉低到VGL；
阶段5，Qn点及Gn点低电平维持阶段：当Qn点变为低电平后，T7处于截止状态，当CKV4跳变为高电平时T8导通，Pn点被充电，那么T4和T6均处于导通的状态，可以保证Qn点及Gn点低电平的稳定，同时C2对Pn点的高电平具有一定的保持作用。
对于对应于Gn+1级输出的第n+1级GOA电路单元，所使用的时钟信号为CKV1和CKV3，工作过程可结合图2得出。
参见图3，其为图1的GOA电路反向扫描时序示意图，现结合图1，对电路的具体工作过程(反向扫描)介绍如下：
以Gn级输出为例；反向扫描时：D2U为高电平，U2D为低电平；
阶段1，预充电：Gn+2与D2U同时为高电平，T3导通，Hn点被预充电。当Hn点为高电平时，T5处于导通状态，Qn点被预充电。当Hn点为高电平时，T7处于导通状态，Pn点被拉低；
阶段2，Gn输出高电平：在阶段1中，Qn点被预充电，C1对电荷具有一定的保持作用，T2处于导通状态，CKV2的高电平输出到Gn端；
阶段3，Gn输出低电平：C1对Qn点的高电平具有保持作用，而此时CKV2的低电平将Gn点拉低；
阶段4，Qn点拉低到VGL：当Gn-2为高电平，此时U2D为低电平，T1处于导通的状态，那么Qn点被拉低到VGL；
阶段5，Qn点及Gn点低电平维持阶段：当Qn点变为低电平后，T7处于截止状态，当CKV4跳变为高电平时T8导通，Pn点被充电，那么T4和T6均处于导通的状态，可以保证Qn点及Gn点低电平的稳定，同时C2对Pn点的高电平具有一定的保持作用。
对于对应于Gn+1级输出的第n+1级GOA电路单元，所使用的时钟信号为CKV1和CKV3，工作过程可结合图3得出。
现有的GOA电路Gn的输出的高低电平分别为VGH和VGL且为两阶驱动，这种栅极驱动方式的对应的馈通(Feed Through)电压较大，进而造 成面板不同区域对应的最佳化公共电压(Vcom)不一致，也就是说两阶驱动容易造成面板的Vcom的均一性较差，影响显示的品质。
发明内容
本发明的目的在于提供一种新的GOA电路，该电路可以实现多级栅极(MLG)功能。
为实现上述目的，本发明提供了一种GOA电路，包括级联的多个GOA电路单元，其中，设n为大于0的自然数，第n级GOA电路单元包括：
第一薄膜晶体管，其源极和漏极分别连接第一节点和输入正向扫描控制信号，当第n级非为首端两级时，其栅极连接第n-2级GOA电路单元的信号输出点，否则其栅极输入第一启动信号；
第三薄膜晶体管，其源极和漏极分别连接第一节点和输入反向扫描控制信号，当第n级非为末端两级时，其栅极连接第n+2级GOA电路单元的信号输出点，否则其栅极输入第二启动信号；
第七薄膜晶体管，其栅极连接第一节点，源极和漏极分别连接第四节点和恒压低电位；
第六薄膜晶体管，其栅极连接第四节点，源极和漏极分别连接第一节点和恒压低电位；
第五薄膜晶体管，其栅极连接第一恒压高电位，源极和漏极分别连接第一节点和第二节点；
第八薄膜晶体管，其栅极输入第一时钟信号，源极和漏极分别连接第四节点和第一恒压高电位；
第九薄膜晶体管，其栅极输入第一控制信号，源极和漏极分别连接第三节点和输入第二时钟信号；
第十薄膜晶体管，其栅极输入第二控制信号，源极和漏极分别连接第三节点和第二恒压高电位；
第二薄膜晶体管，其栅极连接第二节点，源极和漏极分别连接第n级GOA电路单元的信号输出点和第三节点；
第一电容，其两端分别连接第二节点和第n级GOA电路单元的信号输出点；
第四薄膜晶体管，其栅极连接第四节点，源极和漏极分别连接第n级GOA电路单元的信号输出点和恒压低电位；
第二电容，其两端分别连接第四节点和恒压低电位；
当第一控制信号为高电平时，第二控制信号为低电平；当第一控制信 号为高电平时，第二控制信号为低电平。
其中，该第二恒压高电位的电压小于第一恒压高电位的电压。
其中，通过调整该第二恒压高电位所对应的电压来调整消角电压。
其中，通过调整该第一控制信号与第二控制信号所对应的时间关系来调整消角时间。
其中，该第一时钟信号和第二时钟信号为占空比为0.25的矩形波，该第一时钟信号和第二时钟信号的相位相差四分之一周期。
其中，对于首端两级GOA电路单元，正向扫描开始时，该第一薄膜晶体管的栅极输入高电平信号作为该第一启动信号。
其中，对于末端两级GOA电路单元，反向扫描开始时，该第三薄膜晶体管的栅极输入高电平信号作为该第二启动信号。
其中，其为LTPS面板的GOA电路。
其中，其为OLED面板的GOA电路。
本发明还提供一种GOA电路，包括级联的多个GOA电路单元，其中，设n为大于0的自然数，第n级GOA电路单元包括：
第一薄膜晶体管，其源极和漏极分别连接第一节点和输入正向扫描控制信号，当第n级非为首端两级时，其栅极连接第n-2级GOA电路单元的信号输出点，否则其栅极输入第一启动信号；
第三薄膜晶体管，其源极和漏极分别连接第一节点和输入反向扫描控制信号，当第n级非为末端两级时，其栅极连接第n+2级GOA电路单元的信号输出点，否则其栅极输入第二启动信号；
第七薄膜晶体管，其栅极连接第一节点，源极和漏极分别连接第四节点和恒压低电位；
第六薄膜晶体管，其栅极连接第四节点，源极和漏极分别连接第一节点和恒压低电位；
第五薄膜晶体管，其栅极连接第一恒压高电位，源极和漏极分别连接第一节点和第二节点；
第八薄膜晶体管，其栅极输入第一时钟信号，源极和漏极分别连接第四节点和第一恒压高电位；
第九薄膜晶体管，其栅极输入第一控制信号，源极和漏极分别连接第三节点和输入第二时钟信号；
第十薄膜晶体管，其栅极输入第二控制信号，源极和漏极分别连接第三节点和第二恒压高电位；
第二薄膜晶体管，其栅极连接第二节点，源极和漏极分别连接第n级 GOA电路单元的信号输出点和第三节点；
第一电容，其两端分别连接第二节点和第n级GOA电路单元的信号输出点；
第四薄膜晶体管，其栅极连接第四节点，源极和漏极分别连接第n级GOA电路单元的信号输出点和恒压低电位；
第二电容，其两端分别连接第四节点和恒压低电位；
工作中，当第一控制信号为高电平时，第二控制信号为低电平；当第一控制信号为高电平时，第二控制信号为低电平；
其中，该第二恒压高电位的电压小于第一恒压高电位的电压；
其中，该第一时钟信号和第二时钟信号为占空比为0.25的矩形波，该第一时钟信号和第二时钟信号的相位相差四分之一周期。
综上，本发明提出了一种新的GOA电路，该电路具有MLG功能，可以有效的降低馈通，改善面内Vcom均一性，提高画面显示的品质。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其他有益效果显而易见。
附图中，
图1为现有的GOA电路示意图；
图2为图1的GOA电路正向扫描时序示意图；
图3为图1的GOA电路反向扫描时序示意图；
图4为本发明的GOA电路示意图；
图5为图4的GOA电路正向扫描时序示意图；
图6为图4的GOA电路反向扫描时序示意图。
具体实施方式
参见图4，其为本发明的GOA电路示意图。本发明的GOA电路包括级联的多个GOA电路单元，其中，设n为大于0的自然数，输出第n级水平扫描信号的第n级GOA电路单元包括：薄膜晶体管T1，当第n级非为首端两级时，其栅极连接第n-2级GOA电路单元的信号输出点Gn-2，源极和漏极分别连接节点Hn和输入正向扫描控制信号U2D；薄膜晶体管T2，其栅极连接节点Qn，源极和漏极分别连接第n级GOA电路单元的信号输出点Gn和节点Mn；薄膜晶体管T3，当第n级非为末端两级时，其栅极连接第n+2级GOA电路单元的信号输出点Gn+2，源极和漏极分别连接节点 Hn和输入反向扫描控制信号D2U；薄膜晶体管T4，其栅极连接节点Pn，源极和漏极分别连接信号输出点Gn和恒压低电位VGL；薄膜晶体管T5，其栅极连接恒压高电位VGH，源极和漏极分别连接节点Hn和节点Qn；薄膜晶体管T6，其栅极连接节点Pn，源极和漏极分别连接节点Hn和恒压低电位VGL；薄膜晶体管T7，其栅极连接节点Hn，源极和漏极分别连接节点Pn和恒压低电位VGL；薄膜晶体管T8，其栅极输入时钟信号CKV4，源极和漏极分别连接节点Pn和恒压高电位VGH；薄膜晶体管T9，其栅极输入控制信号Select1，源极和漏极分别连接节点Mn和输入时钟信号CKV2；薄膜晶体管T10，其栅极输入控制信号Select2，源极和漏极分别连接节点Mn和恒压高电位Vgh1；电容C1，其两端分别连接节点Qn和信号输出点Gn；电容C2，其两端分别连接节点Pn和恒压低电位VGL；工作时，当控制信号Select1为高电平时，控制信号Select2为低电平；当控制信号Select1为高电平时，控制信号Select2为低电平。本发明的GOA电路可作为LTPS面板或OLED面板的GOA电路。
图4以对应于Gn级输出的第n级GOA电路单元为例绘示本发明GOA电路单元的结构，本领域技术人员可以理解，相邻的对应于Gn+1级输出的第n+1级GOA电路单元结构与图4所示相同，仅是在工作时采用不同的时钟信号，在此不再赘述第n+1级GOA电路单元的结构。
参见图5，其为图4的GOA电路正向扫描时序示意图。现结合图4，对电路的具体工作过程(正向扫描)介绍如下：
以Gn级输出为例；正向扫描时：U2D为高电平，D2U为低电平；
阶段1，预充电：Gn-2与U2D同时为高电平，T1导通，Hn点被预充电。当Hn点为高电平时，T5处于导通状态，Qn点被预充电。当Hn点为高电平时，T7处于导通状态，Pn点被拉低；
阶段2，Gn输出高电平：在阶段1中，Qn点被预充电，C1对电荷具有一定的保持作用，T2处于导通状态:当CKV2与Select1同时为高电平时，CKV2对应的高电平输出到Mn点，而此时T2处于导通状态，因此Mn点的高电平输出到Gn点；当Select2为高电平时，Vgh1对应的高电平输出到Mn点，而此时T2处于导通状态，Mn对应的高电平再次输出到Gn点，而Vgh1＜VGH，这样Gn点输出就实现了MLG功能。实现MLG功能的同时，消角电压的大小，即Gn点输出自高电平VGH降低后的电压，可以通过调整Vgh1所对应的电压来实现；而消角时间的长短，即Gn点输出自高电平VGH降低为输出Vgh1的时间，可以通过调整Select1与Select2所对应的时间关系来实现。
阶段3，Gn输出低电平：C1对Qn点的高电平具有保持作用，而此时Select1为高电平，CKV2的低电平将Gn点拉低；
阶段4，Qn点拉低到VGL：当Gn+2为高电平，此时D2U为低电平，T3处于导通的状态，那么Qn点被拉低到VGL；
阶段5，Qn点及Gn点低电平维持阶段：当Qn点变为低电平后，T7处于截止状态，当CKV4跳变为高电平时T8导通，Pn点被充电，那么T4和T6均处于导通的状态，可以保证Qn点及Gn点低电平的稳定，同时C2对Pn点的高电平具有一定的保持作用。
对于首端两级GOA电路单元，正向扫描开始时，薄膜晶体管T1的栅极需要输入高电平信号作为启动信号。对于首、末端级联的GOA单元可以采用输入启动信号的方式来代替缺少的信号输入。
对应于Gn+1级输出的第n+1级GOA电路单元，即Gn+1级，正向扫描时所使用的时钟信号为CKV1和CKV3，工作过程同样可结合图5得出。
参见图6，其为图4的GOA电路反向扫描时序示意图。现结合图4，对电路的具体工作过程(反向扫描)介绍如下：
以Gn级输出为例；反向扫描时：D2U为高电平，U2D为低电平；
阶段1，预充电：Gn+2与D2U同时为高电平，T3导通，Hn点被预充电。当Hn点为高电平时，T5处于导通状态，Qn点被预充电。当Hn点为高电平时，T7处于导通状态，Pn点被拉低；
阶段2，Gn输出高电平：在阶段1中，Qn点被预充电，C1对电荷具有一定的保持作用，T2处于导通状态:当CKV2与Select1同时为高电平时，CKV2对应的高电平输出到Mn点，而此时T2处于导通状态，因此Mn点的高电平输出到Gn点；当Select2为高电平时，Vgh1对应的高电平输出到Mn点，而此时T2处于导通状态，Mn对应的高电平再次输出到Gn点，而Vgh1＜VGH，这样Gn点输出就实现了MLG功能。同时消角电压可以通过调整Vgh1所对应的电压来实现，而消角时间可以通过调整Select1与Select2所对应的时间关系来实现。
阶段3，Gn输出低电平：C1对Qn点的高电平具有保持作用，而此时Select1为高电平CKV2的低电平将Gn点拉低；
阶段4，Qn点拉低到VGL：当Gn-2为高电平，此时U2D为低电平，T1处于导通的状态，那么Qn点被拉低到VGL；
阶段5，Qn点及Gn点低电平维持阶段：当Qn点变为低电平后，T7处于截止状态，当CKV4跳变为高电平时T8导通，Pn点被充电，那么T4和T6均处于导通的状态，可以保证Qn点及Gn点低电平的稳定，同时C2 对Pn点的高电平具有一定的保持作用。
对于末端两级GOA电路单元，反向扫描开始时，薄膜晶体管T3需要输入高电平信号作为启动信号。对于首、末端级联的GOA单元可以采用输入启动信号的方式来代替缺少的信号输入。
对应于Gn+1级输出的第n+1级GOA电路单元，即Gn+1级，反向扫描时所使用的时钟信号为CKV1和CKV3，工作过程同样可结合图6得出。
由图5，图6还可知，时钟信号CKV1～4为占空比为0.25的矩形波，时钟信号CKV4和时钟信号CKV2的相位相差四分之一周期，时钟信号CKV3和时钟信号CKV1的相位相差四分之一周期。
如图4虚线框部分所示，本发明在现有的GOA电路的基础上引入2个控制信号，Select1、Select2。在Qn点被自举为高电平时:当Select1为高电平时，CKV2对应的高电平输出到Gn点，当Select2为高电平时，Vgh1对应的高电平输出到Gn点，而Vgh1对应的高电平小于VGH，即Vgh1＜VGH。这样Gn点输出就实现了3阶MLG功能。可以有效的降低馈通，改善面内Vcom均一性，提高画面显示的品质。同时消角电压可以通过调整Vgh1所对应的电压来实现，而消角时间可以通过调整Select1与Select2所对应的时间关系来实现。
本发明的GOA电路已知和潜在的技术/产品应用领域及其应用方式如下：1、集成在阵列基板上的液晶显示器行扫描(Gate)驱动电路；2、应用于手机，显示器，电视的栅极驱动领域；3、可涵盖LCD和OLED的行业先进技术；4、本电路的稳定性适用于高解析度的面板设计当中。
综上，本发明提出了一种新的GOA电路，该电路具有MLG功能，可以有效的降低馈通，改善面内Vcom均一性，提高画面显示的品质。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。

Claims (16)

  1. 一种GOA电路，包括级联的多个GOA电路单元，其中，设n为大于0的自然数，第n级GOA电路单元包括：
    第一薄膜晶体管，其源极和漏极分别连接第一节点和输入正向扫描控制信号，当第n级非为首端两级时，其栅极连接第n-2级GOA电路单元的信号输出点，否则其栅极输入第一启动信号；
    第三薄膜晶体管，其源极和漏极分别连接第一节点和输入反向扫描控制信号，当第n级非为末端两级时，其栅极连接第n+2级GOA电路单元的信号输出点，否则其栅极输入第二启动信号；
    第七薄膜晶体管，其栅极连接第一节点，源极和漏极分别连接第四节点和恒压低电位；
    第六薄膜晶体管，其栅极连接第四节点，源极和漏极分别连接第一节点和恒压低电位；
    第五薄膜晶体管，其栅极连接第一恒压高电位，源极和漏极分别连接第一节点和第二节点；
    第八薄膜晶体管，其栅极输入第一时钟信号，源极和漏极分别连接第四节点和第一恒压高电位；
    第九薄膜晶体管，其栅极输入第一控制信号，源极和漏极分别连接第三节点和输入第二时钟信号；
    第十薄膜晶体管，其栅极输入第二控制信号，源极和漏极分别连接第三节点和第二恒压高电位；
    第二薄膜晶体管，其栅极连接第二节点，源极和漏极分别连接第n级GOA电路单元的信号输出点和第三节点；
    第一电容，其两端分别连接第二节点和第n级GOA电路单元的信号输出点；
    第四薄膜晶体管，其栅极连接第四节点，源极和漏极分别连接第n级GOA电路单元的信号输出点和恒压低电位；
    第二电容，其两端分别连接第四节点和恒压低电位；
    工作中，当第一控制信号为高电平时，第二控制信号为低电平；当第一控制信号为高电平时，第二控制信号为低电平。
  2. 如权利要求1所述的GOA电路，其中，该第二恒压高电位的电压小于第一恒压高电位的电压。
  3. 如权利要求1所述的GOA电路，其中，通过调整该第二恒压高电位所对应的电压来调整消角电压。
  4. 如权利要求1所述的GOA电路，其中，通过调整该第一控制信号与第二控制信号所对应的时间关系来调整消角时间。
  5. 如权利要求1所述的GOA电路，其中，该第一时钟信号和第二时钟信号为占空比为0.25的矩形波，该第一时钟信号和第二时钟信号的相位相差四分之一周期。
  6. 如权利要求1所述的GOA电路，其中，对于首端两级GOA电路单元，正向扫描开始时，该第一薄膜晶体管的栅极输入高电平信号作为该第一启动信号。
  7. 如权利要求1所述的GOA电路，其中，对于末端两级GOA电路单元，反向扫描开始时，该第三薄膜晶体管的栅极输入高电平信号作为该第二启动信号。
  8. 如权利要求1所述的GOA电路，其中，其为LTPS面板的GOA电路。
  9. 如权利要求1所述的GOA电路，其中，其为OLED面板的GOA电路。
  10. 一种GOA电路，包括级联的多个GOA电路单元，其中，设n为大于0的自然数，第n级GOA电路单元包括：
    第一薄膜晶体管，其源极和漏极分别连接第一节点和输入正向扫描控制信号，当第n级非为首端两级时，其栅极连接第n-2级GOA电路单元的信号输出点，否则其栅极输入第一启动信号；
    第三薄膜晶体管，其源极和漏极分别连接第一节点和输入反向扫描控制信号，当第n级非为末端两级时，其栅极连接第n+2级GOA电路单元的信号输出点，否则其栅极输入第二启动信号；
    第七薄膜晶体管，其栅极连接第一节点，源极和漏极分别连接第四节点和恒压低电位；
    第六薄膜晶体管，其栅极连接第四节点，源极和漏极分别连接第一节点和恒压低电位；
    第五薄膜晶体管，其栅极连接第一恒压高电位，源极和漏极分别连接第一节点和第二节点；
    第八薄膜晶体管，其栅极输入第一时钟信号，源极和漏极分别连接第四节点和第一恒压高电位；
    第九薄膜晶体管，其栅极输入第一控制信号，源极和漏极分别连接第 三节点和输入第二时钟信号；
    第十薄膜晶体管，其栅极输入第二控制信号，源极和漏极分别连接第三节点和第二恒压高电位；
    第二薄膜晶体管，其栅极连接第二节点，源极和漏极分别连接第n级GOA电路单元的信号输出点和第三节点；
    第一电容，其两端分别连接第二节点和第n级GOA电路单元的信号输出点；
    第四薄膜晶体管，其栅极连接第四节点，源极和漏极分别连接第n级GOA电路单元的信号输出点和恒压低电位；
    第二电容，其两端分别连接第四节点和恒压低电位；
    工作中，当第一控制信号为高电平时，第二控制信号为低电平；当第一控制信号为高电平时，第二控制信号为低电平；
    其中，该第二恒压高电位的电压小于第一恒压高电位的电压；
    其中，该第一时钟信号和第二时钟信号为占空比为0.25的矩形波，该第一时钟信号和第二时钟信号的相位相差四分之一周期。
  11. 如权利要求10所述的GOA电路，其中，通过调整该第二恒压高电位所对应的电压来调整消角电压。
  12. 如权利要求10所述的GOA电路，其中，通过调整该第一控制信号与第二控制信号所对应的时间关系来调整消角时间。
  13. 如权利要求10所述的GOA电路，其中，对于首端两级GOA电路单元，正向扫描开始时，该第一薄膜晶体管的栅极输入高电平信号作为该第一启动信号。
  14. 如权利要求10所述的GOA电路，其中，对于末端两级GOA电路单元，反向扫描开始时，该第三薄膜晶体管的栅极输入高电平信号作为该第二启动信号。
  15. 如权利要求10所述的GOA电路，其中，其为LTPS面板的GOA电路。
  16. 如权利要求10所述的GOA电路，其中，其为OLED面板的GOA电路。
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