WO2018119963A1 - Goa电路 - Google Patents

Goa电路 Download PDF

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Publication number
WO2018119963A1
WO2018119963A1 PCT/CN2016/113317 CN2016113317W WO2018119963A1 WO 2018119963 A1 WO2018119963 A1 WO 2018119963A1 CN 2016113317 W CN2016113317 W CN 2016113317W WO 2018119963 A1 WO2018119963 A1 WO 2018119963A1
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WIPO (PCT)
Prior art keywords
goa circuit
thin film
source
film transistor
drain
Prior art date
Application number
PCT/CN2016/113317
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English (en)
French (fr)
Inventor
李亚锋
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武汉华星光电技术有限公司
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Priority to US15/506,240 priority Critical patent/US10255869B2/en
Publication of WO2018119963A1 publication Critical patent/WO2018119963A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/067—Special waveforms for scanning, where no circuit details of the gate driver are given
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present invention relates to the field of liquid crystal displays, and more particularly to a GOA circuit.
  • the Gate Driver On Array (GOA) technology utilizes an existing thin film transistor liquid crystal display array (Array) process to fabricate a gate scan driving signal circuit on an array substrate to realize gate-by-row operation.
  • Array thin film transistor liquid crystal display array
  • the gate-by-row output of the gate is realized by multi-stage cascading.
  • FIG. 1 which is a schematic diagram of a conventional GOA circuit
  • the upper GOA unit of FIG. 1 outputs a horizontal scan signal corresponding to the nth row
  • the lower GOA unit of FIG. 1 outputs a horizontal scan signal of the n+1th row.
  • the structure of the existing GOA circuit is described by taking the nth stage GOA unit as an example.
  • the existing GOA circuit includes a plurality of cascaded GOA circuit units, wherein the nth stage GOA circuit unit that outputs the nth horizontal scanning signal includes:
  • the thin film transistor T1 has a gate connected to the signal output point Gn-2 of the n-2th GOA circuit unit, a source and a drain respectively connected to the node Hn and an input forward scan control signal U2D; and a thin film transistor T2 whose gate is connected The node Qn, the source and the drain are respectively connected to the signal output point Gn of the nth stage GOA circuit unit and the input clock signal CKV1;
  • the thin film transistor T3 whose gate is connected to the signal output point Gn+2 of the n+2th stage GOA circuit unit
  • the source and the drain are respectively connected to the node Hn and the input reverse scan control signal D2U;
  • the thin film transistor T4 has a gate connected to the node Pn, and the source and the drain are respectively connected to the signal output point Gn and the constant
  • the node Q (i.e., Qn) is a point for controlling the gate drive signal output; the node P (i.e., Pn) is a stable point for maintaining the low point of the Q point and the Gn point.
  • the portion of the dotted line in Fig. 1 is the forward and reverse scanning unit of the GOA circuit.
  • the circuit structure of the n+1th stage GOA circuit unit is similar to that of the nth stage and will not be described again.
  • FIG. 2 it is a schematic diagram of the forward scanning timing of the GOA circuit of FIG. 1.
  • FIG. 1 the specific working process (forward scanning) of the circuit is introduced as follows:
  • Phase 1 pre-charge: Gn-2 and U2D are simultaneously high, T1 is on, and Hn is pre-charged.
  • T1 is on
  • Hn is pre-charged.
  • T5 is in an on state
  • the Qn point is precharged.
  • T7 is in an on state, and the Pn point is pulled down;
  • Gn outputs a high level: in phase 1, the Qn point is precharged, C1 has a certain holding effect on the charge, T2 is in a conducting state, and a high level of CKV1 is output to the Gn terminal;
  • Gn outputs a low level: C1 has a holding effect on the high level of the Qn point, and at this time, the low level of CKV1 pulls the Gn point low;
  • Phase 5 Qn point and Gn point low level maintenance phase: When Qn point becomes low level, T7 is in the off state. When CKV3 jumps to high level, T8 turns on, P point is charged, then T4 and T6 Both are in the on state, which can ensure the stability of the low level of the Qn point and the Gn point, and the C2 has a certain holding effect on the high level of the Pn point.
  • the Gn+1 output is similar in principle to the Gn output, except that the control timing is cycled according to a certain law.
  • FIG. 3 is a schematic diagram of the reverse scan timing of the GOA circuit of FIG. 1, the specific working process (reverse scan) of the circuit is described below with reference to FIG.
  • Phase 1 pre-charge: Gn+2 and D2U are simultaneously high, T3 is on, and Hn is pre-charged.
  • T5 is in an on state and the Qn point is precharged.
  • T7 is in an on state, and the Pn point is pulled down;
  • Gn outputs a high level: in phase 1, the Qn point is precharged, C1 has a certain holding effect on the charge, T2 is in a conducting state, and a high level of CKV1 is output to the Gn terminal;
  • Gn outputs a low level: C1 has a holding effect on the high level of the Qn point, and at this time, the low level of CKV1 pulls the Gn point low;
  • Phase 5 Qn point and Gn point low level maintenance phase: When Qn point becomes low level, T7 is in the off state. When CKV3 jumps to high level, T8 turns on, P point is charged, then T4 and T6 Both are in the on state, which can ensure the stability of the low level of the Qn point and the Gn point, and the C2 has a certain holding effect on the high level of the Pn point.
  • the Gn+1 output is similar in principle to the Gn output, except that the control timing is cycled according to a certain law.
  • the gate-to-row output of the gate is realized by multi-stage cascading.
  • the GOA circuit diagram is shown in Figure 1, corresponding to the Gn+1 and Gn-level outputs.
  • the detailed timing is shown in Figure 2.
  • Figure 3 For example, the full HD (FHD) interlace driving method has a total of 960 gate outputs on one side, and then corresponds to the layout (Layout) shown in FIG.
  • the existing GOA circuit design method may not meet the design requirements.
  • the data (Data) drive mostly adopts the method of dot inversion (Dot Inversion), that is, the high-low jump of the data signal, but for the dot inversion
  • Dot Inversion the method of dot inversion
  • the corresponding power consumption is relatively high, and the power consumption calculation formula is as follows:
  • C is the capacitance
  • f is the frequency
  • V is the voltage
  • the object of the present invention is to propose a new GOA circuit architecture to reduce the layout space occupied by the GOA circuit.
  • the present invention provides a GOA circuit comprising a plurality of cascaded GOA circuit units, wherein n is a natural number, and is responsible for outputting the nth-th row and the second n-th horizontal scanning signal of the n-th stage GOA circuit unit.
  • a first thin film transistor having a gate connected to a first node of the n-2th stage GOA circuit unit, a source and a drain respectively connected to the second node and inputting a forward scan control signal;
  • a second thin film transistor having a gate connected to the third node, a source and a drain respectively connected to the first node of the nth stage GOA circuit unit and inputting the first clock signal;
  • a third thin film transistor having a gate connected to a first node of the n+2th stage GOA circuit unit, a source and a drain respectively connected to the second node and an input reverse scan control signal;
  • a fourth thin film transistor having a gate connected to the fourth node, wherein the source and the drain are respectively connected to the first node of the nth stage GOA circuit unit and the constant voltage low potential;
  • a fifth thin film transistor having a gate connected to a constant voltage high potential, and a source and a drain connected to the second node and the third node, respectively;
  • a sixth thin film transistor having a gate connected to the fourth node, a source and a drain respectively connected to the second node and a constant voltage low potential;
  • a seventh thin film transistor having a gate connected to the second node, a source and a drain respectively connected to the fourth node and a constant voltage low potential;
  • the eighth thin film transistor has a gate inputting a second clock signal, and a source and a drain are respectively connected Four nodes and constant voltage high potential;
  • a ninth thin film transistor having a gate inputting a first control signal, a first source/drain connected to a first node of the nth stage GOA circuit unit, and a second source/drain connected to the eleventh thin film transistor and the twelfth a first source/drain of the thin film transistor;
  • a tenth thin film transistor having a second control signal input to the gate thereof, a first source/drain connected to the first node of the nth stage GOA circuit unit, and a second source/drain connected to the thirteenth thin film transistor and the fourteenth a first source/drain of the thin film transistor;
  • An eleventh thin film transistor having a gate inputting a first control signal, and a second source/drain connected to a first signal output point of the nth stage GOA circuit unit;
  • a twelfth thin film transistor having a second control signal input to the gate thereof and a constant voltage low potential connected to the second source/drain;
  • a thirteenth thin film transistor having a gate inputting a first control signal and a second source/drain connected to a constant voltage low potential
  • a fourteenth thin film transistor having a second control signal input to the gate thereof and a second signal output point of the nth stage GOA circuit unit connected to the second source/drain;
  • the second capacitor has two ends connected to the fourth node and a constant voltage low potential.
  • the nth stage GOA circuit unit further includes:
  • a fifteenth thin film transistor the gate thereof inputs a second control signal, and the source and the drain are respectively connected to the first signal output point of the nth stage GOA circuit unit and the constant voltage low potential;
  • a sixteenth thin film transistor having a gate inputting a first control signal, and a source and a drain respectively connected to a second signal output point of the nth stage GOA circuit unit and a constant voltage low potential;
  • a seventeenth thin film transistor the gate thereof inputs a third control signal, and the source and the drain are respectively connected to the first signal output point of the nth stage GOA circuit unit and the first source/drain of the eighteenth thin film transistor;
  • the eighteenth thin film transistor has a gate inputting a third control signal, and the second source/drain is connected to the first node of the nth stage GOA circuit unit;
  • the nineteenth thin film transistor has a gate inputting a third control signal, the first source/drain is connected to the first node of the nth stage GOA circuit unit, and the second source/drain is connected to the first of the twentieth thin film transistor Source/drain;
  • the twentieth thin film transistor has a gate inputting a third control signal, and a second source/drain is connected to the second signal output point of the nth stage GOA circuit unit.
  • first clock signal and the second clock signal are rectangular waves with a duty ratio of 0.25,
  • the phase between the first clock signal and the second clock signal is different by one-half cycle.
  • the first control signal and the second control signal are alternately at a high level, and the third control signal is always at a low level.
  • the first control signal and the second control signal are both low level, and the third control signal is always at a high level.
  • a high level signal is input from the first node of the n-2th stage GOA circuit unit as an enable signal.
  • a high level signal is input from the first node of the n+2th stage GOA circuit unit as an enable signal.
  • the low power display state is a standby mode.
  • the low power display state is a power saving mode.
  • the present invention also provides a GOA circuit comprising a plurality of cascaded GOA circuit units, wherein n is a natural number, and the nth stage GOA circuit unit responsible for outputting the 2n-1th row and the 2nth row horizontal scan signal comprises:
  • a first thin film transistor having a gate connected to a first node of the n-2th stage GOA circuit unit, a source and a drain respectively connected to the second node and inputting a forward scan control signal;
  • a second thin film transistor having a gate connected to the third node, a source and a drain respectively connected to the first node of the nth stage GOA circuit unit and inputting the first clock signal;
  • a third thin film transistor having a gate connected to a first node of the n+2th stage GOA circuit unit, a source and a drain respectively connected to the second node and an input reverse scan control signal;
  • a fourth thin film transistor having a gate connected to the fourth node, wherein the source and the drain are respectively connected to the first node of the nth stage GOA circuit unit and the constant voltage low potential;
  • a fifth thin film transistor having a gate connected to a constant voltage high potential, and a source and a drain connected to the second node and the third node, respectively;
  • a sixth thin film transistor having a gate connected to the fourth node, a source and a drain respectively connected to the second node and a constant voltage low potential;
  • a seventh thin film transistor having a gate connected to the second node, a source and a drain respectively connected to the fourth node and a constant voltage low potential;
  • the eighth thin film transistor has a gate inputting a second clock signal, and a source and a drain are respectively connected to the fourth node and a constant voltage high potential;
  • a ninth thin film transistor having a gate inputting a first control signal, a first source/drain connected to a first node of the nth stage GOA circuit unit, and a second source/drain connected to the eleventh thin film transistor and the twelfth a first source/drain of the thin film transistor;
  • a tenth thin film transistor having a gate inputting a second control signal and a first source/drain connection n a first node of the stage GOA circuit unit, the second source/drain connecting the first source/drain of the thirteenth thin film transistor and the fourteenth thin film transistor;
  • An eleventh thin film transistor having a gate inputting a first control signal, and a second source/drain connected to a first signal output point of the nth stage GOA circuit unit;
  • a twelfth thin film transistor having a second control signal input to the gate thereof and a constant voltage low potential connected to the second source/drain;
  • a thirteenth thin film transistor having a gate inputting a first control signal and a second source/drain connected to a constant voltage low potential
  • a fourteenth thin film transistor having a second control signal input to the gate thereof and a second signal output point of the nth stage GOA circuit unit connected to the second source/drain;
  • the nth stage GOA circuit unit further includes:
  • a fifteenth thin film transistor the gate thereof inputs a second control signal, and the source and the drain are respectively connected to the first signal output point of the nth stage GOA circuit unit and the constant voltage low potential;
  • a sixteenth thin film transistor having a gate inputting a first control signal, and a source and a drain respectively connected to a second signal output point of the nth stage GOA circuit unit and a constant voltage low potential;
  • a seventeenth thin film transistor the gate thereof inputs a third control signal, and the source and the drain are respectively connected to the first signal output point of the nth stage GOA circuit unit and the first source/drain of the eighteenth thin film transistor;
  • the eighteenth thin film transistor has a gate inputting a third control signal, and the second source/drain is connected to the first node of the nth stage GOA circuit unit;
  • the nineteenth thin film transistor has a gate inputting a third control signal, the first source/drain is connected to the first node of the nth stage GOA circuit unit, and the second source/drain is connected to the first of the twentieth thin film transistor Source/drain;
  • a twentieth thin film transistor having a gate inputting a third control signal and a second source/drain connected to a second signal output point of the nth stage GOA circuit unit;
  • a high level signal is input from the first node of the n-2th GOA circuit unit as an enable signal
  • a high level signal is input from the first node of the n+2th stage GOA circuit unit as an enable signal.
  • the present invention provides a GOA circuit, which can effectively reduce the layout space occupied by the GOA circuit, and can play a certain role in the development of the narrow frame technology; in some special display modes. It can reduce the driving power consumption of the panel.
  • 1 is a schematic diagram of a conventional GOA circuit
  • FIG. 2 is a schematic diagram of a forward scan timing of the GOA circuit of FIG. 1;
  • FIG. 3 is a schematic diagram of a reverse scan timing of the GOA circuit of FIG. 1;
  • FIG. 4 is a schematic view of a second preferred embodiment of the GOA circuit of the present invention.
  • FIG. 5 is a schematic diagram of a forward scan timing of the GOA circuit of FIG. 4;
  • FIG. 6 is a schematic diagram of a reverse scan timing of the GOA circuit of FIG. 4;
  • FIG. 7 is a schematic diagram of corresponding data driving of a second preferred embodiment of the GOA circuit of the present invention.
  • Figure 8 is a schematic view showing a first preferred embodiment of the GOA circuit of the present invention.
  • FIG. 9 is a schematic diagram of a forward scan timing of the GOA circuit of FIG. 8;
  • FIG. 10 is a schematic diagram showing the reverse scan timing of the GOA circuit of FIG. 8.
  • FIG. 10 is a schematic diagram showing the reverse scan timing of the GOA circuit of FIG. 8.
  • the GOA circuit of the present invention includes a plurality of cascaded GOA circuit units, wherein n is a natural number, and is responsible for outputting the 2n-1th row and the 2ndth.
  • the nth stage GOA circuit unit of the horizontal scanning signal includes:
  • the thin film transistor T1 has a gate connected to the node Wn-2 of the n-2th stage GOA circuit unit, and the source and the drain are respectively connected to the node Hn and the input forward scan control signal U2D;
  • the thin film transistor T2 has a gate connection node Qn, and a source and a drain are respectively connected to the node Wn of the nth stage GOA circuit unit and the input clock signal CKV1;
  • the thin film transistor T3 has a gate connected to the node Wn+2 of the n+2th stage GOA circuit unit, and the source and the drain are respectively connected to the node Hn and the input reverse scan control signal D2U;
  • the thin film transistor T4 has a gate connection node Pn, and a source and a drain are respectively connected to the node Wn of the nth stage GOA circuit unit and the constant voltage low potential VGL;
  • the thin film transistor T5 has a gate connected to a constant voltage high potential VGH, and a source and a drain are respectively connected to the node Hn and the node Qn;
  • the thin film transistor T6 has a gate connected to the node Pn, and the source and the drain are respectively connected to the node Hn and the constant voltage low potential VGL;
  • the thin film transistor T7 has its gate connected to the node Hn, and the source and the drain are respectively connected to the node Pn and Constant voltage low potential VGL;
  • the thin film transistor T8 has a gate input clock signal CKV3, and a source and a drain are respectively connected to the node Pn and the constant voltage high potential VGH;
  • the thin film transistor T9 has a gate input control signal Select1, the first source/drain is connected to the node Wn of the nth stage GOA circuit unit, and the second source/drain is connected to the first source of the thin film transistor T11 and the thin film transistor T12. /drain;
  • the thin film transistor T10 has a gate input control signal Select2, the first source/drain is connected to the node Wn of the nth stage GOA circuit unit, and the second source/drain is connected to the first source of the thin film transistor T13 and the thin film transistor T14. /drain;
  • Thin film transistor T11 its gate input control signal Select1, the second source/drain is connected to the signal output point G2n-1 of the nth stage GOA circuit unit;
  • the thin film transistor T12 has a gate input control signal Select2 and a second source/drain connected to the constant voltage low potential VGL;
  • the thin film transistor T13 has a gate input control signal Select1 and a second source/drain connected to the constant voltage low potential VGL;
  • the thin film transistor T14 has a gate input control signal Select2, and a second source/drain is connected to the signal output point G2n of the nth stage GOA circuit unit;
  • a capacitor C1 having two ends connected to the node Qn and the node Wn of the nth stage GOA circuit unit;
  • the capacitor C2 has two ends connected to the node Pn and the constant voltage low potential VGL.
  • the dotted frame portion in Fig. 8 is the forward and reverse scanning unit of the GOA circuit.
  • FIG. 9 is a schematic diagram of the forward scan timing of the GOA circuit of FIG. Referring now to Figure 8, the specific working process of the circuit (forward scanning) is described as follows:
  • Wn-level GOA unit that outputs the G2n-1 and G2n line scan signals as an example; during forward scanning: U2D is high level and D2U is low level;
  • Phase 1 pre-charge: Wn-2 and U2D are simultaneously high, T1 is on, and Hn is pre-charged.
  • T1 is on
  • Hn is pre-charged.
  • T5 is in an on state
  • the Qn point is precharged.
  • T7 is in an on state, and the Pn point is pulled down;
  • Phase 2 Wn outputs a high level: In phase 1, Q point is precharged, C1 has a certain holding effect on the charge, T2 is in the on state, and the high level of CKV1 is output to the Wn terminal;
  • Wn outputs a low level: C1 has a holding effect on the high level of the Qn point, and at this time, the low level of CKV1 pulls the Wn point low;
  • Stage 5 Qn point and Wn point low level maintenance phase: When Qn point becomes low level, T7 In the off state, when CKV3 jumps to high level, T8 turns on, Pn is charged, then T4 and T6 are both on, which can ensure the stability of Qn point and Wn point low level, and C2 to Pn point.
  • the high level has a certain retention effect.
  • the main difference between the present invention and the prior art is that a control unit composed of T9 to T14 is introduced.
  • Select1 corresponds to a high level, T9 and T11 are in an open state, and G2n-1 is pulled low.
  • Select2 corresponds to a high level, T10 and T14 are in an open state, and G2n is pulled low.
  • Select1 corresponds to a high level, T9 and T11 are in an open state, and G2n-1 is pulled high.
  • Select2 corresponds to a high level, T10 and T14 are in an open state, and G2n is pulled high.
  • the clock signal CKV1 and the clock signal CKV3 are rectangular waves having a duty ratio of 0.25, and the phase difference between the clock signal CKV1 and the clock signal CKV3 is one-half cycle.
  • a high level signal is required to be input as a start signal at the first node Wn-2 of the n-2th stage GOA circuit unit at the beginning of the forward scan.
  • FIG. 10 it is a schematic diagram of the reverse scan timing of the GOA circuit of FIG.
  • Figure 8 the specific working process of the circuit (reverse scan) is introduced as follows:
  • Wn-level GOA unit that outputs the G2n-1 and G2n line scan signals as an example; during forward scan: D2U is high level and U2D is low level;
  • Phase 1 pre-charge: Wn+2 and D2U are simultaneously high, T3 is on, and Hn is pre-charged.
  • T5 is in an on state and the Qn point is precharged.
  • T7 is in an on state, and the Pn point is pulled down;
  • Phase 2 Wn outputs a high level: In phase 1, the Qn point is precharged, C1 has a certain holding effect on the charge, T2 is in the on state, and the high level of CKV1 is output to the Wn terminal;
  • Wn outputs a low level: C1 has a holding effect on the high level of the Qn point, and at this time, the low level of CKV1 pulls the Wn point low;
  • Qn point and Wn point low level maintenance phase When Qn point becomes low level, T7 is in the off state. When CKV3 jumps to high level, T8 turns on, Pn point is charged, then T4 and T6 Both are in the on state, which can ensure the stability of the low level of Qn point and Wn point, and C2 has a certain holding effect on the high level of Pn point.
  • the main difference between the present invention and the prior art is that a control unit composed of T9 to T14 is introduced.
  • Select2 corresponds to a high level, T10 and T14 are in an open state, and G2n is pulled low.
  • Select1 corresponds to a high level, T9 and T11 are in an open state, and G2n-1 is pulled low.
  • Wn output is high
  • Select2 corresponds to a high level, and T10 and T14 are turned on. State, G2n is pulled high.
  • Select1 corresponds to a high level, T9 and T11 are in an open state, and G2n-1 is pulled high.
  • a high level signal needs to be input as the enable signal at the first node Wn+2 of the n+2th stage GOA circuit unit.
  • the first preferred embodiment of the present invention proposes adding a control unit based on the existing GOA architecture, and decomposing a certain level of GOA output into two levels of GOA output through the control unit.
  • the layout space occupied by the GOA can be reduced to a certain extent, which plays a certain role in the development of the narrow frame technology.
  • the GOA circuit of the present invention includes a plurality of cascaded GOA circuit units, wherein n is a natural number, and is responsible for outputting the 2n-1th row and the 2ndth.
  • the nth stage GOA circuit unit of the horizontal scanning signal includes:
  • the thin film transistor T1 has a gate connected to the node Wn-2 of the n-2th stage GOA circuit unit, and the source and the drain are respectively connected to the node Hn and the input forward scan control signal U2D;
  • the thin film transistor T2 has a gate connection node Qn, and a source and a drain are respectively connected to the node Wn of the nth stage GOA circuit unit and the input clock signal CKV1;
  • the thin film transistor T3 has a gate connected to the node Wn+2 of the n+2th stage GOA circuit unit, and the source and the drain are respectively connected to the node Hn and the input reverse scan control signal D2U;
  • the thin film transistor T4 has a gate connection node Pn, and a source and a drain are respectively connected to the node Wn of the nth stage GOA circuit unit and the constant voltage low potential VGL;
  • the thin film transistor T5 has a gate connected to a constant voltage high potential VGH, and a source and a drain are respectively connected to the node Hn and the node Qn;
  • the thin film transistor T6 has a gate connected to the node Pn, and the source and the drain are respectively connected to the node Hn and the constant voltage low potential VGL;
  • the thin film transistor T7 has a gate connection node Hn, and a source and a drain are respectively connected to the node Pn and the constant voltage low potential VGL;
  • the thin film transistor T8 has a gate input clock signal CKV3, and a source and a drain are respectively connected to the node Pn and the constant voltage high potential VGH;
  • the thin film transistor T9 has a gate input control signal Select1, the first source/drain is connected to the node Wn of the nth stage GOA circuit unit, and the second source/drain is connected to the first source of the thin film transistor T11 and the thin film transistor T12. /drain;
  • the thin film transistor T10 has a gate input control signal Select2, the first source/drain is connected to the node Wn of the nth stage GOA circuit unit, and the second source/drain is connected to the first source of the thin film transistor T13 and the thin film transistor T14. /drain;
  • Thin film transistor T11 its gate input control signal Select1, the second source/drain is connected to the signal output point G2n-1 of the nth stage GOA circuit unit;
  • the thin film transistor T12 has a gate input control signal Select2 and a second source/drain connected to the constant voltage low potential VGL;
  • the thin film transistor T13 has a gate input control signal Select1 and a second source/drain connected to the constant voltage low potential VGL;
  • the thin film transistor T14 has a gate input control signal Select2, and a second source/drain is connected to the signal output point G2n of the nth stage GOA circuit unit;
  • the thin film transistor T15 has a gate input control signal Select2, and a source and a drain are respectively connected to the signal output point G2n-1 and the constant voltage low potential VGL of the nth stage GOA circuit unit;
  • the thin film transistor T16 has a gate input control signal Select1, and a source and a drain are respectively connected to the signal output point G2n of the nth stage GOA circuit unit and the constant voltage low potential VGL;
  • the thin film transistor T17 has a gate input control signal Select3, and a source and a drain are respectively connected to the signal output point G2n-1 of the nth stage GOA circuit unit and the first source/drain of the thin film transistor T18;
  • a thin film transistor T18 having a gate input control signal Select3 and a second source/drain connected to a node Wn of the nth stage GOA circuit unit;
  • the thin film transistor T19 has a gate input control signal Select3, the first source/drain is connected to the node Wn of the nth stage GOA circuit unit, and the second source/drain is connected to the first source/drain of the thin film transistor T20;
  • the thin film transistor T20 has a gate input control signal Select3, and a second source/drain is connected to the signal output point G2n of the nth stage GOA circuit unit;
  • a capacitor C1 having two ends connected to the node Qn and the node Wn of the nth stage GOA circuit unit;
  • the capacitor C2 has two ends connected to the node Pn and the constant voltage low potential VGL.
  • the dotted frame portion in Fig. 4 is the forward and reverse scanning unit of the GOA circuit.
  • FIG. 5 it is a schematic diagram of the forward scan timing of the GOA circuit of FIG.
  • the specific working process of the circuit is as follows:
  • Wn-level GOA unit that outputs the G2n-1 and G2n line scan signals as an example; during forward scanning: U2D is high level and D2U is low level;
  • Phase 1 pre-charge: Wn-2 and U2D are simultaneously high, T1 is on, and Hn is pre-charged.
  • T1 is on
  • Hn is pre-charged.
  • T5 is in an on state
  • the Qn point is precharged.
  • T7 is in an on state, and the Pn point is pulled down;
  • Phase 2 Wn outputs a high level: In phase 1, Q point is precharged, C1 has a certain holding effect on the charge, T2 is in the on state, and the high level of CKV1 is output to the Wn terminal;
  • Wn outputs a low level: C1 has a holding effect on the high level of the Qn point, and at this time, the low level of CKV1 pulls the Wn point low;
  • Qn point and Wn point low level maintenance phase When Qn point becomes low level, T7 is in the off state. When CKV3 jumps to high level, T8 turns on, Pn point is charged, then T4 and T6 Both are in the on state, which can ensure the stability of the low level of Qn point and Wn point, and C2 has a certain holding effect on the high level of Pn point.
  • Select1 corresponds to a high level, T9 and T11 are in an open state, and G2n-1 is pulled low.
  • Select2 corresponds to a high level, T10 and T14 are in an open state, and G2n is pulled low.
  • Select1 corresponds to a high level, T9 and T11 are in an open state, and G2n-1 is pulled high.
  • Select2 corresponds to a high level, T10 and T14 are in an open state, and G2n is pulled high.
  • Select1 and Select2 are both low, and Select3 always outputs high.
  • the clock signal CKV1 and the clock signal CKV3 are rectangular waves having a duty ratio of 0.25, and the phase difference between the clock signal CKV1 and the clock signal CKV3 is one-half cycle.
  • a high level signal is required to be input as a start signal at the first node Wn-2 of the n-2th stage GOA circuit unit at the beginning of the forward scan.
  • FIG. 6 is a schematic diagram of the reverse scan timing of the GOA circuit of FIG.
  • Reverse scan the specific working process of the circuit (reverse scan) is introduced as follows:
  • Wn-level GOA unit that outputs the G2n-1 and G2n line scan signals as an example; during forward scan: D2U is high level and U2D is low level;
  • Phase 1 pre-charge: Wn+2 and D2U are simultaneously high, T3 is on, and Hn is pre-charged.
  • T5 is in an on state and the Qn point is precharged.
  • T7 is in the on state, and the Pn point is pulled down;
  • Phase 2 Wn outputs a high level: In phase 1, the Qn point is precharged, C1 has a certain holding effect on the charge, T2 is in the on state, and the high level of CKV1 is output to the Wn terminal;
  • Wn outputs a low level: C1 has a holding effect on the high level of the Qn point, and at this time, the low level of CKV1 pulls the Wn point low;
  • Qn point and Wn point low level maintenance phase When Qn point becomes low level, T7 is in the off state. When CKV3 jumps to high level, T8 turns on, Pn point is charged, then T4 and T6 Both are in the on state, which can ensure the stability of the low level of Qn point and Wn point, and C2 has a certain holding effect on the high level of Pn point.
  • Select2 when the Wn output is low, Select2 corresponds to a high level, T10 and T14 are in an open state, and G2n is pulled low.
  • Select1 corresponds to a high level, T9 and T11 are in an open state, and G2n-1 is pulled low.
  • Select2 When the Wn output is high, Select2 corresponds to a high level, T10 and T14 are in an open state, and G2n is pulled high.
  • Select1 corresponds to a high level, T9 and T11 are in an open state, and G2n-1 is pulled high.
  • Select1 and Select2 are both low, and Select3 always outputs high.
  • a high level signal needs to be input as the enable signal at the first node Wn+2 of the n+2th stage GOA circuit unit.
  • FIG. 7 is a schematic diagram of corresponding data driving of a second preferred embodiment of the GOA circuit of the present invention.
  • the second preferred embodiment of the present invention adds a control unit to the existing GOA architecture.
  • three control signals are introduced, Select1, Select2, and Select3, wherein Select1 and Select2 are a group of opposite phase signals, and the main function is to divide the GOA gate output into two; in some special display modes.
  • Select3 outputs a high level when both Select1 and Select2 output are low, and the above two-stage output becomes the same output signal, that is, the first-stage and second-stage gates.
  • the output is the same, the third and fourth stage gate outputs are the same, and so on, then the corresponding frequency of the data (Data) signal will be halved, and the corresponding drive power consumption will also be reduced.
  • the known and potential technology/product application fields of the GOA circuit of the present invention and their application modes are as follows: 1. A liquid crystal display (Gate) driving circuit integrated on an array substrate; 2. A grid applied to a mobile phone, a display, and a television Extreme drive field; 3, can cover the advanced technology of LCD and OLED industry; 4, the stability of this circuit is suitable for high-resolution panel design.
  • Gate liquid crystal display
  • the present invention provides a GOA circuit, which can effectively reduce the layout space occupied by the GOA circuit, and can contribute to the development of a narrow bezel technology; in some special display modes, the driving power consumption of the panel can be reduced. .

Abstract

一种GOA电路。该GOA电路包括：第一薄膜晶体管(T1)至第十四薄膜晶体管(T14)，第一电容(C1)和第二电容(C2)。在现有的GOA电路架构的基础上增加了薄膜晶体管(T9～T14)组成的一控制单元，引入一组相位相反的控制信号(Select1、Select2)，主要作用是将GOA电路栅极输出一分为二。在一些特殊的显示模式下，数据(Data)信号对应的频率将会减半，对应的驱动功耗也会降低。提供一种GOA电路，可以有效的减小GOA电路所占的布局空间，对发展窄边框技术起到一定的帮助作用；在一些特殊的显示模式下能够降低面板的驱动功耗。

Description

GOA电路 技术领域
本发明涉及液晶显示器领域，尤其涉及一种GOA电路。
背景技术
阵列基板行驱动(Gate Driver On Array，简称GOA)技术是利用现有薄膜晶体管液晶显示器阵列(Array)制程将栅极(Gate)行扫描驱动信号电路制作在阵列基板上，实现对栅极逐行扫描的驱动方式的一项技术。
而对于现有的GOA电路在设计时，都是通过多级级联的方式实现栅极的逐行输出。参见图1，其为现有的GOA电路示意图，图1上部GOA单元对应输出第n行水平扫描信号，图1下部GOA单元对应输出第n+1行水平扫描信号。现以第n级GOA单元为例来说明现有GOA电路的结构，现有的GOA电路包括级联的多个GOA电路单元，其中输出第n行水平扫描信号的第n级GOA电路单元包括：薄膜晶体管T1，其栅极连接第n-2级GOA电路单元的信号输出点Gn-2，源极和漏极分别连接节点Hn和输入正向扫描控制信号U2D；薄膜晶体管T2，其栅极连接节点Qn，源极和漏极分别连接第n级GOA电路单元的信号输出点Gn和输入时钟信号CKV1；薄膜晶体管T3，其栅极连接第n+2级GOA电路单元的信号输出点Gn+2，源极和漏极分别连接节点Hn和输入反向扫描控制信号D2U；薄膜晶体管T4，其栅极连接节点Pn，源极和漏极分别连接信号输出点Gn和恒压低电位VGL；薄膜晶体管T5，其栅极连接恒压高电位VGH，源极和漏极分别连接节点Hn和节点Qn；薄膜晶体管T6，其栅极连接节点Pn，源极和漏极分别连接节点Hn和恒压低电位VGL；薄膜晶体管T7，其栅极连接节点Hn，源极和漏极分别连接节点Pn和恒压低电位VGL；薄膜晶体管T8，其栅极输入时钟信号CKV3，源极和漏极分别连接节点Pn和恒压高电位VGH；电容C1，其两端分别连接节点Qn和信号输出点Gn；电容C2，其两端分别连接节点Pn和恒压低电位VGL。节点Q(即Qn)为用于控制栅极驱动信号输出的点；节点P(即Pn)为用于维持Q点及Gn点低电平的稳定点。图1中虚线框部分即为GOA电路的正反向扫描单元。第n+1级GOA电路单元电路结构与第n级类似，不再赘述。
参见图2，其为图1的GOA电路正向扫描时序示意图，现结合图1，对电路的具体工作过程(正向扫描)介绍如下：
以Gn级输出为例；正向扫描时：U2D为高电平，D2U为低电平；
阶段1，预充电：Gn-2与U2D同时为高电平，T1导通，Hn点被预充电。当Hn点为高时，T5处于导通状态，Qn点被预充电。当Hn点为高时，T7处于导通状态，Pn点被拉低；
阶段2，Gn输出高电平：在阶段1中，Qn点被预充电，C1对电荷具有一定的保持作用，T2处于导通状态，CKV1的高电平输出到Gn端；
阶段3，Gn输出低电平：C1对Qn点的高电平具有保持作用，而此时CKV1的低电平将Gn点拉低；
阶段4，Qn点拉低到VGL：当Gn+2为高电平，此时D2U为低电平，T3处于导通的状态，那么Qn点被拉低到VGL；
阶段5，Qn点及Gn点低电平维持阶段：当Qn点变为低电平后，T7处于截止状态，当CKV3跳变为高电平时T8导通，P点被充电，那么T4和T6均处于导通的状态，可以保证Qn点及Gn点低电平的稳定，同时C2对Pn点的高电平具有一定的保持作用。
当然Gn+1级输出原理上于Gn输出相似，只是控制时序按照一定的规律循环。
参见图3，其为图1的GOA电路反向扫描时序示意图，现结合图1，对电路的具体工作过程(反向扫描)介绍如下：
以Gn级输出为例；正向扫描时：U2D为高电平，D2U为低电平；
阶段1，预充电：Gn+2与D2U同时为高电平，T3导通，Hn点被预充电。当Hn点为高时，T5处于导通状态，Qn点被预充电。当Hn点为高时，T7处于导通状态，Pn点被拉低；
阶段2，Gn输出高电平：在阶段1中，Qn点被预充电，C1对电荷具有一定的保持作用，T2处于导通状态，CKV1的高电平输出到Gn端；
阶段3，Gn输出低电平：C1对Qn点的高电平具有保持作用，而此时CKV1的低电平将Gn点拉低；
阶段4，Qn点拉低到VGL：当Gn-2为高电平，此时U2D为低电平，T1处于导通的状态，那么Qn点被拉低到VGL；
阶段5，Qn点及Gn点低电平维持阶段：当Qn点变为低电平后，T7处于截止状态，当CKV3跳变为高电平时T8导通，P点被充电，那么T4和T6均处于导通的状态，可以保证Qn点及Gn点低电平的稳定，同时C2对Pn点的高电平具有一定的保持作用。
当然Gn+1级输出原理上于Gn输出相似，只是控制时序按照一定的规律循环。一方面，按照目前LCD的发展趋势，窄边框越来越受到大家的欢 迎，尤其是左右边框的减小。对于现有的GOA电路在设计时，都是通过多级级联的方式实现栅极(Gate)的逐行输出，GOA电路图见图1，对应Gn+1、Gn级输出，详细时序见图2和图3。以全高清(FHD)隔行(Interlace)驱动方式为例，单边共计960级栅极输出，那么就对应480级图1所示的布局(Layout)。当左右边框(border)在不断减小时，现有的GOA电路设计方式可能就不能满足设计需求。
另一方面，有时为了满足现实画面高品质的需求，数据(Data)驱动多采用点反转(Dot Inversion)的方式，也就是数据信号要不停的高低跳变，但是对于点反转而言对应的功耗相对较高，功耗计算公式见下：
Figure PCTCN2016113317-appb-000001
其中，C为电容，f为频率，V为电压。
发明内容
本发明的目的在于提出一种新的GOA电路架构，减小GOA电路所占的布局空间。
为实现上述目的，本发明提供了一种GOA电路，包括级联的多个GOA电路单元，设n为自然数，负责输出第2n-1行和第2n行水平扫描信号的第n级GOA电路单元包括：
第一薄膜晶体管，其栅极连接第n-2级GOA电路单元的第一节点，源极和漏极分别连接第二节点和输入正向扫描控制信号；
第二薄膜晶体管，其栅极连接第三节点，源极和漏极分别连接第n级GOA电路单元的第一节点和输入第一时钟信号；
第三薄膜晶体管，其栅极连接第n+2级GOA电路单元的第一节点，源极和漏极分别连接第二节点和输入反向扫描控制信号；
第四薄膜晶体管，其栅极连接第四节点，源极和漏极分别连接第n级GOA电路单元的第一节点和恒压低电位；
第五薄膜晶体管，其栅极连接恒压高电位，源极和漏极分别连接第二节点和第三节点；
第六薄膜晶体管，其栅极连接第四节点，源极和漏极分别连接第二节点和恒压低电位；
第七薄膜晶体管，其栅极连接第二节点，源极和漏极分别连接第四节点和恒压低电位；
第八薄膜晶体管，其栅极输入第二时钟信号，源极和漏极分别连接第 四节点和恒压高电位；
第九薄膜晶体管，其栅极输入第一控制信号，第一源极/漏极连接第n级GOA电路单元的第一节点，第二源极/漏极连接第十一薄膜晶体管和第十二薄膜晶体管的第一源极/漏极；
第十薄膜晶体管，其栅极输入第二控制信号，第一源极/漏极连接第n级GOA电路单元的第一节点，第二源极/漏极连接第十三薄膜晶体管和第十四薄膜晶体管的第一源极/漏极；
第十一薄膜晶体管，其栅极输入第一控制信号，第二源极/漏极连接第n级GOA电路单元的第一信号输出点；
第十二薄膜晶体管，其栅极输入第二控制信号，第二源极/漏极连接恒压低电位；
第十三薄膜晶体管，其栅极输入第一控制信号，第二源极/漏极连接恒压低电位；
第十四薄膜晶体管，其栅极输入第二控制信号，第二源极/漏极连接第n级GOA电路单元的第二信号输出点；
第一电容，其两端分别连接第三节点和第n级GOA电路单元的第一节点；
第二电容，其两端分别连接第四节点和恒压低电位。
其中，该第n级GOA电路单元还包括：
第十五薄膜晶体管，其栅极输入第二控制信号，源极和漏极分别连接第n级GOA电路单元的第一信号输出点和恒压低电位；
第十六薄膜晶体管，其栅极输入第一控制信号，源极和漏极分别连接第n级GOA电路单元的第二信号输出点和恒压低电位；
第十七薄膜晶体管，其栅极输入第三控制信号，源极和漏极分别连接第n级GOA电路单元的第一信号输出点和第十八薄膜晶体管的第一源极/漏极；
第十八薄膜晶体管，其栅极输入第三控制信号，第二源极/漏极连接第n级GOA电路单元的第一节点；
第十九薄膜晶体管，其栅极输入第三控制信号，第一源极/漏极连接第n级GOA电路单元的第一节点，第二源极/漏极连接第二十薄膜晶体管的第一源极/漏极；
第二十薄膜晶体管，其栅极输入第三控制信号，第二源极/漏极连接第n级GOA电路单元的第二信号输出点。
其中，该第一时钟信号和第二时钟信号为占空比为0.25的矩形波，该 第一时钟信号和第二时钟信号之间相位相差二分之一周期。
其中，正常显示状态下，该第一控制信号、第二控制信号交替为高电平，第三控制信号一直为低电平。
其中，低功率显示状态下，第一控制信号、第二控制信号均为低电平，第三控制信号一直为高电平。
其中，对于最初一级GOA电路单元，正向扫描开始时，从该第n-2级GOA电路单元的第一节点输入高电平信号作为启动信号。
其中，对于最后一级GOA电路单元，反向扫描开始时，从该第n+2级GOA电路单元的第一节点输入高电平信号作为启动信号。
其中，该低功率显示状态为待机模式。
其中，该低功率显示状态为省电模式。
本发明还提供一种GOA电路，包括级联的多个GOA电路单元，设n为自然数，负责输出第2n-1行和第2n行水平扫描信号的第n级GOA电路单元包括：
第一薄膜晶体管，其栅极连接第n-2级GOA电路单元的第一节点，源极和漏极分别连接第二节点和输入正向扫描控制信号；
第二薄膜晶体管，其栅极连接第三节点，源极和漏极分别连接第n级GOA电路单元的第一节点和输入第一时钟信号；
第三薄膜晶体管，其栅极连接第n+2级GOA电路单元的第一节点，源极和漏极分别连接第二节点和输入反向扫描控制信号；
第四薄膜晶体管，其栅极连接第四节点，源极和漏极分别连接第n级GOA电路单元的第一节点和恒压低电位；
第五薄膜晶体管，其栅极连接恒压高电位，源极和漏极分别连接第二节点和第三节点；
第六薄膜晶体管，其栅极连接第四节点，源极和漏极分别连接第二节点和恒压低电位；
第七薄膜晶体管，其栅极连接第二节点，源极和漏极分别连接第四节点和恒压低电位；
第八薄膜晶体管，其栅极输入第二时钟信号，源极和漏极分别连接第四节点和恒压高电位；
第九薄膜晶体管，其栅极输入第一控制信号，第一源极/漏极连接第n级GOA电路单元的第一节点，第二源极/漏极连接第十一薄膜晶体管和第十二薄膜晶体管的第一源极/漏极；
第十薄膜晶体管，其栅极输入第二控制信号，第一源极/漏极连接第n 级GOA电路单元的第一节点，第二源极/漏极连接第十三薄膜晶体管和第十四薄膜晶体管的第一源极/漏极；
第十一薄膜晶体管，其栅极输入第一控制信号，第二源极/漏极连接第n级GOA电路单元的第一信号输出点；
第十二薄膜晶体管，其栅极输入第二控制信号，第二源极/漏极连接恒压低电位；
第十三薄膜晶体管，其栅极输入第一控制信号，第二源极/漏极连接恒压低电位；
第十四薄膜晶体管，其栅极输入第二控制信号，第二源极/漏极连接第n级GOA电路单元的第二信号输出点；
第一电容，其两端分别连接第三节点和第n级GOA电路单元的第一节点；
第二电容，其两端分别连接第四节点和恒压低电位；
其中，该第n级GOA电路单元还包括：
第十五薄膜晶体管，其栅极输入第二控制信号，源极和漏极分别连接第n级GOA电路单元的第一信号输出点和恒压低电位；
第十六薄膜晶体管，其栅极输入第一控制信号，源极和漏极分别连接第n级GOA电路单元的第二信号输出点和恒压低电位；
第十七薄膜晶体管，其栅极输入第三控制信号，源极和漏极分别连接第n级GOA电路单元的第一信号输出点和第十八薄膜晶体管的第一源极/漏极；
第十八薄膜晶体管，其栅极输入第三控制信号，第二源极/漏极连接第n级GOA电路单元的第一节点；
第十九薄膜晶体管，其栅极输入第三控制信号，第一源极/漏极连接第n级GOA电路单元的第一节点，第二源极/漏极连接第二十薄膜晶体管的第一源极/漏极；
第二十薄膜晶体管，其栅极输入第三控制信号，第二源极/漏极连接第n级GOA电路单元的第二信号输出点；
其中，对于最初一级GOA电路单元，正向扫描开始时，从该第n-2级GOA电路单元的第一节点输入高电平信号作为启动信号；
其中，对于最后一级GOA电路单元，反向扫描开始时，从该第n+2级GOA电路单元的第一节点输入高电平信号作为启动信号。
综上，本发明提供一种GOA电路，可以有效的减小GOA电路所占的布局空间，对发展窄边框技术起到一定的帮助作用；在一些特殊的显示模 式下能够降低面板的驱动功耗。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其他有益效果显而易见。
附图中，
图1为现有的GOA电路示意图；
图2为图1的GOA电路正向扫描时序示意图；
图3为图1的GOA电路反向扫描时序示意图；
图4为本发明的GOA电路第二较佳实施例的示意图；
图5为图4的GOA电路正向扫描时序示意图；
图6为图4的GOA电路反向扫描时序示意图；
图7为本发明的GOA电路第二较佳实施例对应数据驱动的示意图；
图8为本发明的GOA电路第一较佳实施例的示意图；
图9为图8的GOA电路正向扫描时序示意图；
图10为图8的GOA电路反向扫描时序示意图。
具体实施方式
参见图8，其为本发明的GOA电路第一较佳实施例的示意图，本发明的GOA电路包括级联的多个GOA电路单元，设n为自然数，负责输出第2n-1行和第2n行水平扫描信号的第n级GOA电路单元包括：
薄膜晶体管T1，其栅极连接第n-2级GOA电路单元的节点Wn-2，源极和漏极分别连接节点Hn和输入正向扫描控制信号U2D；
薄膜晶体管T2，其栅极连接节点Qn，源极和漏极分别连接第n级GOA电路单元的节点Wn和输入时钟信号CKV1；
薄膜晶体管T3，其栅极连接第n+2级GOA电路单元的节点Wn+2，源极和漏极分别连接节点Hn和输入反向扫描控制信号D2U；
薄膜晶体管T4，其栅极连接节点Pn，源极和漏极分别连接第n级GOA电路单元的节点Wn和恒压低电位VGL；
薄膜晶体管T5，其栅极连接恒压高电位VGH，源极和漏极分别连接节点Hn和节点Qn；
薄膜晶体管T6，其栅极连接节点Pn，源极和漏极分别连接节点Hn和恒压低电位VGL；
薄膜晶体管T7，其栅极连接节点Hn，源极和漏极分别连接节点Pn和 恒压低电位VGL；
薄膜晶体管T8，其栅极输入时钟信号CKV3，源极和漏极分别连接节点Pn和恒压高电位VGH；
薄膜晶体管T9，其栅极输入控制信号Select1，第一源极/漏极连接第n级GOA电路单元的节点Wn，第二源极/漏极连接薄膜晶体管T11和薄膜晶体管T12的第一源极/漏极；
薄膜晶体管T10，其栅极输入控制信号Select2，第一源极/漏极连接第n级GOA电路单元的节点Wn，第二源极/漏极连接薄膜晶体管T13和薄膜晶体管T14的第一源极/漏极；
薄膜晶体管T11，其栅极输入控制信号Select1，第二源极/漏极连接第n级GOA电路单元的信号输出点G2n-1；
薄膜晶体管T12，其栅极输入控制信号Select2，第二源极/漏极连接恒压低电位VGL；
薄膜晶体管T13，其栅极输入控制信号Select1，第二源极/漏极连接恒压低电位VGL；
薄膜晶体管T14，其栅极输入控制信号Select2，第二源极/漏极连接第n级GOA电路单元的信号输出点G2n；
电容C1，其两端分别连接节点Qn和第n级GOA电路单元的节点Wn；
电容C2，其两端分别连接节点Pn和恒压低电位VGL。
图8中虚线框部分为GOA电路的正反向扫描单元。
参见图9，其为图8的GOA电路正向扫描时序示意图。现结合图8，对电路的具体工作过程(正向扫描)介绍如下：
以输出G2n-1和G2n行扫描信号的Wn级GOA单元为例；正向扫描时：U2D为高电平，D2U为低电平；
阶段1，预充电：Wn-2与U2D同时为高电平，T1导通，Hn点被预充电。当Hn点为高时，T5处于导通状态，Qn点被预充电。当Hn点为高时，T7处于导通状态，Pn点被拉低；
阶段2，Wn输出高电平：在阶段1中，Q点被预充电，C1对电荷具有一定的保持作用，T2处于导通状态，CKV1的高电平输出到Wn端；
阶段3，Wn输出低电平：C1对Qn点的高电平具有保持作用，而此时CKV1的低电平将Wn点拉低；
阶段4，Qn点拉低到VGL：当Wn+2为高电平，此时D2U为低电平，T3处于导通的状态，那么Qn点被拉低到VGL；
阶段5，Qn点及Wn点低电平维持阶段：当Qn点变为低电平后，T7 处于截止状态，当CKV3跳变为高电平时T8导通，Pn点被充电，那么T4和T6均处于导通的状态，可以保证Qn点及Wn点低电平的稳定，同时C2对Pn点的高电平具有一定的保持作用。
本发明与现有技术的主要区别在于引入了T9～T14组成的控制单元。在Wn输出为低电平时，Select1对应高电平，T9、T11处于打开的状态，G2n-1被拉低。Select2对应高电平，T10、T14处于打开的状态，G2n被拉低。当在Wn输出为高电平时，Select1对应高电平，T9、T11处于打开的状态，G2n-1被拉拉高。Select2对应高电平，T10、T14处于打开的状态，G2n被拉高。
由图9可见，时钟信号CKV1和时钟信号CKV3为占空比为0.25的矩形波，该时钟信号CKV1和时钟信号CKV3之间相位相差二分之一周期。
对于最初一级GOA电路单元，正向扫描开始时，需要在该第n-2级GOA电路单元的第一节点Wn-2输入高电平信号作为启动信号。
参见图10，其为图8的GOA电路反向扫描时序示意图。现结合图8，对电路的具体工作过程(反向扫描)介绍如下：
以输出G2n-1和G2n行扫描信号的Wn级GOA单元为例；正向扫描时：D2U为高电平，U2D为低电平；
阶段1，预充电：Wn+2与D2U同时为高电平，T3导通，Hn点被预充电。当Hn点为高时，T5处于导通状态，Qn点被预充电。当Hn点为高时，T7处于导通状态，Pn点被拉低；
阶段2，Wn输出高电平：在阶段1中，Qn点被预充电，C1对电荷具有一定的保持作用，T2处于导通状态，CKV1的高电平输出到Wn端；
阶段3，Wn输出低电平：C1对Qn点的高电平具有保持作用，而此时CKV1的低电平将Wn点拉低；
阶段4，Qn点拉低到VGL：当Gn-2为高电平，此时U2D为低电平，T1处于导通的状态，那么Qn点被拉低到VGL；
阶段5，Qn点及Wn点低电平维持阶段：当Qn点变为低电平后，T7处于截止状态，当CKV3跳变为高电平时T8导通，Pn点被充电，那么T4和T6均处于导通的状态，可以保证Qn点及Wn点低电平的稳定，同时C2对Pn点的高电平具有一定的保持作用。
本发明与现有技术的主要区别在于引入了T9～T14组成的控制单元。在Wn输出为低电平时，Select2对应高电平，T10、T14处于打开的状态，G2n被拉低。Select1对应高电平，T9、T11处于打开的状态，G2n-1被拉低。当在Wn输出为高电平时，Select2对应高电平，T10、T14处于打开的 状态，G2n被拉高。Select1对应高电平，T9、T11处于打开的状态，G2n-1被拉高。
对于最后一级GOA电路单元，反向扫描开始时，需要在该第n+2级GOA电路单元的第一节点Wn+2输入高电平信号作为启动信号。
本发明第一较佳实施例提出了在现有的GOA架构的基础上增加某一控制单元，将某一级GOA输出通过该控制单元分解成两级GOA输出。这样与现有两级GOA输出就需要两级GOA电路级联的方式相比，一定程度上可以减小GOA所占的布局空间，对于发展窄边框技术起到了一定的帮助作用。
参见图4，其为本发明的GOA电路第二较佳实施例的示意图，本发明的GOA电路包括级联的多个GOA电路单元，设n为自然数，负责输出第2n-1行和第2n行水平扫描信号的第n级GOA电路单元包括：
薄膜晶体管T1，其栅极连接第n-2级GOA电路单元的节点Wn-2，源极和漏极分别连接节点Hn和输入正向扫描控制信号U2D；
薄膜晶体管T2，其栅极连接节点Qn，源极和漏极分别连接第n级GOA电路单元的节点Wn和输入时钟信号CKV1；
薄膜晶体管T3，其栅极连接第n+2级GOA电路单元的节点Wn+2，源极和漏极分别连接节点Hn和输入反向扫描控制信号D2U；
薄膜晶体管T4，其栅极连接节点Pn，源极和漏极分别连接第n级GOA电路单元的节点Wn和恒压低电位VGL；
薄膜晶体管T5，其栅极连接恒压高电位VGH，源极和漏极分别连接节点Hn和节点Qn；
薄膜晶体管T6，其栅极连接节点Pn，源极和漏极分别连接节点Hn和恒压低电位VGL；
薄膜晶体管T7，其栅极连接节点Hn，源极和漏极分别连接节点Pn和恒压低电位VGL；
薄膜晶体管T8，其栅极输入时钟信号CKV3，源极和漏极分别连接节点Pn和恒压高电位VGH；
薄膜晶体管T9，其栅极输入控制信号Select1，第一源极/漏极连接第n级GOA电路单元的节点Wn，第二源极/漏极连接薄膜晶体管T11和薄膜晶体管T12的第一源极/漏极；
薄膜晶体管T10，其栅极输入控制信号Select2，第一源极/漏极连接第n级GOA电路单元的节点Wn，第二源极/漏极连接薄膜晶体管T13和薄膜晶体管T14的第一源极/漏极；
薄膜晶体管T11，其栅极输入控制信号Select1，第二源极/漏极连接第n级GOA电路单元的信号输出点G2n-1；
薄膜晶体管T12，其栅极输入控制信号Select2，第二源极/漏极连接恒压低电位VGL；
薄膜晶体管T13，其栅极输入控制信号Select1，第二源极/漏极连接恒压低电位VGL；
薄膜晶体管T14，其栅极输入控制信号Select2，第二源极/漏极连接第n级GOA电路单元的信号输出点G2n；
薄膜晶体管T15，其栅极输入控制信号Select2，源极和漏极分别连接第n级GOA电路单元的信号输出点G2n-1和恒压低电位VGL；
薄膜晶体管T16，其栅极输入控制信号Select1，源极和漏极分别连接第n级GOA电路单元的信号输出点G2n和恒压低电位VGL；
薄膜晶体管T17，其栅极输入控制信号Select3，源极和漏极分别连接第n级GOA电路单元的信号输出点G2n-1和薄膜晶体管T18的第一源极/漏极；
薄膜晶体管T18，其栅极输入控制信号Select3，第二源极/漏极连接第n级GOA电路单元的节点Wn；
薄膜晶体管T19，其栅极输入控制信号Select3，第一源极/漏极连接第n级GOA电路单元的节点Wn，第二源极/漏极连接薄膜晶体管T20的第一源极/漏极；
薄膜晶体管T20，其栅极输入控制信号Select3，第二源极/漏极连接第n级GOA电路单元的信号输出点G2n；
电容C1，其两端分别连接节点Qn和第n级GOA电路单元的节点Wn；
电容C2，其两端分别连接节点Pn和恒压低电位VGL。
图4中虚线框部分为GOA电路的正反向扫描单元。
参见图5，其为图4的GOA电路正向扫描时序示意图。现结合图4，对电路的具体工作过程(正向扫描)介绍如下：
正常显示状态下，Select1、Select2交替为高电平，Select3一直输出为低电平；
以输出G2n-1和G2n行扫描信号的Wn级GOA单元为例；正向扫描时：U2D为高电平，D2U为低电平；
阶段1，预充电：Wn-2与U2D同时为高电平，T1导通，Hn点被预充电。当Hn点为高时，T5处于导通状态，Qn点被预充电。当Hn点为高时，T7处于导通状态，Pn点被拉低；
阶段2，Wn输出高电平：在阶段1中，Q点被预充电，C1对电荷具有一定的保持作用，T2处于导通状态，CKV1的高电平输出到Wn端；
阶段3，Wn输出低电平：C1对Qn点的高电平具有保持作用，而此时CKV1的低电平将Wn点拉低；
阶段4，Qn点拉低到VGL：当Wn+2为高电平，此时D2U为低电平，T3处于导通的状态，那么Qn点被拉低到VGL；
阶段5，Qn点及Wn点低电平维持阶段：当Qn点变为低电平后，T7处于截止状态，当CKV3跳变为高电平时T8导通，Pn点被充电，那么T4和T6均处于导通的状态，可以保证Qn点及Wn点低电平的稳定，同时C2对Pn点的高电平具有一定的保持作用。
本发明在Wn输出为低电平时，Select1对应高电平，T9、T11处于打开的状态，G2n-1被拉低。Select2对应高电平，T10、T14处于打开的状态，G2n被拉低。当在Wn输出为高电平时，Select1对应高电平，T9、T11处于打开的状态，G2n-1被拉拉高。Select2对应高电平，T10、T14处于打开的状态，G2n被拉高。
在这一过程中，Select3一直输出为低电平，T17-T20一直处于截止状态。
低功率显示状态下，Select1、Select2均为低电平，Select3一直输出为高电平；
由于Select1与Select2一直处于低电平，T9-T16均处于截止状态，而此时Select3为高，T17-T20均处于导通状态，在Wn输出为高电平时，G2n-1与G2n同时输出高电平。
由图5可见，时钟信号CKV1和时钟信号CKV3为占空比为0.25的矩形波，该时钟信号CKV1和时钟信号CKV3之间相位相差二分之一周期。
对于最初一级GOA电路单元，正向扫描开始时，需要在该第n-2级GOA电路单元的第一节点Wn-2输入高电平信号作为启动信号。
参见图6，其为图4的GOA电路反向扫描时序示意图。现结合图4，对电路的具体工作过程(反向扫描)介绍如下：
正常显示状态下，Select1、Select2交替为高电平，Select3一直输出为低电平；
以输出G2n-1和G2n行扫描信号的Wn级GOA单元为例；正向扫描时：D2U为高电平，U2D为低电平；
阶段1，预充电：Wn+2与D2U同时为高电平，T3导通，Hn点被预充电。当Hn点为高时，T5处于导通状态，Qn点被预充电。当Hn点为高时， T7处于导通状态，Pn点被拉低；
阶段2，Wn输出高电平：在阶段1中，Qn点被预充电，C1对电荷具有一定的保持作用，T2处于导通状态，CKV1的高电平输出到Wn端；
阶段3，Wn输出低电平：C1对Qn点的高电平具有保持作用，而此时CKV1的低电平将Wn点拉低；
阶段4，Qn点拉低到VGL：当Gn-2为高电平，此时U2D为低电平，T1处于导通的状态，那么Qn点被拉低到VGL；
阶段5，Qn点及Wn点低电平维持阶段：当Qn点变为低电平后，T7处于截止状态，当CKV3跳变为高电平时T8导通，Pn点被充电，那么T4和T6均处于导通的状态，可以保证Qn点及Wn点低电平的稳定，同时C2对Pn点的高电平具有一定的保持作用。
本发明在Wn输出为低电平时，Select2对应高电平，T10、T14处于打开的状态，G2n被拉低。Select1对应高电平，T9、T11处于打开的状态，G2n-1被拉低。当在Wn输出为高电平时，Select2对应高电平，T10、T14处于打开的状态，G2n被拉高。Select1对应高电平，T9、T11处于打开的状态，G2n-1被拉高。
在这一过程中，Select3一直输出为低电平，T17-T20一直处于截止状态。
低功率显示状态下，Select1、Select2均为低电平，Select3一直输出为高电平；
由于Select1与Select2一直处于低电平，T9-T16均处于截止状态，而此时Select3为高，T17-T20均处于导通状态，在Wn输出为高电平时，G2n-1与G2n同时输出高电平。
对于最后一级GOA电路单元，反向扫描开始时，需要在该第n+2级GOA电路单元的第一节点Wn+2输入高电平信号作为启动信号。
图7为本发明的GOA电路第二较佳实施例对应数据驱动的示意图，结合图4-6可知，本发明第二较佳实施例在现有的GOA架构的基础上增加一控制单元，在现有的GOA电路的基础上引入3个控制信号，Select1、Select2、Select3，其中Select1、Select2为一组相位相反信号，主要作用是将GOA栅极输出一分为二；在一些特殊的显示模式下：例如待机模式、或者省电模式下，Select3在Select1、Select2均输出为低时输出高电平，将上述的两级输出变为同一输出信号，也就是第一级与第二级栅极输出一样、第三级与第四级栅极输出一样、以此类推，那么此时数据(Data)信号的对应的频率将会减半，对应的驱动功耗也会降低。
本发明的GOA电路已知和潜在的技术/产品应用领域及其应用方式如下：1、集成在阵列基板上的液晶显示器行扫描(Gate)驱动电路；2、应用于手机，显示器，电视的栅极驱动领域；3、可涵盖LCD和OLED的行业先进技术；4、本电路的稳定性适用于高解析度的面板设计当中。
综上，本发明提供一种GOA电路，可以有效的减小GOA电路所占的布局空间，对发展窄边框技术起到一定的帮助作用；在一些特殊的显示模式下能够降低面板的驱动功耗。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。

Claims (15)

  1. 一种GOA电路，包括级联的多个GOA电路单元，设n为自然数，负责输出第2n-1行和第2n行水平扫描信号的第n级GOA电路单元包括：
    第一薄膜晶体管，其栅极连接第n-2级GOA电路单元的第一节点，源极和漏极分别连接第二节点和输入正向扫描控制信号；
    第二薄膜晶体管，其栅极连接第三节点，源极和漏极分别连接第n级GOA电路单元的第一节点和输入第一时钟信号；
    第三薄膜晶体管，其栅极连接第n+2级GOA电路单元的第一节点，源极和漏极分别连接第二节点和输入反向扫描控制信号；
    第四薄膜晶体管，其栅极连接第四节点，源极和漏极分别连接第n级GOA电路单元的第一节点和恒压低电位；
    第五薄膜晶体管，其栅极连接恒压高电位，源极和漏极分别连接第二节点和第三节点；
    第六薄膜晶体管，其栅极连接第四节点，源极和漏极分别连接第二节点和恒压低电位；
    第七薄膜晶体管，其栅极连接第二节点，源极和漏极分别连接第四节点和恒压低电位；
    第八薄膜晶体管，其栅极输入第二时钟信号，源极和漏极分别连接第四节点和恒压高电位；
    第九薄膜晶体管，其栅极输入第一控制信号，第一源极/漏极连接第n级GOA电路单元的第一节点，第二源极/漏极连接第十一薄膜晶体管和第十二薄膜晶体管的第一源极/漏极；
    第十薄膜晶体管，其栅极输入第二控制信号，第一源极/漏极连接第n级GOA电路单元的第一节点，第二源极/漏极连接第十三薄膜晶体管和第十四薄膜晶体管的第一源极/漏极；
    第十一薄膜晶体管，其栅极输入第一控制信号，第二源极/漏极连接第n级GOA电路单元的第一信号输出点；
    第十二薄膜晶体管，其栅极输入第二控制信号，第二源极/漏极连接恒压低电位；
    第十三薄膜晶体管，其栅极输入第一控制信号，第二源极/漏极连接恒压低电位；
    第十四薄膜晶体管，其栅极输入第二控制信号，第二源极/漏极连接第 n级GOA电路单元的第二信号输出点；
    第一电容，其两端分别连接第三节点和第n级GOA电路单元的第一节点；
    第二电容，其两端分别连接第四节点和恒压低电位。
  2. 如权利要求1所述的GOA电路，其中，该第n级GOA电路单元还包括：
    第十五薄膜晶体管，其栅极输入第二控制信号，源极和漏极分别连接第n级GOA电路单元的第一信号输出点和恒压低电位；
    第十六薄膜晶体管，其栅极输入第一控制信号，源极和漏极分别连接第n级GOA电路单元的第二信号输出点和恒压低电位；
    第十七薄膜晶体管，其栅极输入第三控制信号，源极和漏极分别连接第n级GOA电路单元的第一信号输出点和第十八薄膜晶体管的第一源极/漏极；
    第十八薄膜晶体管，其栅极输入第三控制信号，第二源极/漏极连接第n级GOA电路单元的第一节点；
    第十九薄膜晶体管，其栅极输入第三控制信号，第一源极/漏极连接第n级GOA电路单元的第一节点，第二源极/漏极连接第二十薄膜晶体管的第一源极/漏极；
    第二十薄膜晶体管，其栅极输入第三控制信号，第二源极/漏极连接第n级GOA电路单元的第二信号输出点。
  3. 如权利要求1所述的GOA电路，其中，该第一时钟信号和第二时钟信号为占空比为0.25的矩形波，该第一时钟信号和第二时钟信号之间相位相差二分之一周期。
  4. 如权利要求2所述的GOA电路，其中，正常显示状态下，该第一控制信号、第二控制信号交替为高电平，第三控制信号一直为低电平。
  5. 如权利要求2所述的GOA电路，其中，低功率显示状态下，第一控制信号、第二控制信号均为低电平，第三控制信号一直为高电平。
  6. 如权利要求1所述的GOA电路，其中，对于最初一级GOA电路单元，正向扫描开始时，从该第n-2级GOA电路单元的第一节点输入高电平信号作为启动信号。
  7. 如权利要求1所述的GOA电路，其中，对于最后一级GOA电路单元，反向扫描开始时，从该第n+2级GOA电路单元的第一节点输入高电平信号作为启动信号。
  8. 如权利要求5所述的GOA电路，其中，该低功率显示状态为待机 模式。
  9. 如权利要求5所述的GOA电路，其中，该低功率显示状态为省电模式。
  10. 一种GOA电路，包括级联的多个GOA电路单元，设n为自然数，负责输出第2n-1行和第2n行水平扫描信号的第n级GOA电路单元包括：
    第一薄膜晶体管，其栅极连接第n-2级GOA电路单元的第一节点，源极和漏极分别连接第二节点和输入正向扫描控制信号；
    第二薄膜晶体管，其栅极连接第三节点，源极和漏极分别连接第n级GOA电路单元的第一节点和输入第一时钟信号；
    第三薄膜晶体管，其栅极连接第n+2级GOA电路单元的第一节点，源极和漏极分别连接第二节点和输入反向扫描控制信号；
    第四薄膜晶体管，其栅极连接第四节点，源极和漏极分别连接第n级GOA电路单元的第一节点和恒压低电位；
    第五薄膜晶体管，其栅极连接恒压高电位，源极和漏极分别连接第二节点和第三节点；
    第六薄膜晶体管，其栅极连接第四节点，源极和漏极分别连接第二节点和恒压低电位；
    第七薄膜晶体管，其栅极连接第二节点，源极和漏极分别连接第四节点和恒压低电位；
    第八薄膜晶体管，其栅极输入第二时钟信号，源极和漏极分别连接第四节点和恒压高电位；
    第九薄膜晶体管，其栅极输入第一控制信号，第一源极/漏极连接第n级GOA电路单元的第一节点，第二源极/漏极连接第十一薄膜晶体管和第十二薄膜晶体管的第一源极/漏极；
    第十薄膜晶体管，其栅极输入第二控制信号，第一源极/漏极连接第n级GOA电路单元的第一节点，第二源极/漏极连接第十三薄膜晶体管和第十四薄膜晶体管的第一源极/漏极；
    第十一薄膜晶体管，其栅极输入第一控制信号，第二源极/漏极连接第n级GOA电路单元的第一信号输出点；
    第十二薄膜晶体管，其栅极输入第二控制信号，第二源极/漏极连接恒压低电位；
    第十三薄膜晶体管，其栅极输入第一控制信号，第二源极/漏极连接恒压低电位；
    第十四薄膜晶体管，其栅极输入第二控制信号，第二源极/漏极连接第 n级GOA电路单元的第二信号输出点；
    第一电容，其两端分别连接第三节点和第n级GOA电路单元的第一节点；
    第二电容，其两端分别连接第四节点和恒压低电位；
    其中，该第n级GOA电路单元还包括：
    第十五薄膜晶体管，其栅极输入第二控制信号，源极和漏极分别连接第n级GOA电路单元的第一信号输出点和恒压低电位；
    第十六薄膜晶体管，其栅极输入第一控制信号，源极和漏极分别连接第n级GOA电路单元的第二信号输出点和恒压低电位；
    第十七薄膜晶体管，其栅极输入第三控制信号，源极和漏极分别连接第n级GOA电路单元的第一信号输出点和第十八薄膜晶体管的第一源极/漏极；
    第十八薄膜晶体管，其栅极输入第三控制信号，第二源极/漏极连接第n级GOA电路单元的第一节点；
    第十九薄膜晶体管，其栅极输入第三控制信号，第一源极/漏极连接第n级GOA电路单元的第一节点，第二源极/漏极连接第二十薄膜晶体管的第一源极/漏极；
    第二十薄膜晶体管，其栅极输入第三控制信号，第二源极/漏极连接第n级GOA电路单元的第二信号输出点；
    其中，对于最初一级GOA电路单元，正向扫描开始时，从该第n-2级GOA电路单元的第一节点输入高电平信号作为启动信号；
    其中，对于最后一级GOA电路单元，反向扫描开始时，从该第n+2级GOA电路单元的第一节点输入高电平信号作为启动信号。
  11. 如权利要求10所述的GOA电路，其中，该第一时钟信号和第二时钟信号为占空比为0.25的矩形波，该第一时钟信号和第二时钟信号之间相位相差二分之一周期。
  12. 如权利要求10所述的GOA电路，其中，正常显示状态下，该第一控制信号、第二控制信号交替为高电平，第三控制信号一直为低电平。
  13. 如权利要求10所述的GOA电路，其中，低功率显示状态下，第一控制信号、第二控制信号均为低电平，第三控制信号一直为高电平。
  14. 如权利要求13所述的GOA电路，其中，该低功率显示状态为待机模式。
  15. 如权利要求13所述的GOA电路，其中，该低功率显示状态为省电模式。
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