WO2018119958A1 - 薄膜晶体管和薄膜晶体管的制备方法和阵列基板 - Google Patents

薄膜晶体管和薄膜晶体管的制备方法和阵列基板 Download PDF

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WO2018119958A1
WO2018119958A1 PCT/CN2016/113295 CN2016113295W WO2018119958A1 WO 2018119958 A1 WO2018119958 A1 WO 2018119958A1 CN 2016113295 W CN2016113295 W CN 2016113295W WO 2018119958 A1 WO2018119958 A1 WO 2018119958A1
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layer
drain
active layer
source
thin film
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PCT/CN2016/113295
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English (en)
French (fr)
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陈小明
赵晓辉
曹慧敏
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深圳市柔宇科技有限公司
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Priority to CN201680049276.6A priority Critical patent/CN108064419A/zh
Priority to PCT/CN2016/113295 priority patent/WO2018119958A1/zh
Publication of WO2018119958A1 publication Critical patent/WO2018119958A1/zh

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    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78663—Amorphous silicon transistors
    • H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Definitions

  • the present invention relates to the field of transistors, and more particularly to a method of fabricating a thin film transistor and a thin film transistor and an array substrate.
  • a thin film transistor is widely used in an array substrate.
  • an active layer of a thin film transistor is easily etched by an etching solution in a step of preparing a source/drain. And destroy the original electrical characteristics.
  • a protective layer is formed on the active layer to protect the active layer before the step of preparing the source/drain.
  • the arrangement of the protective layer causes the resistance between the active layer and the source/drain to become large, which is disadvantageous for improving the electrical characteristics of the thin film transistor.
  • embodiments of the present invention aim to at least solve one of the technical problems existing in the related art. To this end, embodiments of the present invention need to provide a method of fabricating a thin film transistor and a thin film transistor and an array substrate.
  • a thin film transistor includes a gate, an active layer, a source, a drain, a first protective layer, and a second protective layer, the first protective layer being located at the source and the active And connecting the source and the active layer between the layers, the second protective layer being located between the drain and the active layer and connecting the drain and the active layer,
  • the first protective layer and the second protective layer each include at least two sub-layers stacked, the doping concentrations of the at least two sub-layers being different.
  • the protective layer connecting the active layer and the source/drain includes at least two sub-layers having different doping concentrations, so that the active layer and the source/drain can be optimized in the case where the protective layer is provided The contact resistance between them improves the electrical characteristics of the thin film transistor.
  • the protective layer comprising at least two sub-layers stacked, the doping concentrations of the at least two sub-layers being different;
  • An array substrate according to an embodiment of the present invention includes the above thin film transistor.
  • the protective layer connecting the active layer and the source/drain includes at least two sub-layers having different doping concentrations, so that the active layer and the source/drain can be optimized in the case where the protective layer is provided.
  • the contact resistance between them improves the electrical characteristics of the thin film transistor.
  • FIG. 1 is a schematic structural view of a thin film transistor according to an embodiment of the present invention.
  • FIG. 2 is a schematic structural view of a thin film transistor in the related art
  • 3 is a comparison diagram of transfer curves of a thin film transistor
  • FIG. 4 and FIG. 5 are comparison diagrams of leakage current and on-state current of a TFT having no amorphous silicon layer and a TFT having an amorphous silicon layer (heavily doped), respectively;
  • FIG. 6 to FIG. 8 are energy band diagrams of an amorphous silicon-free TFT, an amorphous silicon (heavily doped) TFT, and an amorphous silicon (intrinsic) TFT, respectively;
  • FIG. 9 is a Fermi level diagram of a metal, amorphous silicon, and active layer of a thin film transistor
  • 10 is another Fermi level diagram of a metal, amorphous silicon, and active layer of a thin film transistor
  • FIG. 11 is a partial schematic structural view of a thin film transistor according to an embodiment of the present invention.
  • FIG. 12 is a schematic flow chart of a method of fabricating a thin film transistor according to an embodiment of the present invention.
  • FIG. 13 is a schematic view showing the process of a method of fabricating a thin film transistor according to an embodiment of the present invention.
  • first and second are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated.
  • features defining “first” or “second” may include one or more of the described features either explicitly or implicitly.
  • the meaning of "a plurality" is two or more unless specifically and specifically defined otherwise.
  • connecting should be understood broadly, unless it is specifically defined and defined, for example, it may be a fixed connection, a detachable connection, or an integral connection; They are mechanical connections, they can be electrically connected or can communicate with each other; they can be directly connected or indirectly connected through an intermediate medium, which can be the internal communication of two elements or the interaction of two elements.
  • intermediate medium which can be the internal communication of two elements or the interaction of two elements.
  • a thin film transistor 100 includes a gate 102 , an active layer 104 , a source 106 , a drain 108 , a first protective layer 110 , and a second protective layer 112 .
  • the layer 110 is located between the source 106 and the active layer 104 and connects the source 106 and the active layer 104.
  • the second protection layer 112 is located between the drain 108 and the active layer 104 and connects the drain 108 and the active layer 104.
  • the first protective layer 110 and the second protective layer 112 each include at least two sub-layers 114 stacked, and the doping concentrations of the at least two sub-layers 114 are different.
  • the protective layer connecting the active layer 104 and the source 106/drain 108 includes at least two sub-layers 114 having different doping concentrations, and thus, in the case where the protective layer is provided, the active layer 104 can be optimized.
  • the contact resistance between the source 106 and the drain 108 improves the electrical characteristics of the thin film transistor 100.
  • the thin film transistor (TFT) 100 is a back channel etch (BCE) thin film transistor.
  • the thin film transistor 100 further includes a substrate 115 as a bottom layer of the thin film transistor 100.
  • a gate insulating layer 116 is formed between the active layer 104, the source 106, and the drain 108 and the gate 102.
  • the gate electrode 102 and the gate insulating layer 116 are disposed on the substrate 115, and the source 106, the drain electrode 108, and the active layer 104 are disposed on the gate insulating layer 116.
  • a first protective layer 110 and a second protective layer 112 are respectively added between the source 106/drain 108 and the active layer 104.
  • the protective layer is, for example, an amorphous silicon layer, and the amorphous silicon layer can not only protect the active layer.
  • Layer 104 also capable of acting as an electron injection layer, reduces the electron injection barrier.
  • FIG. 2 is a structure of the thin film transistor 200 in the related art
  • FIG. 1 is an embodiment of the present invention.
  • the structure of the thin film transistor 100 The material of the active layer 104 of FIGS. 1 and 2 may be amorphous silicon or an oxide semiconductor. In the following description, indium gallium zinc oxide (IGZO) is used as the active layer 104, and aluminum is used. The work function is set to 4.3eV) As a material of the source 106/drain 108, the thin film transistor 100 is a TFT having an amorphous silicon layer (heavily doped).
  • 3 is a transfer curve of a TFT, which simulates a TFT having no amorphous silicon layer, a TFT having an amorphous silicon layer (heavily doped), and a TFT having an amorphous silicon layer (intrinsic).
  • 4 and 5 are comparisons of leakage current and on-state current of a TFT having no amorphous silicon layer and a TFT having an amorphous silicon layer (heavily doped), respectively. From this we can see the conclusion:
  • the electrical conductivity of a TFT with a heavily doped amorphous silicon layer is similar to that of a TFT without an amorphous silicon layer, but the leakage current and the on-state current of the former are slightly higher than the latter, possibly because of the heavily doped amorphous silicon layer. It is advantageous for electrons to be injected from the source into the active layer 104.
  • the intrinsic amorphous silicon layer will reduce the electrical characteristics of the TFT, possibly because the implantation barrier becomes higher.
  • the energy band diagram near the source 106 (shown by a chain line AB in Fig. 1) is compared.
  • 6 to 8 are energy band diagrams of a TFT having no amorphous silicon layer, a TFT having an amorphous silicon layer (heavily doped), and a TFT having an amorphous silicon layer (intrinsic), respectively.
  • the conduction band of IGZO is about 0.194 eV higher than the Fermi level of aluminum, and the conduction band is bent downward in contact with aluminum.
  • FIG. 1 the conduction band of IGZO is about 0.194 eV higher than the Fermi level of aluminum
  • the conduction band of the heavily doped amorphous silicon is about 0.037 eV higher than the Fermi level of aluminum, and is under the IGZO conduction band; the conduction band of the IGZO is bent downward at the contact surface.
  • the intrinsic amorphous silicon has a higher conduction band than IGZO.
  • the heavily doped amorphous silicon can reduce the injection barrier of electrons and facilitate the increase of current. It can be inferred that the electrical characteristics of the TFT can be further improved by adjusting the doping concentration of the amorphous silicon.
  • Figure 3 shows that undoped amorphous silicon reduces the current (including leakage current and on-state current) of the IGZO TFT, while the heavily doped (n-doped, concentration is 1 ⁇ 10 20 cm -3 ) amorphous Silicon can increase the current. This phenomenon can be explained in conjunction with FIGS. 7 and 8.
  • the conduction band of undoped amorphous silicon is above IGZO and metal (referred to as the Fermi level of metal, the same below) (see Figure 8), which is not conducive to electron injection; heavily doped amorphous silicon, due to impurity energy
  • the grade is broadened into an energy band that coincides with the conduction band, so the impurity can be bottomed, which is equivalent to forming a new conduction band bottom.
  • the new conduction band is located between IGZO and the metal, and closer to the metal (see Figure 7), which makes it easier for electrons to be injected into the amorphous silicon, so the current increases; however, the new conduction band is closer to the metal, meaning IGZO
  • the conduction band is still far away, and the barrier of electron injection from amorphous silicon to IGZO is still high, which is not conducive to the injection of electrons from amorphous silicon to IGZO. If the doping concentration of amorphous silicon is lowered, the new conduction band bottom will rise and approach IGZO. In the process, there must be a doping concentration, so that electrons are injected from the metal into the amorphous silicon, and then from the amorphous silicon.
  • the Fermi level of amorphous silicon When injected into IGZO, the required energy is the smallest. At this time, the Fermi level of amorphous silicon should be at the midpoint of the Fermi level of metal and IGZO, and the doping concentration should be less than 1 ⁇ 10 20 cm -3 . In other embodiments, if the work function of the metal is sufficiently low, the doping concentration of the amorphous silicon layer in contact with the metal may also be greater than or equal to 1 ⁇ 10 20 cm -3 .
  • E vac is a vacuum level
  • E FM , E F1 , E F2 are the Fermi level of metal, amorphous silicon, and active layer 104, respectively
  • ⁇ E is the work function of the metal and the active layer. Poor
  • x is the work function difference between metal and amorphous silicon. If there is no amorphous silicon layer (protective layer), according to quantum mechanics, the contact resistance between the metal and the active layer is:
  • the contact resistance is the sum of the contact resistance R MS of the metal-amorphous silicon and the resistance R SS of the amorphous silicon-active layer 104:
  • R 0 is small, and for calculation convenience, it is set to 1 ⁇ ; and R c1 is of the order of e 7 ( ⁇ 1000) ⁇ .
  • R c3 is the smallest.
  • the contact resistance of the source or the drain and the active layer is between e n ⁇ e n+1 (n is a positive integer) ⁇
  • the number of layers is n, which is most advantageous for reducing the contact resistance, so The actual situation adjusts the number of layers. Therefore, it can be qualitatively explained that the layered doping of the amorphous silicon layer can reduce the contact resistance.
  • the amorphous silicon layer can be divided into 7 sub-layers, but the number of layers can be adjusted according to actual conditions.
  • the material of the source and the drain may be a metal having a lower work function such as Ti, Al, or Mo than amorphous silicon, or a metal or metal oxide having a higher work function than amorphous silicon such as Cu, Ni, ITO, or Au.
  • the contact resistance is on the order of e 7 ( ⁇ 1000) ⁇ .
  • the doping of different concentrations of amorphous silicon at different concentrations can make the contact resistance of the metal and the active layer 104 smaller, and the amorphous silicon layer as a protective layer is divided into 7 layers having different doping concentrations.
  • the contact resistance of the metal and the active layer 104 can be minimized.
  • a feature of amorphous silicon is that whether a physical vapor deposition (PVD) method or a chemical vapor deposition (CVD) method is used, as long as a certain amount of a dopant gas such as phosphine (PH 3 ) is added to the reaction gas, Doping at various concentrations can be achieved, the process is simple, mature, and low in cost. It should be pointed out that for other materials which can be used as a protective layer, the analysis and selection of the amorphous silicon as an example can be configured and selected, and will not be mentioned here. As the material of the protective layer, when the source 106 and the drain 108 are formed by an etching process, the active layer 104 should be protected from the etching liquid.
  • PVD physical vapor deposition
  • CVD chemical vapor deposition
  • the material of the active layer 104 is indium gallium zinc oxide (IGZO), and the material of the source 106 and the drain 108 is a metal or metal oxide having a higher work function than the active layer 104, at least two The doping concentration of the sub-layers 114 is sequentially increased in the direction of the source 106 and the drain 108 to the active layer 104.
  • IGZO indium gallium zinc oxide
  • the material of the source 106 and the drain 108 is a metal or metal oxide having a higher work function than the active layer 104
  • the doping of the protective layer at different densities at different depths is achieved, so that the contact resistance of the source 106/drain 108 and the active layer 104 is small.
  • the material of the source 106 and the drain 108 may be selected from a metal or a metal oxide having a higher work function such as Cu, Ni, ITO, or Au.
  • the doping concentration of at least two sub-layers 114 is sequentially increased from the top to the bottom.
  • the number of sub-layers 114 is seven, the material of the first protective layer 110 and the second protective layer 112 is amorphous silicon, the doped element is phosphorus, and the topmost sub-layer 114 and source 106 In contact with the drain 108, the bottommost sub-layer 114 is in contact with the active layer 104.
  • the doping concentration of the seven sub-layers 114 is sequentially increased from the top to the bottom, that is, the doping concentration n1 ⁇ n2 ⁇ n3 ⁇ n4 ⁇ n5 ⁇ n6 ⁇ n7.
  • the material of the active layer 104 is indium gallium zinc oxide, source 106 and drain
  • the material of 108 is a metal having a lower work function than the active layer 104, and the doping concentration of the at least two sub-layers 114 is sequentially decreased in the direction of the source 106 and the drain 108 to the active layer 104.
  • the doping of the protective layer at different densities at different depths is achieved, so that the contact resistance of the source 106/drain 108 and the active layer 104 is small.
  • the material of the source 106 and the drain 108 may be selected from metals having a lower work function such as Ti, Al, or Mo.
  • the doping concentration of at least two sub-layers 114 is successively decreased from top to bottom.
  • the number of sub-layers 114 is seven, the material of the first protective layer 110 and the second protective layer 112 is amorphous silicon, the doped element is phosphorus, and the topmost sub-layer 114 and source 106 In contact with the drain 108, the bottommost sub-layer 114 is in contact with the active layer 104.
  • the doping concentration of the seven sub-layers 114 is sequentially decreased from top to bottom, that is, the doping concentration n1>n2>n3>n4>n5>n6>n7.
  • the material of the active layer 104 is amorphous silicon
  • the material of the source 106 and the drain 108 is a metal or metal oxide having a higher work function than the active layer 104, and the at least two sub-layers 114 are doped.
  • the impurity concentration decreases in the direction of the source 106 and the drain 108 to the active layer 104 in order.
  • the doping of the protective layer at different densities at different depths is achieved, so that the contact resistance of the source 106/drain 108 and the active layer 104 is small.
  • the material of the source 106 and the drain 108 may be selected from a metal or a metal oxide having a higher work function such as Cu, Ni, ITO, or Au.
  • the doping concentration of at least two sub-layers 114 is successively decreased from top to bottom.
  • the number of sub-layers 114 is seven, the material of the first protective layer 110 and the second protective layer 112 is amorphous silicon, the doped element is boron, and the topmost sub-layer 114 and source 106 In contact with the drain 108, the bottommost sub-layer 114 is in contact with the active layer 104.
  • the doping concentration of the seven sub-layers 114 is sequentially decreased from top to bottom, that is, the doping concentration n1>n2>n3>n4>n5>n6>n7.
  • the material of the active layer 104 is amorphous silicon
  • the material of the source 106 and the drain 108 is a metal having a lower work function than the active layer 104
  • the doping concentration of at least two sub-layers 114 is along the source. The direction of the pole 106 and the drain 108 to the active layer 104 is sequentially decreased.
  • the doping of the protective layer at different densities at different depths is achieved, so that the contact resistance of the source 106/drain 108 and the active layer 104 is small.
  • the material of the source 106 and the drain 108 may be selected from metals having a lower work function such as Ti, Al, or Mo.
  • the doping concentration of at least two sub-layers 114 is successively decreased from top to bottom.
  • the number of sub-layers 114 is seven, the material of the first protective layer 110 and the second protective layer 112 is amorphous silicon, the doped element is phosphorus, and the topmost sub-layer 114 and source 106 In contact with the drain 108, the bottommost sub-layer 114 is in contact with the active layer 104.
  • the doping concentration of the seven sub-layers 114 is sequentially decreased from top to bottom, that is, the doping concentration n1>n2>n3>n4>n5>n6>n7.
  • the thin film transistor 100 further includes a passivation layer 118 covering the source 106, the drain 108, and the active layer 104, and a passivation layer 118.
  • the via hole 122 of the drain electrode 108 is exposed, the electrode layer 120 is disposed on the passivation layer 118, and the electrode layer 120 is connected to the drain electrode 108 through the via hole 122.
  • the passivation of the back channel of the active layer 104 is achieved, which contributes to the improvement of the electrical characteristics of the thin film transistor 100, and the electrode layer 120 can facilitate the external circuit to electrically connect the thin film transistor 100.
  • a method for fabricating a thin film transistor according to an embodiment of the present invention includes the following steps:
  • the cover layer 123 includes at least two sub-layers 114 stacked, and at least two sub-layers 114 have different doping concentrations;
  • a source 106 and a drain 108 are formed on the protective layer 123, and the source 106 and the drain 108 are spaced apart to form a gap 124;
  • the protective layer 123 is etched from the gap 124 to expose the active layer 104 and separate the protective layer 123 into the first protective layer 110 and the second protective layer 112.
  • the first protective layer 110 is located at the source 106 and the active layer 104.
  • the source 106 and the active layer 104 are connected in parallel, and the second protective layer 112 is located between the drain 108 and the active layer 104 and connects the drain 108 and the active layer 104.
  • the protective layer connecting the active layer 104 and the source 106/drain 108 includes at least two sub-layers 114 having different doping concentrations, so that the active layer can be optimized in the case where the protective layer is provided.
  • the contact resistance between layer 104 and source 106/drain 108 improves the electrical characteristics of the thin film transistor.
  • a first metal layer 126 is deposited on the substrate 115, and then the first metal layer 126 is patterned to form the gate 102.
  • a buffer layer is deposited on the substrate 115 prior to depositing the first metal layer 126, after which the first metal layer 126 is redeposited on the buffer layer.
  • the first metal layer 126 can be patterned by a yellow light process to form the gate 102.
  • a gate insulating layer 116 is deposited over the gate 102 to space the gate 102 apart.
  • step S12 the active layer 104 is defined by an etching process.
  • step S12 the protective layer 123 is formed on the active layer 104 by a deposition method.
  • the deposition method makes it easier to form the protective layer 123 on the active layer 104, and the cost is low.
  • methods of deposition include physical vapor deposition (PVD) methods and chemical vapor deposition (CVD) methods. Therefore, one of the deposition methods can be used according to actual needs.
  • PVD physical vapor deposition
  • CVD chemical vapor deposition
  • doping gases of different set concentrations are added to the reaction gas such that the doping concentrations of the at least two sub-layers 114 are different.
  • the doping process is simple, mature, and low in cost.
  • the material of the protective layer is amorphous silicon.
  • a certain amount of doping gas such as phosphine (PH 3 ), may be added to the reaction gas. .
  • the material of the active layer 104 is indium gallium zinc oxide
  • the material of the source 106 and the drain 108 is a metal or metal oxide having a higher work function than the active layer 104
  • at least two sub-layers 114 The doping concentration sequentially increases in the direction from the source 106 and the drain 108 to the active layer 104.
  • the number of sub-layers 114 is seven, the material of the first protective layer 110 and the second protective layer 112 is amorphous silicon, the doped element is phosphorus, and the topmost sub-layer 114 and source 106 In contact with the drain 108, the bottommost sub-layer 114 is in contact with the active layer 104.
  • the material of the active layer 104 is indium gallium zinc oxide
  • the material of the source 106 and the drain 108 is a metal having a lower work function than the active layer 104
  • the doping concentration of the at least two sub-layers 114 The direction along the source 106 and the drain 108 to the active layer 104 is sequentially decreased.
  • the number of sub-layers 114 is seven, the material of the first protective layer 110 and the second protective layer 112 is amorphous silicon, the doped element is phosphorus, and the topmost sub-layer 114 and source 106 In contact with the drain 108, the bottommost sub-layer 114 is in contact with the active layer 104.
  • the material of the active layer 104 is amorphous silicon
  • the material of the source 106 and the drain 108 is a metal or metal oxide having a higher work function than the active layer 104, and the at least two sub-layers 114 are doped.
  • the impurity concentration decreases in the direction of the source 106 and the drain 108 to the active layer 104 in order.
  • the number of sub-layers 114 is seven, the material of the first protective layer 110 and the second protective layer 112 is amorphous silicon, the doped element is boron, and the topmost sub-layer 114 and source 106 In contact with the drain 108, the bottommost sub-layer 114 is in contact with the active layer 104.
  • the material of the active layer 104 is amorphous silicon
  • the material of the source 106 and the drain 108 is a metal having a lower work function than the active layer 104
  • the doping concentration of at least two sub-layers 114 is along the source. The direction of the pole 106 and the drain 108 to the active layer 104 is sequentially decreased.
  • the number of sub-layers 114 is seven, the material of the first protective layer 110 and the second protective layer 112 is amorphous silicon, the doped element is phosphorus, and the topmost sub-layer 114 and source 106 In contact with the drain 108, the bottommost sub-layer 114 is in contact with the active layer 104.
  • the doping concentration of the at least two sub-layers 114 is less than 1 x 10 20 cm -3 .
  • step S12 a material layer 127 as the active layer 104 is deposited on the gate insulating layer 116 and a protective layer 123 is deposited on the material layer 127, and then the active layer is defined by an etching process. 104.
  • a second metal layer 128 is first deposited on the protective layer 123, and then a source 106 and a drain 108 are defined on the second metal layer 128 by a wet etching process to make the source 106. It is spaced apart from the drain 108.
  • the active layer 104 such as an oxide semiconductor
  • step S14 in some embodiments, the method of dry etching is used to etch away from the gap 124. Cover 123.
  • the first protective layer 110 and the second protective layer 112 are formed in a relatively simple manner.
  • the protective layer 123 between the two electrodes is removed by dry etching to form the first protective layer 110 and the second protective layer 112 which are spaced apart.
  • suitable gas and process parameters can be selected to further reduce damage to the active layer 104.
  • a method of fabricating a thin film transistor further includes the steps of:
  • an electrode layer 120 is formed on the passivation layer 118, and the electrode layer 120 is connected to the drain electrode 108 through the via 122.
  • the passivation of the back channel of the active layer 104 is achieved, which contributes to the improvement of the electrical characteristics of the thin film transistor 100, and the electrode layer 120 can facilitate the external circuit to electrically connect the thin film transistor 100.
  • a certain amount of hydrogen or oxygen may be introduced to passivate the back channel of the active layer 104.
  • An array substrate according to an embodiment of the present invention includes the thin film transistor 100 of any of the above embodiments.
  • the protective layer connecting the active layer 104 and the source 106/drain 108 includes at least two sub-layers 114 having different doping concentrations, so that in the case where the protective layer is provided, the active layer 104 and the active layer 104 can be optimized.
  • the contact resistance between the source 106/drain 108 improves the electrical characteristics of the thin film transistor 100.
  • the array substrate can be used to include, but is not limited to, a display device such as a liquid crystal display device, an organic light emitting diode display device, or the like.

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Abstract

一种薄膜晶体管（100）和薄膜晶体管（100）的制备方法和阵列基板，薄膜晶体管（100）包括栅极（102）、有源层（104）、源极（106）、漏极（108）、第一保护层（110）和第二保护层（112），所述第一保护层（110）位于所述源极（106）和所述有源层（104）之间并连接所述源极（106）和所述有源层（104），所述第二保护层（112）位于所述漏极（108）和所述有源层（104）之间并连接所述漏极（108）和所述有源层（104），所述第一保护层（110）和所述第二保护层（112）均包括层叠的至少两个子层（114），所述至少两个子层（114）的掺杂浓度不相同。上述薄膜晶体管（100）中，连接有源层（104）和源极（106）/漏极（108）的保护层（110、112）包括掺杂浓度不同的至少两个子层（114），如此，在设置保护层（110、112）的情况下，能够优化有源层（104）和源极（106）/漏极（108）之间的接触电阻，进而改善薄膜晶体管（100）的电学特性。

Description

薄膜晶体管和薄膜晶体管的制备方法和阵列基板 技术领域
本发明涉及于晶体管领域，更具体而言，涉及一种薄膜晶体管和薄膜晶体管的制备方法和阵列基板。
背景技术
在相关技术中，薄膜晶体管被广泛地用于阵列基板中，在薄膜晶体管的制备过程中，薄膜晶体管的有源层，在制备源极/漏极的步骤中，容易受到刻蚀液的刻蚀而破坏原来的电学特性。
为解决上述问题，相关技术中，在制备源极/漏极的步骤前，会在有源层上形成保护层以保护有源层。但是，保护层的设置会使得有源层与源极/漏极之间的电阻变大，不利于改善薄膜晶体管的电学特性。
发明内容
本发明实施方式旨在至少解决相关技术中存在的技术问题之一。为此，本发明实施方式需要提供一种薄膜晶体管和薄膜晶体管的制备方法和阵列基板。
本发明实施方式的一种薄膜晶体管，包括栅极、有源层、源极、漏极、第一保护层和第二保护层，所述第一保护层位于所述源极和所述有源层之间并连接所述源极和所述有源层，所述第二保护层位于所述漏极和所述有源层之间并连接所述漏极和所述有源层，所述第一保护层和所述第二保护层均包括层叠的至少两个子层，所述至少两个子层的掺杂浓度不相同。
上述薄膜晶体管中，连接有源层和源极/漏极的保护层包括掺杂浓度不同的至少两个子层，如此，在设置保护层的情况下，能够优化有源层和源极/漏极之间的接触电阻，进而改善薄膜晶体管的电学特性。
本发明实施方式的一种薄膜晶体管的制备方法，包括以下步骤：
形成栅极；
在所述栅极上形成有源层和在所述有源层上形成保护层，所述保护层包括层叠的至少两个子层，所述至少两个子层的掺杂浓度不相同；
在所述保护层上形成源极和漏极，所述源极和所述漏极间隔形成间隙；
自所述间隙刻蚀所述保护层以露出所述有源层并将所述保护层分隔成第一保护层和第二保护层，所述第一保护层位于所述源极和所述有源层之间并连接所述源极和所述有源层，所述第二保护层位于所述漏极和所述有源层之间并连接所述漏极和所述有源层。
本发明实施方式的一种阵列基板，包括上述的薄膜晶体管。
上述阵列基板中，连接有源层和源极/漏极的保护层包括掺杂浓度不同的至少两个子层，如此，在设置保护层的情况下，能够优化有源层和源极/漏极之间的接触电阻，进而改善薄膜晶体管的电学特性。
本发明实施方式的附加方面和优点将在下面的描述中部分给出，部分将从下面的描述中变得明显，或通过本发明实施方式的实践了解到。
附图说明
本发明实施方式的上述和/或附加的方面和优点从结合下面附图对实施方式的描述中将变得明显和容易理解，其中：
图1是本发明实施方式的薄膜晶体管的结构示意图；
图2是相关技术中的薄膜晶体管的结构示意图；
图3是薄膜晶体管的转移曲线比较图；
图4、图5分别是无非晶硅层TFT和有非晶硅层(重掺杂)TFT的漏电流、开态电流对比图；
图6-图8分别是无非晶硅层TFT、有非晶硅层(重掺杂)TFT和有非晶硅层(本征)TFT的能带图；
图9是薄膜晶体管的金属、非晶硅、有源层的费米能级图；
图10是薄膜晶体管的金属、非晶硅、有源层的另一费米能级图；
图11是本发明实施方式的薄膜晶体管的部分结构示意图；
图12是本发明实施方式的薄膜晶体管的制备方法的流程示意图；
图13是本发明实施方式的薄膜晶体管的制备方法的过程示意图。
具体实施方式
下面详细描述本发明的实施方式，所述实施方式的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施方式是示例性的，仅用于解释本发明，而不能理解为对本发明的限制。
在本发明的描述中，需要理解的是，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本发明的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
在本发明的描述中，需要说明的是，除非另有明确的规定和限定，术语“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接或可以相互通信；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本发明中的具体含义。
下文的公开提供了许多不同的实施方式或例子用来实现本发明的不同结构。为了简化本发明的公开，下文中对特定例子的部件和设定进行描述。当然，它们仅仅为示例，并且目的不在于限制本发明。此外，本发明可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设定之间的关系。此外，本发明提供了的各种特定 的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的应用和/或其他材料的使用。
请参图1，本发明实施方式提供的一种薄膜晶体管100，包括栅极102、有源层104、源极106、漏极108、第一保护层110和第二保护层112，第一保护层110位于源极106和有源层104之间并连接源极106和有源层104，第二保护层112位于漏极108和有源层104之间并连接漏极108和有源层104，第一保护层110和第二保护层112均包括层叠的至少两个子层114，至少两个子层114的掺杂浓度不相同。
上述薄膜晶体管100中，连接有源层104和源极106/漏极108的保护层包括掺杂浓度不同的至少两个子层114，如此，在设置保护层的情况下，能够优化有源层104和源极106/漏极108之间的接触电阻，进而改善薄膜晶体管100的电学特性。
具体地，在本发明实施方式中，薄膜晶体管(TFT)100为背沟道刻蚀(BCE)薄膜晶体管。
薄膜晶体管100还包括衬底115，衬底115作为承载薄膜晶体管100的底层。有源层104、源极106和漏极108与栅极102之间形成有栅极绝缘层116。栅极102和栅极绝缘层116设置在衬底115上，源极106、漏极108和有源层104设置在栅极绝缘层116上。
进一步地，在源极106/漏极108与有源层104之间，分别增加第一保护层110和第二保护层112，保护层例如是非晶硅层，非晶硅层不仅能够保护有源层104，还能够充当电子注入层，降低电子的注入势垒。
为了说明本发明实施方式的薄膜晶体管100的原理，对图1及图2所示的薄膜晶体管的结构进行了数值模拟，图2为相关技术中薄膜晶体管200的结构，图1是本发明实施方式的薄膜晶体管100的结构。图1及图2的有源层104的材料可以是非晶硅或氧化物半导体，在下面的说明中，采用铟镓锌氧化物(indium gallium zinc oxide,IGZO)作为有源层104，用铝(功函数设置为4.3eV) 作为源极106/漏极108的材料，薄膜晶体管100为有非晶硅层(重掺杂)的TFT。图3是TFT的转移曲线，分别模拟了无非晶硅层的TFT、有非晶硅层(重掺杂)的TFT，有非晶硅层(本征)的TFT。图4、图5分别是无非晶硅层的TFT和有非晶硅层(重掺杂)的TFT的漏电流、开态电流对比。从中可看出结论：
1.有重掺杂非晶硅层的TFT的电性与无非晶硅层的TFT相近，但前者的漏电流及开态电流均稍高于后者，可能是因为重掺杂非晶硅层有利于电子从源极注入到有源层104中。
2.本征非晶硅层会降低TFT的电学特性，有可能是因为注入势垒变高了。
为了验证以上结论，对比了源极106附近(如图1中点划线AB所示)的能带图。图6-图8分别是无非晶硅层的TFT、有非晶硅层(重掺杂)的TFT和有非晶硅层(本征)的TFT的能带图。从图6可见，IGZO的导带比铝的费米能级高0.194eV左右，其导带在与铝的接触面向下弯曲。从图7可见，重掺杂的非晶硅的导带比铝的费米能级高0.037eV左右，在IGZO导带之下；IGZO的导带在接触面处向下弯曲。从图8可见，本征非晶硅的导带比IGZO高。
从上述分析可知，重掺杂的非晶硅能够降低电子的注入势垒，有利于电流的增加。可以推断，通过调整非晶硅的掺杂浓度，能够进一步改善TFT的电学特性。图3显示，无掺杂的非晶硅会降低IGZO TFT的电流(包括漏电流和开态电流)，而重掺杂(n型掺杂，浓度为1×1020cm-3)的非晶硅却可以增加电流。结合图7、图8可以解释这种现象。无掺杂的非晶硅的导带在IGZO和金属(指金属的费米能级，下同)之上(见图8)，不利于电子注入；重掺杂的非晶硅，由于杂质能级展宽成能带，与导带重合，所以杂质能带底，就相当于形成新的导带底。新的导带底位于IGZO和金属之间，且更接近金属(见图7)，这使得电子更容易注入非晶硅，所以电流增加；然而，新导带底更靠近金属，意味着离IGZO的导带还较远，电子从非晶硅注入到IGZO的势垒还较高，不利于电子从非晶硅注入到IGZO。如果降低非晶硅的掺杂浓度，新导带底会升高，向IGZO靠近些，在这过程中，必然存在一个掺杂浓度，使得电子从金属注入到 非晶硅，再从非晶硅注入到IGZO，其所需能量最小，此时非晶硅的费米能级应位于金属和IGZO的费米能级的中点处，其掺杂浓度应小于1×1020cm-3。在其它实施方式中，如果金属的功函数足够低，与金属接触的非晶硅层的掺杂浓度也可以大于或等于1×1020cm-3。
接下来用半定量的方法证明以上分析。如图9所示，Evac是真空能级，EFM、EF1、EF2分别是金属、非晶硅、有源层104的费米能级，△E为金属和有源层的功函数差，x为金属和非晶硅的功函数差。假如没有非晶硅层(保护层)，根据量子力学，金属与有源层的接触电阻为：
Figure PCTCN2016113295-appb-000001
如果加入非晶硅层，且其均匀掺杂，则接触电阻为金属-非晶硅的接触电阻RMS及非晶硅-有源层104的电阻RSS之和：
Rc2＝RMS+RSS＝R0exp[A*x]+R0’exp[A*(△E-x)]
其中，A为
Figure PCTCN2016113295-appb-000002
可知当x＝△E/2时Rc是最小的。
也可以在非晶硅不同深度掺杂不同的浓度，使得非晶硅的功函数在不同区域有不同的值，如图10所示。假设相邻区域费米能级的间隔均为△E/n(n为正整数)，则：
Rc3＝nR0exp[A*x/n]
对于非晶硅内部，R0很小，为计算方便，设其为1Ω；设Rc1数量级为e7(～1000)Ω。忽略金属与非晶硅层的接触电阻，则当n为7时，即非晶硅分为7层，不同层的掺杂浓度不同，接触电阻Rc3最小。实际上，当源极或漏极与有源层的接触电阻介于en～en+1(n为正整数)Ω时，分层数为n最有利于减小接触电阻，故可根据实际情况调节层数。因此，可定性地说明，对非晶硅层进行分层掺杂，可降低接触电阻。
在某些实施方式中，非晶硅层可分为7子层，但可根据实际情况调节层数。源极、漏极的材料可以是Ti、Al、Mo等功函数较非晶硅低的金属，也可以是Cu、Ni、ITO、Au等功函数较非晶硅高的金属或金属氧化物，接触电阻的数量 级大约为e7(～1000)Ω。
综上，对不同深度的非晶硅进行不同浓度的掺杂，能够使金属和有源层104的接触电阻较小，将作为保护层的非晶硅层分为掺杂浓度不同的7层，能够使金属和有源层104的接触电阻最小。
进一步地，非晶硅的一个特点是，无论用物理气相沉积(PVD)法还是化学气相沉积(CVD)法，只要在反应气体中加入一定量的掺杂气体，如磷烷(PH3)，就可以实现各种浓度的掺杂，工艺简单，成熟，成本低。需要指出的是，对于其它能作为保护层的材料，可参以上对非晶硅为例的分析进行配置及选择，在此不再一一例举。能作为保护层的材料，在利用刻蚀工艺形成源极106和漏极108时，应能够保护有源层104免受刻蚀液损坏。
在某些实施方式中，有源层104的材料为铟镓锌氧化物(IGZO)，源极106和漏极108的材料为功函数较有源层104高的金属或金属氧化物，至少两个子层114的掺杂浓度沿源极106和漏极108至有源层104的方向依次递增。
如此，实现了保护层在不同深度进行不同浓度的掺杂，使源极106/漏极108和有源层104的接触电阻较小。
具体地，源极106和漏极108的材料可选择Cu、Ni、ITO、Au等功函数较高的金属或金属氧化物。在图11所示的方向中，至少两个子层114的掺杂浓度从上往下依次递增。
在某些实施方式中，子层114的数量为7层，第一保护层110和第二保护层112的材料是非晶硅，掺杂的元素是磷，最顶层的子层114与源极106和漏极108接触，最底层的子层114与有源层104接触。
如此，实现了子层114的数量为7层时，使源极106/漏极108和有源层104的接触电阻最小。
具体地，在图11所示的方向中，7个子层114的掺杂浓度从上往下依次递增，即掺杂浓度n1<n2<n3<n4<n5<n6<n7。
在某些实施方式中，有源层104的材料为铟镓锌氧化物，源极106和漏极 108的材料为功函数较有源层104低的金属，至少两个子层114的掺杂浓度沿源极106和漏极108至有源层104的方向依次递减。
如此，实现了保护层在不同深度进行不同浓度的掺杂，使源极106/漏极108和有源层104的接触电阻较小。
具体地，源极106和漏极108的材料可选择Ti、Al、Mo等功函数较低的金属。在图11所示的方向中，至少两个子层114的掺杂浓度从上往下依次递减。
在某些实施方式中，子层114的数量为7层，第一保护层110和第二保护层112的材料是非晶硅，掺杂的元素是磷，最顶层的子层114与源极106和漏极108接触，最底层的子层114与有源层104接触。
如此，实现了子层114的数量为7层时，使源极106/漏极108和有源层104的接触电阻最小。
具体地，在图11所示的方向中，7个子层114的掺杂浓度从上往下依次递减，即掺杂浓度n1>n2>n3>n4>n5>n6>n7。
在某些实施方式中，有源层104的材料为非晶硅，源极106和漏极108的材料为功函数较有源层104高的金属或金属氧化物，至少两个子层114的掺杂浓度沿源极106和漏极108至有源层104的方向依次递减。
如此，实现了保护层在不同深度进行不同浓度的掺杂，使源极106/漏极108和有源层104的接触电阻较小。
具体地，源极106和漏极108的材料可选择Cu、Ni、ITO、Au等功函数较高的金属或金属氧化物。在图11所示的方向中，至少两个子层114的掺杂浓度从上往下依次递减。
在某些实施方式中，子层114的数量为7层，第一保护层110和第二保护层112的材料是非晶硅，掺杂的元素是硼，最顶层的子层114与源极106和漏极108接触，最底层的子层114与有源层104接触。
如此，实现了子层114的数量为7层时，使源极106/漏极108和有源层104的接触电阻最小。
具体地，在图11所示的方向中，7个子层114的掺杂浓度从上往下依次递减，即掺杂浓度n1>n2>n3>n4>n5>n6>n7。
在某些实施方式中，有源层104的材料为非晶硅，源极106和漏极108的材料为功函数较有源层104低的金属，至少两个子层114的掺杂浓度沿源极106和漏极108至有源层104的方向依次递减。
如此，实现了保护层在不同深度进行不同浓度的掺杂，使源极106/漏极108和有源层104的接触电阻较小。
具体地，源极106和漏极108的材料可选择Ti、Al、Mo等功函数较低的金属。在图11所示的方向中，至少两个子层114的掺杂浓度从上往下依次递减。
在某些实施方式中，子层114的数量为7层，第一保护层110和第二保护层112的材料是非晶硅，掺杂的元素是磷，最顶层的子层114与源极106和漏极108接触，最底层的子层114与有源层104接触。
如此，实现了子层114的数量为7层时，使源极106/漏极108和有源层104的接触电阻最小。
具体地，在图11所示的方向中，7个子层114的掺杂浓度从上往下依次递减，即掺杂浓度n1>n2>n3>n4>n5>n6>n7。
在某些实施方式中，请参图1，薄膜晶体管100还包括钝化层118和电极层120，钝化层118覆盖源极106、漏极108和有源层104，钝化层118设有露出漏极108的通孔122，电极层120设置在钝化层118上，电极层120通过通孔122连接漏极108。
如此，实现了对有源层104的背沟道进行钝化，有助于薄膜晶体管100电学特性的提高，同时电极层120可方便外部电路电连接薄膜晶体管100。
请参图12和图13，本发明实施方式的一种薄膜晶体管的制备方法，包括以下步骤：
S11，形成栅极102；
S12，在栅极102上形成有源层104和在有源层104上形成保护层123，保 护层123包括层叠的至少两个子层114，至少两个子层114的掺杂浓度不相同；
S13，在保护层123上形成源极106和漏极108，源极106和漏极108间隔形成间隙124；
S14，自间隙124刻蚀保护层123以露出有源层104并将保护层123分隔成第一保护层110和第二保护层112，第一保护层110位于源极106和有源层104之间并连接源极106和有源层104，第二保护层112位于漏极108和有源层104之间并连接漏极108和有源层104。
上述薄膜晶体管的制备方法中，连接有源层104和源极106/漏极108的保护层包括掺杂浓度不同的至少两个子层114，如此，在设置保护层的情况下，能够优化有源层104和源极106/漏极108之间的接触电阻，进而改善薄膜晶体管的电学特性。
具体地，请参图13，在步骤S11中，在衬底115上沉积第一金属层126，之后，对第一金属层126进行图形化以形成栅极102。可选地，在沉积第一金属层126前，在衬底115上先沉积一层缓冲层，之后第一金属层126再沉积在缓冲层上。在一个例子中，可通过黄光制程图形化第一金属层126以形成栅极102。
形成栅极102后，在栅极102上沉积栅极绝缘层116以间隔开栅极102。
在步骤S12中，通过刻蚀工艺定义有源层104。
在步骤S12中，保护层123通过沉积的方法形成在有源层104上。
如此，沉积的方法较容易在有源层104上形成保护层123，而且成本较低。
具体地，沉积的方法包括物理气相沉积(PVD)法和化学气相沉积(CVD)法。因此，可根据实际需要采用其中一种沉积法。
在某些实施方式中，在形成保护层123时，在反应气体中加入不同设定浓度的掺杂气体而使至少两个子层114的掺杂浓度不相同。
如此，掺杂工艺简单，成熟，成本低。
具体地，在一个例子中，保护层的材料是非晶硅，要实现子层114的不同 掺杂浓度时，只要在反应气体中加入一定量的掺杂气体，如磷烷(PH3)即可。
在某些实施方式中，有源层104的材料为铟镓锌氧化物，源极106和漏极108的材料为功函数较有源层104高的金属或金属氧化物，至少两个子层114的掺杂浓度沿源极106和漏极108至有源层104的方向依次递增。
需要说明的是，上述对薄膜晶体管的实施方式的解释说明也适用于本实施方式的薄膜晶体管的制备方法，为避免冗余，在此不再详细展开。
在某些实施方式中，子层114的数量为7层，第一保护层110和第二保护层112的材料是非晶硅，掺杂的元素是磷，最顶层的子层114与源极106和漏极108接触，最底层的子层114与有源层104接触。
需要说明的是，上述对薄膜晶体管的实施方式的解释说明也适用于本实施方式的薄膜晶体管的制备方法，为避免冗余，在此不再详细展开。
在某些实施方式中，有源层104的材料为铟镓锌氧化物，源极106和漏极108的材料为功函数较有源层104低的金属，至少两个子层114的掺杂浓度沿源极106和漏极108至有源层104的方向依次递减。
需要说明的是，上述对薄膜晶体管的实施方式的解释说明也适用于本实施方式的薄膜晶体管的制备方法，为避免冗余，在此不再详细展开。
在某些实施方式中，子层114的数量为7层，第一保护层110和第二保护层112的材料是非晶硅，掺杂的元素是磷，最顶层的子层114与源极106和漏极108接触，最底层的子层114与有源层104接触。
需要说明的是，上述对薄膜晶体管的实施方式的解释说明也适用于本实施方式的薄膜晶体管的制备方法，为避免冗余，在此不再详细展开。
在某些实施方式中，有源层104的材料为非晶硅，源极106和漏极108的材料为功函数较有源层104高的金属或金属氧化物，至少两个子层114的掺杂浓度沿源极106和漏极108至有源层104的方向依次递减。
需要说明的是，上述对薄膜晶体管的实施方式的解释说明也适用于本实施方式的薄膜晶体管的制备方法，为避免冗余，在此不再详细展开。
在某些实施方式中，子层114的数量为7层，第一保护层110和第二保护层112的材料是非晶硅，掺杂的元素是硼，最顶层的子层114与源极106和漏极108接触，最底层的子层114与有源层104接触。
需要说明的是，上述对薄膜晶体管的实施方式的解释说明也适用于本实施方式的薄膜晶体管的制备方法，为避免冗余，在此不再详细展开。
在某些实施方式中，有源层104的材料为非晶硅，源极106和漏极108的材料为功函数较有源层104低的金属，至少两个子层114的掺杂浓度沿源极106和漏极108至有源层104的方向依次递减。
需要说明的是，上述对薄膜晶体管的实施方式的解释说明也适用于本实施方式的薄膜晶体管的制备方法，为避免冗余，在此不再详细展开。
在某些实施方式中，子层114的数量为7层，第一保护层110和第二保护层112的材料是非晶硅，掺杂的元素是磷，最顶层的子层114与源极106和漏极108接触，最底层的子层114与有源层104接触。
需要说明的是，上述对薄膜晶体管的实施方式的解释说明也适用于本实施方式的薄膜晶体管制备方法，为避免冗余，在此不再详细展开。
在某些实施方式中，至少两个子层114的掺杂浓度小于1×1020cm-3。
需要说明的是，上述对薄膜晶体管的实施方式的解释说明也适用于本实施方式的薄膜晶体管的制备方法，为避免冗余，在此不再详细展开。
本发明实施方式中，在步骤S12中，在栅极绝缘层116上沉积一层作为有源层104的材料层127和在材料层127上沉积保护层123，之后用刻蚀工艺定义有源层104。
在步骤S13中，请参图13，先在保护层123上沉积第二金属层128，然后用湿法刻蚀工艺在第二金属层128上定义源极106和漏极108，使源极106和漏极108间隔。在刻蚀第二金属层128时，有源层104(如氧化物半导体)在保护层123的保护下，不会被酸性刻蚀液损坏。
在步骤S14中，在某些实施方式中，用干法刻蚀的方法自间隙124刻蚀保 护层123。
如此，以较简单的方法形成第一保护层110和第二保护层112。
具体地，以源极106和漏极108作为遮挡层，用干法刻蚀将两电极间的保护层123去除以形成间隔的第一保护层110和第二保护层112。而且，干法刻蚀时，可选择合适的气体和工艺参数，可以进一步降低有源层104受到的损坏。
在某些实施方式中，薄膜晶体管的制备方法，还包括步骤：
S15，在源极106、漏极108和有源层104上形成钝化层118，钝化层118设有露出漏极108的通孔122；
S16，在钝化层118上形成电极层120，电极层120通过通孔122连接漏极108。
如此，实现了对有源层104的背沟道进行钝化，有助于薄膜晶体管100电学特性的提高，同时电极层120可方便外部电路电连接薄膜晶体管100。
具体地，在刻蚀完保护层以露出有源层104后，可通入一定量的氢气或氧气，对有源层104的背沟道进行钝化。
本发明实施方式的一种阵列基板，包括以上任一实施方式的薄膜晶体管100。
上述阵列基板中，连接有源层104和源极106/漏极108的保护层包括掺杂浓度不同的至少两个子层114，如此，在设置保护层的情况下，能够优化有源层104和源极106/漏极108之间的接触电阻，进而改善薄膜晶体管100的电学特性。
具体地，阵列基板可用于包括但不限于显示装置，显示装置例如是液晶显示装置、有机发光二极管显示装置等。
在本说明书的描述中，参考术语“一个实施方式”、“某些实施方式”、“示意性实施方式”、“示例”、“具体示例”、或“一些示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本发明的至少一个实施方式或示例中。在本说明书中，对上述术语的示意性表述不一定指的是相同 的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
尽管上面已经示出和描述了本发明的实施方式，可以理解的是，上述实施方式是示例性的，不能理解为对本发明的限制，本领域的普通技术人员在本发明的范围内可以对上述实施方式进行变化、修改、替换和变型。

Claims (27)

  1. 一种薄膜晶体管，其特征在于，包括栅极、有源层、源极、漏极、第一保护层和第二保护层，所述第一保护层位于所述源极和所述有源层之间并连接所述源极和所述有源层，所述第二保护层位于所述漏极和所述有源层之间并连接所述漏极和所述有源层，所述第一保护层和所述第二保护层均包括层叠的至少两个子层，所述至少两个子层的掺杂浓度不相同。
  2. 如权利要求1所述的薄膜晶体管，其特征在于，所述有源层的材料为铟镓锌氧化物，所述源极和所述漏极的材料为功函数较所述有源层高的金属或金属氧化物，所述至少两个子层的掺杂浓度沿所述源极和所述漏极至所述有源层的方向依次递增。
  3. 如权利要求2所述的薄膜晶体管，其特征在于，所述子层的数量为7层，所述第一保护层和第二保护层的材料是非晶硅，掺杂的元素是磷，最顶层的所述子层与所述源极和所述漏极接触，最底层的所述子层与所述有源层接触。
  4. 如权利要求1所述的薄膜晶体管，其特征在于，所述有源层的材料为铟镓锌氧化物，所述源极和所述漏极的材料为功函数较所述有源层低的金属，所述至少两个子层的掺杂浓度沿所述源极和所述漏极至所述有源层的方向依次递减。
  5. 如权利要求4所述的薄膜晶体管，其特征在于，所述子层的数量为7层，所述第一保护层和所述第二保护层的材料是非晶硅，掺杂的元素是磷，最顶层的所述子层与所述源极和所述漏极接触，最底层的所述子层与所述有源层接触。
  6. 如权利要求1所述的薄膜晶体管，其特征在于，所述有源层的材料为非晶硅，所述源极和所述漏极的材料为功函数较所述有源层高的金属或金属氧化物，所述至少两个子层的掺杂浓度沿所述源极和所述漏极至所述有源层的方向依次递减。
  7. 如权利要求6所述的薄膜晶体管，其特征在于，所述子层的数量为7层，所述第一保护层和所述第二保护层的材料是非晶硅，掺杂的元素是硼，最顶层 的所述子层与所述源极和所述漏极接触，最底层的所述子层与所述有源层接触。
  8. 如权利要求1所述的薄膜晶体管，其特征在于，所述有源层的材料为非晶硅，所述源极和所述漏极的材料为功函数较所述有源层低的金属，所述至少两个子层的掺杂浓度沿所述源极和所述漏极至所述有源层的方向依次递减。
  9. 如权利要求8所述的薄膜晶体管，其特征在于，所述子层的数量为7层，所述第一保护层和所述第二保护层的材料是非晶硅，掺杂的元素是磷，最顶层的所述子层与所述源极和所述漏极接触，最底层的所述子层与所述有源层接触。
  10. 如权利要求1所述的薄膜晶体管，其特征在于，所述至少两个子层的掺杂浓度小于1×1020cm-3。
  11. 如权利要求1所述的薄膜晶体管，其特征在于，所述薄膜晶体管还包括钝化层和电极层，所述钝化层覆盖所述源极、所述漏极和所述有源层，所述钝化层设有露出所述漏极的通孔，所述电极层设置在所述钝化层上，所述电极层通过所述通孔连接所述漏极。
  12. 一种薄膜晶体管的制备方法，其特征在于，包括以下步骤：
    形成栅极；
    在所述栅极上形成有源层和在所述有源层上形成保护层，所述保护层包括层叠的至少两个子层，所述至少两个子层的掺杂浓度不相同；
    在所述保护层上形成源极和漏极，所述源极和所述漏极间隔形成间隙；
    自所述间隙刻蚀所述保护层以露出所述有源层并将所述保护层分隔成第一保护层和第二保护层，所述第一保护层位于所述源极和所述有源层之间并连接所述源极和所述有源层，所述第二保护层位于所述漏极和所述有源层之间并连接所述漏极和所述有源层。
  13. 如权利要求12所述的薄膜晶体管的制备方法，其特征在于，所述保护层通过沉积的方法形成在所述有源层上。
  14. 如权利要求13所述的薄膜晶体管的制备方法，其特征在于，在形成所述保护层时，在反应气体中加入不同设定浓度的掺杂气体而使所述至少两个子 层的掺杂浓度不相同。
  15. 如权利要求13所述的薄膜晶体管的制备方法，其特征在于，所述沉积的方法包括物理气相沉积和化学气相沉积。
  16. 如权利要求12所述的薄膜晶体管的制备方法，其特征在于，所述有源层的材料为铟镓锌氧化物，所述源极和所述漏极的材料为功函数较所述铟镓锌氧化物高的金属或金属氧化物，所述至少两个子层的掺杂浓度沿所述源极和所述漏极至所述有源层的方向依次递增。
  17. 如权利要求16所述的薄膜晶体管的制备方法，其特征在于，所述子层的数量为7层，所述第一保护层和所述第二保护层的材料是非晶硅，掺杂的元素是磷，最顶层的所述子层与所述源极和所述漏极接触，最底层的所述子层与所述有源层接触。
  18. 如权利要求12所述的薄膜晶体管的制备方法，其特征在于，所述有源层的材料为铟镓锌氧化物，所述源极和所述漏极的材料为功函数较所述铟镓锌氧化物低的金属，所述至少两个子层的掺杂浓度沿所述源极和所述漏极至所述有源层的方向依次递减。
  19. 如权利要求18所述的薄膜晶体管的制备方法，其特征在于，所述子层的数量为7层，所述第一保护层和所述第二保护层的材料是非晶硅，掺杂的元素是磷，最顶层的所述子层与所述源极和所述漏极接触，最底层的所述子层与所述有源层接触。
  20. 如权利要求12所述的薄膜晶体管的制备方法，其特征在于，所述有源层的材料为非晶硅，所述源极和所述漏极的材料为功函数较所述非晶硅高的金属或金属氧化物，所述至少两个子层的掺杂浓度沿所述源极和所述漏极至所述有源层的方向依次递减。
  21. 如权利要求20所述的薄膜晶体管的制备方法，其特征在于，所述子层的数量为7层，所述第一保护层和所述第二保护层的材料是非晶硅，掺杂的元素是硼，最顶层的所述子层与所述源极和所述漏极接触，最底层的所述子层与 所述有源层接触。
  22. 如权利要求12所述的薄膜晶体管的制备方法，其特征在于，所述有源层的材料为非晶硅，所述源极和所述漏极的材料为功函数较所述非晶硅低的金属，所述至少两个子层的掺杂浓度沿所述源极和所述漏极至所述有源层的方向依次递减。
  23. 如权利要求22所述的薄膜晶体管的制备方法，其特征在于，所述子层的数量为7层，所述第一保护层和所述第二保护层的材料是非晶硅，掺杂的元素是磷，最顶层的所述子层与所述源极和所述漏极接触，最底层的所述子层与所述有源层接触。
  24. 如权利要求12所述的薄膜晶体管的制备方法，其特征在于，所述至少两个子层的掺杂浓度小于1×1020cm-3。
  25. 如权利要求12所述的薄膜晶体管的制备方法，其特征在于，用干法刻蚀的方法自所述间隙刻蚀所述保护层。
  26. 如权利要求12所述的薄膜晶体管的制备方法，其特征在于，还包括步骤：
    在所述源极、所述漏极和所述有源层上形成钝化层，所述钝化层设有露出所述漏极的通孔；
    在所述钝化层上形成电极层，所述电极层通过所述通孔连接所述漏极。
  27. 一种阵列基板，其特征在于，包括如权利要求1-11任一项所述的薄膜晶体管。
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