WO2018113066A1 - 有机发光显示面板及其制作方法 - Google Patents

有机发光显示面板及其制作方法 Download PDF

Info

Publication number
WO2018113066A1
WO2018113066A1 PCT/CN2017/071590 CN2017071590W WO2018113066A1 WO 2018113066 A1 WO2018113066 A1 WO 2018113066A1 CN 2017071590 W CN2017071590 W CN 2017071590W WO 2018113066 A1 WO2018113066 A1 WO 2018113066A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
gate
oxide semiconductor
metal oxide
contact portion
Prior art date
Application number
PCT/CN2017/071590
Other languages
English (en)
French (fr)
Inventor
周星宇
迟世鹏
Original Assignee
深圳市华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to US15/504,473 priority Critical patent/US10263057B2/en
Publication of WO2018113066A1 publication Critical patent/WO2018113066A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment

Definitions

  • the invention belongs to the technical field of organic light emitting display, and in particular to an organic light emitting display panel and a manufacturing method thereof.
  • OLED display panels have become very popular emerging flat display panel products at home and abroad. This is because OLED display panels have self-luminous, wide viewing angle (above 175°), and short response. Time (1 ⁇ s), high luminous efficiency, wide color gamut, low operating voltage (3 ⁇ 10V), thin thickness (less than 1mm), large size and flexible panel and simple process, and it also has The potential for low cost.
  • the existing OLED display panels can be classified into a passive OLED display panel (PM-OLED) and an active OLED display panel (AM-OLED) according to the driving manner.
  • a thin film transistor TFT
  • a capacitor to store a signal to control the brightness gray scale performance of the OLED.
  • each pixel needs to be composed of at least two TFTs and one storage capacitor.
  • the two TFTs are generally of the same type, such as metal oxide semiconductor thin film transistors or low temperature polysilicon thin film transistors.
  • the current supplied to the OLED by the metal oxide semiconductor thin film transistor may be unstable, resulting in unstable OLED light emission; and when low temperature polysilicon thin film transistor is used as an introduction When a thin film transistor is externally supplied with a voltage signal, the leakage of the low temperature polysilicon thin film transistor is high, so that a superior circuit shutdown effect cannot be achieved.
  • an object of the present invention is to provide an organic light emitting display panel capable of simultaneously achieving stable OLED light emission and superior circuit shutdown effect, and a method of fabricating the same.
  • an organic light emitting display panel includes: a substrate and a driving thin film transistor, a switching thin film transistor, a storage capacitor, and an organic light emitting layer formed on the substrate a device, an external voltage signal is stored in the storage capacitor via the switching thin film transistor, the external voltage signal controlling a magnitude of an on current of the driving thin film transistor to control a gray scale of the organic light emitting device,
  • the driving thin film transistor is a low temperature polysilicon thin film transistor
  • the switching thin film transistor is a metal oxide semiconductor thin film transistor.
  • the low temperature polysilicon thin film transistor is a P-type low temperature polysilicon thin film transistor
  • the metal oxide semiconductor thin film transistor is an N-type metal oxide semiconductor thin film transistor
  • a method of fabricating the above-described organic light-emitting display panel comprising: forming a polysilicon layer and a metal oxide semiconductor layer on a substrate; and a substrate, a polysilicon layer, and a metal oxide semiconductor layer Forming a gate insulating layer; forming a first gate, a second gate, and a first storage capacitor electrode on the gate insulating layer; forming a first source contact portion and a first portion at both ends of the polysilicon layer a drain contact portion, and a second source contact portion and a second drain contact portion are respectively formed at both ends of the metal oxide semiconductor layer; at the gate insulating layer, the first gate electrode, the second gate electrode, and the first Forming an interlayer insulating layer on the storage capacitor electrode; forming a first source, a first drain, a second source, a second drain, and a second storage capacitor electrode on the interlayer insulating layer; the first source a pole, a first drain, a second source, and
  • a buffer layer is formed on the substrate before the polysilicon layer and the metal oxide semiconductor layer are formed on the substrate.
  • a passivation layer is formed on the interlayer insulating layer, the first source, the first drain, the second source, the second drain, and the second storage capacitor electrode before the formation of the planarization layer.
  • the method for forming a polysilicon layer and a metal oxide semiconductor layer on the substrate comprises the steps of: depositing an amorphous silicon layer on the substrate; recrystallizing the amorphous silicon layer by annealing to form a polysilicon layer; A metal oxide semiconductor layer separated from the polysilicon layer is deposited.
  • the portion of the gate insulating layer opposite to the polysilicon layer or the gate insulating layer opposite to the metal oxide semiconductor layer Partially thinned.
  • the method of forming the first gate, the second gate, and the first storage capacitor electrode on the gate insulating layer includes the steps of: depositing a gate metal layer on the gate insulating layer; on the gate metal layer Coating a photoresist; exposing and developing the photoresist to remove photoresist other than the photoresist on the first gate, the second gate and the first storage capacitor electrode to be formed; the exposed gate metal layer Etch removal.
  • the method of forming the first source contact portion, the first drain contact portion, the second source contact portion, and the second drain contact portion includes the steps of: facing both ends of the polysilicon layer and the metal oxide semiconductor layer The two ends are respectively ion-implanted; the photoresist on the first gate, the second gate and the first storage capacitor electrode is removed; the polysilicon layer and the metal oxide semiconductor layer after ion implantation are heated and activated, thereby being in the polysilicon layer The two ends respectively form a first source contact portion and a first drain contact portion, and a second source contact portion and a second drain contact portion are respectively formed at both ends of the metal oxide semiconductor layer.
  • the ions used are boron ions.
  • a low-temperature polysilicon thin film transistor is used as a driving thin film transistor whose drain is in contact with a bottom electrode of an OLED, thereby providing current stability to an OLED, stabilizing OLED light emission, and utilizing a metal oxide semiconductor
  • the thin film transistor is a switching thin film transistor that introduces a voltage signal that is externally supplied, and the metal oxide semiconductor thin film transistor has a low leakage current, thereby achieving a better circuit shutdown effect.
  • the metal oxide semiconductor thin film transistor has poor illumination reliability, its poor light reliability is only a small effect on the entire device when it is used as a switching thin film transistor, and the low-temperature polysilicon thin film transistor has better illumination reliability, so that it is not necessary to make a light-shielding on the substrate.
  • Layer; and both are top gate structures, so the process is not increased, and the parasitic capacitance is relatively small.
  • FIG. 1 is a pixel circuit diagram of an OLED display panel in accordance with an embodiment of the present invention.
  • FIGS. 2A through 2L are flowcharts showing the fabrication of an OLED display panel in accordance with an embodiment of the present invention.
  • 3A through 3C illustrate a fabrication flow diagram of a polysilicon layer and a metal oxide semiconductor layer in accordance with an embodiment of the present invention
  • FIGS. 4A through 4D are flowcharts showing fabrication of a first gate, a second gate, and a first storage capacitor electrode, in accordance with an embodiment of the present invention
  • 5A-5C are flow diagrams of fabrication of a first source contact, a first drain contact, a second source contact, and a second drain contact, in accordance with an embodiment of the present invention.
  • FIG. 1 is a pixel circuit diagram of an OLED display panel in accordance with an embodiment of the present invention.
  • an active driving method has a TFT and a storage capacitor to control brightness and darkness of a pixel.
  • a voltage signal sent by an external circuit is stored in a storage capacitor via a data line and a switching TFT 100.
  • the voltage signal controls the magnitude of the conduction current of the driving TFT 200, and the magnitude of the current determines the gray scale of the OLED 400.
  • the scanning line is turned off, the voltage stored in the storage capacitor 300 can keep the driving TFT 200 in a conducting state, so Provides a fixed current for the OLED in one picture time.
  • the driving TFT 200 is a low temperature polysilicon thin film transistor
  • the switching TFT 100 is a metal oxide semiconductor thin film transistor.
  • the low temperature polysilicon thin film transistor is a P-type low temperature polysilicon thin film transistor
  • the metal oxide semiconductor thin film transistor is an N-type metal oxide semiconductor thin film transistor.
  • FIG. 2A through 2L are flowcharts showing the fabrication of an OLED display panel in accordance with an embodiment of the present invention. It should be noted that, in FIG. 2A to FIG. 2L, the scan lines, the data lines, the power lines, and the capacitance lines in FIG. 1 are not shown for convenience of illustration, and these are omitted in the actual OLED display panel. Component.
  • Step 1 Referring to FIG. 2A, a buffer layer 1021 is formed on the substrate 500. It should be noted that, as another embodiment of the present invention, if the buffer layer 1021 is not required according to actual needs, the step one may be omitted.
  • the substrate 500 may be, for example, an insulating and transparent glass substrate or a resin substrate.
  • the buffer layer 1021 may be, for example, a SiN x /SiO x structure formed on the substrate 500 by a PECVD process or the like, but the present invention is not limited thereto.
  • the buffer layer 1021 may also be a single-layer SiN x structure or a SiO x structure.
  • Step 2 Referring to FIG. 2B, a separate polysilicon layer 210 and a metal oxide semiconductor layer 110 are formed on the buffer layer 1021.
  • 3A through 3C illustrate a fabrication flow diagram of a polysilicon layer 210 and a metal oxide semiconductor layer 110, in accordance with an embodiment of the present invention.
  • an amorphous silicon layer a-Si is deposited on the buffer layer 1021.
  • an amorphous silicon layer a-Si may be formed on the surface of the buffer layer 1021, for example, by sputtering.
  • the amorphous silicon layer a-Si is recrystallized in an annealing manner to form a polysilicon layer 210.
  • a metal oxide semiconductor layer 110 spaced apart from the polysilicon layer 210 is deposited on the buffer layer 1021.
  • the metal oxide semiconductor layer 110 may be made of, for example, a metal oxide material such as indium gallium zinc oxide (IGZO) or indium tin zinc oxide (ITZO).
  • a gate insulating layer 1022 is formed on the buffer layer 1021, the polysilicon layer 210, and the metal oxide semiconductor layer 110.
  • the gate insulating layer 1022 may be, for example, a SiN x /SiO x structure formed on the buffer layer 1021, the polysilicon layer 210, and the metal oxide semiconductor layer 110 by a PECVD process, but the present invention is not limited thereto, such as a gate.
  • the insulating layer 1022 may also be a single layer SiN x structure or SiO x structure.
  • the corresponding gate insulating layer 1022 can be thinned according to the subsequent ion concentration implanted when the polysilicon layer 210 and the metal oxide semiconductor layer 110 are implanted, for example, when the ions of the polysilicon layer 210 are implanted.
  • the concentration is higher than the ion concentration of the implanted metal oxide semiconductor layer 110
  • the gate insulating layer 1022 opposite to the polysilicon layer 210 is thinned; when the ion concentration of the implanted polysilicon layer 210 is lower than that of the implanted metal oxide semiconductor layer 110 At the concentration, the gate insulating layer 1022 opposed to the metal oxide semiconductor layer 110 is thinned.
  • Step 4 Referring to FIG. 2D, a first gate 220, a second gate 120, and a first storage capacitor electrode 310 are formed on the gate insulating layer 1022.
  • 4A-4D are flow diagrams of fabrication of a first gate, a second gate, and a first storage capacitor electrode, in accordance with an embodiment of the present invention.
  • a gate metal layer IM is deposited on the gate insulating layer 1022.
  • the gate metal layer IM may be, for example, a molybdenum aluminum molybdenum (MoAlMo) structure or a titanium aluminum titanium (TiAlTi) structure, or may be a single layer molybdenum structure or a single layer aluminum structure.
  • a photoresist PR is applied on the gate metal layer IM.
  • the photoresist PR is exposed and developed to remove the photoresist PR other than the photoresist PR on the first gate 220, the second gate 120, and the first storage capacitor electrode 310 to be formed.
  • the exposed gate metal layer IM is etched away to form a first gate 220, a second gate 120, and a first storage capacitor electrode 310.
  • the first gate 220 is opposite to the polysilicon layer 210, the second gate 120 is separated from the metal oxide semiconductor layer 110, and the first gate 220, the second gate 120, and the first storage capacitor electrode 310 are spaced apart from each other.
  • Step 5 Referring to FIG. 2E, a first source contact portion 210a and a first drain contact portion 210b are formed on both ends of the polysilicon layer 210, and a second source is formed on both ends of the metal oxide semiconductor layer 110.
  • 5A-5C are flow diagrams of fabrication of a first source contact, a first drain contact, a second source contact, and a second drain contact, in accordance with an embodiment of the present invention.
  • ion implantation is performed simultaneously on both ends of the polysilicon layer 210 and both ends of the metal oxide semiconductor layer 110.
  • ion implantation is performed using boron ions, but the present invention is not limited thereto.
  • the concentration of ions implanted at both ends of the polysilicon layer 210 is higher than that of the metal oxide semiconductor
  • the ion concentration injected at both ends of the layer 110 is specifically described in the above step 3.
  • the photoresist PR on the first gate 220, the second gate 120, and the first storage capacitor electrode 310 is removed.
  • the polysilicon layer 210 and the metal oxide semiconductor layer 110 after ion implantation are heated and activated, so that the first source contact portion 210a and the first drain contact portion are respectively formed on both ends of the polysilicon layer 210.
  • 210b, and a second source contact portion 110a and a second drain contact portion 110b are formed on both ends of the metal oxide semiconductor layer 110, respectively.
  • an interlayer insulating layer (ILD) 1023 is formed on the gate insulating layer 1022, the first gate 220, the second gate 120, and the first storage capacitor electrode 310.
  • the interlayer insulating layer 1023 may be, for example, a SiN x /SiO x structure formed on the gate insulating layer 1022, the first gate 220, the second gate 120, and the first storage capacitor electrode 310 by a PECVD process, but The invention is not limited thereto, and for example, the interlayer insulating layer 1023 may also be a single-layer SiN x structure or a SiO x structure.
  • Step 7 Referring to FIG. 2G, a first source 230, a first drain 240, a second source 130, a second drain 140, and a second storage capacitor electrode 320 are formed on the interlayer insulating layer 1023; A source 230, a first drain 240, a second source 130, and a second drain 140 penetrate the interlayer insulating layer 1023 and the gate insulating layer 1022 to respectively correspond to the corresponding first source contact portion 210a, first The drain contact portion 210b, the second source contact portion 110a, and the second drain contact portion 110b are in contact.
  • the method of fabricating the first source 230, the first drain 240, the second source 130, the second drain 140, and the second storage capacitor electrode 320 is similar to the fabrication of the first gate 220 and the second in step four.
  • the method of the gate 120 and the first storage capacitor electrode 310 will not be described herein.
  • the first source 230, the first drain 240, the second source 130, the second drain 140, and the second storage capacitor electrode 320 may have a molybdenum aluminum molybdenum (MoAlMo) structure or a titanium aluminum titanium (TiAlTi) structure, or It is a single-layer molybdenum structure or a single-layer aluminum structure.
  • Step 8 Referring to FIG. 2H, a passivation layer is formed on the interlayer insulating layer 1023, the first source 230, the first drain 240, the second source 130, the second drain 140, and the second storage capacitor electrode 320. (PV) 1024. It should be noted that, as another embodiment of the present invention, if the passivation layer 1024 is not required according to actual needs, the step VIII may be omitted.
  • Step 9 Referring to FIG. 2I, a planarization layer (PLN) 1025 is formed on the passivation layer 1024.
  • PPN planarization layer
  • Step 10 Referring to FIG. 2J, a bottom electrode 410 is formed on the flat layer 1025; the bottom electrode 410 penetrates the flat layer 1025 and the passivation layer 1024 to be in contact with the first drain electrode 240.
  • the bottom electrode 410 may be made of, for example, indium tin oxide (ITO), but the present invention is not limited thereto.
  • the bottom electrode 210 may also be made of a reflective metal and should be thin enough to be There is partial light transmission at the wavelength of the emitted light, which is said to be translucent.
  • Step 11 Referring to FIG. 2K, a pixel defining layer (PDL) 1026 is formed on the flat layer 1025 and the bottom electrode 410, and a recess 1026a exposing the bottom electrode 410 is formed in the pixel defining layer 1026.
  • PDL pixel defining layer
  • Step 12 Referring to FIG. 2L, the organic electroluminescent device 420 and the top electrode 430 are sequentially formed on the exposed bottom electrode 410.
  • the organic electroluminescent device 420 sequentially includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer from the bottom electrode 410 to the top electrode 430 ( EIL), but the invention is not limited thereto.
  • the top electrode 430 may be made of a reflective metal and should be thick enough to be substantially opaque and a full mirror, but the invention is not limited thereto.
  • a low temperature polysilicon thin film transistor is used as a driving thin film transistor, and a drain thereof is in contact with a bottom electrode of the OLED, thereby providing current stability to the OLED to stabilize the OLED light emission; using a metal oxide semiconductor
  • the thin film transistor is a switching thin film transistor that introduces a voltage signal that is externally supplied, and the metal oxide semiconductor thin film transistor has a low leakage current, thereby achieving a better circuit shutdown effect.
  • the metal oxide semiconductor thin film transistor has poor illumination reliability, its poor light reliability is only a small effect on the entire device when it is used as a switching thin film transistor, and the low-temperature polysilicon thin film transistor has better illumination reliability, so that it is not necessary to make a light-shielding on the substrate.
  • Layer; and both are top gate structures, so the process is not increased, and the parasitic capacitance is relatively small.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Geometry (AREA)
  • Thin Film Transistor (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

一种有机发光显示面板及其制作方法，其包括：基板（500）以及形成在基板（500）上的驱动薄膜晶体管（200）、开关薄膜晶体管（100）、存储电容（300）、有机发光器件（420），外部电压信号经开关薄膜晶体管（100）储存在存储电容（300）中，外部电压信号控制驱动薄膜晶体管（200）的导通电流的大小，以控制有机发光器件（420）的灰阶，驱动薄膜晶体管（200）为低温多晶硅薄膜晶体管，开关薄膜晶体管（100）为金属氧化物半导体薄膜晶体管。该低温多晶硅薄膜晶体管的漏极与有机发光器件（420）的底电极接触，从而提供给有机发光器件（420）的电流稳定，使有机发光器件（420）发光稳定；金属氧化物半导体薄膜晶体管的漏电较低，从而能够实现更优的电路关闭效果。

Description

有机发光显示面板及其制作方法 技术领域
本发明属于有机发光显示技术领域，具体地讲，涉及一种有机发光显示面板及其制作方法。
背景技术
近年来，有机发光二极管(Organic Light-Emitting Diode，OLED)显示面板成为国内外非常热门的新兴平面显示面板产品，这是因为OLED显示面板具有自发光、广视角(达175°以上)、短反应时间(1μs)、高发光效率、广色域、低工作电压(3～10V)、薄厚度(可小于1mm)、可制作大尺寸与可挠曲的面板及制程简单等特性，而且它还具有低成本的潜力。
现有的OLED显示面板依驱动方式可分为被动式OLED显示面板(PM-OLED)和主动式OLED显示面板(AM-OLED)。在主动式OLED显示面板中，通常利用薄膜晶体管(TFT)搭配电容储存信号来控制OLED的亮度灰阶表现。为了达到定电流驱动的目的，每个像素至少需要两个TFT和一个储存电容来构成。然而，这两个TFT通常都是同种类型的，例如都是金属氧化物半导体薄膜晶体管或者低温多晶硅薄膜晶体管。然而，当利用金属氧化物半导体薄膜晶体管作为驱动薄膜晶体管时，金属氧化物半导体薄膜晶体管提供给OLED的电流会出现不稳定的现象，从而导致OLED发光不稳定；而当利用低温多晶硅薄膜晶体管作为引入外部送入的电压信号的开关薄膜晶体管时，低温多晶硅薄膜晶体管的漏电较高，从而无法实现更优的电路关闭效果。
发明内容
为了解决上述现有技术的问题，本发明的目的在于提供一种能够同时实现OLED发光稳定且电路关闭效果更优的有机发光显示面板及其制作方法。
根据本发明的一方面，提供了一种有机发光显示面板，其包括：基板以及形成在所述基板上的驱动薄膜晶体管、开关薄膜晶体管、存储电容、有机发光 器件，外部电压信号经所述开关薄膜晶体管储存在所述存储电容中，所述外部电压信号控制所述驱动薄膜晶体管的导通电流的大小，以控制所述有机发光器件的灰阶，所述驱动薄膜晶体管为低温多晶硅薄膜晶体管，所述开关薄膜晶体管为金属氧化物半导体薄膜晶体管。
进一步地，所述低温多晶硅薄膜晶体管为P型低温多晶硅薄膜晶体管，所述金属氧化物半导体薄膜晶体管为N型金属氧化物半导体薄膜晶体管。
根据本发明的一方面，还提供了一种上述的有机发光显示面板的制作方法，其包括：在基板上制作形成多晶硅层和金属氧化物半导体层；在基板、多晶硅层和金属氧化物半导体层上制作形成栅极绝缘层；在栅极绝缘层上制作形成第一栅极、第二栅极和第一存储电容电极；在多晶硅层的两端分别制作形成第一源极接触部和第一漏极接触部，且在金属氧化物半导体层的两端分别制作形成第二源极接触部和第二漏极接触部；在栅极绝缘层、第一栅极、第二栅极和第一存储电容电极上制作形成层间绝缘层；在层间绝缘层上制作形成第一源极、第一漏极、第二源极、第二漏极和第二存储电容电极；所述第一源极、第一漏极、第二源极和第二漏极贯穿层间绝缘层和栅极绝缘层，以分别与对应的第一源极接触部、第一漏极接触部、第二源极接触部和第二漏极接触部接触；在层间绝缘层、第一源极、第一漏极、第二源极、第二漏极和第二存储电容电极上制作形成平坦层；在平坦层上制作形成底电极；所述底电极贯穿平坦层，以与第一漏极接触；在平坦层和底电极上形成像素限定层，并且在像素限定层中形成暴露底电极的凹槽；在暴露的底电极上顺序形成有机电致发光器件和顶电极。
可选地，在基板上制作形成多晶硅层和金属氧化物半导体层之前，先在基板上制作形成缓冲层。
可选地，在制作形成平坦层之前，先在层间绝缘层、第一源极、第一漏极、第二源极、第二漏极和第二存储电容电极上制作形成钝化层。
可选地，在基板上制作形成多晶硅层和金属氧化物半导体层的方法包括步骤：在基板上沉积非晶硅层；以退火方式使非晶硅层再结晶，从而形成多晶硅层；在基板上沉积与所述多晶硅层分隔开的金属氧化物半导体层。
可选地，在基板、多晶硅层和金属氧化物半导体层上制作形成栅极绝缘层之后，对栅极绝缘层的与多晶硅层相对的部分或栅极绝缘层的与金属氧化物半导体层相对的部分进行减薄。
可选地，在栅极绝缘层上制作形成第一栅极、第二栅极和第一存储电容电极的方法包括步骤：在栅极绝缘层上沉积栅极金属层；在栅极金属层上涂布光阻；对光阻进行曝光、显影，以去除将要形成的第一栅极、第二栅极和第一存储电容电极上的光阻以外的光阻；将暴露出的栅极金属层刻蚀去除。
可选地，制作形成第一源极接触部、第一漏极接触部、第二源极接触部和第二漏极接触部的方法包括步骤：对多晶硅层的两端和金属氧化物半导体层的两端分别进行离子注入；去除第一栅极、第二栅极和第一存储电容电极上的光阻；对离子注入后的多晶硅层和金属氧化物半导体层进行加热活化，从而在多晶硅层的两端分别形成第一源极接触部和第一漏极接触部，且在金属氧化物半导体层的两端分别形成第二源极接触部和第二漏极接触部。
可选地，在对多晶硅层的两端和金属氧化物半导体层的两端分别进行离子注入的步骤中，采用的离子为硼离子。
本发明的有益效果：在本发明中，利用低温多晶硅薄膜晶体管作为驱动薄膜晶体管，其漏极与OLED的底电极接触，从而提供给OLED的电流稳定，使OLED发光稳定；并且利用金属氧化物半导体薄膜晶体管作为引入外部送入的电压信号的开关薄膜晶体管，金属氧化物半导体薄膜晶体管的漏电较低，从而能够实现更优的电路关闭效果。此外，金属氧化物半导体薄膜晶体管虽然光照可靠性差，但是其只作为开关薄膜晶体管时光照可靠性差对整个器件影响较小，而低温多晶硅薄膜晶体管的光照可靠性比较好，因此无需在基板上制作遮光层；并且二者都是顶栅结构，所以不会增加制程工序，而且寄生电容都比较小。
附图说明
通过结合附图进行的以下描述，本发明的实施例的上述和其它方面、特点和优点将变得更加清楚，附图中：
图1是根据本发明的实施例的OLED显示面板的像素电路图；
图2A至图2L是根据本发明的实施例的OLED显示面板的制作流程图；
图3A至图3C示出根据本发明的实施例的多晶硅层和金属氧化物半导体层的制作流程图；
图4A至图4D是根据本发明的实施例的第一栅极、第二栅极和第一存储电容电极的制作流程图；
图5A至图5C是根据本发明的实施例的第一源极接触部、第一漏极接触部、第二源极接触部和第二漏极接触部的制作流程图。
具体实施方式
以下，将参照附图来详细描述本发明的实施例。然而，可以以许多不同的形式来实施本发明，并且本发明不应该被解释为限制于这里阐述的具体实施例。相反，提供这些实施例是为了解释本发明的原理及其实际应用，从而使本领域的其他技术人员能够理解本发明的各种实施例和适合于特定预期应用的各种修改。
在附图中，为了清楚器件，夸大了层和区域的厚度。相同的标号在整个说明书和附图中表示相同的元器件。
图1是根据本发明的实施例的OLED显示面板的像素电路图。
参照图1，在主动式OLED显示面板中，主动驱动方式是有TFT和储存电容来控制像素的明暗，当扫描线开启时，外部电路送入的电压信号经数据线和开关TFT100储存在储存电容300中，该电压信号控制驱动TFT200导通电流的大小，该电流大小决定OLED400的灰阶，当扫描线关闭时，储存于储存电容300中的电压仍能保持驱动TFT200处于导通状态，故能在一个画面时间内能为OLED提供固定电流。
在本实施例中，驱动TFT200为低温多晶硅薄膜晶体管，开关TFT100为金属氧化物半导体薄膜晶体管。进一步地，所述低温多晶硅薄膜晶体管为P型低温多晶硅薄膜晶体管，所述金属氧化物半导体薄膜晶体管为N型金属氧化物半导体薄膜晶体管。
以下对本实施例的OLED显示面板的制作方法进行说明。图2A至图2L是根据本发明的实施例的OLED显示面板的制作流程图。需要说明的是，在图2A至图2L中，为了便于图示，没有示出图1中的扫描线、数据线、电源线和电容线，在实际的OLED显示面板中是具有这些被省略的元件的。
根据本发明的实施例的OLED显示面板的制作方法包括：
步骤一：参照图2A，在基板500上制作形成缓冲层1021。应当说明的是，作为本发明的另一实施方式，如果根据实际需求不需要缓冲层1021时，该步骤一可以被省略。
这里，基板500可例如为一绝缘且透明的玻璃基板或树脂基板。缓冲层1021可例如为通过PECVD工艺等在基板500上形成的SiNx/SiOx结构，但本发明并不限制于此，例如缓冲层1021也可以是单层的SiNx结构或SiOx结构。
步骤二：参照图2B，在缓冲层1021上制作形成分隔开的多晶硅层210和金属氧化物半导体层110。图3A至图3C示出根据本发明的实施例的多晶硅层210和金属氧化物半导体层110的制作流程图。
首先，参照图3A，在缓冲层1021上沉积非晶硅层a-Si。这里，可例如以溅射方式在缓冲层1021表面形成一非晶硅层a-Si。
接着，参照图3B，以退火方式使非晶硅层a-Si再结晶，从而形成多晶硅层210。
最后，参照图3C，在缓冲层1021上沉积与多晶硅层210分隔开的金属氧化物半导体层110。这里，金属氧化物半导体层110可例如由铟镓锌氧化物(IGZO)、铟锡锌氧化物(ITZO)等金属氧化物材料制成。
步骤三：参照图2C，在缓冲层1021、多晶硅层210和金属氧化物半导体层110上制作形成栅极绝缘层1022。这里，栅极绝缘层1022可例如为通过PECVD工艺在缓冲层1021、多晶硅层210和金属氧化物半导体层110上形成的SiNx/SiOx结构，但本发明并不限制于此，例如栅极绝缘层1022也可以是单层的SiNx结构或SiOx结构。
在步骤三中，可以根据之后的对多晶硅层210和金属氧化物半导体层110进行注入时所注入的离子浓度不同而对相应的栅极绝缘层1022进行减薄，例如当注入多晶硅层210的离子浓度高于注入金属氧化物半导体层110的离子浓度时，对与多晶硅层210相对的栅极绝缘层1022进行减薄；当注入多晶硅层210的离子浓度低于注入金属氧化物半导体层110的离子浓度时，对与金属氧化物半导体层110相对的栅极绝缘层1022进行减薄。
步骤四：参照图2D，在栅极绝缘层1022上制作形成第一栅极220、第二栅极120和第一存储电容电极310。图4A至图4D是根据本发明的实施例的第一栅极、第二栅极和第一存储电容电极的制作流程图。
首先，参照图4A，在栅极绝缘层1022上沉积栅极金属层IM。栅极金属层IM可例如是钼铝钼(MoAlMo)结构或钛铝钛(TiAlTi)结构，也可以是单层的钼结构或者单层的铝结构。
接着，参照图4B，在栅极金属层IM上涂布光阻PR。
接着，参照图4C，对光阻PR进行曝光、显影，以去除将要形成的第一栅极220、第二栅极120和第一存储电容电极310上的光阻PR以外的光阻PR。
最后，参照图4D，将暴露出的栅极金属层IM刻蚀去除，以形成第一栅极220、第二栅极120和第一存储电容电极310。其中，第一栅极220与多晶硅层210相对，第二栅极120与金属氧化物半导体层110，并且第一栅极220、第二栅极120和第一存储电容电极310相互分隔开。
步骤五：参照图2E，在多晶硅层210的两端分别制作形成第一源极接触部210a和第一漏极接触部210b，且在金属氧化物半导体层110的两端分别制作形成第二源极接触部110a和第二漏极接触部110b。图5A至图5C是根据本发明的实施例的第一源极接触部、第一漏极接触部、第二源极接触部和第二漏极接触部的制作流程图。
首先，参照图5A，同时对多晶硅层210的两端和金属氧化物半导体层110的两端分别进行离子注入。优选地，采用硼离子进行离子注入，但本发明并不限制于此。这里，多晶硅层210的两端注入的离子浓度高于金属氧化物半导体 层110的两端注入的离子浓度，具体参照上述步骤三中的描述。
接着，参照图5B，去除第一栅极220、第二栅极120和第一存储电容电极310上的光阻PR。
最后，参照图5C，对离子注入后的多晶硅层210和金属氧化物半导体层110进行加热活化，从而在多晶硅层210的两端分别制作形成第一源极接触部210a和第一漏极接触部210b，且在金属氧化物半导体层110的两端分别制作形成第二源极接触部110a和第二漏极接触部110b。
步骤六：参照图2F，在栅极绝缘层1022、第一栅极220、第二栅极120和第一存储电容电极310上制作形成层间绝缘层(ILD)1023。这里，层间绝缘层1023可例如为通过PECVD工艺在栅极绝缘层1022、第一栅极220、第二栅极120和第一存储电容电极310上形成的SiNx/SiOx结构，但本发明并不限制于此，例如层间绝缘层1023也可以是单层的SiNx结构或SiOx结构。
步骤七：参照图2G，在层间绝缘层1023上制作形成第一源极230、第一漏极240、第二源极130、第二漏极140和第二存储电容电极320；所述第一源极230、第一漏极240、第二源极130、第二漏极140贯穿层间绝缘层1023和栅极绝缘层1022，以分别与对应的第一源极接触部210a、第一漏极接触部210b、第二源极接触部110a和第二漏极接触部110b接触。
这里，制作第一源极230、第一漏极240、第二源极130、第二漏极140和第二存储电容电极320的方法类同于步骤四中制作第一栅极220、第二栅极120和第一存储电容电极310的方法，在此不再赘述。第一源极230、第一漏极240、第二源极130、第二漏极140和第二存储电容电极320可采用钼铝钼(MoAlMo)结构或钛铝钛(TiAlTi)结构，也可以是单层的钼结构或者单层的铝结构。
步骤八：参照图2H，在层间绝缘层1023、第一源极230、第一漏极240、第二源极130、第二漏极140和第二存储电容电极320上制作形成钝化层(PV)1024。应当说明的是，作为本发明的另一实施方式，如果根据实际需求不需要钝化层1024时，该步骤八可以被省略。
步骤九：参照图2I，在钝化层1024上制作形成平坦层(PLN)1025。
步骤十：参照图2J，在平坦层1025上形成底电极410；该底电极410贯穿平坦层1025和钝化层1024，以与第一漏极240接触。在本实施例中，底电极410可例如由氧化铟锡(ITO)制成，但本发明并不限制于此，例如，底电极210也可以由反射性金属制成，并且应该足够薄以便在发射光的波长下具有部分透光率，这被称为是半透明的。
步骤十一：参照图2K，在平坦层1025和底电极410上形成像素限定层(PDL)1026，并在像素限定层1026中形成暴露出底电极410的凹槽1026a。
步骤十二：参照图2L，在暴露的底电极410上顺序形成有机电致发光器件420和顶电极430。这里，有机电致发光器件420从底电极410到顶电极430顺序包括空穴注入层(HIL)、空穴传输层(HTL)、发光层(EML)、电子传输层(ETL)以及电子注入层(EIL)，但本发明并不限制于此。顶电极430可以由反射性金属制成，并且应该足够厚，以使其基本上是不透光的且是全反光镜，但本发明并不限制于此。
综上所述，根据本发明的实施例，利用低温多晶硅薄膜晶体管作为驱动薄膜晶体管，其漏极与OLED的底电极接触，从而提供给OLED的电流稳定，使OLED发光稳定；利用金属氧化物半导体薄膜晶体管作为引入外部送入的电压信号的开关薄膜晶体管，金属氧化物半导体薄膜晶体管的漏电较低，从而能够实现更优的电路关闭效果。此外，金属氧化物半导体薄膜晶体管虽然光照可靠性差，但是其只作为开关薄膜晶体管时光照可靠性差对整个器件影响较小，而低温多晶硅薄膜晶体管的光照可靠性比较好，因此无需在基板上制作遮光层；并且二者都是顶栅结构，所以不会增加制程工序，而且寄生电容都比较小。
虽然已经参照特定实施例示出并描述了本发明，但是本领域的技术人员将理解：在不脱离由权利要求及其等同物限定的本发明的精神和范围的情况下，可在此进行形式和细节上的各种变化。

Claims (20)

  1. 一种有机发光显示面板，其中，包括：基板以及形成在所述基板上的驱动薄膜晶体管、开关薄膜晶体管、存储电容、有机发光器件，外部电压信号经所述开关薄膜晶体管储存在所述存储电容中，所述外部电压信号控制所述驱动薄膜晶体管的导通电流的大小，以控制所述有机发光器件的灰阶，所述驱动薄膜晶体管为低温多晶硅薄膜晶体管，所述开关薄膜晶体管为金属氧化物半导体薄膜晶体管。
  2. 根据权利要求1所述的有机发光显示面板。其中，所述低温多晶硅薄膜晶体管为P型低温多晶硅薄膜晶体管，所述金属氧化物半导体薄膜晶体管为N型金属氧化物半导体薄膜晶体管。
  3. 一种权利要求1所述的有机发光显示面板的制作方法，其中，包括：
    在基板上制作形成多晶硅层和金属氧化物半导体层；
    在基板、多晶硅层和金属氧化物半导体层上制作形成栅极绝缘层；
    在栅极绝缘层上制作形成第一栅极、第二栅极和第一存储电容电极；
    在多晶硅层的两端分别制作形成第一源极接触部和第一漏极接触部，且在金属氧化物半导体层的两端分别制作形成第二源极接触部和第二漏极接触部；
    在栅极绝缘层、第一栅极、第二栅极和第一存储电容电极上制作形成层间绝缘层；
    在层间绝缘层上制作形成第一源极、第一漏极、第二源极、第二漏极和第二存储电容电极；所述第一源极、第一漏极、第二源极和第二漏极贯穿层间绝缘层和栅极绝缘层，以分别与对应的第一源极接触部、第一漏极接触部、第二源极接触部和第二漏极接触部接触；
    在层间绝缘层、第一源极、第一漏极、第二源极、第二漏极和第二存储电容电极上制作形成平坦层；
    在平坦层上制作形成底电极；所述底电极贯穿平坦层，以与第一漏极接触；
    在平坦层和底电极上形成像素限定层，并且在像素限定层中形成暴露底电极的凹槽；
    在暴露的底电极上顺序形成有机电致发光器件和顶电极。
  4. 根据权利要求3所述的有机发光显示面板的制作方法，其中，在基板上制作形成多晶硅层和金属氧化物半导体层之前，先在基板上制作形成缓冲层。
  5. 根据权利要求3所述的有机发光显示面板的制作方法，其中，在制作形成平坦层之前，先在层间绝缘层、第一源极、第一漏极、第二源极、第二漏极和第二存储电容电极上制作形成钝化层。
  6. 根据权利要求3所述的有机发光显示面板的制作方法，其中，在基板上制作形成多晶硅层和金属氧化物半导体层的方法包括步骤：
    在基板上沉积非晶硅层；
    以退火方式使非晶硅层再结晶，从而形成多晶硅层；
    在基板上沉积与所述多晶硅层分隔开的金属氧化物半导体层。
  7. 根据权利要求4所述的有机发光显示面板的制作方法，其中，在基板上制作形成多晶硅层和金属氧化物半导体层的方法包括步骤：
    在基板上沉积非晶硅层；
    以退火方式使非晶硅层再结晶，从而形成多晶硅层；
    在基板上沉积与所述多晶硅层分隔开的金属氧化物半导体层。
  8. 根据权利要求5所述的有机发光显示面板的制作方法，其中，在基板上制作形成多晶硅层和金属氧化物半导体层的方法包括步骤：
    在基板上沉积非晶硅层；
    以退火方式使非晶硅层再结晶，从而形成多晶硅层；
    在基板上沉积与所述多晶硅层分隔开的金属氧化物半导体层。
  9. 根据权利要求3所述的有机发光显示面板的制作方法，其中，在基板、多晶硅层和金属氧化物半导体层上制作形成栅极绝缘层之后，对栅极绝缘层的与多晶硅层相对的部分或栅极绝缘层的与金属氧化物半导体层相对的部分进行减薄。
  10. 根据权利要求4所述的有机发光显示面板的制作方法，其中，在基板、多晶硅层和金属氧化物半导体层上制作形成栅极绝缘层之后，对栅极绝缘层的与多晶硅层相对的部分或栅极绝缘层的与金属氧化物半导体层相对的部分进行减薄。
  11. 根据权利要求5所述的有机发光显示面板的制作方法，其中，在基板、多晶硅层和金属氧化物半导体层上制作形成栅极绝缘层之后，对栅极绝缘层的与多晶硅层相对的部分或栅极绝缘层的与金属氧化物半导体层相对的部分进行减薄。
  12. 根据权利要求3所述的有机发光显示面板的制作方法，其中，在栅极绝缘层上制作形成第一栅极、第二栅极和第一存储电容电极的方法包括步骤：
    在栅极绝缘层上沉积栅极金属层；
    在栅极金属层上涂布光阻；
    对光阻进行曝光、显影，以去除将要形成的第一栅极、第二栅极和第一存储电容电极上的光阻以外的光阻；
    将暴露出的栅极金属层刻蚀去除。
  13. 根据权利要求4所述的有机发光显示面板的制作方法，其中，在栅极绝缘层上制作形成第一栅极、第二栅极和第一存储电容电极的方法包括步骤：
    在栅极绝缘层上沉积栅极金属层；
    在栅极金属层上涂布光阻；
    对光阻进行曝光、显影，以去除将要形成的第一栅极、第二栅极和第一存储电容电极上的光阻以外的光阻；
    将暴露出的栅极金属层刻蚀去除。
  14. 根据权利要求5所述的有机发光显示面板的制作方法，其中，在栅极绝缘层上制作形成第一栅极、第二栅极和第一存储电容电极的方法包括步骤：
    在栅极绝缘层上沉积栅极金属层；
    在栅极金属层上涂布光阻；
    对光阻进行曝光、显影，以去除将要形成的第一栅极、第二栅极和第一存储电容电极上的光阻以外的光阻；
    将暴露出的栅极金属层刻蚀去除。
  15. 根据权利要求12所述的有机发光显示面板的制作方法，其中，制作形成第一源极接触部、第一漏极接触部、第二源极接触部和第二漏极接触部的方法包括步骤：
    对多晶硅层的两端和金属氧化物半导体层的两端分别进行离子注入；
    去除第一栅极、第二栅极和第一存储电容电极上的光阻；
    对离子注入后的多晶硅层和金属氧化物半导体层进行加热活化，从而在多晶硅层的两端分别形成第一源极接触部和第一漏极接触部，且在金属氧化物半导体层的两端分别形成第二源极接触部和第二漏极接触部。
  16. 根据权利要求13所述的有机发光显示面板的制作方法，其中，制作形成第一源极接触部、第一漏极接触部、第二源极接触部和第二漏极接触部的方法包括步骤：
    对多晶硅层的两端和金属氧化物半导体层的两端分别进行离子注入；
    去除第一栅极、第二栅极和第一存储电容电极上的光阻；
    对离子注入后的多晶硅层和金属氧化物半导体层进行加热活化，从而在多 晶硅层的两端分别形成第一源极接触部和第一漏极接触部，且在金属氧化物半导体层的两端分别形成第二源极接触部和第二漏极接触部。
  17. 根据权利要求14所述的有机发光显示面板的制作方法，其中，制作形成第一源极接触部、第一漏极接触部、第二源极接触部和第二漏极接触部的方法包括步骤：
    对多晶硅层的两端和金属氧化物半导体层的两端分别进行离子注入；
    去除第一栅极、第二栅极和第一存储电容电极上的光阻；
    对离子注入后的多晶硅层和金属氧化物半导体层进行加热活化，从而在多晶硅层的两端分别形成第一源极接触部和第一漏极接触部，且在金属氧化物半导体层的两端分别形成第二源极接触部和第二漏极接触部。
  18. 根据权利要求15所述的有机发光显示面板的制作方法，其中，在对多晶硅层的两端和金属氧化物半导体层的两端分别进行离子注入的步骤中，采用的离子为硼离子。
  19. 根据权利要求16所述的有机发光显示面板的制作方法，其中，在对多晶硅层的两端和金属氧化物半导体层的两端分别进行离子注入的步骤中，采用的离子为硼离子。
  20. 根据权利要求17所述的有机发光显示面板的制作方法，其中，在对多晶硅层的两端和金属氧化物半导体层的两端分别进行离子注入的步骤中，采用的离子为硼离子。
PCT/CN2017/071590 2016-12-22 2017-01-18 有机发光显示面板及其制作方法 WO2018113066A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/504,473 US10263057B2 (en) 2016-12-22 2017-01-18 Organic light emitting display panel and manufacturing method thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201611196057.9 2016-12-22
CN201611196057.9A CN106783921A (zh) 2016-12-22 2016-12-22 有机发光显示面板及其制作方法

Publications (1)

Publication Number Publication Date
WO2018113066A1 true WO2018113066A1 (zh) 2018-06-28

Family

ID=58897490

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/071590 WO2018113066A1 (zh) 2016-12-22 2017-01-18 有机发光显示面板及其制作方法

Country Status (3)

Country Link
US (1) US10263057B2 (zh)
CN (1) CN106783921A (zh)
WO (1) WO2018113066A1 (zh)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105810573A (zh) * 2016-03-15 2016-07-27 深圳市华星光电技术有限公司 薄膜晶体管的制作方法
CN107293552A (zh) * 2017-06-05 2017-10-24 深圳市华星光电技术有限公司 一种阵列基板及显示装置
CN109273404B (zh) * 2017-07-12 2021-01-26 京东方科技集团股份有限公司 一种阵列基板及其制备方法、显示面板、显示装置
CN107403829A (zh) * 2017-08-07 2017-11-28 京东方科技集团股份有限公司 显示单元及其制备方法、显示面板
CN108206008B (zh) * 2018-01-11 2019-12-31 京东方科技集团股份有限公司 像素电路、驱动方法、电致发光显示面板及显示装置
CN109166869A (zh) * 2018-09-05 2019-01-08 合肥鑫晟光电科技有限公司 阵列基板及其制备方法、显示装置
WO2020102985A1 (en) * 2018-11-20 2020-05-28 Boe Technology Group Co., Ltd. Display substrate, display apparatus, and method of fabricating display substrate
CN111403418B (zh) * 2018-12-29 2023-04-18 广东聚华印刷显示技术有限公司 阵列基板及其制作方法、显示器件
CN109904173B (zh) * 2019-01-11 2021-08-06 惠科股份有限公司 一种显示面板、显示面板的制造方法和显示装置
US11302760B2 (en) 2019-04-19 2022-04-12 Boe Technology Group Co., Ltd. Array substrate and fabrication method thereof, and display device
CN110264946A (zh) * 2019-05-21 2019-09-20 合肥维信诺科技有限公司 一种像素电路和显示装置
CN110299322B (zh) * 2019-07-03 2022-03-08 京东方科技集团股份有限公司 一种显示基板及其制作方法、显示装置
CN110610900A (zh) * 2019-08-19 2019-12-24 武汉华星光电半导体显示技术有限公司 显示面板的制备方法及显示面板
CN110660813A (zh) * 2019-08-21 2020-01-07 福建华佳彩有限公司 一种oled面板及制作方法
CN110993612A (zh) * 2019-11-27 2020-04-10 深圳市华星光电半导体显示技术有限公司 阵列基板及其制作方法
CN114730738A (zh) * 2020-09-22 2022-07-08 京东方科技集团股份有限公司 阵列基板、显示面板和显示装置
CN112530978B (zh) * 2020-12-01 2024-02-13 京东方科技集团股份有限公司 开关器件结构及其制备方法、薄膜晶体管膜层、显示面板
WO2023021623A1 (ja) * 2021-08-18 2023-02-23 シャープディスプレイテクノロジー株式会社 表示装置及びその製造方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010131827A1 (ko) * 2009-05-13 2010-11-18 포인트엔지니어링 다공성 기판을 이용한 유기발광소자 및 그 제조 방법
CN102280491A (zh) * 2011-06-02 2011-12-14 友达光电股份有限公司 混合式薄膜晶体管及其制造方法以及显示面板
CN103715196A (zh) * 2013-12-27 2014-04-09 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示装置
CN104538401A (zh) * 2014-12-23 2015-04-22 深圳市华星光电技术有限公司 Tft基板结构
CN105612620A (zh) * 2014-02-25 2016-05-25 乐金显示有限公司 显示器底板及其制造方法
CN105931988A (zh) * 2016-05-30 2016-09-07 深圳市华星光电技术有限公司 Amoled像素驱动电路的制作方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20080016245A (ko) * 2006-08-18 2008-02-21 삼성전자주식회사 표시 패널과 이를 구비한 표시 장치
CN103456765B (zh) * 2013-09-10 2015-09-16 深圳市华星光电技术有限公司 有源式有机电致发光器件背板及其制作方法
KR102222901B1 (ko) * 2014-07-07 2021-03-04 엘지디스플레이 주식회사 유기발광 표시장치 구동 방법
KR102484383B1 (ko) * 2014-09-30 2023-01-03 엘지디스플레이 주식회사 유기발광다이오드 표시패널 및 이의 표시장치
CN105929615B (zh) * 2016-06-21 2019-05-03 武汉华星光电技术有限公司 一种薄膜晶体管阵列基板及液晶面板

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010131827A1 (ko) * 2009-05-13 2010-11-18 포인트엔지니어링 다공성 기판을 이용한 유기발광소자 및 그 제조 방법
CN102280491A (zh) * 2011-06-02 2011-12-14 友达光电股份有限公司 混合式薄膜晶体管及其制造方法以及显示面板
CN103715196A (zh) * 2013-12-27 2014-04-09 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示装置
CN105612620A (zh) * 2014-02-25 2016-05-25 乐金显示有限公司 显示器底板及其制造方法
CN104538401A (zh) * 2014-12-23 2015-04-22 深圳市华星光电技术有限公司 Tft基板结构
CN105931988A (zh) * 2016-05-30 2016-09-07 深圳市华星光电技术有限公司 Amoled像素驱动电路的制作方法

Also Published As

Publication number Publication date
US20180226462A1 (en) 2018-08-09
CN106783921A (zh) 2017-05-31
US10263057B2 (en) 2019-04-16

Similar Documents

Publication Publication Date Title
WO2018113066A1 (zh) 有机发光显示面板及其制作方法
US9793252B2 (en) Method of integrating inorganic light emitting diode with oxide thin film transistor for display applications
US10056445B2 (en) Manufacture method of AMOLED pixel drive circuit
US9768323B2 (en) Manufacture method of dual gate oxide semiconductor TFT substrate and structure thereof
US10361256B2 (en) OLED back plate
US9799677B2 (en) Structure of dual gate oxide semiconductor TFT substrate
CN106057735B (zh) Tft背板的制作方法及tft背板
US20170271418A1 (en) Oled display substrate and manufacturing method thereof and display apparatus
CN109326624B (zh) 像素电路、其制造方法及显示装置
US10559639B2 (en) Organic light-emitting display device and method for manufacturing the same
WO2017024658A1 (zh) 有机发光显示器及其制造方法
KR101506671B1 (ko) 유기 발광 장치 및 그 제조 방법
US20110240986A1 (en) Pixel structure of electroluminescent display panel and method of making the same
WO2015100808A1 (zh) 一种具有氧化物薄膜电晶体的发光装置及其制造方法
US20220302321A1 (en) Thin film transistor array substrate, display panel and display device
US20170352711A1 (en) Manufacturing method of tft backplane and tft backplane
TWI375282B (en) Thin film transistor(tft)manufacturing method and oled display having tft manufactured by the same
KR20180069974A (ko) 트랜지스터 표시판 및 이를 포함하는 표시 장치
US10192903B2 (en) Method for manufacturing TFT substrate
KR100728196B1 (ko) 유기 발광 표시 장치의 제조 방법
WO2018223434A1 (zh) 一种阵列基板及显示装置
CN100454572C (zh) 有源式有机发光二极管的像素结构及其制造方法
KR100659714B1 (ko) 유기 발광 표시 장치 및 그 제조방법
KR100728128B1 (ko) 유기 발광 표시 장치 및 그 제조방법
KR101067939B1 (ko) 유기전계발광표시소자의 제조방법

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 15504473

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17882898

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 17882898

Country of ref document: EP

Kind code of ref document: A1