WO2018094597A1 - Tft阵列基板制作方法及tft阵列基板 - Google Patents

Tft阵列基板制作方法及tft阵列基板 Download PDF

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WO2018094597A1
WO2018094597A1 PCT/CN2016/106888 CN2016106888W WO2018094597A1 WO 2018094597 A1 WO2018094597 A1 WO 2018094597A1 CN 2016106888 W CN2016106888 W CN 2016106888W WO 2018094597 A1 WO2018094597 A1 WO 2018094597A1
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layer
channel
oxide
tft array
array substrate
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李文辉
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Shenzhen Royole Technologies Co Ltd
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Shenzhen Royole Technologies Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/86—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group II-VI materials, e.g. ZnO
    • H10D62/864—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group II-VI materials, e.g. ZnO further characterised by the dopants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the present invention relates to the field of touch panel manufacturing technologies, and in particular, to a TFT array substrate manufacturing method and a TFT array substrate.
  • a conventional oxide semiconductor TFT (Thin Film Transistor) device is often provided with an etch barrier layer (ESL) which can protect the semiconductor layer and prevent damage to the semiconductor during etching of the second metal.
  • ESL etch barrier layer
  • a TFT having an etch barrier structure has a large channel length, which causes a decrease in the conductivity of the TFT, and thus it is necessary to design a TFT of a larger size to affect the aperture ratio.
  • the present application provides a TFT array substrate manufacturing method and a TFT array substrate, which reduces the channel length of the TFT array substrate and increases the aperture ratio.
  • the method for fabricating a TFT array substrate according to the present application includes sequentially forming a gate electrode, an insulating layer, and an oxide conductor layer on a substrate; wherein an oxide layer is projected onto the gate electrode;
  • the oxide conductor layer region is treated at a position opposite to the channel to form a semiconductor channel.
  • the processing of the oxide conductor layer region opposite to the channel, forming a semiconductor channel is increasing the oxygen content of the oxide conductor layer region of the opposite position of the channel, and making the oxide conductor corresponding to the channel
  • the layer region becomes a semiconductor to form the semiconductor channel.
  • the manner of increasing the oxygen content of the oxide conductor layer at the relative position of the channel comprises: high temperature baking at the channel in a high oxygen environment.
  • the method for increasing the oxygen content of the oxide conductor layer at the relative position of the channel comprises: plasma-treating the channel with the patterned second metal layer as a mask.
  • the plasma is O 2 or N 2 O.
  • the step sequentially forms a gate electrode, an insulating layer and an oxide conductor layer on the substrate, and the oxide conductor layer is formed by low temperature sputtering.
  • the step of sequentially forming a gate electrode, an insulating layer and an oxide conductor layer on the substrate comprises a step of sputtering to form an oxide semiconductor base layer film and baking the oxide semiconductor base layer film at a high temperature.
  • the step of baking the oxide semiconductor base film at a high temperature is vacuum baking or baking in an N 2 environment.
  • the step of forming an etch barrier on the oxide conductor layer comprises the steps of forming a barrier layer material layer on the oxide conductor layer and the insulating layer, and patterning the barrier material layer to form an etch barrier layer.
  • the TFT array substrate of the present application includes a substrate, a gate electrode sequentially formed on the surface of the substrate, a gate insulating layer, an oxide layer, an etch barrier layer, and a second metal layer having a pattern; the second metal layer is formed on the second metal layer a channel; the oxide layer includes a semiconductor region at a position opposite to the channel and an oxide conductor region on both sides of the semiconductor region, the channel forming a semiconductor channel with the semiconductor region.
  • the second metal electrode is used as a mask to define a channel length, and a semiconductor channel is formed according to the channel processing oxide conductor layer, thereby reducing the channel length of the TFT. Increase the aperture ratio.
  • FIG. 1 is a flow chart of a method of fabricating a TFT array substrate according to an embodiment of the present application.
  • FIG. 2 to FIG. 5 are schematic cross-sectional views showing respective steps of a method for fabricating a TFT array substrate of the present application.
  • FIG. 6 is a schematic cross-sectional view showing a TFT array substrate formed by the method of fabricating the TFT array substrate shown in FIG. 1.
  • the method for fabricating the TFT array substrate according to the embodiment of the present application may be, but not limited to, a liquid crystal display such as a mobile phone, a computer, a display, or an e-reader, which is not specifically limited in the embodiment of the present application.
  • the present invention provides a method for fabricating a TFT array substrate, including
  • step S1 the gate electrode 11, the insulating layer 12 and the oxide conductor layer 13 are sequentially formed on the substrate 10; wherein the oxide conductor layer 13 is projected onto the gate electrode 11.
  • the oxide conductor layer 13 is formed by low-temperature sputtering, that is, in a low-oxygen environment, sputtering, film formation, oxide semiconductor substrate film oxygen content is reduced, oxygen vacancies are more, partial body characteristics, and then oxidation The conductor layer 13.
  • the oxide semiconductor base film 13 is formed by step sputtering, and the oxide semiconductor base film is formed by high-temperature baking.
  • the step of baking the oxide conductor layer at a high temperature is vacuum baking or baking in an N2 environment. That is, in conventional sputtering of an oxide semiconductor base film, and then baking in a low-oxygen environment at a high temperature, such as vacuum baking, or baking under N2 atmosphere, the oxide semiconductor substrate film has a reduced oxygen content, more oxygen vacancies, and a bias
  • the conductor characteristics further form the oxide conductor layer 13.
  • it is not limited to the above two modes listed in the present application, and other embodiments in which an oxide conductor layer can be formed may be included.
  • step S2 an etching stopper layer 14 and a second metal layer 15 are sequentially formed on the oxide conductor layer 13.
  • the method includes the steps of: forming a barrier layer material layer on the oxide conductor layer 13 and the insulating layer 12, and step: patterning the barrier material layer to form an etch barrier layer 14.
  • the second metal layer 15 is patterned to form a channel 151.
  • a second metal layer (not shown) is formed on the etch stop layer 14, and the second metal layer 15 is patterned by a process such as development, exposure, etching, etc., in the process, a patterned second A photoresist layer is provided on the metal layer 15.
  • the photoresist layer can be removed after the next step or after the step is completed.
  • the second metal layer 15 is patterned to form a source line and a drain line.
  • the photoresist layer can be removed after the next step (step S4), which serves to protect the patterned second metal layer 15.
  • step S4 the oxide conductor layer region at a position opposite to the channel 151 is processed to form a semiconductor channel 16. Finally, the photoresist layer (not shown) is peeled off.
  • the oxide conductor layer region is disposed at a position opposite to the channel 151, and the semiconductor channel layer is formed to increase the oxygen content of the oxide conductor layer region relative to the relative position of the channel 151.
  • Oxygen penetrates the etch stop layer in combination with the oxide conductor layer, and the oxide conductor layer region corresponding to the channel becomes semiconductor gold to form the semiconductor channel 16.
  • the main principle is to treat the channel so that the oxygen content of the oxide layer in the channel increases, the oxygen vacancy decreases, and the movable electrons decrease, causing oxidation.
  • the material conductor is semiconducting.
  • One specific treatment method is:
  • the channel 151 is plasma treated with a patterned second metal, 15 as a mask.
  • the plasma is O 2 or N 2 O. That is, in the case where the etch barrier layer 14 is thin (which can be formed according to the design), the plasma can penetrate through the etch barrier layer, combine with the oxide of the oxide conductor layer, reduce oxygen vacancies, reduce movable electrons, and form a semiconductor. Thereby forming a semiconductor channel.
  • the other is: high temperature baking at the channel 151 in a high oxygen environment. That is to say, high temperature baking in a high oxygen atmosphere, part of the oxygen can penetrate through the etching barrier layer 14, combine with the oxide, reduce oxygen vacancies, reduce movable electrons, and form the semiconductor channel 16.
  • the high or low temperatures described herein refer to high temperature or low temperature data commonly used in the art.
  • a TFT array substrate In the method for fabricating a TFT array substrate according to the present application, after the gate insulating layer, an oxide conductor layer is formed, and then a second metal is formed, and a second metal electrode is used as a mask to define a channel length. Daoxinger handles the oxide conductor layer to form a semiconductor channel, thereby reducing the channel length of the TFT and improving the conductivity of the TFT, thereby designing a TFT of a smaller size and increasing the aperture ratio.
  • the present application further provides a TFT array substrate including a substrate 10, a gate electrode 11 sequentially formed on the surface of the substrate 10, a gate insulating layer 12, an oxide layer 13, an etch barrier layer 14, and a second metal layer.
  • a second surface of the second metal layer 15 is formed with a channel 151;
  • the oxide layer 13 includes a semiconductor region opposite to the channel 151 and an oxide conductor region 131 on both sides of the semiconductor region.
  • the channel and the semiconductor region form a semiconductor channel 16.

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  • Thin Film Transistor (AREA)

Abstract

一种TFT阵列基板及其制作方法，包括，在基板（10）上依次形成栅极（11）、绝缘层（12）及氧化物导体层（13）；其中氧化物层正投影于该栅极；在该氧化物导体层上依次形成蚀刻阻挡层（14）及第二金属层（15）；图案化该第二金属层形成沟道（151）；对与该沟道相对位置的氧化物导体层区域处理，形成半导体沟道。

Description

TFT阵列基板制作方法及TFT阵列基板 技术领域
本发明涉及触控面板制造技术领域，尤其涉及一种TFT阵列基板制作方法及TFT阵列基板。
背景技术
现有氧化物半导体TFT(Thin Film Transistor)器件，常采用具有刻蚀阻挡层(ESL)的结构，该刻蚀阻挡层可以保护半导体层，可以防止第二道金属蚀刻时损伤半导体。但是，具有刻蚀阻挡层结构的TFT，沟道长度偏大，造成TFT导电能力下降，从而需要设计较大尺寸的TFT，影响开口率。
发明内容
基于上述问题，本申请提供一种TFT阵列基板制作方法及TFT阵列基板，减小TFT阵列基板沟道长度，提高开口率。
本申请所述的TFT阵列基板制作方法包括，在基板上依次形成栅极、绝缘层及氧化物导体层；其中氧化物层正投影于所述栅极；
在所述氧化物导体层上依次形成蚀刻阻挡层及第二金属层；
图案化所述第二金属层形成沟道；
对与所述沟道相对位置的氧化物导体层区域处理，形成半导体沟道。
其中，所述对与所述沟道相对位置的氧化物导体层区域处理，形成半导体沟道是增加所述沟道相对位置的氧化物导体层区域含氧量，使沟道对应的氧化物导体层区域变成半导体而形成所述半导体沟道。
其中，所述增加所述沟道相对位置的氧化物导体层含氧量的方式包括：在高氧气环境下对沟道处高温烘烤。
其中，所述增加所述沟道相对位置的氧化物导体层含氧量的方式包括：以图案化的第二金属层为掩膜板对沟道进行等离子处理。
其中，所述等离子为O2或N2O。
其中，所述步骤在基板上依次形成栅极、绝缘层及氧化物导体层中，所述氧化物导体层通过低温溅镀形成。
其中，所述步骤在基板上依次形成栅极、绝缘层及氧化物导体层中，包括溅镀形成氧化物半导体基层薄膜，对氧化物半导体基层薄膜高温烘烤的步骤。
其中，所述对氧化物半导体基层薄膜高温烘烤的步骤为真空烘烤，或在N2环境下烘烤。
其中，步骤在所述氧化物导体层上形成蚀刻阻挡中，包括在所述氧化物导体层及绝缘层上形成阻挡层材料层，对阻挡材料层图案化形成蚀刻阻挡层的步骤。
本申请所述的TFT阵列基板包括基板、依次形成于基板表面的栅极、栅极绝缘层、氧化物层、蚀刻阻挡层及具有图形的第二金属层；所述第二金属层上形成有沟道；所述氧化物层包括与所述沟道相对位置的半导体区域及位于所述半导体区域两侧的氧化物导体区域，所述沟道与半导体区域形成半导体沟道。
本申请所述的TFT阵列基板制造方法中，以第二道金属电极作掩模，先定义沟道长度，在根据沟道处理氧化物导体层形成半导体沟道，进而减小TFT沟道长度，提高开口率。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例的TFT阵列基板制作方法的流程图。
图2至图5是本申请TFT阵列基板制作方法的各个步骤截面示意图。
图6是图1所示的TFT阵列基板制作方法形成的TFT阵列基板截面示意图。
具体实施方式
下面将结合本申请实施方式中的附图，对本申请实施方式中的技术方案进行清楚、完整地描述。
本申请实施例涉及的TFT阵列基板制作方法可以为但不限于手机、电脑、显示器或电子阅读器等液晶显示器中，本申请实施例对此不作具体限定。
请参阅图1与图2，本发明提供一种TFT阵列基板制作方法，包括，
步骤S1，在基板10上依次形成栅极11、绝缘层12及氧化物导体层13；其中氧化物导体层13正投影于所述栅极11。
其中，氧化物导体层13形成方式为：通过低温溅镀形成，即在低氧气环境下，溅镀成膜，氧化物半导体基层薄膜氧含量降低，氧空缺较多，偏向导体特性，进而形成氧化物导体层13。
或者是，通过步骤溅镀形成氧化物半导体基层薄膜13，及步骤对氧化物半导体基层薄膜高温烘烤形成。所述对氧化物导体层高温烘烤的步骤为真空烘烤，或在N2环境下烘烤。即，在常规溅镀成氧化物半导体基层薄膜，然后在低氧环境下高温烘烤，如真空烘烤，或N2气氛下烘烤，氧化物半导体基层薄膜氧含量降低，氧空缺较多，偏向导体特性，进而形成氧化物导体层13。当然，也不限于本申请列举的上述两种方式，还可以包含其它可以形成氧化物导体层的实施方式。
请参阅图3与图4，步骤S2，在所述氧化物导体层13上依次形成蚀刻阻挡层14及第二金属层15。本步骤中，包括步骤：在所述氧化物导体层13及绝缘层12上形成阻挡层材料层，以及步骤：对阻挡材料层图案化形成蚀刻阻挡层14。
步骤S3，图案化所述第二金属层15形成沟道151。其中，在所述蚀刻阻挡层14上形成第二金属层(图未示)，通过显影、曝光、蚀刻等工艺形成图案化所述第二金属层15，在此过程中，图案化的第二金属层15上设有光阻层。该光阻层可以在下一个步骤进行后去除，也可以在此步骤完成后去除。本实施例中，图案化所述第二金属层15主要为形成源极线及漏极线。该光阻层可在下一个步骤(步骤S4)进行后去除，这样可以起到保护图案化的第二金属层15的作用。
请参阅图5，步骤S4，对与所述沟道151相对位置的氧化物导体层区域处理，形成半导体沟道16。最后剥离所述光阻层(图未示)。
本申请中，所述对与所述沟道151相对位置的氧化物导体层区域处理，形成半导体沟道层是增加所述沟道151相对位置的氧化物导体层区域含氧量，以使部分氧穿透所述蚀刻阻挡层与氧化物导体层结合，所述沟道对应的氧化物导体层区域变成半导体金而形成所述半导体沟道16。主要原理是，对沟道进行处理，使沟道处氧化物层含氧量增加，氧空缺减少，可移动电子减少，使氧化 物导体呈半导体特性。具体处理方法一种是：
以图案化的第二金属，15为掩膜板对沟道151进行等离子处理。所述等离子为O2或N2O。即在刻蚀阻挡层14较薄(可以根据设计形成)的情况下，等离子可以渗透穿过刻蚀阻挡层，与氧化物导体层的氧化物结合，减少氧空缺，减少可移动电子，形成半导体，进而形成半导体沟道。
另一种是：在高氧气环境下对沟道151处高温烘烤。也就是说在高氧氛围下高温烘烤，部分氧可以渗透穿过刻蚀阻挡层14，与氧化物结合，减少氧空缺，减少可移动电子，形成半导体沟道16。本申请所述的高温或者低温均是指本领域内常用的高温或低温数据。
本申请所述的TFT阵列基板制造方法中，在栅极绝缘层后，制作氧化物导体层，然后制作第二道金属，以第二道金属电极作掩模，定义沟道长度，在根据沟道星创处理氧化物导体层形成半导体沟道，进而减小TFT沟道长度，提高TFT导电能力，从而可以设计较小尺寸的TFT，提高开口率。
参阅图5，本申请还提供一种TFT阵列基板，其包括基板10、依次形成于基板10表面的栅极11、栅极绝缘层12、氧化物层13、蚀刻阻挡层14及第二金属层15；所述第二金属层15上形成有沟道151；所述氧化物层13包括与所述沟道151相对位置的半导体区域及位于所述半导体区域两侧的氧化物导体区域131，所述沟道与半导体区域形成半导体沟道16。
以上所述是本申请的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本申请原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也视为本申请的保护范围。

Claims (10)

  1. 一种TFT阵列基板制作方法，其特征在于，包括，在基板上依次形成栅极、绝缘层及氧化物导体层；
    在所述氧化物导体层上依次形成蚀刻阻挡层及第二金属层；
    图案化所述第二金属层形成沟道；
    对与所述沟道相对位置的氧化物导体层区域处理，形成半导体沟道。
  2. 如权利要求1所述的TFT阵列基板制作方法，其特征在于，所述对与所述沟道相对位置的氧化物导体层区域处理，形成半导体沟道是增加所述沟道相对位置的氧化物导体层区域含氧量，以使部分氧穿透所述蚀刻阻挡层与氧化物导体层结合，所述沟道对应的氧化物导体层区域变成半导体而形成所述半导体沟道。
  3. 如权利要求2所述的TFT阵列基板制作方法，其特征在于，所述增加所述沟道相对位置的氧化物导体层含氧量的方式包括：在高氧气环境下对沟道处高温烘烤。
  4. 如权利要求2所述的TFT阵列基板制作方法，其特征在于，所述增加所述沟道相对位置的氧化物导体层含氧量的方式包括：以图案化的第二金属层为掩膜板对沟道进行等离子处理。
  5. 如权利要求4所述的TFT阵列基板制作方法，其特征在于，所述等离子为O2或N2O。
  6. 如权利要求1所述的TFT阵列基板制作方法，其特征在于，所述步骤在基板上依次形成栅极、绝缘层及氧化物导体层中，所述氧化物导体层通过低温溅镀形成。
  7. 如权利要求1所述的TFT阵列基板制作方法，其特征在于，所述步骤在基板上依次形成栅极、绝缘层及氧化物导体层中，包括溅镀形成氧化物半导体基层薄膜，对氧化物半导体基层薄膜高温烘烤的步骤。
  8. 如权利要求7所述的TFT阵列基板制作方法，其特征在于，所述对氧化物半导体基层薄膜高温烘烤的步骤为真空烘烤，或在N2环境下烘烤。
  9. 如权利要求1所述的TFT阵列基板制作方法，其特征在于，步骤在所述氧化物导体层上形成蚀刻阻挡中，包括在所述氧化物导体层及绝缘层上形成阻 挡层材料层，对阻挡材料层图案化形成蚀刻阻挡层的步骤。
  10. 一种TFT阵列基板，其特征在于，包括基板、依次形成于基板表面的栅极、栅极绝缘层、氧化物层、蚀刻阻挡层及具有图形的第二金属层；所述第二金属层上形成有沟道；所述氧化物层包括与所述沟道相对位置的半导体区域及位于所述半导体区域两侧的氧化物导体区域，所述沟道与半导体区域形成半导体沟道。
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