WO2017117974A1 - 一种阵列基板的制作方法、阵列基板和显示面板 - Google Patents

一种阵列基板的制作方法、阵列基板和显示面板 Download PDF

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WO2017117974A1
WO2017117974A1 PCT/CN2016/091505 CN2016091505W WO2017117974A1 WO 2017117974 A1 WO2017117974 A1 WO 2017117974A1 CN 2016091505 W CN2016091505 W CN 2016091505W WO 2017117974 A1 WO2017117974 A1 WO 2017117974A1
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layer
pattern
oxide
oxide layer
pixel electrode
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PCT/CN2016/091505
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English (en)
French (fr)
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舒适
冯京
徐传祥
何晓龙
王久石
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京东方科技集团股份有限公司
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Priority to US15/329,212 priority Critical patent/US10461178B2/en
Publication of WO2017117974A1 publication Critical patent/WO2017117974A1/zh

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    • H—ELECTRICITY
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02565—Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a method for fabricating an array substrate, an array substrate, and a display panel.
  • a thin film transistor (TFT) in the array substrate may be formed of an oxide semiconductor to form an active layer.
  • Oxide semiconductors have high mobility and can be manufactured in large size products.
  • oxide semiconductors also have some disadvantages, such as unstable characteristics, and often suffer from defects such as threshold voltage (Vth) drift, thereby limiting their wide range of uses.
  • Vth threshold voltage
  • One reason why the characteristics of the oxide semiconductor are unstable is that the lattice structure thereof does not match the gate insulating layer in the thin film transistor, resulting in a large number of defects at the contact interface between the two, and the defect is caused by the defect trapping the charge.
  • the present disclosure provides a method for fabricating an array substrate, an array substrate, and a display panel to solve the problem that the contact interface between the oxide semiconductor layer and the gate insulating layer in the existing array substrate does not match.
  • the present disclosure provides a method for fabricating an array substrate, comprising: sequentially forming a pattern of a gate metal layer and a gate insulating layer on a substrate; forming a pattern of the semiconductor layer, wherein the pattern of the semiconductor layer includes a pattern of an active layer region and a pixel electrode region, the semiconductor layer including a first oxide layer and a second oxide layer disposed in an overlapping manner, the first oxide layer being an insulating oxide layer, and the second oxide
  • the material layer is a semiconducting oxide layer, the first oxide layer is located between the gate insulating layer and the second oxide layer; a pattern forming a source/drain metal layer; and a region of the pixel electrode region
  • the second oxide layer is plasma treated such that the second oxide layer of the pixel electrode region is converted into a conductor.
  • the step of forming a pattern of the semiconductor layer comprises: forming a first oxide film by a sputtering process, wherein the sputtering process comprises a sputtering gas comprising oxygen and argon, and the ratio of oxygen is a ratio such that the first oxide film is an insulating oxide film; a second oxide film is formed by a sputtering process, and the sputtering gas used in the sputtering process includes oxygen and argon, and the ratio of oxygen is second a ratio of the second oxide film to a semiconducting oxide film; patterning the first oxide film and the second oxide film by a patterning process to form a pattern of a semiconductor layer, wherein the semiconductor layer comprises A first oxide layer formed of the first oxide film and a second oxide layer formed of the second oxide film.
  • the first ratio ranges from 60% to 90%, and the second ratio ranges from 30% to 55%.
  • the pattern of the gate metal layer includes a pattern of a gate
  • the pattern of the source/drain metal layer includes a pattern of a source and a drain
  • an orthographic projection of the pattern of the drain on the substrate The region completely falls within the orthographic projection area of the gate pattern on the substrate.
  • the step of forming a pattern of the source/drain metal layer further comprises: forming a pattern of the protective layer, the protective layer is an insulating oxide layer, and the pattern of the protective layer completely covers the source and the drain a second oxide layer corresponding to the gap region; forming a pattern of the passivation layer, the protective layer being located between the passivation layer and the second oxide layer.
  • the pattern of the source/drain metal layer includes a pattern of a source and a drain and a pattern of a pixel electrode region, the pattern of the protection layer further covering a pattern of a source and a drain, and the pattern forming the protective layer
  • the method further includes: etching the source/drain metal layer by using the protective layer as a mask to remove the pixel electrode region. Source and drain metal layer pattern.
  • the photoresist on the pattern of the protective layer is retained; wherein the step of performing plasma processing on the second oxide layer of the pixel electrode region is specifically: adopting the a photoresist is used as a mask to plasma-treat the second oxide layer of the pixel electrode region such that the semiconductor oxide of the pixel electrode region is converted into a conductor, wherein plasma treatment is performed using a reducing gas; The photoresist is stripped.
  • the pattern of the gate metal layer includes a pattern of a common electrode line; the pattern forming the passivation layer further includes: forming a pattern of a common electrode layer, the common electrode layer passing through the passivation layer and A via of the gate insulating layer is connected to the common electrode line.
  • the insulating oxide layer is an oxygen-rich oxide layer.
  • the present disclosure also provides an array substrate fabricated by the above method.
  • the array substrate comprises: a substrate substrate; a pattern of a gate metal layer, the pattern of the gate metal layer includes a gate; a pattern of a gate insulating layer; an active layer region pattern and a pixel electrode disposed in the same layer a region pattern, the active layer region pattern includes a first oxide layer and a second oxide layer disposed in an overlapping manner, the first oxide layer being located between the gate insulating layer and the second oxide layer
  • the pattern of the pixel electrode region includes: a first oxide layer and a conductor layer disposed in an overlapping manner, the first oxide layer is an insulating oxide, and the second oxide layer is a semiconducting oxide; a source and a drain a pattern of a pole, the orthographic projection area of the drain pattern on the substrate substrate completely falling within the orthographic projection area of the gate pattern on the substrate substrate.
  • the array substrate further includes: a pattern of a protective layer, wherein the protective layer is an insulating oxide layer, and the pattern of the protective layer completely covers a second oxidation corresponding to a gap region between the source and the drain a layer of matter; and a pattern of the passivation layer.
  • the pattern of the protective layer is between the pattern of the passivation layer and the second oxide layer.
  • the present disclosure also provides a display panel including the above array substrate.
  • the beneficial effects of the above technical solutions of the present disclosure are as follows: since an insulating oxide layer is disposed between the semiconducting oxide layer and the gate insulating layer, the insulating oxide layer and the semiconducting oxide layer have a good lattice matching degree. Therefore, the interface defects of the thin film transistor can be improved, and the defect due to the interface defect can be avoided. At the same time, by simultaneously forming the active layer and the pixel electrode by one patterning process, the number of masks can be reduced, and the production cost of the array substrate can be reduced.
  • FIG. 1 is a schematic diagram of a method for fabricating an array substrate according to some embodiments of the present disclosure.
  • base substrate 101 gate electrode 1021; common electrode line 1022; gate insulating layer 103; first oxide layer 1041; second oxide layer 1042; active layer 10421; pixel electrode 10422; 1051; drain 1052; source/drain metal layer pattern 1053 of the pixel electrode region; protective layer 106; passivation layer 107; via 108; common electrode 109;
  • the embodiment of the present disclosure provides a method for fabricating an array substrate, including the following steps.
  • Step S11 A pattern of a gate metal layer and a gate insulating layer is sequentially formed on the base substrate.
  • the pattern of the gate metal layer includes at least a pattern of gate electrodes.
  • a pattern of gate lines may also be included.
  • a pattern of common electrode lines can also be included.
  • the gate insulating layer may be made of an insulating material such as silicon dioxide (SiO 2 ).
  • Step S12 forming a pattern of a semiconductor layer, the pattern of the semiconductor layer including a pattern of an active layer region and a pixel electrode region, the semiconductor layer including a first oxide layer and a second oxide layer disposed in an overlapping manner, the first The first oxide layer is an insulating oxide layer, and the first oxide layer is between the gate insulating layer and the second oxide layer.
  • the insulating oxide in the present embodiment refers to an insulating oxide which is formed by increasing the proportion of oxygen during sputtering to form an oxide semiconductor, and such an insulating oxide is also called an oxygen-rich oxide.
  • Oxygen-rich oxides are insulative due to their low oxygen vacancies, and their lattice structure matches well with normal semiconducting oxides, thereby improving interface defects of thin film transistors and avoiding defects due to interface defects.
  • Step S13 forming a pattern of the source/drain metal layer.
  • the pattern of the source/drain metal layer includes at least a pattern of a source and a drain.
  • it can also be packaged Includes a graphic of the data line.
  • Step S14 performing plasma treatment on the second oxide layer of the pixel electrode region such that the second oxide layer of the pixel electrode region is converted into a conductor. After the second oxide layer of the pixel electrode region is converted into a conductor, it becomes a pixel electrode.
  • the insulating oxide and the semiconducting oxide are both transparent oxides.
  • IGZO or the like can be employed.
  • the insulating oxide layer and the semiconducting oxide layer have a good lattice matching degree. Therefore, the interface defects of the thin film transistor can be improved, and the defect due to the interface defect can be avoided.
  • the number of masks can be reduced, and the production cost of the array substrate can be reduced.
  • the step of forming a pattern of the semiconductor layer includes:
  • Step S121 forming a first oxide film by a sputtering process, the sputtering gas used in the sputtering process includes oxygen and argon, and the ratio of oxygen is a first ratio, so that the first oxide film is an insulating oxide a film (ie, an oxygen-rich oxide layer);
  • Step S122 forming a second oxide film by a sputtering process, the sputtering gas used in the sputtering process includes oxygen and argon, and the ratio of oxygen is a second ratio, so that the second oxide film is a semiconducting oxide film;
  • Step S123 patterning the first oxide film and the second oxide film by a patterning process to form a pattern of a semiconductor layer, the semiconductor layer including a first oxide layer formed of the first oxide film and a second oxide layer formed of the second oxide film.
  • the first ratio ranges from 60% to 90%, and the second ratio ranges from 30% to 55%.
  • an insulating oxide film and a semiconducting oxide film may be formed by a magnetron sputtering process.
  • the process conditions for forming the insulating oxide film by the magnetron sputtering process may be: the power is 2000-6000 W, the temperature is 20-50 ° C, and the oxygen ratio (ie the first ratio) is 60%-90%, argon gas. The ratio is 10 to 40%.
  • the process conditions for forming a semiconducting oxide film by a magnetron sputtering process may be: power of 2000 to 6000 W, temperature of 20 to 50 ° C, oxygen The ratio (ie the second ratio above) is 30% to 55%, and the argon ratio is 45% to 70%.
  • the passivation layer After forming the source/drain metal layer, it is also necessary to form a passivation layer. Since the lattice structure of the passivation layer and the semiconducting oxide layer are also not matched, if the passivation layer corresponds to a semiconductor oxide layer corresponding to a gap region between the source and the drain (the gap region is a channel region) In direct contact, the interface between the two also has defects, and the defect will cause defects after trapping the charge.
  • the step S15 and the step S16 are further included after the step of forming the pattern of the source/drain metal layer.
  • Step S15 forming a pattern of a protective layer, the protective layer being an insulating oxide layer, the pattern of the protective layer completely covering a second oxide layer corresponding to a gap region between the source and the drain (the gap region That is, the channel region between the source and the drain).
  • the insulating oxide in the present embodiment also refers to an insulating oxide which is formed by increasing the proportion of oxygen during sputtering to form an oxide semiconductor, and such an insulating oxide is also called an oxygen-rich oxide.
  • Step S16 forming a pattern of the passivation layer.
  • the protective layer is located between the passivation layer and the second oxide layer such that a second oxide layer (ie, a semiconducting oxide layer) and a protective layer (insulating oxide layer) of the channel region Direct contact without contact with the passivation layer.
  • the semiconductor oxide layer and the insulating oxide layer have a good lattice matching degree, thereby improving interface defects of the thin film transistor and avoiding defects due to interface defects.
  • the patterning process (including exposure, development, etching, etc.) is required, in order to avoid the second oxide layer of the etching liquid to the pixel electrode region during the etching process
  • the (semiconductor oxide layer) affects the pattern of the source/drain metal layer in the pixel electrode region when the pattern of the source/drain metal layer is formed. That is, the pattern of the source/drain metal layer includes a pattern of pixel electrode regions in addition to the pattern including the source and the drain. Therefore, when the pattern of the protective layer is formed, since the pixel electrode region is completely covered by the pattern of the source/drain metal layer, the etching process can be prevented from affecting the semiconductor oxide layer of the pixel electrode region.
  • the method further includes: etching the source/drain metal layer by using the protective layer as a mask to remove the pixel electrode region. The step of source and drain metal layer pattern.
  • plasma treatment may be performed using a reducing gas such as hydrogen.
  • a reducing gas such as hydrogen
  • the protective layer oxygen-rich oxide layer
  • the light on the pattern of the protective layer is retained. Engraved.
  • the step of performing plasma treatment on the second oxide layer of the pixel electrode region is specifically: performing plasma treatment on the second oxide layer of the pixel electrode region by using the photoresist as a mask.
  • the semiconductor oxide of the pixel electrode region is converted into a conductor to form a pixel electrode, wherein plasma treatment is performed using a reducing gas; and then the photoresist is stripped.
  • the pattern of the formed drain electrode completely falls into the gate pattern on the orthographic projection area on the substrate substrate.
  • the boundary between the conductive portion and the unconducted portion of the second oxide layer is located above the gate pattern, so that when the thin film transistor is turned on, it is ensured from the data line to the pixel electrode. Conductive.
  • the orthographic projection area of the formed drain pattern on the base substrate does not necessarily need to completely fall into the orthographic projection area of the gate pattern on the base substrate. Within the gate pattern, as long as the boundary between the conductor portion of the second oxide layer and the unconducted portion is ensured.
  • the pattern of the gate metal layer formed may further include a pattern of the common electrode lines; and after forming the pattern of the passivation layer, further comprising: forming a pattern of the common electrode layer, the common electrode layer passing through the blunt Via holes of the layer and the gate insulating layer are connected to the common electrode line.
  • the gate metal layer and the source/drain metal layer in each of the above embodiments may be made of a metal material having a small resistivity such as copper (Cu) to improve the conductive effect.
  • a metal material having a small resistivity such as copper (Cu) to improve the conductive effect.
  • An embodiment of the present disclosure further provides an array substrate fabricated by the method described in any of the above embodiments.
  • the array substrate includes:
  • a pattern of a gate metal layer the pattern of the gate metal layer including a gate
  • the active layer region pattern and a pixel electrode region pattern disposed in the same layer, the active layer region pattern including a first oxide layer and a second oxide layer disposed in an overlapping manner, the first oxide layer being located at the gate Between the insulating layer and the second oxide layer, the pattern of the pixel electrode region includes: a first oxide layer and a conductor layer disposed in an overlapping manner, and the first oxide layer is an insulating oxide, the first The dioxide layer is a semiconducting oxide;
  • the orthographic projection area of the drain pattern on the substrate substrate completely falling within the orthographic projection area of the gate pattern on the substrate substrate.
  • the active layer and the pixel electrode can be simultaneously formed by one patterning process, which can reduce the production cost of the array substrate.
  • the array substrate further includes: a pattern of a protective layer, wherein the protective layer is an insulating oxide layer, and the pattern of the protective layer completely covers a second oxidation corresponding to a gap region between the source and the drain a layer of matter; and a pattern of the passivation layer.
  • the protective layer is located between the passivation layer and the second oxide layer such that the second oxide layer (ie, the semiconducting oxide layer) is in direct contact with the protective layer (insulating oxide layer), and Without contacting the passivation layer, the semiconductor oxide layer and the insulating oxide layer have a good lattice matching degree, thereby improving interface defects at the channel of the thin film transistor and avoiding defects due to interface defects.
  • the present disclosure also provides a display panel comprising the array substrate in any of the above embodiments.
  • the present disclosure also provides a display device comprising the display panel of any of the above embodiments.
  • FIG. 1 is a schematic diagram of a method for fabricating an array substrate according to an embodiment of the present disclosure.
  • the manufacturing method includes the following steps:
  • Step S21 Referring to FIG. 1, a base substrate 101 is provided, and a pattern of a gate metal layer and a pattern of the gate insulating layer 103 are sequentially formed on the base substrate 101.
  • the pattern of the gate metal layer includes a pattern of a gate electrode 1021, a gate line (not shown), and a common electrode line 1022.
  • Step S22 Referring to FIG. 2, a pattern of a semiconductor layer is formed on the gate insulating layer 103.
  • the pattern of the semiconductor layer includes a pattern of an active layer region and a pixel electrode region, and the semiconductor layer includes a first oxide disposed in an overlapping manner.
  • the first oxide layer 1041 is an insulating oxide layer
  • the second oxide layer 1042 is a semiconducting oxide layer
  • the first oxide layer 1041 is located in the gate insulating layer 103 and the first Between the dioxide layers 1042.
  • Step S23 Referring to FIG. 3, a pattern of source and drain metal layers is formed.
  • the pattern of the source/drain metal layer includes a pattern of the source electrode 1051, a pattern of the drain electrode 1052, a data line (not shown), and a source/drain metal layer pattern 1053 of the pixel electrode region.
  • the source/drain metal layer pattern 1053 of the pixel electrode region completely covers the pixel electrode region.
  • the orthographic projection area of the formed drain electrode 1052 on the base substrate 101 completely falls within the orthographic projection area of the gate electrode 1021 pattern on the base substrate 101.
  • Step S24 Referring to FIG. 4, a pattern of the protective layer 106 is formed, and the photoresist 201 on the pattern of the protective layer 106 is retained.
  • the protective layer 106 is an insulating oxide layer, and the pattern of the protective layer 106 completely covers the source electrode 1051, the drain electrode 1052, and the second oxide layer corresponding to the gap region between the source electrode 1051 and the drain electrode 1052.
  • the gap region is the channel region between the source electrode 1051 and the drain electrode 1052).
  • Step S25 Referring to FIG. 5, the source/drain metal layer is etched by using the pattern 106 of the protective layer as a mask to remove the source/drain metal layer pattern 1053 of the pixel electrode region.
  • Step S26 Referring to FIG. 6, the second oxide layer (semiconductor oxide layer) of the pixel electrode region is plasma-treated by using the photoresist 201 as a mask, so that the pixel electrode region is The semiconducting oxide layer is converted into a conductor, and a pattern of the active layer 10421 and the pixel electrode 10422 is formed. In this step, plasma treatment is performed using hydrogen gas. Then, the photoresist 201 is peeled off.
  • Step S27 Please refer to FIG. 7, a pattern 107 of a passivation layer is formed, and a via hole 108 penetrating through the passivation layer and the gate insulating layer is formed on the passivation layer;
  • Step S28 Referring to FIG. 8, a pattern 109 of a common electrode layer is formed, which is connected to the common electrode line 1022 through a via 108 penetrating the passivation layer and the gate insulating layer.
  • an insulating oxide layer is disposed between the semiconducting oxide layer and the gate insulating layer, the insulating oxide layer and the semiconducting oxide layer have a good lattice matching degree, thereby improving interface defects.
  • An insulating oxide layer ie, a protective layer is disposed between the semiconductor oxide layer and the insulating oxide layer (ie, the protective layer) without being in contact with the passivation layer, the semiconducting oxide layer and the insulating layer.
  • the lattice structure of the oxide layer has a good matching degree, thereby improving interface defects in the channel region and avoiding defects due to interface defects.
  • the active layer and the pixel electrode are simultaneously formed by one patterning process, which can reduce the production cost of the array substrate.

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Abstract

一种阵列基板的制作方法、阵列基板和显示面板。该制作方法包括：在衬底基板（101）上形成栅金属层和栅极绝缘层（103）的图形；形成半导体层的图形，半导体层的图形包括有源层区域和像素电极区域的图形，半导体层包括重叠设置的绝缘性氧化物层和半导体性氧化物层，绝缘性氧化物层位于栅极绝缘层（103）和半导体性氧化物层之间；形成源漏金属层的图形；对像素电极区域的半导体性氧化物层进行等离子体处理，使得像素电极区域的半导体性氧化物层转化为导体。

Description

一种阵列基板的制作方法、阵列基板和显示面板
相关申请的交叉引用
本申请主张在2016年1月7日在中国提交的中国专利申请号No.201610008575.7的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，尤其涉及一种阵列基板的制作方法、阵列基板和显示面板。
背景技术
阵列基板中的薄膜晶体管(TFT)可以采用氧化物半导体制作有源层。氧化物半导体具有迁移率高、可制作大尺寸产品等特点。然而，氧化物半导体也存在一些缺点，例如特性不稳定，常常发生阈值电压(Vth)漂移等不良，从而限制了其大范围的使用。氧化物半导体特性不稳定的一个原因在于：其晶格结构与薄膜晶体管中的栅极绝缘层不匹配，导致两者的接触界面存在大量缺陷，缺陷捕获电荷后就会导致上述不良。
发明内容
有鉴于此，本公开提供一种阵列基板的制作方法、阵列基板和显示面板，用以解决现有的阵列基板中的氧化物半导体层与栅极绝缘层的接触界面不匹配的问题。
为解决上述技术问题，本公开提供一种阵列基板的制作方法，包括：在衬底基板上依次形成栅金属层和栅极绝缘层的图形；形成半导体层的图形，所述半导体层的图形包括有源层区域和像素电极区域的图形，所述半导体层包括重叠设置的第一氧化物层和第二氧化物层，所述第一氧化物层为绝缘性氧化物层，所述第二氧化物层为半导体性氧化物层，所述第一氧化物层位于所述栅极绝缘层和所述第二氧化物层之间；形成源漏金属层的图形；以及对所述像素电极区域的第二氧化物层进行等离子体处理，使得所述像素电极区域的第二氧化物层转化为导体。
可选地，所述形成半导体层的图形的步骤包括：采用溅射工艺形成第一氧化物薄膜，溅射工艺采用的溅射气体包括氧气和氩气，且氧气的比例为第 一比例，使得所述第一氧化物薄膜为绝缘性氧化物薄膜；采用溅射工艺形成第二氧化物薄膜，溅射工艺采用的溅射气体包括氧气和氩气，且氧气的比例为第二比例，使得所述第二氧化物薄膜为半导体性氧化物薄膜；采用构图工艺对所述第一氧化物薄膜和第二氧化物薄膜进行构图，形成半导体层的图形，所述半导体层包括由所述第一氧化物薄膜形成的第一氧化物层以及由所述第二氧化物薄膜形成的第二氧化物层。
可选地，所述第一比例的取值范围为60％～90％，所述第二比例的取值范围为30％～55％。
可选地，所述栅金属层的图形包括栅极的图形，所述源漏金属层的图形包括源极和漏极的图形，所述漏极的图形在所述衬底基板上的正投影区域完全落入所述栅极图形在所述衬底基板上的正投影区域内。
可选地，所述形成源漏金属层的图形的步骤之后还包括：形成保护层的图形，所述保护层为绝缘性氧化物层，所述保护层的图形完全覆盖源极和漏极之间的间隙区域对应的第二氧化物层；形成钝化层的图形，所述保护层位于所述钝化层和所述第二氧化物层之间。
可选地，所述源漏金属层的图形包括源极和漏极的图形以及像素电极区域的图形，所述保护层的图形还覆盖源极和漏极的图形，所述形成保护层的图形步骤之后，对所述像素电极区域的第二氧化物层进行等离子体处理的步骤之前还包括：以所述保护层为掩膜，对所述源漏金属层进行刻蚀，去除像素电极区域的源漏金属层图形。
可选地，形成保护层的图形之后，保留所述保护层的图形上的光刻胶；其中，对所述像素电极区域的第二氧化物层进行等离子体处理的步骤具体为：采用所述光刻胶作为掩膜，对所述像素电极区域的第二氧化物层进行等离子体处理，使得所述像素电极区域的半导体性氧化物转化为导体，其中，采用还原性气体执行等离子处理；以及剥离所述光刻胶。
可选地，所述栅金属层的图形包括公共电极线的图形；所述形成钝化层的图形之后还包括：形成公共电极层的图形，所述公共电极层通过贯穿所述钝化层和栅极绝缘层的过孔与所述公共电极线连接。
可选地，所述绝缘性氧化物层为富氧氧化物层。
本公开还提供一种阵列基板，采用上述方法制作而成。
可选地，所述阵列基板包括：衬底基板；栅金属层的图形，所述栅金属层的图形包括栅极；栅极绝缘层的图形；同层设置的有源层区域图形和像素电极区域图形，所述有源层区域图形包括重叠设置的第一氧化物层和第二氧化物层，所述第一氧化物层位于所述栅极绝缘层和所述第二氧化物层之间，所述像素电极区域的图形包括：重叠设置的第一氧化物层和导体层，所述第一氧化物层为绝缘性氧化物，所述第二氧化物层为半导体性氧化物；源漏极的图形，所述漏极图形在所述衬底基板上的正投影区域完全落入所述栅极图形在所述衬底基板上的正投影区域内。
可选地，所述阵列基板还包括：保护层的图形，所述保护层为绝缘性氧化物层，所述保护层的图形完全覆盖源极和漏极之间的间隙区域对应的第二氧化物层；以及钝化层的图形。
可选地，所述保护层的图形位于所述钝化层的图形和所述第二氧化物层之间。
本公开还提供一种显示面板，包括上述阵列基板。
本公开的上述技术方案的有益效果如下：由于半导体性氧化物层与栅极绝缘层之间设置绝缘性氧化物层，该绝缘性氧化物层与半导体性氧化物层晶格结构匹配度好，因而可改善薄膜晶体管的界面缺陷，避免因界面缺陷导致不良。同时，通过一次构图工艺同时形成有源层和像素电极，可减少掩膜版的数量，降低阵列基板的成产成本。
附图说明
图1-图8为本公开一些实施例的阵列基板的制作方式示意图。
附图标记说明：衬底基板101；栅极1021；公共电极线1022；栅极绝缘层103；第一氧化物层1041；第二氧化物层1042；有源层10421；像素电极10422；源极1051；漏极1052；像素电极区域的源漏金属层图形1053；保护层106；钝化层107；过孔108；公共电极109；光刻胶201。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然， 所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开专利申请说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”或者“一”等类似词语也不表示数量限制，而是表示存在至少一个。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也相应地改变。
为解决阵列基板中的氧化物半导体层与栅极绝缘层的接触界面不匹配的问题，本公开实施例提供了一种阵列基板的制作方法，包括以下步骤。
步骤S11：在衬底基板上依次形成栅金属层和栅极绝缘层的图形。
所述栅金属层的图形至少包括栅极的图形。可选地，还可以包括栅线的图形。在有些实施例中，还可以包括公共电极线的图形。所述栅极绝缘层可以采用二氧化硅(SiO2)等绝缘材料制成。
步骤S12：形成半导体层的图形，所述半导体层的图形包括有源层区域和像素电极区域的图形，所述半导体层包括重叠设置的第一氧化物层和第二氧化物层，所述第一氧化物层为绝缘性氧化物层，所述第二氧化物层为半导体性氧化物层，所述第一氧化物层位于所述栅极绝缘层和所述第二氧化物层之间。
本实施例中的绝缘性氧化物是指在溅射形成氧化物半导体过程中，增加氧气的比例而形成的呈绝缘性的氧化物，该种绝缘性氧化物也称为富氧氧化物。富氧氧化物由于其氧空位较少，因而显绝缘性，而其晶格结构与正常的半导体性氧化物匹配度较好，因而可改善薄膜晶体管的界面缺陷，避免因界面缺陷导致不良。
步骤S13：形成源漏金属层的图形。
所述源漏金属层的图形至少包括源极和漏极的图形。可选地，还可以包 括数据线的图形。
步骤S14：对所述像素电极区域的第二氧化物层进行等离子体处理，使得所述像素电极区域的第二氧化物层转化为导体。像素电极区域的第二氧化物层转化为导体之后，成为像素电极。
当然，为了实现像素区域的透光，上述绝缘性氧化物和半导体性氧化物均为透明氧化物。可选地，可采用IGZO等。
本公开实施例中，由于半导体性氧化物层与栅极绝缘层之间设置绝缘性氧化物层，该绝缘性氧化物层与半导体性氧化物层晶格结构匹配度好。因而可改善薄膜晶体管的界面缺陷，避免因界面缺陷导致不良。同时，通过一次构图工艺同时形成有源层和像素电极，可减少掩膜版的数量，降低阵列基板的成产成本。
下面对如何形成半导体层的图形的方法进行详细说明。
在本公开的一具体实施例中，所述形成半导体层的图形的步骤包括：
步骤S121：采用溅射工艺形成第一氧化物薄膜，溅射工艺采用的溅射气体包括氧气和氩气，且氧气的比例为第一比例，使得所述第一氧化物薄膜为绝缘性氧化物薄膜(即富氧氧化物层)；
步骤S122：采用溅射工艺形成第二氧化物薄膜，溅射工艺采用的溅射气体包括氧气和氩气，且氧气的比例为第二比例，使得所述第二氧化物薄膜为半导体性氧化物薄膜；
步骤S123：采用构图工艺对所述第一氧化物薄膜和第二氧化物薄膜进行构图，形成半导体层的图形，所述半导体层包括由所述第一氧化物薄膜形成的第一氧化物层以及由所述第二氧化物薄膜形成的第二氧化物层。
可选地，所述第一比例的取值范围为60％～90％，所述第二比例的取值范围为30％～55％。
在本公开的一具体实施例中，可采用磁控溅射工艺形成绝缘性氧化物薄膜和半导体性氧化物薄膜。其中，磁控溅射工艺形成绝缘性氧化物薄膜的工艺条件可以是：功率为2000～6000W，温度为20～50℃，氧气比例(即上述第一比例)为60％～90％，氩气比例为10～40％。磁控溅射工艺形成半导体性氧化物薄膜的工艺条件可以是：功率为2000～6000W，温度为20～50℃，氧气 比例(即上述第二比例)为30％～55％，氩气比例为45％～70％
本公开实施例中，在形成源漏金属层之后，还需要形成钝化层。由于钝化层和半导体性氧化物层的晶格结构也不匹配，如果钝化层与源极和漏极之间的间隙区域对应的半导体性氧化物层(所述间隙区域即沟道区域)直接接触的话，两者接触界面也存在缺陷，缺陷捕获电荷后就会导致不良。
为解决上述问题，本公开实施例中，在形成源漏金属层的图形的步骤之后还包括步骤S15和步骤S16。
步骤S15：形成保护层的图形，所述保护层为绝缘性氧化物层，所述保护层的图形完全覆盖源极和漏极之间的间隙区域对应的第二氧化物层(所述间隙区域即源极和漏极之间的沟道区域)。本实施例中的绝缘性氧化物同样是指在溅射形成氧化物半导体过程中，增加氧气的比例而形成的呈绝缘性的氧化物，该种绝缘性氧化物也称为富氧氧化物。
步骤S16：形成钝化层的图形。所述保护层位于所述钝化层和所述第二氧化物层之间，从而使得沟道区域的第二氧化物层(即半导体性氧化物层)与保护层(绝缘性氧化物层)直接接触，而不与钝化层接触。半导体性氧化物层和绝缘性氧化物层晶格结构匹配度好，因而可改善薄膜晶体管的界面缺陷，避免因界面缺陷导致不良。
在形成保护层的图形的过程中，由于需要进行构图工艺(包括曝光、显影和刻蚀等)，为了避免在进行刻蚀工艺的过程中，刻蚀液对像素电极区域的第二氧化物层(半导体性氧化物层)造成影响，可在制作源漏金属层的图形时，在像素电极区域也形成源漏金属层的图形。即所述源漏金属层的图形除了包括源极和漏极的图形之外，还包括像素电极区域的图形。从而，在形成保护层的图形时，由于像素电极区域被源漏金属层的图形完全覆盖，因而可避免刻蚀工艺对像素电极区域的半导体性氧化物层造成影响。
当然，在形成保护层的图形之后，还需要对像素电极区域的源漏金属层的图形进行刻蚀去除，以对像素电极区域的半导体性氧化物层进行等离子处理。在对像素电极区域的源漏金属层的图形进行刻蚀时，需要将源极和漏极区域的源漏金属层图形保护起来，避免被刻蚀掉。因而，可选地，上述形成的所述保护层的图形还覆盖源极和漏极的图形。此时，在形成保护层的图形 步骤之后，对所述像素电极区域的第二氧化物层进行等离子体处理的步骤之前还包括：以所述保护层为掩膜，对所述源漏金属层进行刻蚀，去除像素电极区域的源漏金属层图形的步骤。
在对像素电极区域的第二氧化物层进行等离子体处理时，可采用还原性气体，例如氢气，执行等离子处理。为避免还原性气体与保护层(富氧氧化物层)中的氧反应，本公开实施例中，可选地，在形成所述保护层的图形之后，保留所述保护层的图形上的光刻胶。其中，对所述像素电极区域的第二氧化物层进行等离子体处理的步骤具体为：采用所述光刻胶作为掩膜，对所述像素电极区域的第二氧化物层进行等离子体处理，使得所述像素电极区域的半导体性氧化物转化为导体，形成像素电极，其中，采用还原性气体执行等离子处理；然后剥离所述光刻胶。
上述各实施例中，为保证可以对像素电极(即上述像素区域的导体)充电，可选地，形成的漏极的图形在所述衬底基板上的正投影区域完全落入栅极图形在所述衬底基板上的正投影区域内。此时，第二氧化物层的导体化的部分和未导体化的部分的交界处，位于栅极图形之上，这样在薄膜晶体管打开的时候，才能保证从数据线到像素电极之间，处处导电。
当然，在本公开的其他一些实施例中，形成的漏极的图形在所述衬底基板上的正投影区域也不一定需要完全落入栅极图形在所述衬底基板上的正投影区域内，只要保证第二氧化物层的导体化的部分和未导体化的部分的交界处，位于栅极图形之上即可。
上述各实施例中，形成的栅金属层的图形还可以包括公共电极线的图形；在形成钝化层的图形之后还包括：形成公共电极层的图形，所述公共电极层通过贯穿所述钝化层和栅极绝缘层的过孔与所述公共电极线连接。
上述各实施例中的栅金属层和源漏金属层可采用铜(Cu)等电阻率较小的金属材料制成，以提高导电效果。
本公开实施例还提供一种阵列基板，采用上述任一实施例所述的方法制作而成。
在本公开的一可选实施例中，所述阵列基板包括：
衬底基板；
栅金属层的图形，所述栅金属层的图形包括栅极；
栅极绝缘层的图形；
同层设置的有源层区域图形和像素电极区域图形，所述有源层区域图形包括重叠设置的第一氧化物层和第二氧化物层，所述第一氧化物层位于所述栅极绝缘层和所述第二氧化物层之间，所述像素电极区域的图形包括：重叠设置的第一氧化物层和导体层，所述第一氧化物层为绝缘性氧化物，所述第二氧化物层为半导体性氧化物；
源漏极的图形，所述漏极图形在所述衬底基板上的正投影区域完全落入所述栅极图形在所述衬底基板上的正投影区域内。
由于半导体性氧化物层与栅极绝缘层之间设置绝缘性氧化物层，该绝缘性氧化物层与半导体性氧化物层晶格结构匹配度好，因而可改善薄膜晶体管的界面缺陷，避免因界面缺陷导致不良。同时，可通过一次构图工艺同时形成有源层和像素电极，可降低阵列基板的成产成本。
可选地，所述阵列基板还包括：保护层的图形，所述保护层为绝缘性氧化物层，所述保护层的图形完全覆盖源极和漏极之间的间隙区域对应的第二氧化物层；以及钝化层的图形。
所述保护层位于所述钝化层和所述第二氧化物层之间，从而使得第二氧化物层(即半导体性氧化物层)与保护层(绝缘性氧化物层)直接接触，而不与钝化层接触，半导体性氧化物层和绝缘性氧化物层晶格结构匹配度好，因而可改善薄膜晶体管的沟道处的界面缺陷，避免因界面缺陷导致不良。
本公开还提供一种显示面板，包括上述任一实施例中的阵列基板。
本公开还提供一种显示装置，包括上述任一实施例中的显示面板。
下面将结合附图和实施例，对本公开的具体实施方式作进一步详细描述。以下实施例用于说明本公开，但不用来限制本公开的范围。
请参考图1-图8，图1-图8为本公开一实施例的阵列基板的制作方式示意图，该制作方法包括以下步骤：
步骤S21：请参考图1，提供一衬底基板101，并在该衬底基板101上依次形成栅金属层的图形和栅极绝缘层103的图形。所述栅金属层的图形包括栅极1021、栅线(图未示出)和公共电极线1022的图形。
步骤S22：请参考图2，在栅极绝缘层103上形成半导体层的图形，所述半导体层的图形包括有源层区域和像素电极区域的图形，所述半导体层包括重叠设置的第一氧化物层1041和第二氧化物层1042。所述第一氧化物层1041为绝缘性氧化物层，所述第二氧化物层1042为半导体性氧化物层，所述第一氧化物层1041位于所述栅极绝缘层103和所述第二氧化物层1042之间。
步骤S23：请参考图3，形成源漏金属层的图形。所述源漏金属层的图形包括源极1051的图形、漏极1052的图形、数据线(图未示出)和像素电极区域的源漏金属层图形1053。像素电极区域的源漏金属层图形1053完全覆盖像素电极区域。形成的漏极1052的图形在所述衬底基板101上的正投影区域完全落入栅极1021图形在所述衬底基板101上的正投影区域内。
步骤S24：请参考图4，形成保护层106的图形，并保留所述保护层106的图形上的光刻胶201。所述保护层106为绝缘性氧化物层，所述保护层106的图形完全覆盖源极1051、漏极1052以及源极1051和漏极1052之间的间隙区域对应的第二氧化物层(所述间隙区域即源极1051和漏极1052之间的沟道区域)。
步骤S25：请参考图5，以所述保护层的图形106为掩膜，对所述源漏金属层进行刻蚀，去除像素电极区域的源漏金属层图形1053。
步骤S26：请参考图6，采用所述光刻胶201作为掩膜，对所述像素电极区域的第二氧化物层(半导体性氧化物层)进行等离子体处理，使得所述像素电极区域的半导体性氧化物层转化为导体，形成有源层10421和像素电极10422的图形。本步骤中，采用氢气执行等离子处理。然后，剥离所述光刻胶201。
步骤S27：请参考图7，形成钝化层的图形107，钝化层上形成有贯通钝化层和栅极绝缘层的过孔108；
步骤S28：请参考图8，形成公共电极层的图形109，所述公共电极层通过贯穿所述钝化层和栅极绝缘层的过孔108与所述公共电极线1022连接。
本公开实施例中，由于半导体性氧化物层与栅极绝缘层之间设置绝缘性氧化物层，该绝缘性氧化物层与半导体性氧化物层晶格结构匹配度好，因而可改善界面缺陷，避免因界面缺陷导致不良。在钝化层和半导体性氧化物层 之间设置绝缘性氧化物层(即保护层)，使得半导体性氧化物层与绝缘性氧化物层(即保护层)直接接触，而不与钝化层接触，半导体性氧化物层和绝缘性氧化物层晶格结构匹配度好，因而可改善沟道区域的界面缺陷，避免因界面缺陷导致不良。同时，通过一次构图工艺同时形成有源层和像素电极，可降低阵列基板的成产成本。
以上所述是本公开的可选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (13)

  1. 一种阵列基板的制作方法，包括：
    在衬底基板上依次形成栅金属层和栅极绝缘层的图形；
    形成半导体层的图形，所述半导体层的图形包括有源层区域和像素电极区域的图形，所述半导体层包括重叠设置的第一氧化物层和第二氧化物层，所述第一氧化物层为绝缘性氧化物层，所述第二氧化物层为半导体性氧化物层，所述第一氧化物层位于所述栅极绝缘层和所述第二氧化物层之间；
    形成源漏金属层的图形；以及
    对所述像素电极区域的第二氧化物层进行等离子体处理，使得所述像素电极区域的第二氧化物层转化为导体。
  2. 根据权利要求1所述的阵列基板的制作方法，其中，所述形成半导体层的图形的步骤包括：
    采用溅射工艺形成第一氧化物薄膜，溅射工艺采用的溅射气体包括氧气和氩气，且氧气的比例为第一比例，使得所述第一氧化物薄膜为绝缘性氧化物薄膜；
    采用溅射工艺形成第二氧化物薄膜，溅射工艺采用的溅射气体包括氧气和氩气，且氧气的比例为第二比例，使得所述第二氧化物薄膜为半导体性氧化物薄膜；
    采用构图工艺对所述第一氧化物薄膜和第二氧化物薄膜进行构图，形成半导体层的图形，所述半导体层包括由所述第一氧化物薄膜形成的第一氧化物层以及由所述第二氧化物薄膜形成的第二氧化物层。
  3. 根据权利要求2所述的阵列基板的制作方法，其中，所述第一比例的取值范围为60％～90％，所述第二比例的取值范围为30％～55％。
  4. 根据权利要求1所述的阵列基板的制作方法，其中，所述栅金属层的图形包括栅极的图形，所述源漏金属层的图形包括源极和漏极的图形，所述漏极的图形在所述衬底基板上的正投影区域完全落入所述栅极图形在所述衬底基板上的正投影区域内。
  5. 根据权利要求1所述的阵列基板的制作方法，其中，所述形成源漏金 属层的图形的步骤之后还包括：
    形成保护层的图形，所述保护层为绝缘性氧化物层，所述保护层的图形完全覆盖源极和漏极之间的间隙区域对应的第二氧化物层；
    形成钝化层的图形，所述保护层位于所述钝化层和所述第二氧化物层之间。
  6. 根据权利要求5所述的阵列基板的制作方法，其中，所述源漏金属层的图形包括源极和漏极的图形以及像素电极区域的图形，所述保护层的图形还覆盖源极和漏极的图形，所述形成保护层的图形步骤之后，对所述像素电极区域的第二氧化物层进行等离子体处理的步骤之前还包括：
    以所述保护层为掩膜，对所述源漏金属层进行刻蚀，去除像素电极区域的源漏金属层图形。
  7. 根据权利要求5所述的阵列基板的制作方法，其中，形成所述保护层的图形之后，保留所述保护层的图形上的光刻胶；
    其中，对所述像素电极区域的第二氧化物层进行等离子体处理的步骤具体为：
    采用所述光刻胶作为掩膜，对所述像素电极区域的第二氧化物层进行等离子体处理，使得所述像素电极区域的半导体性氧化物转化为导体，其中，采用还原性气体执行等离子处理；以及
    剥离所述光刻胶。
  8. 根据权利要求5所述的阵列基板的制作方法，其中，所述栅金属层的图形包括公共电极线的图形；所述形成钝化层的图形之后还包括：
    形成公共电极层的图形，所述公共电极层通过贯穿所述钝化层和栅极绝缘层的过孔与所述公共电极线连接。
  9. 根据权利要求1-8任一项所述的阵列基板的制作方法，其中，所述绝缘性氧化物层为富氧氧化物层。
  10. 一种阵列基板，包括：
    衬底基板；
    栅金属层的图形，所述栅金属层的图形包括栅极；
    栅极绝缘层的图形；
    同层设置的有源层区域图形和像素电极区域图形，其中，所述有源层区域图形包括重叠设置的第一氧化物层和第二氧化物层，所述第一氧化物层位于所述栅极绝缘层和所述第二氧化物层之间；所述像素电极区域的图形包括：重叠设置的第一氧化物层和导体层；所述第一氧化物层为绝缘性氧化物，所述第二氧化物层为半导体性氧化物；以及
    源漏极的图形，所述漏极图形在所述衬底基板上的正投影区域完全落入所述栅极图形在所述衬底基板上的正投影区域内。
  11. 根据权利要求10所述的阵列基板，还包括：
    保护层的图形，所述保护层为绝缘性氧化物层，所述保护层的图形完全覆盖源极和漏极之间的间隙区域对应的第二氧化物层；以及
    钝化层的图形。
  12. 根据权利要求11所述的阵列基板，其中，所述保护层的图形位于所述钝化层的图形和所述第二氧化物层之间。
  13. 一种显示面板，包括如权利要求10-12任一项所述的阵列基板。
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