WO2018086214A1 - 顶栅薄膜晶体管的制作方法及顶栅薄膜晶体管 - Google Patents

顶栅薄膜晶体管的制作方法及顶栅薄膜晶体管 Download PDF

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WO2018086214A1
WO2018086214A1 PCT/CN2016/112541 CN2016112541W WO2018086214A1 WO 2018086214 A1 WO2018086214 A1 WO 2018086214A1 CN 2016112541 W CN2016112541 W CN 2016112541W WO 2018086214 A1 WO2018086214 A1 WO 2018086214A1
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oxide semiconductor
semiconductor layer
source
thin film
film transistor
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French (fr)
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张合静
葛世民
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the present invention relates to the field of liquid crystal display, and more particularly to a method for fabricating a top gate thin film transistor and a top gate thin film transistor.
  • oxide semiconductor TFTs have attracted extensive attention due to their high mobility.
  • oxide semiconductor TFTs have mainly employed conventional ESL and BCE structures belonging to the bottom gate, as well as conventional top gate structures.
  • the TFT of the above conventional structure has a disadvantage of relatively large parasitic capacitance and difficulty in downsizing, it is increasingly unsuitable for use in a large-sized and high-resolution display. Therefore, the application of self-aligned top-gate TFTs in large-sized and high-resolution display devices is particularly important.
  • the structure of the self-aligned top gate TFT is as shown in FIG.
  • a barrier layer 11 is disposed on a surface of the glass substrate 10
  • an oxide semiconductor layer 12 is disposed on the surface of the barrier layer
  • a gate insulating layer 13 and a gate electrode 14 are disposed over the oxide semiconductor layer.
  • the surface of the oxide semiconductor layer 12 and the gate electrode 14 is covered with an interlayer dielectric 16 disposed on both sides of the gate electrode 14 and electrically connected to the oxide semiconductor layer 12.
  • the source and drain electrodes 15 and the gate 14 In the process of the self-aligned top gate TFT, in order to reduce the contact resistance between the source/drain 15 and the channel region of the oxide semiconductor layer 12, the source and drain electrodes 15 and the gate 14 The oxide semiconductor layer between them needs to be subjected to a conductor treatment, that is, a conductive layer is formed. As shown in FIG. 1, the oxide semiconductor layer of d length often needs to be subjected to a conductor treatment.
  • the surface of the oxide semiconductor layer is generally treated with a gas such as H2, NH3, CF4, SF6, He, Ar, or N2.
  • a gas such as H2, NH3, CF4, SF6, He, Ar, or N2.
  • impurity gases such as H, F plasma
  • H, F plasma impurity gases
  • the technical problem to be solved by the present invention is to provide a method for fabricating a top-gate thin film transistor and a top-gate thin film transistor, which can be conductorized when depositing an interlayer dielectric, and can ensure high mobility and on-state current.
  • the present invention provides a method for fabricating a top gate thin film transistor, comprising the steps of: providing a glass substrate; forming an oxide semiconductor layer on the glass substrate, the oxide semiconductor layer including a source region, a drain region and a channel region; forming a gate insulating layer at a corresponding position of the channel region on the oxide semiconductor layer; forming a gate electrode on the gate insulating layer; and the oxide semiconductor on the gate surface
  • the source and drain areas are electrically connected.
  • a barrier layer is formed on the surface of the glass substrate before the step of forming the oxide semiconductor layer, and the oxide semiconductor layer is formed on the barrier layer.
  • the interlayer medium is SiO2.
  • the decomposed ions bombard the source and drain regions of the oxide semiconductor layer in a high energy state to electrically conduct the source and drain regions of the oxide semiconductor layer.
  • the method of forming the source and the drain includes the following steps:
  • a metal is deposited in the via to form a source electrically coupled to the source region and a drain electrically coupled to the drain region.
  • the chemical vapor deposition power is greater than or equal to 1900 W, and for the sixth generation or higher thin film transistor display device production line, the chemical vapor deposition power is greater than or equal to 13,000 W.
  • the present invention also provides a top gate thin film transistor comprising a glass substrate, a barrier layer disposed on a surface of the glass substrate, and an oxide semiconductor layer disposed on a surface of the barrier layer, the oxide semiconductor layer including a source region and a drain a region and a channel region, a gate insulating layer and a gate are disposed on a surface of the channel region, and an interlayer dielectric is covered on the glass substrate, the oxide semiconductor layer, and the gate surface, and the source and the drain are disposed at The two sides of the gate are electrically connected to the source and drain regions of the oxide semiconductor layer through via holes of the interlayer dielectric, and the source and drain regions of the oxide semiconductor layer are electrically conductive.
  • the interlayer medium is SiO2.
  • the decomposed ions bombard the source region and the drain region surface conductorized surface of the oxide semiconductor layer in a high energy state to make the oxide semiconductor layer
  • the source and drain regions are surface-conducted.
  • the chemical vapor deposition power is greater than or equal to 1900 W, and for the sixth generation or higher thin film transistor display device production line, the chemical vapor deposition power is greater than or equal to 13,000 W.
  • the third-phase gas is introduced into the conductor treatment, which is diffused in a subsequent high-temperature process, thereby limiting the subsequent process temperature, and the method for fabricating the top-gate thin film transistor of the present invention does not use a third-party gas. Therefore, the impurity gas is not introduced to affect the characteristics of the thin film transistor.
  • the manufacturing method of the top gate thin film transistor of the present invention saves the process of conducting the conductor, thereby improving efficiency and cost.
  • FIG. 1 is a schematic structural view of a conventional self-aligned top gate thin film transistor
  • FIG. 2 is a schematic view showing the steps of a method for fabricating a top gate thin film transistor of the present invention
  • 3A-3F are process flow diagrams of a method of fabricating a top gate thin film transistor of the present invention.
  • FIG. 4 is a schematic structural view of a top gate thin film transistor fabricated by the method of the present invention.
  • FIG. 5 is an Id-Vg data of a top gate thin film transistor fabricated in accordance with a method of fabricating a top gate thin film transistor of the present invention.
  • the present invention provides a method for fabricating a top gate thin film transistor, the method comprising the steps of: step S20, providing a glass substrate; and step S21, forming an oxide semiconductor layer on the glass substrate, the oxidizing The semiconductor layer includes a source region, a drain region, and a channel region; step S22, forming a gate insulating layer at a corresponding position of the channel region on the oxide semiconductor layer; and step S23, forming a gate on the gate insulating layer Step S24, depositing an interlayer dielectric by chemical vapor deposition on the surface of the gate, the surface of the oxide semiconductor layer, and the surface of the glass substrate, the source and drain regions are electrically conductive; step S25, forming a source And a drain, the source and the drain are electrically connected to a source region and a drain region of the oxide semiconductor layer, respectively.
  • 3A-3F are process flow diagrams of a method of fabricating a top gate thin film transistor of the present invention.
  • a glass substrate 30 is provided.
  • a barrier layer 31 may also be formed on the surface of the glass substrate 30.
  • an oxide semiconductor layer 32 is formed on the glass substrate 30.
  • an oxide semiconductor layer 32 is formed on the barrier layer 31.
  • the method of forming the oxide semiconductor layer 32 is the same as the method of forming an oxide semiconductor layer in the prior art self-aligned top gate TFT structure, which can be obtained by those skilled in the art from the prior art.
  • the oxide semiconductor layer 32 includes a source region 321, a drain region 322, and a channel region 323.
  • a gate insulating layer 33 is formed at a corresponding position of the channel region 323 of the oxide semiconductor layer 32. This step may be performed by a deposition method to form the gate insulating layer 33.
  • a gate electrode 34 is formed on the gate insulating layer 33.
  • an interlayer dielectric is deposited by chemical vapor deposition on the surface of the gate 34, the surface of the source region 321 and the drain region 322 of the oxide semiconductor layer 32, and the surface of the glass substrate 30 or the barrier layer 31. 35.
  • the material of the interlayer dielectric 35 is SiO 2 .
  • the chemical vapor deposition power is greater than or equal to 1900 W, and for the sixth generation or higher thin film transistor display device production line, the chemical vapor deposition power is greater than or equal to 13000 W, deposition
  • the decomposed ions bombard the surface of the source region 321 and the drain region 322 of the oxide semiconductor layer 32 in a high-energy state, and since the oxide semiconductor layer 32 itself is thin and sensitive, the source region 321 and the drain region of the oxide semiconductor layer 32 are formed.
  • the surface of the 322 is electrically formed to form the conductor layer 39, thereby achieving low contact resistance between the source drain and the oxide semiconductor layer.
  • the gate and gate insulating layers in turn protect the channel region 323 of the oxide semiconductor layer 32 from damage.
  • a source 36 and a drain 37 are formed.
  • the source 36 and the drain 37 are electrically connected to the source region 321 and the drain region 322 of the oxide semiconductor layer, respectively.
  • the method of forming the source 36 and the drain 37 includes the following steps:
  • Via holes 38 are formed in the interlayer dielectric 35, and the via holes 38 expose the source region 321 and the drain region 322 of the oxide semiconductor layer 32, respectively.
  • Metal is deposited in the via 38 to form a source 36 electrically coupled to the source region 321 and a drain 37 electrically coupled to the drain region 322.
  • the fabrication method of the top gate thin film transistor of the present invention eliminates the semiconductor layer conductor process in the self-aligned top gate TFT process, in the subsequent interlayer dielectric (ILD)
  • ILD interlayer dielectric
  • SiOx CVD
  • the deposition parameters are changed to achieve the conduction of the source and drain regions when depositing the interlayer dielectric, which ensures high mobility and on-state current.
  • the present invention also provides a top gate thin film transistor.
  • the top gate thin film transistor includes a glass substrate 40, a barrier layer 41 provided on a surface of the glass substrate 40, and an oxide semiconductor layer 42 provided on a surface of the barrier layer 41.
  • the oxide semiconductor layer 42 includes a source region 421, a drain region 422, and a channel region 423.
  • a gate insulating layer 43 and a gate electrode 44 are provided on the surface of the channel region 423.
  • the surface of the glass substrate 40, the oxide semiconductor layer 42, and the gate electrode 44 is covered with an interlayer dielectric 45.
  • a source 46 and a drain 47 are disposed on both sides of the gate 44, and are electrically connected to the source region 421 and the drain region 422 of the oxide semiconductor layer 42 through the via 48 of the interlayer dielectric 45, respectively.
  • the source region 421 and the drain region 422 of the semiconductor layer 42 are surface-conducted to form a conductor layer 49.

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  • Thin Film Transistor (AREA)

Abstract

提供一种顶栅薄膜晶体管的制作方法及顶栅薄膜晶体管，该方法包括步骤：提供玻璃基板（40）；在玻璃基板（40）上形成氧化物半导体层（42），氧化物半导体层（42）包括源区（421）、漏区（422）和沟道区（423）；在氧化物半导体层（42）上沟道区（423）对应的位置形成栅极绝缘层（43）；在栅极绝缘层（43）上形成栅极（44）；在栅极（44）表面、氧化物半导体层（42）表面及玻璃基板（40）表面采用化学气相沉积法沉积层间介质（45），使源区（421）及漏区（422）表面导体化；形成源漏极（46,47），该源漏极（46,47）分别与氧化物半导体层（42）的源区（421）和漏区（422）电连接。如此能够在沉积层间介质时导体化氧化物半导体层，保证较高的迁移率及开态电流。

Description

顶栅薄膜晶体管的制作方法及顶栅薄膜晶体管 技术领域
本发明涉及液晶显示领域，尤其涉及一种顶栅薄膜晶体管的制作方法及顶栅薄膜晶体管。
 背景技术
在高分辨高框架的现实装置中，每一个子像素的TFT需要有足够快的速度去转换子像素，因此急需低寄生电容及高迁移率的TFT。氧化物半导体TFT由于其较高的迁移率而引起了广泛重视。但到目前为止，氧化物半导体TFT主要采用了常规的属于底栅的ESL和BCE结构，以及常规的顶栅型结构。然而，由于上述常规结构的TFT具有相对较大的寄生电容及不易小尺寸化的缺点，越来越不能适用于大尺寸以及高分辨的显示器中。因此，自对准型的顶栅TFT在大尺寸及高分辨的显示装置中的应用显得尤为重要。
自对准型的顶栅TFT的结构如图1所示。在玻璃基板10表面设置有阻挡层11，在所述阻挡层表面设置有氧化物半导体层12，在所述氧化物半导体层上方设置有栅极绝缘层13及栅极14，在所述阻挡层11、氧化物半导体层12及栅极14表面覆盖有层间介质16，源漏极15设置在所述栅极14两侧并与所述氧化物半导体层12电连接。在自对准型的顶栅TFT的制程中，为了减小源漏极15（Source/Drain）与氧化物半导体层12的沟道区（channel）的接触阻抗，源漏极15与栅极14之间的氧化物半导体层需要进行导体化处理，即形成可导电层，如图1所示，d长度的氧化物半导体层往往需要进行导体化处理。
在导体化的技术中，一般运用H2，NH3，CF4，SF6，He，Ar，N2等气体对氧化物半导体层的表面进行处理。然而采用第三方气体进行处理往往会引入杂质气体，比如H，F等离子，这些离子在后续的制程会扩散至氧化物半导体层，影响TFT的特性；另一方面，若采用惰性气体，又往往达不到预想的导体化效果，源漏极15（Source/Drain）与氧化物半导体层12的沟道区（channel）的接触阻抗仍然较高，会导致TFT开态电流较低等问题。
因此，亟需一种降低源漏极15（Source/Drain）与氧化物半导体层12的沟道区（channel）的接触阻抗的制程。
 技术问题
本发明所要解决的技术问题是，提供一种顶栅薄膜晶体管的制作方法及顶栅薄膜晶体管，其能够在沉积层间介质时便可导体化，可以保证较高的迁移率及开态电流。
 技术解决方案
为了解决上述问题，本发明提供了一种顶栅薄膜晶体管的制作方法，包括如下步骤：提供一玻璃基板；在所述玻璃基板上形成氧化物半导体层，所述氧化物半导体层包括源区、漏区及沟道区；在所述氧化物半导体层上沟道区对应位置形成栅极绝缘层；在所述栅极绝缘层上形成栅极；在所述栅极表面、所述氧化物半导体层表面及玻璃基板表面采用化学气相沉积的方法沉积层间介质，所述源区及漏区表面导体化；形成源极及漏极，所述源极及漏极分别与所述氧化物半导体层的源区及漏区电连接。
进一步，在形成氧化物半导体层步骤之前，在所述玻璃基板表面形成阻挡层，所述氧化物半导体层形成在所述阻挡层上。
进一步，所述层间介质为SiO2。
进一步，在化学气相沉积时，分解的离子以高能态轰击所述氧化物半导体层的所述源区及漏区，以使所述氧化物半导体层的所述源区及漏区表面导体化。
进一步，形成源极及漏极的方法包括如下步骤：
在所述层间介质成上形成过孔，所述过孔分别暴露出所述氧化物半导体层的源区及漏区；
在所述过孔内沉积金属，形成与所述源区电连接的源极及与所述漏区电连接的漏极。
对于第六世代及以下的薄膜晶体管显示装置产线，所述化学气相沉积的功率大于等于1900W，对于第六世代以上的薄膜晶体管显示装置产线，所述化学气相沉积的功率大于等于13000W。
本发明还提供一种顶栅薄膜晶体管，包括玻璃基板、在所述玻璃基板表面设置的阻挡层及在所述阻挡层表面设置的氧化物半导体层，所述氧化物半导体层包括源区、漏区及沟道区，在所述沟道区表面设置有栅极绝缘层及栅极，在所述玻璃基板、氧化物半导体层及栅极表面覆盖有层间介质，源极和漏极设置在所述栅极两侧，并分别通过层间介质的过孔与所述氧化物半导体层的源区和漏区电连接，所述氧化物半导体层的所述源区及漏区表面导体化。
进一步，所述层间介质为SiO2。
进一步，在化学气相沉积形成层间介质层时，分解的离子以高能态轰击所述氧化物半导体层的所述源区及漏区表面导体化表面，以使所述氧化物半导体层的所述源区及漏区表面导体化。
对于第六世代及以下的薄膜晶体管显示装置产线，所述化学气相沉积的功率大于等于1900W，对于第六世代以上的薄膜晶体管显示装置产线，所述化学气相沉积的功率大于等于13000W。
 有益效果
本发明的优点在于，
（1）在现有的自对准型的顶栅薄膜晶体管制程中，虽然需要的光罩数量相对较少，但需要导体化处理，制程及技术难度较为复杂，本发明顶栅薄膜晶体管的制作方法省去导体化过程，大大减小了制程的复杂程度，在沉积层间介质时便可导体化，可以保证较高的迁移率及开态电流。
（2）在现有技术中，导体化处理引入第三方气体，在后续的高温制程中会扩散，因此限制了后续的制程温度，而本发明顶栅薄膜晶体管的制作方法不采用第三方气体，因此不会引入杂质气体而影响薄膜晶体管的特性。
（3）本发明顶栅薄膜晶体管的制作方法省去导体化这一制程，既提高效率又节约成本。
 附图说明
图1是现有的自对准型顶栅薄膜晶体管的结构示意图；
图2是本发明顶栅薄膜晶体管的制作方法的步骤示意图；
图3A~图3F是本发明顶栅薄膜晶体管的制作方法的工艺流程图；
图4是采用本发明方法制作的顶栅薄膜晶体管的结构示意图；
图5是根据本发明顶栅薄膜晶体管的制作方法制作的顶栅薄膜晶体管的Id-Vg数据。
 本发明的最佳实施方式
下面结合附图对本发明提供的顶栅薄膜晶体管的制作方法及顶栅薄膜晶体管的具体实施方式做详细说明。
参见图2，本发明提供一种顶栅薄膜晶体管的制作方法，所述方法包括如下步骤：步骤S20、提供一玻璃基板；步骤S21、在所述玻璃基板上形成氧化物半导体层，所述氧化物半导体层包括源区、漏区及沟道区；步骤S22、在所述氧化物半导体层上沟道区对应位置形成栅极绝缘层；步骤S23、在所述栅极绝缘层上形成栅极；步骤S24、在所述栅极表面、所述氧化物半导体层表面及玻璃基板表面采用化学气相沉积的方法沉积层间介质，所述源区及漏区表面导体化；步骤S25、形成源极及漏极，所述源极及漏极分别与所述氧化物半导体层的源区及漏区电连接。
图3A~图3F是本发明顶栅薄膜晶体管的制作方法的工艺流程图。
参见图3A及步骤S20，提供一玻璃基板30。在本步骤中，作为可选步骤，还可以在所述玻璃基板30表面形成阻挡层31。
参见图3B及步骤S21，在所述玻璃基板30上形成氧化物半导体层32，在本具体实施方式中，在所述阻挡层31上形成氧化物半导体层32。形成所述氧化物半导体层32的方法与现有技术中的自对准型顶栅TFT结构中形成氧化物半导体层的方法相同，本领域技术人员可从现有技术中获取。所述氧化物半导体层32包括源区321、漏区322及沟道区323。
参见图3C及步骤S22，在所述氧化物半导体层32的沟道区323对应位置上形成栅极绝缘层33，此步骤可采用沉积的方法形成栅极绝缘层33。
参见图3D及步骤S23，在所述栅极绝缘层33上形成栅极34。
参见图3E及步骤S24，在所述栅极34表面、所述氧化物半导体层32的源区321及漏区322表面及玻璃基板30或阻挡层31表面采用化学气相沉积的方法沉积层间介质35。在本具体实施方式中，所述层间介质35的材料为SiO2。
对于第六世代及以下的薄膜晶体管显示装置产线，所述化学气相沉积的功率大于等于1900W，对于第六世代以上的薄膜晶体管显示装置产线，所述化学气相沉积的功率大于等于13000W，沉积时分解的离子以高能态轰击氧化物半导体层32的源区321及漏区322的表面，由于氧化物半导体层32本身较薄且敏感，因此，氧化物半导体层32的源区321及漏区322的表面导体化，形成导体层39，进而实现源漏极与氧化物半导体层的低接触阻抗。同时，栅极及栅极绝缘层又能保护氧化物半导体层32的沟道区323不受损伤。
参见图3F及步骤S25，形成源极36及漏极37，所述源极36及漏极37分别与所述氧化物半导体层的源区321及漏区322电连接。形成源极36及漏极37的方法包括如下步骤：
在所述层间介质35上形成过孔38，所述过孔38分别暴露出所述氧化物半导体层32的源区321及漏区322。在所述过孔38内沉积金属，形成与所述源区321电连接的源极36及与所述漏区322电连接的漏极37。
本发明顶栅薄膜晶体管的制作方法在自对准型的顶栅TFT制程中，省去半导体层导体化制程，在后续的层间介质（ILD CVD（SiOx））沉积中改变沉积参数，达到在沉积层间介质时便可使源区及漏区导体化，可以保证较高的迁移率及开态电流。
参见图4，本发明还提供一种顶栅薄膜晶体管。所述顶栅薄膜晶体管包括玻璃基板40、在所述玻璃基板40表面设置的阻挡层41及在所述阻挡层41表面设置的氧化物半导体层42。所述氧化物半导体层42包括源区421、漏区422及沟道区423。在所述沟道区423表面设置有栅极绝缘层43及栅极44。在所述玻璃基板40、氧化物半导体层42及栅极44表面覆盖有层间介质45。源极46和漏极47设置在所述栅极44两侧，并分别通过层间介质45的过孔48与所述氧化物半导体层42的源区421和漏区422电连接，所述氧化物半导体层42的所述源区421及漏区422表面导体化，形成导体层49。
图5是根据本发明顶栅薄膜晶体管的制作方法制作的顶栅薄膜晶体管的Id-Vg数据，W/L=0.5，得到的迁移率可达到16.42；然而采用其它常规方式沉积的层间介质，制备常规的顶栅薄膜晶体管，所得到的薄膜晶体管无明显半导体特性。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (11)

  1. 一种顶栅薄膜晶体管的制作方法，其中，包括如下步骤：
    提供一玻璃基板；
    在所述玻璃基板表面形成阻挡层；
    在所述阻挡层上形成氧化物半导体层，所述氧化物半导体层包括源区、漏区及沟道区；
    在所述氧化物半导体层上沟道区对应位置形成栅极绝缘层；
    在所述栅极绝缘层上形成栅极；
    在所述栅极表面、所述氧化物半导体层表面及玻璃基板表面采用化学气相沉积的方法沉积层间介质，所述源区及漏区表面导体化，所述层间介质为SiO2，在化学气相沉积时，分解的离子以高能态轰击所述氧化物半导体层的所述源区及漏区，以使所述氧化物半导体层的所述源区及漏区表面导体化，对于第六世代及以下的薄膜晶体管显示装置产线，所述化学气相沉积的功率大于等于1900W，对于第六世代以上的薄膜晶体管显示装置产线，所述化学气相沉积的功率大于等于13000W；
    形成源极及漏极，所述源极及漏极分别与所述氧化物半导体层的源区及漏区电连接
  2. 一种顶栅薄膜晶体管的制作方法，其中，包括如下步骤：
    提供一玻璃基板；
    在所述玻璃基板上形成氧化物半导体层，所述氧化物半导体层包括源区、漏区及沟道区；
    在所述氧化物半导体层上沟道区对应位置形成栅极绝缘层；
    在所述栅极绝缘层上形成栅极；
    在所述栅极表面、所述氧化物半导体层表面及玻璃基板表面采用化学气相沉积的方法沉积层间介质，所述源区及漏区表面导体化；
    形成源极及漏极，所述源极及漏极分别与所述氧化物半导体层的源区及漏区电连接。
  3. 根据权利要求2所述的顶栅薄膜晶体管的制作方法，其中，在形成氧化物半导体层步骤之前，在所述玻璃基板表面形成阻挡层，所述氧化物半导体层形成在所述阻挡层上。
  4. 根据权利要求2所述的顶栅薄膜晶体管的制作方法，其中，所述层间介质为SiO2。
  5. 根据权利要求2所述的顶栅薄膜晶体管的制作方法，其中，在化学气相沉积时，分解的离子以高能态轰击所述氧化物半导体层的所述源区及漏区，以使所述氧化物半导体层的所述源区及漏区表面导体化。
  6. 根据权利要求2所述的顶栅薄膜晶体管的制作方法，其中，形成源极及漏极的方法包括如下步骤：
    在所述层间介质成上形成过孔，所述过孔分别暴露出所述氧化物半导体层的源区及漏区；
    在所述过孔内沉积金属，形成与所述源区电连接的源极及与所述漏区电连接的漏极。
  7. 根据权利要求2所述的顶栅薄膜晶体管的制作方法，其中，对于第六世代及以下的薄膜晶体管显示装置产线，所述化学气相沉积的功率大于等于1900W，对于第六世代以上的薄膜晶体管显示装置产线，所述化学气相沉积的功率大于等于13000W。
  8. 一种顶栅薄膜晶体管，其中，包括玻璃基板、在所述玻璃基板表面设置的阻挡层及在所述阻挡层表面设置的氧化物半导体层，所述氧化物半导体层包括源区、漏区及沟道区，在所述沟道区表面设置有栅极绝缘层及栅极，在所述玻璃基板、氧化物半导体层及栅极表面覆盖有层间介质，源极和漏极设置在所述栅极两侧，并分别通过层间介质的过孔与所述氧化物半导体层的源区和漏区电连接，所述氧化物半导体层的所述源区及漏区表面导体化。
  9. 根据权利要求8所述的顶栅薄膜晶体管，其中，所述层间介质为SiO2。
  10. 根据权利要求8所述的顶栅薄膜晶体管，其中，在化学气相沉积形成层间介质层时，分解的离子以高能态轰击所述氧化物半导体层的所述源区及漏区表面导体化表面，以使所述氧化物半导体层的所述源区及漏区表面导体化。
  11. 根据权利要求10所述的顶栅薄膜晶体管，其中，对于第六世代及以下的薄膜晶体管显示装置产线，所述化学气相沉积的功率大于等于1900W，对于第六世代以上的薄膜晶体管显示装置产线，所述化学气相沉积的功率大于等于13000W。
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