WO2018040477A1 - 一种goa驱动电路 - Google Patents

一种goa驱动电路 Download PDF

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Publication number
WO2018040477A1
WO2018040477A1 PCT/CN2017/070852 CN2017070852W WO2018040477A1 WO 2018040477 A1 WO2018040477 A1 WO 2018040477A1 CN 2017070852 W CN2017070852 W CN 2017070852W WO 2018040477 A1 WO2018040477 A1 WO 2018040477A1
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Prior art keywords
signal
voltage
goa driving
unit
driving circuit
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English (en)
French (fr)
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陈帅
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US15/328,963 priority Critical patent/US10347190B2/en
Publication of WO2018040477A1 publication Critical patent/WO2018040477A1/zh
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13454—Drivers integrated on the active matrix substrate
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the invention belongs to the field of liquid crystal display, and in particular relates to a GOA driving circuit.
  • the GOA (Gate Driver on Array) driving circuit integrates the gate driving circuit of the TFT LCD on the glass substrate to form a scanning drive for the liquid crystal panel.
  • the GOA drive technology can greatly reduce the manufacturing cost, and the Bonging process of the Gate side COF is omitted, which is also extremely beneficial to the capacity increase.
  • the GOA drive module includes a pull-up control unit 110 that performs pre-charging primarily for the Q(N) point.
  • the pull-up unit 120 mainly increases the potential of the G(N) point and outputs a line scan signal.
  • the pull-down unit 130 mainly pulls down the Q(N) and G(N) point potentials to Vss.
  • the pull-down maintaining unit 140 mainly controls the Q(N) and G(N) point potentials to remain unchanged at Vss.
  • the multi-level GOA driving module forms a GOA driving circuit by cascading, and the adjacent two-stage GOA driving modules are driven by clock signals with equal frequency and opposite phases.
  • CK/XCK is a clock trigger signal
  • Vss is a DC source
  • G(N) is a line scan output signal
  • Q(N) is a pre- Charge the potential signal.
  • the function of the pull-down maintaining unit is to reduce the signal caused by the capacitive coupling by the voltage regulation of the DC source. abnormal.
  • the voltage of the critical circuit node in the GOA driving circuit is not affected, so that it is reliably maintained at the design value point, which is an urgent problem in the design of the GOA driving circuit, and the present invention proposes a solution to the problem.
  • One of the technical problems to be solved by the present invention is to provide a GOA driving circuit that reliably maintains the voltage of a critical circuit node at a design value point without affecting it.
  • the embodiment of the present application first provides a GOA driving circuit, including a multi-level GOA driving module, each level of the GOA driving module is used to drive a row of pixel units, and the adjacent two-stage GOA driving module adopts a frequency.
  • the equal, opposite phase clock signal is driven;
  • the GOA driving module includes a pull-up control unit, a pull-up unit, a pull-down unit, a pull-down maintaining unit, and a downlink unit, and the downlink unit includes: a lower pass transistor, and a drain thereof
  • the clock signal input end and the control signal input end respectively connected to the gate unit and the control signal input end generate a downlink signal acting on the next-stage driving module under the action of the clock signal and the control signal, and the source thereof is used as the downlink signal.
  • An output terminal a voltage stabilizing capacitor, one of the plates is connected to the source of the down transistor, and the other of the plates is connected to the common electrode, the common electrode transmits a DC voltage signal, and the Zener capacitor is coupled The voltage maintains the stability of the down signal.
  • the coupling voltage generated by the voltage stabilizing capacitors of the adjacent two stages of the downlink unit is opposite in phase.
  • the voltage of the constant voltage capacitor ranges from 1 to 100 pf.
  • the embodiment of the present application further provides another GOA driving circuit, including a multi-level GOA driving module.
  • Each level of the GOA driving module is used to drive a row of pixel units, and adjacent two-stage GOA driving modules adopt equal frequency and opposite phases.
  • the clock signal is driven;
  • the GOA driving module includes a pull-up control unit, a pull-up unit, a pull-down unit, a pull-down maintaining unit, and a downlink unit
  • the downlink unit includes: a lower pass transistor, and a drain and a gate thereof respectively Connected to the clock signal input end of the pull-up unit and the control signal input end, under the action of the clock signal and the control signal, generate a downlink signal acting on the next-stage driving module, and the source thereof is used as a downlink signal output terminal; a capacitor, one of the plates is connected to the source of the lower pass transistor; the other plate of the adjacent two-stage voltage stabilizing capacitor is respectively spaced apart from the first regulated signal line and the second regulated signal line
  • the alternating current signal has the same frequency and opposite phase as its corresponding downlink signal.
  • the first regulated signal line and the second regulated signal line transmit an alternating voltage signal having the same frequency and opposite phases.
  • the coupling voltage generated by the voltage stabilizing capacitors of the adjacent two stages of the downlink unit is opposite in phase.
  • the highest voltage value and the lowest voltage value of the AC voltage signal transmitted by the first regulated signal line and the second regulated signal line are respectively adjusted according to interference conditions of the actual circuit.
  • the first voltage stabilizing signal line and the second voltage stabilizing signal line are disposed on the first metal layer or the second metal layer.
  • the voltage of the constant voltage capacitor ranges from 1 to 100 pf.
  • the reliability of the signal of the key node in the driving circuit can be improved, and the stability of the liquid crystal panel display can be improved.
  • FIG. 1 is a schematic structural diagram of a first-level driving module of a GOA driving circuit of the prior art
  • FIG. 2 is a timing diagram of a prior art GOA driving circuit in operation
  • FIG. 3 is a schematic structural diagram of a GOA driving circuit according to an embodiment of the invention.
  • FIG. 5 is a schematic diagram of waveforms of adjacent two-stage downlink signals according to an embodiment of the invention.
  • FIG. 6 is a schematic structural diagram of a GOA driving circuit according to still another embodiment of the present invention.
  • FIG. 7 is a waveform diagram of an AC voltage stabilizing signal according to still another embodiment of the present invention.
  • FIG. 8 is a schematic diagram of waveforms of an adjacent two-stage downlink signal and its corresponding AC signal according to still another embodiment of the present invention.
  • the GOA driving circuit includes a multi-level GOA driving module, and each level of the GOA driving module is used to drive a row of pixel units, adjacent to two
  • the stage GOA driver module is driven by clock signals of equal frequency and opposite phase.
  • the GOA driving module specifically includes a pull-up control unit, a pull-up unit, a pull-down unit, a pull-down maintaining unit, and a downlink transmitting unit 310.
  • the downlink unit 310 includes a down transistor T22 and a voltage stabilizing capacitor Cs.
  • the drain and the gate of the down transistor T22 are respectively connected to the clock signal input end of the pull-up unit (the drain of the transistor T21) and the control signal input end (the gate of the transistor T21), in the clock signal and control. Under the action of the signal, a downlink signal acting on the next-level driving module is generated.
  • the source of the down transistor T22 is used as the down signal output terminal, and the pull-up control unit of the Nth stage driving module uses the underpass signal ST(N-1) generated by the N-1th stage, and the Nth stage driving module The down signal is used as an input signal to the pull-up control unit of the N+1th stage drive module.
  • One plate of the voltage stabilizing capacitor Cs is connected to the source of the down transistor T22, and the other plate is connected to the common electrode (Acom electrode).
  • the common electrode of the liquid crystal display panel transmits a DC voltage signal, and the voltage stabilizing capacitor Cs maintains the stability of the downlink signal by generating a coupling voltage.
  • the row scan signal of the previous stage is generally used to activate the driver module of the latter stage.
  • the gate and the drain of the transistor T11 of the pull-up unit shown in FIG. 1 are coupled together to receive the row-scan signal G(N-1) of the previous stage. It is easy to know that at this time, the transistor T11 is equivalent to one diode, that is, the gate-source voltage Vgs of T11 is 0, so there is a large leakage current inside the transistor T11, which in turn affects the point voltage of Q(N).
  • the down signal ST(N) is generated and output by adding the down transistor T22, because the low potential of the down signal ST(N-1) is the low level of the clock signal CK (or XCK). , generally -8V.
  • the low potential of the row scan signal G(N-1) is Vss, which is generally -6V, that is, the gate-source voltage Vgs ⁇ 0 of T11. Therefore, the internal leakage current of the transistor can be reduced by using the downlink signal ST(N). (N) The impact.
  • the downlink signal ST(N) has a certain degree of variation due to the existence of capacitive coupling.
  • the single-stage signal variation is shown in Figure 4. Due to the periodic inversion of the CK (or XCK) signal, This causes periodic fluctuations in the ST(N), which is extremely unfavorable for the control of the lower-level signals, and has the risk of causing abnormalities in the Q(N+1) signal and abnormalities in the Vss signal.
  • a voltage stabilizing capacitor is disposed in each of the downlink units 310 of each stage.
  • Cs one plate of Cs is connected with the common electrode Acom, and the common electrode Acom transmits a DC voltage signal, and the coupling voltage is generated by the coupling action of the voltage stabilizing capacitor Cs, and the coupling voltage is superimposed with the fluctuation of the downlink signal.
  • the fluctuation of the partial downlink signal is offset, and the downlink signal is stabilized to reduce the signal variation.
  • each stage downlink signal ST(N) is connected to the common electrode Acom through the voltage stabilizing capacitor Cs, the coupling voltage generated by the voltage stabilizing capacitor Cs of the adjacent two-stage down-converting unit 310 is opposite in phase. (as shown in Figure 5), therefore, does not significantly affect the potential of the common electrode Acom.
  • the capacitance values of the voltage stabilizing capacitors can be equal, and the non-equal value can be designed according to the actual RC condition of the panel.
  • the capacitance value of the voltage stabilizing capacitor Cs is generally 1 to 100 pf.
  • the downlink unit 310 of the embodiment of the invention can stabilize the voltage of the key node in the GOA driving circuit and improve the reliability of the circuit operation. At the same time, no additional wiring is required, saving the design space of the panel.
  • FIG. 6 is a schematic structural diagram of a GOA driving circuit according to still another embodiment of the present invention, and only a part different from the previous embodiment will be described below.
  • one plate of the voltage stabilizing capacitor Cs is connected to different regulated signal lines.
  • the N-th voltage stabilizing capacitor Cs is connected to the first regulated signal line VS1
  • the N+1-th order stabilizing capacitor Cs is connected to the second regulated signal line VS2, the N+2th stabilizing capacitor.
  • Cs is connected to the first regulated signal line VS1
  • the N+3 level stabilizing capacitor Cs is connected to the second regulated signal line VS2, and so on
  • the stabilizing capacitor Cs is respectively connected to the first regulated signal line and the second regulated voltage.
  • Signal lines are connected at intervals.
  • the first regulated signal line and the second regulated signal line may be disposed on the first metal layer or the second metal layer.
  • an AC voltage signal is transmitted in the first regulated signal line VS1 and the second regulated signal line VS2, and an AC voltage signal is transmitted in the first regulated signal line and the second regulated signal line as shown in FIG. 7.
  • the frequencies are equal and the phases are opposite.
  • the coupling voltage generated by the voltage stabilizing capacitor Cs of the adjacent two-stage downlink unit 310 is opposite in phase.
  • FIG. 8 is a waveform diagram of the adjacent two-stage downlink signal and its corresponding AC signal.
  • the VS1 waveform is opposite to the capacitive coupling of ST(N), and the VS2 waveform is opposite to the capacitive coupling of ST(N+1).
  • the two opposite capacitive coupling effects can cancel each other out and improve the periodic fluctuation of the downlink signal.
  • the highest voltage value and the lowest voltage value of the AC voltage signals (VS1 and VS2) transmitted by the first regulated signal line and the second regulated signal line may be adjusted according to interference conditions of the actual circuit. Furthermore, the value of the voltage stabilizing capacitor Cs can also be adjusted. When the period of the downlink signal also mutates, the period of the AC voltage signals (VS1 and VS2) can also be adjusted. Drive circuit The debugging is more flexible, which increases the practicality of the circuit design.
  • the capacitance values of the voltage stabilizing capacitors can be equal, and the non-equal value can be designed according to the actual RC condition of the panel.
  • the capacitance value of the voltage stabilizing capacitor Cs is generally 1 to 100 pf.
  • the GOA driving circuit of the embodiment of the present invention can improve the reliability of the signal of the key node in the driving circuit and improve the stability of the display of the liquid crystal panel by generating and outputting the downlink signal and the periodic fluctuation of the possible occurrence of the downlink signal. Sex.

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Abstract

一种GOA驱动电路，包括下传单元（310），所述下传单元（310）包括下传晶体管（T22）与稳压电容（C s），其一个极板与下传晶体管（T22）的源极相连接，其另一个极板与公共电极（Acom）相连接，所述公共电极（Acom）传输直流电压信号，所述稳压电容（C s）产生耦合电压维持下传信号的稳定。该驱动电路可以改善驱动电路中关键节点的信号的可靠性，提高液晶面板显示的稳定性。

Description

一种GOA驱动电路
相关申请的交叉引用
本申请要求享有2016年08月31日提交的名称为“一种GOA驱动电路”的中国专利申请CN201610796866.7的优先权，该申请的全部内容通过引用并入本文中。
技术领域
本发明属于液晶显示领域，尤其涉及一种GOA驱动电路。
背景技术
GOA(Gate Driver on Array)驱动电路是将TFT LCD的栅极驱动电路集成在玻璃基板上，形成对液晶面板的扫描驱动。GOA驱动技术相比传统的利用COF的驱动技术可以大幅度节约制造成本，而且省去了Gate侧COF的Bonging制程，对产能提升也是极为有利的。
图1为现有技术的GOA驱动电路一级驱动模块的结构示意图，每一级GOA驱动模块用于驱动一行的像素单元。如图所示，该GOA驱动模块包括上拉控制单元110，主要为Q(N)点实现预充电。上拉单元120，主要为提高G(N)点电位，输出行扫描信号。下拉单元130，主要为拉低Q(N)、G(N)点电位至Vss。下拉维持单元140，主要为控制Q(N)、G(N)点电位维持在Vss不变。多级GOA驱动模块通过级联构成GOA驱动电路，相邻两级GOA驱动模块采用频率相等、相位相反的时钟信号进行驱动。
图2为现有技术的GOA驱动电路工作时的时序图，如图所示，CK/XCK为时钟触发信号、Vss为直流源、G(N)为行扫描输出信号、Q(N)为预充点电位信号。在GOA电路中，由于各种寄生电容的存在，导致电路中信号会出现不同程度的周期性波动，例如下拉维持单元的作用即是通过直流源的稳压作用减小因电容耦合作用导致的信号异常。
使GOA驱动电路中的关键电路节点的电压不受影响，使其可靠地维持在设计值点上，是GOA驱动电路的设计中一个亟需解决的问题，本发明针对该问题提出解决方案。
发明内容
本发明所要解决的技术问题之一是需要提供一种使关键电路节点的电压不影响，可靠地维持在设计值点上的GOA驱动电路。
为了解决上述技术问题，本申请的实施例首先提供了一种GOA驱动电路，包括多级GOA驱动模块，每一级GOA驱动模块用于驱动一行的像素单元，相邻两级GOA驱动模块采用频率相等、相位相反的时钟信号进行驱动；所述GOA驱动模块包括上拉控制单元、上拉单元、下拉单元、下拉维持单元以及下传单元，所述下传单元包括：下传晶体管，其漏极与栅极分别并接于上拉单元的时钟信号输入端与控制信号输入端，在时钟信号与控制信号的作用下生成作用于下一级驱动模块的下传信号，其源极作为下传信号输出端；稳压电容，其一个极板与所述下传晶体管的源极相连接，其另一个极板与公共电极相连接，所述公共电极传输直流电压信号，所述稳压电容产生耦合电压维持下传信号的稳定。
优选地，相邻两级下传单元的稳压电容所产生的耦合电压相位相反。
优选地，所述稳压电容电容值的范围为1～100pf。
本申请的实施例又提供了另一种GOA驱动电路，包括多级GOA驱动模块，每一级GOA驱动模块用于驱动一行的像素单元，相邻两级GOA驱动模块采用频率相等、相位相反的时钟信号进行驱动；所述GOA驱动模块包括上拉控制单元、上拉单元、下拉单元、下拉维持单元以及下传单元，所述下传单元包括：下传晶体管，其漏极与栅极分别并接于上拉单元的时钟信号输入端与控制信号输入端，在时钟信号与控制信号的作用下生成作用于下一级驱动模块的下传信号，其源极作为下传信号输出端；稳压电容，其一个极板与所述下传晶体管的源极相连接；相邻两级稳压电容的另一个极板分别与第一稳压信号线和第二稳压信号线间隔连接，所述第一稳压信号线和第二稳压信号线均传输交流电压信号，所述稳压电容产生耦合电压维持下传信号的稳定。
优选地，所述交流信号与其对应的下传信号频率相等、相位相反。
优选地，所述第一稳压信号线与第二稳压信号线传输的交流电压信号频率相等、相位相反。
优选地，相邻两级下传单元的稳压电容所产生的耦合电压相位相反。
优选地，根据实际电路的干扰情况分别调整所述第一稳压信号线与第二稳压信号线所传输的交流电压信号的最高电压值与最低电压值。
优选地，所述第一稳压信号线与第二稳压信号线设置在第一金属层或第二金属层上。
优选地，所述稳压电容电容值的范围为1～100pf。
与现有技术相比，上述方案中的一个或多个实施例可以具有如下优点或有益效果：
通过生成并输出下传信号以及针对下传信号可能发生的周期性波动进行稳压，可以改善驱动电路中关键节点的信号的可靠性，提高液晶面板显示的稳定性。
本发明的其他优点、目标，和特征在某种程度上将在随后的说明书中进行阐述，并且在某种程度上，基于对下文的考察研究对本领域技术人员而言将是显而易见的，或者可以从本发明的实践中得到教导。本发明的目标和其他优点可以通过下面的说明书，权利要求书，以及附图中所特别指出的结构来实现和获得。
附图说明
附图用来提供对本申请的技术方案或现有技术的进一步理解，并且构成说明书的一部分。其中，表达本申请实施例的附图与本申请的实施例一起用于解释本申请的技术方案，但并不构成对本申请技术方案的限制。
图1为现有技术的GOA驱动电路一级驱动模块的结构示意图；
图2为现有技术的GOA驱动电路工作时的时序图；
图3为根据本发明一实施例的GOA驱动电路的结构示意图；
图4为利用示波器对下传信号进行观测的波形示意图；
图5为根据本发明一实施例的相邻两级下传信号的波形示意图；
图6为根据本发明又一实施例的GOA驱动电路的结构示意图；
图7为根据本发明又一实施例的交流稳压信号的波形示意图；
图8为根据本发明又一实施例的相邻两级下传信号与其对应的交流信号的波形示意图。
具体实施方式
以下将结合附图及实施例来详细说明本发明的实施方式，借此对本发明如何应用技术手段来解决技术问题，并达成相应技术效果的实现过程能充分理解并据以实施。本申请实施例以及实施例中的各个特征，在不相冲突前提下可以相互结 合，所形成的技术方案均在本发明的保护范围之内。
图3为根据本发明一实施例的GOA驱动电路的结构示意图，如图所示，该GOA驱动电路包括多级GOA驱动模块，每一级GOA驱动模块用于驱动一行的像素单元，相邻两级GOA驱动模块采用频率相等、相位相反的时钟信号进行驱动。GOA驱动模块具体包括上拉控制单元、上拉单元、下拉单元、下拉维持单元以及下传单元310。其中，下传单元310包括下传晶体管T22以及稳压电容Cs。
具体的，下传晶体管T22的漏极与栅极分别并接于上拉单元的时钟信号输入端(晶体管T21的漏极)与控制信号输入端(晶体管T21的栅极)，在时钟信号与控制信号的作用下生成作用于下一级驱动模块的下传信号。下传晶体管T22的源极作为下传信号输出端，第N级驱动模块的上拉控制单元使用的是第N-1级产生的下穿信号ST(N-1)，第N级驱动模块的下传信号作为第N+1级驱动模块的上拉控制单元的一个输入信号。
稳压电容Cs的一个极板与下传晶体管T22的源极相连接，另一个极板与公共电极(Acom电极)相连接。液晶显示面板的公共电极传输的是直流电压信号，稳压电容Cs通过产生耦合电压来维持下传信号的稳定。
现有技术中一般采用前一级的行扫描信号来启动后一级的驱动模块。具体为，如图1所示的上拉单元的晶体管T11的栅极与漏极耦接在一起，接收前一级的行扫描信号G(N-1)。容易知道，此时晶体管T11相当于一个二极管，即T11的栅源电压Vgs＝0，所以在晶体管T11的内部会存在较大的漏电流，进而影响Q(N)的点电压。
而在本发明实施例中，通过增加下传晶体管T22生成并输出下传信号ST(N)，由于下传信号ST(N-1)的低电位为时钟信号CK(或XCK)的低电平，一般为-8V。行扫描信号G(N-1)的低电位则为Vss，一般为-6V，即T11的栅源电压Vgs<0，因此通过采用下传信号ST(N)可以减少晶体管内部漏电流对本级Q(N)的影响。
另一方面，下传信号ST(N)由于电容耦合作用的存在使得该信号存在一定程度的变异，单级信号变异情况如图4所示，由于CK(或XCK)信号周期性的反转，导致ST(N)出现周期性的波动(ripple)，这对下级信号的控制是极为不利的，有导致Q(N+1)信号异常及Vss信号异常的风险。
因此，在本发明的实施例中，在每一级的下传单元310中均设置了稳压电容 Cs，Cs的一个极板与公共电极Acom连接在一起，公共电极Acom中传输的是直流电压信号，经由稳压电容Cs的耦合作用产生耦合电压，耦合电压与下传信号的波动相叠加，能够抵消部分下传信号产生的波动，即将下传信号拉稳，降低信号变异。
进一步地，由于将每一级下传信号ST(N)都通过稳压电容Cs与公共电极Acom连接在一起，因此相邻两级下传单元310的稳压电容Cs所产生的耦合电压相位相反(如图5所示)，因此并不会显著影响公共电极Acom的电位。
各稳压电容的电容值可以相等，也可以根据面板的实际RC情况进行非等值设计，稳压电容Cs的电容值一般为1～100pf。
本发明实施例的下传单元310能够稳定GOA驱动电路中关键节点的电压，提升电路工作的可靠性。同时不用增加额外走线，节省面板的设计空间。
图6为根据本发明又一实施例的GOA驱动电路的结构示意图，下面仅针对其与前一实施例中不同的部分进行说明。
在该实施例中，稳压电容Cs的一个极板分别连接不同的稳压信号线。如图所示，第N级的稳压电容Cs连接第一稳压信号线VS1，第N+1级的稳压电容Cs连接第二稳压信号线VS2，第N+2级的稳压电容Cs连接第一稳压信号线VS1，第N+3级的稳压电容Cs连接第二稳压信号线VS2，以此类推，稳压电容Cs分别与第一稳压信号线和第二稳压信号线间隔连接。
第一稳压信号线与第二稳压信号线可以设置在第一金属层或第二金属层上。
进一步地，在第一稳压信号线VS1和第二稳压信号线VS2中传输交流电压信号，如图7所示，在第一稳压信号线和第二稳压信号线中传输交流电压信号频率相等、相位相反。相邻两级下传单元310的稳压电容Cs所产生的耦合电压相位相反。
同时，上述交流信号分别与其对应的下传信号频率相等、相位相反。如图8所示为相邻两级下传信号与其对应的交流信号的波形示意图，其中VS1波形与ST(N)的电容耦合作用相反，VS2波形与ST(N+1)的电容耦合作用相反，两种相反的电容耦合作用可以相互抵消，改善下传信号的周期性波动。
进一步地，第一稳压信号线与第二稳压信号线所传输的交流电压信号(VS1和VS2)的最高电压值与最低电压值可以根据实际电路的干扰情况进行调整。更进一步地，稳压电容Cs的数值也可以进行调整。当下传信号的周期也发生变异时，还可以对交流电压信号(VS1和VS2)的周期进行调整。使得对驱动电路 的调试更加灵活，更增加了电路设计的实用性。
同样的，各稳压电容的电容值可以相等，也可以根据面板的实际RC情况进行非等值设计，稳压电容Cs的电容值一般为1～100pf。
本发明实施例的GOA驱动电路，通过生成并输出下传信号以及针对下传信号可能发生的周期性波动进行稳压，可以改善驱动电路中关键节点的信号的可靠性，提高液晶面板显示的稳定性。
虽然本发明所揭露的实施方式如上，但所述的内容只是为了便于理解本发明而采用的实施方式，并非用以限定本发明。任何本发明所属技术领域内的技术人员，在不脱离本发明所揭露的精神和范围的前提下，可以在实施的形式上及细节上作任何的修改与变化，但本发明的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (11)

  1. 一种GOA驱动电路，包括多级GOA驱动模块，每一级GOA驱动模块用于驱动一行的像素单元，相邻两级GOA驱动模块采用频率相等、相位相反的时钟信号进行驱动；
    所述GOA驱动模块包括上拉控制单元、上拉单元、下拉单元、下拉维持单元以及下传单元，所述下传单元包括：
    下传晶体管，其漏极与栅极分别并接于上拉单元的时钟信号输入端与控制信号输入端，在时钟信号与控制信号的作用下生成作用于下一级驱动模块的下传信号，其源极作为下传信号输出端；
    稳压电容，其一个极板与所述下传晶体管的源极相连接，其另一个极板与公共电极相连接，所述公共电极传输直流电压信号，所述稳压电容产生耦合电压维持下传信号的稳定。
  2. 根据权利要求1所述的GOA驱动电路，其中，相邻两级下传单元的稳压电容所产生的耦合电压相位相反。
  3. 根据权利要求2所述的GOA驱动电路，其中，所述稳压电容电容值的范围为1～100pf。
  4. 一种GOA驱动电路，包括多级GOA驱动模块，每一级GOA驱动模块用于驱动一行的像素单元，相邻两级GOA驱动模块采用频率相等、相位相反的时钟信号进行驱动；
    所述GOA驱动模块包括上拉控制单元、上拉单元、下拉单元、下拉维持单元以及下传单元，所述下传单元包括：
    下传晶体管，其漏极与栅极分别并接于上拉单元的时钟信号输入端与控制信号输入端，在时钟信号与控制信号的作用下生成作用于下一级驱动模块的下传信号，其源极作为下传信号输出端；
    稳压电容，其一个极板与所述下传晶体管的源极相连接；
    相邻两级稳压电容的另一个极板分别与第一稳压信号线和第二稳压信号线间隔连接，所述第一稳压信号线和第二稳压信号线均传输交流电压信号，所述稳压电容产生耦合电压维持下传信号的稳定。
  5. 根据权利要求4所述的GOA驱动电路，其中，所述交流信号与其对应的下传信号频率相等、相位相反。
  6. 根据权利要求5所述的GOA驱动电路，其中，所述第一稳压信号线与 第二稳压信号线传输的交流电压信号频率相等、相位相反。
  7. 根据权利要求6所述的GOA驱动电路，其中，相邻两级下传单元的稳压电容所产生的耦合电压相位相反。
  8. 根据权利要求4所述的GOA驱动电路，其中，根据实际电路的干扰情况分别调整所述第一稳压信号线与第二稳压信号线所传输的交流电压信号的最高电压值与最低电压值。
  9. 根据权利要求8所述的GOA驱动电路，其中，所述第一稳压信号线与第二稳压信号线设置在第一金属层或第二金属层上。
  10. 根据权利要求9所述的GOA驱动电路，其中，所述稳压电容电容值的范围为1～100pf。
  11. 根据权利要求4所述的GOA驱动电路，其中，根据实际电路的干扰情况分别调整所述第一稳压信号线与第二稳压信号线所传输的交流电压信号的周期。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110767163A (zh) * 2019-11-08 2020-02-07 京东方科技集团股份有限公司 一种像素电路及显示面板
CN112071255A (zh) * 2020-09-22 2020-12-11 南京中电熊猫液晶显示科技有限公司 一种显示面板

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106251817B (zh) 2016-08-31 2019-01-18 深圳市华星光电技术有限公司 一种goa驱动电路
CN106527002B (zh) * 2016-12-29 2019-09-17 深圳市华星光电技术有限公司 一种能够提高goa信赖性的阵列基板
CN107068087B (zh) 2017-03-31 2019-11-26 深圳市华星光电技术有限公司 一种goa驱动电路
CN107578756B (zh) * 2017-10-16 2020-04-14 深圳市华星光电技术有限公司 一种goa电路
CN109064981B (zh) * 2018-07-20 2019-09-17 深圳市华星光电技术有限公司 Goa电路及包括其的显示面板和显示装置
CN109637483A (zh) * 2019-01-22 2019-04-16 深圳市华星光电半导体显示技术有限公司 Goa电路以及液晶显示装置
US11056035B1 (en) * 2020-05-06 2021-07-06 Tcl China Star Optoelectronics Technology Co., Ltd. Gate on array circuit with capacitors connected in parallel
CN111816691B (zh) 2020-08-28 2020-12-15 京东方科技集团股份有限公司 显示基板及其制作方法、显示装置
CN119495248A (zh) * 2024-12-18 2025-02-21 广州华星光电半导体显示技术有限公司 栅极驱动电路及显示面板

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070192659A1 (en) * 2006-02-15 2007-08-16 Samsung Electronics Co., Ltd Shift register, scan driving circuit and display device having the same
CN103559912A (zh) * 2013-08-16 2014-02-05 友达光电股份有限公司 移位寄存器电路
CN103680453A (zh) * 2013-12-20 2014-03-26 深圳市华星光电技术有限公司 阵列基板行驱动电路
CN103680386A (zh) * 2013-12-18 2014-03-26 深圳市华星光电技术有限公司 用于平板显示的goa电路及显示装置
CN104008741A (zh) * 2014-05-20 2014-08-27 深圳市华星光电技术有限公司 一种扫描驱动电路及液晶显示装置
CN106251817A (zh) * 2016-08-31 2016-12-21 深圳市华星光电技术有限公司 一种goa驱动电路

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007317288A (ja) * 2006-05-25 2007-12-06 Mitsubishi Electric Corp シフトレジスタ回路およびそれを備える画像表示装置
WO2009006275A1 (en) * 2007-06-29 2009-01-08 Sandisk Corporation Non-volatile storage with source bias all bit line sensing
CN202677790U (zh) * 2012-04-13 2013-01-16 京东方科技集团股份有限公司 移位寄存器单元、移位寄存器和显示装置
CN104392700B (zh) * 2014-11-07 2016-09-14 深圳市华星光电技术有限公司 用于氧化物半导体薄膜晶体管的扫描驱动电路
CN104505033A (zh) * 2014-12-18 2015-04-08 深圳市华星光电技术有限公司 栅极驱动电路、阵列基板及显示装置
CN104992946B (zh) * 2015-05-29 2018-03-16 京东方科技集团股份有限公司 一种显示基板及其制备方法、显示面板及显示装置
CN105139815A (zh) * 2015-09-18 2015-12-09 友达光电股份有限公司 一种下传控制电路及其goa电路
CN105304057B (zh) * 2015-12-09 2018-11-30 京东方科技集团股份有限公司 一种移位寄存器及其驱动方法、栅极驱动电路
CN105469767B (zh) * 2016-01-05 2017-11-07 京东方科技集团股份有限公司 一种公共电压补偿电路、补偿方法、显示面板及显示装置
CN105590612B (zh) * 2016-03-22 2018-01-16 京东方科技集团股份有限公司 一种移位寄存器及驱动方法、栅极驱动电路和显示装置
CN105761758A (zh) * 2016-05-18 2016-07-13 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路和显示装置
CN106205538A (zh) * 2016-08-31 2016-12-07 深圳市华星光电技术有限公司 一种goa驱动单元及驱动电路
TWI625718B (zh) * 2016-10-04 2018-06-01 創王光電股份有限公司 高穩定性的脈衝寬度可調式移位暫存器
CN106571123B (zh) * 2016-10-18 2018-05-29 深圳市华星光电技术有限公司 Goa驱动电路及液晶显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070192659A1 (en) * 2006-02-15 2007-08-16 Samsung Electronics Co., Ltd Shift register, scan driving circuit and display device having the same
CN103559912A (zh) * 2013-08-16 2014-02-05 友达光电股份有限公司 移位寄存器电路
CN103680386A (zh) * 2013-12-18 2014-03-26 深圳市华星光电技术有限公司 用于平板显示的goa电路及显示装置
CN103680453A (zh) * 2013-12-20 2014-03-26 深圳市华星光电技术有限公司 阵列基板行驱动电路
CN104008741A (zh) * 2014-05-20 2014-08-27 深圳市华星光电技术有限公司 一种扫描驱动电路及液晶显示装置
CN106251817A (zh) * 2016-08-31 2016-12-21 深圳市华星光电技术有限公司 一种goa驱动电路

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110767163A (zh) * 2019-11-08 2020-02-07 京东方科技集团股份有限公司 一种像素电路及显示面板
CN112071255A (zh) * 2020-09-22 2020-12-11 南京中电熊猫液晶显示科技有限公司 一种显示面板

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CN106251817A (zh) 2016-12-21
US10347190B2 (en) 2019-07-09

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