WO2018040409A1 - 一种金属氧化物薄膜晶体管及其制备方法 - Google Patents
一种金属氧化物薄膜晶体管及其制备方法 Download PDFInfo
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- 239000010409 thin film Substances 0.000 title claims abstract description 32
- 229910044991 metal oxide Inorganic materials 0.000 title claims abstract description 22
- 150000004706 metal oxides Chemical class 0.000 title claims abstract description 22
- 238000002360 preparation method Methods 0.000 title abstract description 4
- 239000010410 layer Substances 0.000 claims description 226
- 239000011521 glass Substances 0.000 claims description 33
- 239000000758 substrate Substances 0.000 claims description 33
- 238000000034 method Methods 0.000 claims description 28
- 229910010413 TiO 2 Inorganic materials 0.000 claims description 27
- 239000010408 film Substances 0.000 claims description 23
- 239000011241 protective layer Substances 0.000 claims description 23
- 239000000463 material Substances 0.000 claims description 20
- 230000008569 process Effects 0.000 claims description 17
- 238000000151 deposition Methods 0.000 claims description 16
- 238000005240 physical vapour deposition Methods 0.000 claims description 15
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 10
- 238000005229 chemical vapour deposition Methods 0.000 claims description 9
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 6
- 229910052733 gallium Inorganic materials 0.000 claims description 6
- 229910052738 indium Inorganic materials 0.000 claims description 6
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical group [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 6
- 238000000206 photolithography Methods 0.000 claims description 6
- 239000011787 zinc oxide Substances 0.000 claims description 6
- 239000011651 chromium Substances 0.000 claims description 5
- 239000010949 copper Substances 0.000 claims description 5
- 239000012044 organic layer Substances 0.000 claims description 5
- 239000010936 titanium Substances 0.000 claims description 5
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 4
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical group [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- 229910052804 chromium Inorganic materials 0.000 claims description 4
- 239000011248 coating agent Substances 0.000 claims description 4
- 238000000576 coating method Methods 0.000 claims description 4
- 229910052802 copper Inorganic materials 0.000 claims description 4
- 238000011161 development Methods 0.000 claims description 4
- 229910052750 molybdenum Inorganic materials 0.000 claims description 4
- 239000011733 molybdenum Substances 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- 229920002120 photoresistant polymer Polymers 0.000 claims description 3
- 238000003980 solgel method Methods 0.000 claims description 2
- 239000003344 environmental pollutant Substances 0.000 abstract description 5
- 231100000719 pollutant Toxicity 0.000 abstract description 5
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 abstract 2
- 238000004519 manufacturing process Methods 0.000 description 8
- 229910021417 amorphous silicon Inorganic materials 0.000 description 7
- 230000008901 benefit Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 229910021645 metal ion Inorganic materials 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000010406 cathode material Substances 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Definitions
- the present invention relates to the field of thin film transistors and their preparation technologies, and in particular to a metal oxide thin film transistor and a method for fabricating the same.
- Amorphous silicon thin film transistor (a-Si TFT) backplanes have been the mainstay of the display industry for many years.
- amorphous silicon has inherent limitations and it is difficult to provide the switching characteristics required to drive high-resolution, high-performance displays. Amorphous silicon transistors are too slow to handle: in this material, electrons and holes migrate too slowly, and we call this property mobility.
- metal oxide thin film transistor technology seems to be the most popular, and it is not difficult to use this technology in existing thin film transistor manufacturing plants, because metal oxide is usually deposited by a well-known physical vapor deposition (PVD) process.
- PVD physical vapor deposition
- the material to be considered is not limited in size during deposition, and has a sufficiently high mobility to produce a back sheet suitable for high resolution, high refresh rate flat display.
- Metal oxide thin film transistors have made great progress.
- the best material for the active layer is indium gallium zinc oxide (IGZO), which has a mobility 10 to 20 times higher than that of amorphous silicon.
- IGZO indium gallium zinc oxide
- IGZO is typically deposited using a PVD technique called magnetron sputtering, which uses both a magnetic field and an electric field to remove the cathode material and deposit it onto the backing plate.
- magnetron sputtering uses both a magnetic field and an electric field to remove the cathode material and deposit it onto the backing plate.
- IGZO has the advantages of high mobility, suitable for large-area production, and similar to a-Si process, and has gradually become a research hotspot in the field of display technology.
- the IGZO layer of IGZO-TFT is very sensitive to the process and environment. Therefore, it is often necessary to adopt an ESL structure to protect the IGZO layer and add a Mask, which is not conducive to the reduction of process cost.
- the forbidden band width of IGZO about 3.4eV
- UV light higher than 3.1eV
- IGZO has a good absorption effect on UV light, and the IGZO layer is irradiated with UV light. Electron and other easily absorbed energy transition to the conduction band, which shifts the threshold voltage of the TFT, making the display display unstable.
- the invention aims to solve the problem that the IGZO-TFT device in the prior art has high cost and the stability of the IGZO active layer is susceptible to UV light and external pollutants.
- the present invention provides a metal oxide thin film transistor and a method of fabricating the same.
- a metal oxide thin film transistor comprising:
- a gate electrode layer located on an upper surface adjacent to a side of the glass substrate
- a gate insulating layer on an upper surface of the gate electrode layer and an upper surface of the glass substrate not covered by the gate electrode layer;
- An active layer located on an upper surface of the gate insulating layer on a side of the glass substrate;
- a source drain layer located on an upper surface of the active layer and an upper surface of the gate insulating layer not covered by the active layer on a side close to the glass substrate;
- a protective layer located on an upper surface of the source and drain layers and an upper surface of the gate insulating layer not covered by the source and drain layers;
- a pixel definition region organic layer is located on the anode layer on an upper surface adjacent to both sides of the glass substrate and an upper surface of the planarization layer not covered by the anode layer.
- the material of the gate electrode layer is titanium (Ti), chromium (Cr), aluminum (Al), molybdenum (Mo) or Copper (Cu).
- the gate insulating layer is a silicon nitride layer, a silicon oxide layer or a silicon oxynitride layer.
- the material used for the active layer is indium gallium zinc oxide.
- the material used for the protective layer is silicon oxide.
- the TiO 2 film layer has a thickness of 5 nm to 60 nm.
- a method of fabricating a metal oxide thin film transistor comprising the steps of:
- the material used for the gate electrode layer is titanium, chromium, aluminum, molybdenum or copper.
- the gate insulating layer is a silicon nitride layer, a silicon oxide layer or a silicon oxynitride layer.
- the material used for the active layer is indium gallium zinc oxide.
- the material used for the protective layer is silicon oxide.
- the TiO 2 film layer has a thickness of 5 nm to 60 nm.
- one side in the present invention refers to the same side of the glass substrate; the "other side” refers to the side opposite to the "one side”.
- the invention designs a BCE structure IGZO-TFT device, and adds a layer of nano TiO 2 film on top of the IGZO active layer to shield UV light and external pollutants such as metal ions, thereby preventing the IGZO from having
- the stability of the source layer has an effect, and the stability of the device is improved without adding a photomask.
- the thin film transistor can be applied to both a liquid crystal display and an OLED display.
- FIG. 1 is a schematic structural view of a metal oxide thin film transistor according to an embodiment of the present invention.
- FIG. 2 is a flow chart showing a method of fabricating a metal oxide thin film transistor according to an embodiment of the present invention
- FIG. 3 is a schematic view showing a gate electrode layer formed on a glass substrate in an embodiment of the present invention.
- FIG. 4 is a schematic view showing a gate insulating layer and an active layer formed on a gate electrode layer in an embodiment of the present invention
- FIG. 5 is a schematic view showing a source/drain layer formed on an active layer in an embodiment of the present invention.
- FIG. 6 is a schematic view showing a protective layer formed on a source drain and a TiO 2 thin film deposited on a protective layer in an embodiment of the present invention
- FIG. 7 is a schematic view showing a surface of a TiO 2 film layer coated with a planarization layer and forming a contact hole connecting the planarization layer, the TiO 2 film layer, and the protective layer on the upper surface of the source and drain layers in the embodiment of the present invention. ;
- Figure 8 shows a schematic view after deposition of an anode layer in a contact hole on a planarization layer and an upper surface of a planarization layer covering the contact hole.
- the invention aims to solve the problem that the IGZO-TFT device in the prior art has high cost and the stability of the IGZO active layer is susceptible to UV light and external pollutants.
- an embodiment of the present invention provides a metal oxide thin film transistor.
- FIG. 1 is a schematic structural view of a metal oxide thin film transistor according to an embodiment of the present invention.
- the metal oxide thin film transistor of the present embodiment includes a gate electrode layer 11, a gate insulating layer 12, an active layer 13, a source/drain layer 14, a protective layer 15, a TiO 2 thin film layer 16, and planarization.
- the gate electrode layer 11 is located on the upper surface close to the a side of the glass substrate 10.
- the gate insulating layer 12 is located on the upper surface of the gate electrode layer 11 and the upper surface of the glass substrate 10 not covered by the gate electrode layer 11.
- the active layer 13 is located on the upper surface of the gate insulating layer 12 on the a side of the glass substrate 10.
- the source and drain layer 14 is located on the upper surface of the active layer 13 and the upper surface of the gate insulating layer 12 which is not covered by the active layer 13 near the a side of the glass substrate 10.
- the protective layer 15 is located on the upper surface of the source and drain layer 14 and the upper surface of the gate insulating layer 12 not covered by the source and drain layers 14.
- the TiO 2 film layer 16 is located on the upper surface of the protective layer 15.
- the planarization layer 17 is located on the upper surface of the TiO 2 film layer 16; the planarization layer 17 is provided with a contact hole 20, the contact hole 20 is located close to the b side of the glass substrate 10, and the contact hole 20 is from the The upper surface of the planarization layer 17 extends to the upper surface of the source and drain layer 14.
- the anode layer 19 is formed in the contact hole 20 of the planarization layer 17 and covers the upper surface of the planarization layer 17 of the contact hole 20.
- the pixel defining region organic layer 18 is located on the anode layer 19 on the upper surface of both sides of the glass substrate 10 and the upper surface of the planarizing layer 17 not covered by the anode layer 19.
- the material used for the gate electrode layer 11 is Mo.
- the gate insulating layer 12 is a silicon oxide layer.
- the material used for the active layer 13 is indium gallium zinc oxide.
- the material used for the source and drain layer 14 is Mo.
- the material used for the protective layer 15 is silicon oxide.
- the TiO 2 film layer 16 has a thickness of 40 nm.
- embodiments of the present invention also provide a method of fabricating a metal oxide thin film transistor.
- the preparation method mainly includes steps 101 to 107.
- the gate electrode layer 11 is deposited on the upper surface near the a side of the glass substrate 10 by physical vapor deposition, and then a desired gate electrode pattern is formed by a standard photolithography process, resulting in a structure as shown in FIG.
- the material used for the gate electrode layer 11 is Mo.
- a gate insulating layer 12 is deposited on the upper surface of the gate electrode layer 11 and the upper surface of the glass substrate 10 not covered by the gate electrode layer 11 by chemical vapor deposition; and physical vapor deposition is applied to the glass substrate 10
- the active layer 13 is deposited on the upper surface of the gate insulating layer 11 on the a side, and a desired active layer pattern is formed by applying a photoresist, exposure, development, and etching process to obtain a structure as shown in FIG.
- the gate insulating layer 12 is a silicon oxide layer.
- a source/drain layer 14 is deposited on the upper surface of the active layer 13 and the upper surface of the gate insulating layer 12 not covered by the active layer 13 on the a side of the glass substrate 10 by physical vapor deposition,
- the desired source and drain patterns are then formed by standard photolithography processes to provide the structure shown in FIG.
- the material of the source and drain layer 14 is Mo.
- a protective layer 15 is deposited on the upper surface of the source/drain layer 14 and the upper surface of the gate insulating layer 12 not covered by the source and drain layer 14 by chemical vapor deposition; and then chemical vapor deposition or sol-gel is used.
- a dense nano-TiO 2 film layer 16 is deposited on the surface of the protective layer 15 by a gel method to obtain a structure as shown in FIG.
- the material used for the protective layer 15 is silicon oxide.
- the thickness of the TiO 2 film layer was 40 nm.
- step 105 on the TiO 2 surface-coated thin-film layer 16 and the planarization layer 17 is formed communicating the planarization layer 17, a contact hole 16 TiO 2 thin-film layer and a protective layer 14 on the upper surface of the source-drain layer 15 20, and then a contact hole pattern is formed by an exposure, development, and etching process to obtain a structure as shown in FIG.
- step 106 the anode layer 19 is deposited by physical vapor deposition in the contact hole 20 on the planarization layer 17 and the upper surface of the planarization layer 17 covering the contact hole 20, resulting in a structure as shown in FIG.
- a pixel defining region organic layer 18 is defined on the upper surface of the anode layer 19 adjacent to both sides of the glass substrate 10 and the upper surface of the planarizing layer 17 not covered by the anode layer 19, and a pixel region is defined.
- a metal oxide thin film transistor as shown in FIG. 1 was obtained. The process of the subsequent liquid crystal display and the OLED display is completed, and a display device with good stability is obtained.
- a nano-TiO 2 film is added on the IGZO active layer to shield UV light and external pollutants such as metal ions, thereby preventing the stability of the IGZO active layer from being affected.
- the reticle improves the stability of the device.
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Abstract
一种金属氧化物薄膜晶体管及其制备方法。通过在IGZO有源层(13)的上方加一层纳米TiO 2薄膜(16),起到屏蔽UV光和外界污染物的作用,防止其对IGZO有源层(13)的稳定性产生影响,在不增加光罩的基础上提高了器件的稳定性。
Description
本申请要求享有2016年8月30日提交的名称为“一种金属氧化物薄膜晶体管及其制备方法”的中国专利申请CN201610769871.9的优先权,其全部内容通过引用并入本文中。
本发明涉及薄膜晶体管及其制备技术领域,具体涉及一种金属氧化物薄膜晶体管及其制备方法。
近年来,我们看到平板电视变得越来越大且功能不断提升。全高清(HD)屏幕分辨率(1920x1080像素)已成为标准配置,诸多面板制造商纷纷开始展示或推出更大的超清分辨率屏幕。与此同时,刷新率也在不断提高,为移动影像和3D电视带来了更加出色的画质。
如今,有大量的大屏幕可供消费者选择,这些屏幕画质非常清晰,细节一览无遗,刷新率达到了极高的水平。最近,大屏幕OLED电视已开始进入市场。然而,这些高性能显示的制造却给面板制造商带来了重大挑战,因为制造商们需要找到可行的办法,以足够快的速度和足够低的功耗来驱动集成于超大面积内的所有这些像素。驱动这些像素的是由数百万个薄膜晶体管(TFT)构成的阵列,称之为背板。多年来,非晶硅薄膜晶体管(a-Si TFT)背板一直是显示行业的中流砥柱。但是,非晶硅存在天生的局限性,难以提供驱动高分辨率、高性能显示所需要的开关特性。非晶硅晶体管速度太慢、无法胜任:在这种材料中,电子和空穴迁移速度过慢,我们将这种特性称为迁移率。
能够克服非晶硅薄膜晶体管迁移率障碍的多种技术已经出现。其中,金属氧化物薄膜晶体管技术似乎最受青睐,现有的薄膜晶体管制造工厂采用该技术并不困难,因为金属氧化物通常是用已经广为人知的物理气相沉积(PVD)工艺沉积的。考虑使用的材料在沉积时不受尺寸限制,而且具有足够高的迁移率,能够制造出适用于高分辨率、高刷新率纯平显示的背板。金属氧化物薄膜晶体管已取得长足进展。有源层的最佳材料是铟镓锌氧化物(IGZO),其迁移率比非晶硅高出10到20倍。
IGZO通常用一种被称为磁控溅射的PVD技术进行沉积,该技术同时采用了磁场和电场来移除阴极的材料并沉积到背板上。在金属氧化物薄膜晶体管成熟、量产之前,还有诸多困难需要克服,尤其是在制造OLED电视背板方面。主要改进领域为器件不稳定性。若任一效应强烈到肉眼可见,将会影响消费者的视觉体验。
IGZO具有高迁移率、适用于大面积生产、与a-Si制程相似等优势,逐渐成为目前显示技术领域内的研究热点。但IGZO-TFT的IGZO层对于工艺和环境非常敏感,因此常常需要采用ESL结构,对IGZO层进行保护,增加了一道Mask,不利于制程成本的降低。且由于IGZO的禁带宽度(约为3.4eV)与UV光的禁带宽度(高于3.1eV)相近,IGZO对UV光有很好的吸收作用,IGZO层在UV光的照射下,价带电子等易吸收能量跃迁至导带,使TFT的阈值电压偏移,使显示器显示效果不稳定。
发明内容
本发明旨在解决现有技术中的IGZO-TFT器件成本高,IGZO有源层的稳定性易受UV光和外界污染物影响的问题。
为了解决上述技术问题,本发明提供了一种金属氧化物薄膜晶体管及其制备方法。
根据本发明的第一个方面,提供了一种金属氧化物薄膜晶体管,其包括:
栅电极层,其位于靠近玻璃基板一侧的上表面;
栅绝缘层,其位于所述栅电极层上表面以及未被所述栅电极层覆盖的玻璃基板上表面;
有源层,其位于靠近玻璃基板一侧的栅绝缘层上表面;
源漏极层,其位于所述有源层上表面以及靠近玻璃基板一侧的未被所述有源层覆盖的栅绝缘层上表面;
保护层,其位于所述源漏极层上表面以及未被所述源漏极层覆盖的栅绝缘层上表面;
TiO2薄膜层,其位于所述保护层上表面;
平坦化层,其位于所述TiO2薄膜层上表面;所述平坦化层设有接触孔,所述接触孔的位置靠近玻璃基板的另一侧,所述接触孔从所述平坦化层的上表面延伸到所述源漏极层的上表面;
阳极层,其形成于所述平坦化层的接触孔内以及覆盖接触孔的平坦化层的上表面;
像素定义区有机层,其位于所述阳极层上靠近玻璃基板两侧的上表面以及未被所述阳极层覆盖的平坦化层上表面。
优选的是,所述栅电极层所用材料为钛(Ti)、铬(Cr)、铝(Al)、钼(Mo)或
铜(Cu)。
优选的是,所述栅绝缘层为氮化硅层、氧化硅层或氮氧化硅层。
优选的是,所述有源层所用材料为铟镓锌氧化物。
优选的是,所述保护层所用材料为氧化硅。
优选的是,所述TiO2薄膜层的厚度为5nm~60nm。
根据本发明的第二个方面,提供了一种金属氧化物薄膜晶体管的制备方法,其包括以下步骤:
a)采用物理气相沉积在靠近玻璃基板一侧的上表面沉积栅电极层,然后通过标准光刻工艺,形成所需的栅电极图案;
b)采用化学气相沉积在所述栅电极层上表面以及未被所述栅电极层覆盖的玻璃基板上表面沉积栅绝缘层;
c)采用物理气相沉积在靠近玻璃基板一侧的栅绝缘层上表面沉积有源层,通过涂覆光刻胶、曝光、显影、刻蚀工艺,形成所需的有源层图案;
d)采用物理气相沉积在所述有源层上表面以及靠近玻璃基板一侧的未被所述有源层覆盖的栅绝缘层上表面沉积源漏极层,然后通过标准光刻工艺,形成所需的源漏极图案;
e)采用化学气相沉积在所述源漏极层上表面以及未被所述源漏极层覆盖的栅绝缘层上表面沉积保护层;
f)采用化学气相沉积或溶胶凝胶法在所述保护层上表面沉积致密的纳米TiO2薄膜层;
g)在所述TiO2薄膜层上表面涂覆平坦化层并形成连通平坦化层、TiO2薄膜层以及源漏极层上表面上的保护层的接触孔,然后通过曝光、显影、刻蚀工艺,形成接触孔图案;
h)采用物理气相沉积在所述平坦化层上的接触孔内以及覆盖接触孔的平坦化层的上表面沉积形成阳极层;
i)在所述阳极层上靠近玻璃基板两侧的上表面以及未被所述阳极层覆盖的平坦化层上表面涂覆像素定义区有机层,定义像素区,得到所述金属氧化物薄膜晶体管。
优选的是,所述栅电极层所用材料为钛、铬、铝、钼或铜。
优选的是,所述栅绝缘层为氮化硅层、氧化硅层或氮氧化硅层。
优选的是,所述有源层所用材料为铟镓锌氧化物。
优选的是,所述保护层所用材料为氧化硅。
优选的是,所述TiO2薄膜层的厚度为5nm~60nm。
本发明所述用语“一侧”均指玻璃基板的同一侧;“另一侧”是与“一侧”相对的一侧。
与现有技术相比,上述方案中的一个或多个实施例可以具有如下优点或有益效果:
本发明设计了一种BCE结构的IGZO-TFT器件,在IGZO有源层的上方加一层纳米TiO2薄膜,起到屏蔽UV光和外界污染物如金属离子等的作用,防止其对IGZO有源层的稳定性产生影响,在不增加光罩的基础上提高了器件的稳定性,此薄膜晶体管在液晶显示器和OLED显示器中均可适用。
本发明的其它特征和优点将在随后的说明书中阐述,并且部分地从说明书中变得显而易见,或者通过实施本发明而了解。本发明的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
附图用来提供对本发明的进一步理解,并且构成说明书的一部分,与本发明的实施例共同用于解释本发明,并不构成对本发明的限制。在附图中:
图1示出了本发明实施例金属氧化物薄膜晶体管的结构示意图;
图2示出了本发明实施例制备金属氧化物薄膜晶体管的方法的流程示意图;
图3示出了本发明实施例中在玻璃基板上形成栅电极层后的示意图;
图4示出了本发明实施例中在栅电极层上形成栅绝缘层和有源层后的示意图;
图5示出了本发明实施例中在有源层上形成源漏极层后的示意图;
图6示出了本发明实施例中在源漏极上形成保护层并在保护层上沉积TiO2薄膜层后的示意图;
图7示出了本发明实施例中在TiO2薄膜层上表面涂覆平坦化层并形成连通平坦化层、TiO2薄膜层以及源漏极层上表面上的保护层的接触孔后的示意图;
图8示出了在平坦化层上的接触孔内以及覆盖接触孔的平坦化层的上表面沉积形成阳极层后的示意图。
以下将结合附图及实施例来详细说明本发明的实施方式,借此对本发明如何应用技术手段来解决技术问题,并达成技术效果的实现过程能充分理解并据以实施。需要说明的是,只要不构成冲突,本发明中的各个实施例以及各实施例中的各个特征可以相互结
合,所形成的技术方案均在本发明的保护范围之内。
本发明旨在解决现有技术中的IGZO-TFT器件成本高,IGZO有源层的稳定性易受UV光和外界污染物影响的问题。为了解决上述技术问题,本发明实施例提供了一种金属氧化物薄膜晶体管。
图1为本发明实施例金属氧化物薄膜晶体管的结构示意图。如图1所示,本实施例的金属氧化物薄膜晶体管包括:栅电极层11、栅绝缘层12、有源层13、源漏极层14、保护层15、TiO2薄膜层16、平坦化层17、阳极层19以及像素定义区有机层18。
栅电极层11位于靠近玻璃基板10的a侧的上表面。
栅绝缘层12位于所述栅电极层11上表面以及未被所述栅电极层11覆盖的玻璃基板10上表面。
有源层13位于靠近玻璃基板10的a侧的栅绝缘层12上表面。
源漏极层14位于所述有源层13上表面以及靠近玻璃基板10的a侧的未被所述有源层13覆盖的栅绝缘层12上表面。
保护层15位于所述源漏极层14上表面以及未被所述源漏极层14覆盖的栅绝缘层12上表面。
TiO2薄膜层16位于所述保护层15上表面。
平坦化层17位于所述TiO2薄膜层16上表面;所述平坦化层17设有接触孔20,所述接触孔20的位置靠近玻璃基板10的b侧,所述接触孔20从所述平坦化层17的上表面延伸到所述源漏极层14的上表面。
阳极层19形成于所述平坦化层17的接触孔20内以及覆盖接触孔20的平坦化层17的上表面。
像素定义区有机层18位于所述阳极层19上靠近玻璃基板10两侧的上表面以及未被所述阳极层19覆盖的平坦化层17上表面。
在本发明一优选的实施例中,所述栅电极层11所用材料为Mo。
在本发明一优选的实施例中,所述栅绝缘层12为氧化硅层。
在本发明一优选的实施例中,所述有源层13所用材料为铟镓锌氧化物。
在本发明一优选的实施例中,所述源漏极层14所用材料为Mo。
在本发明一优选的实施例中,所述保护层15所用材料为氧化硅。
在本发明一优选的实施例中,所述TiO2薄膜层16的厚度为40nm。
相应地,本发明实施例还提供了一种金属氧化物薄膜晶体管的制备方法。
图2是本发明实施例中制备金属氧化物薄膜晶体管的方法的流程示意图。本实施例的
制备方法主要包括步骤101至步骤107。
在步骤101中,采用物理气相沉积在靠近玻璃基板10的a侧的上表面沉积栅电极层11,然后通过标准光刻工艺,形成所需的栅电极图案,得到如图3所示的结构。栅电极层11所用材料为Mo。
在步骤102中,采用化学气相沉积在所述栅电极层11上表面以及未被所述栅电极层11覆盖的玻璃基板10上表面沉积栅绝缘层12;再采用物理气相沉积在靠近玻璃基板10的a侧的栅绝缘层11上表面沉积有源层13,通过涂覆光刻胶、曝光、显影、刻蚀工艺,形成所需的有源层图案,得到如图4所示的结构。栅绝缘层12为氧化硅层。
在步骤103中,采用物理气相沉积在所述有源层13上表面以及靠近玻璃基板10的a侧的未被所述有源层13覆盖的栅绝缘层12上表面沉积源漏极层14,然后通过标准光刻工艺,形成所需的源漏极图案,得到如图5所示的结构。源漏极层14的材料为Mo。
在步骤104中,采用化学气相沉积在所述源漏极层14上表面以及未被所述源漏极层14覆盖的栅绝缘层12上表面沉积保护层15;再采用化学气相沉积或溶胶凝胶法在所述保护层15上表面沉积致密的纳米TiO2薄膜层16,得到如图6所示的结构。保护层15所用材料为氧化硅。TiO2薄膜层的厚度为40nm。
在步骤105中,在所述TiO2薄膜层16上表面涂覆平坦化层17并形成连通平坦化层17、TiO2薄膜层16以及源漏极层14上表面上的保护层15的接触孔20,然后通过曝光、显影、刻蚀工艺,形成接触孔图案,得到如图7所示的结构。
在步骤106中,采用物理气相沉积在所述平坦化层17上的接触孔20内以及覆盖接触孔20的平坦化层17的上表面沉积形成阳极层19,得到如图8所示的结构。
在步骤107中,在所述阳极层19上靠近玻璃基板10两侧的上表面以及未被所述阳极层19覆盖的平坦化层17上表面涂覆像素定义区有机层18,定义像素区,得到如图1所示的金属氧化物薄膜晶体管。完成后续液晶显示器和OLED显示器的制程,获得稳定性佳的显示装置。
本实施例在IGZO有源层的上方加一层纳米TiO2薄膜,起到屏蔽UV光和外界污染物如金属离子等的作用,防止其对IGZO有源层的稳定性产生影响,在不增加光罩的基础上提高了器件的稳定性。
虽然本发明所公开的实施方式如上,但所述的内容只是为了便于理解本发明而采用的实施方式,并非用以限定本发明。任何本发明所属技术领域内的技术人员,在不脱离本发明所公开的精神和范围的前提下,可以在实施的形式上及细节上作任何的修改与变化,但本发明的保护范围,仍须以所附的权利要求书所界定的范围为准。
Claims (10)
- 一种金属氧化物薄膜晶体管,其包括:栅电极层,其位于靠近玻璃基板一侧的上表面;栅绝缘层,其位于所述栅电极层上表面以及未被所述栅电极层覆盖的玻璃基板上表面;有源层,其位于靠近玻璃基板一侧的栅绝缘层上表面;源漏极层,其位于所述有源层上表面以及靠近玻璃基板一侧的未被所述有源层覆盖的栅绝缘层上表面;保护层,其位于所述源漏极层上表面以及未被所述源漏极层覆盖的栅绝缘层上表面;TiO2薄膜层,其位于所述保护层上表面;平坦化层,其位于所述TiO2薄膜层上表面;所述平坦化层设有接触孔,所述接触孔的位置靠近玻璃基板的另一侧,所述接触孔从所述平坦化层的上表面延伸到所述源漏极层的上表面;阳极层,其形成于所述平坦化层的接触孔内以及覆盖接触孔的平坦化层的上表面;像素定义区有机层,其位于所述阳极层上靠近玻璃基板两侧的上表面以及未被所述阳极层覆盖的平坦化层上表面。
- 根据权利要求1所述的晶体管,其中,所述栅电极层所用材料为钛、铬、铝、钼或铜。
- 根据权利要求1所述的晶体管,其中,所述栅绝缘层为氮化硅层、氧化硅层或氮氧化硅层。
- 根据权利要求1所述的晶体管,其中,所述有源层所用材料为铟镓锌氧化物。
- 根据权利要求1所述的晶体管,其中,所述TiO2薄膜层的厚度为5nm~60nm。
- 一种金属氧化物薄膜晶体管的制备方法,其包括以下步骤:a)采用物理气相沉积在靠近玻璃基板一侧的上表面沉积栅电极层,然后通过标准光刻工艺,形成所需的栅电极图案;b)采用化学气相沉积在所述栅电极层上表面以及未被所述栅电极层覆盖的玻璃基板上表面沉积栅绝缘层;c)采用物理气相沉积在靠近玻璃基板一侧的栅绝缘层上表面沉积有源层,通过涂覆光刻胶、曝光、显影、刻蚀工艺,形成所需的有源层图案;d)采用物理气相沉积在所述有源层上表面以及靠近玻璃基板一侧的未被所述有源层覆盖的栅绝缘层上表面沉积源漏极层,然后通过标准光刻工艺,形成所需的源漏极图案;e)采用化学气相沉积在所述源漏极层上表面以及未被所述源漏极层覆盖的栅绝缘层上表面沉积保护层;f)采用化学气相沉积或溶胶凝胶法在所述保护层上表面沉积致密的纳米TiO2薄膜层;g)在所述TiO2薄膜层上表面涂覆平坦化层并形成连通平坦化层、TiO2薄膜层以及源漏极层上表面上的保护层的接触孔,然后通过曝光、显影、刻蚀工艺,形成接触孔图案;h)采用物理气相沉积在所述平坦化层上的接触孔内以及覆盖接触孔的平坦化层的上表面沉积形成阳极层;i)在所述阳极层上靠近玻璃基板两侧的上表面以及未被所述阳极层覆盖的平坦化层上表面涂覆像素定义区有机层,定义像素区,得到所述金属氧化物薄膜晶体管。
- 根据权利要求6所述的方法,其中,所述栅电极层所用材料为钛、铬、铝、钼或铜。
- 根据权利要求6所述的方法,其中,所述栅绝缘层为氮化硅层、氧化硅层或氮氧化硅层。
- 根据权利要求6所述的方法,其中,所述有源层所用材料为铟镓锌氧化物。
- 根据权利要求6所述的方法,其中,所述TiO2薄膜层的厚度为5nm~60nm。
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