WO2018034525A1 - Carte de circuit imprimé flexible - Google Patents

Carte de circuit imprimé flexible Download PDF

Info

Publication number
WO2018034525A1
WO2018034525A1 PCT/KR2017/008991 KR2017008991W WO2018034525A1 WO 2018034525 A1 WO2018034525 A1 WO 2018034525A1 KR 2017008991 W KR2017008991 W KR 2017008991W WO 2018034525 A1 WO2018034525 A1 WO 2018034525A1
Authority
WO
WIPO (PCT)
Prior art keywords
test
connection pad
base substrate
pattern
flexible circuit
Prior art date
Application number
PCT/KR2017/008991
Other languages
English (en)
Korean (ko)
Inventor
박성빈
손동은
홍성민
Original Assignee
스템코 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 스템코 주식회사 filed Critical 스템코 주식회사
Priority to JP2019503656A priority Critical patent/JP6918094B2/ja
Priority to CN201780050410.9A priority patent/CN109644550B/zh
Publication of WO2018034525A1 publication Critical patent/WO2018034525A1/fr

Links

Images

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0266—Marks, test patterns or identification means
    • H05K1/0268—Marks, test patterns or identification means for electrical inspection or testing
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
    • G01R31/281—Specific types of tests or tests for a specific type of fault, e.g. thermal mapping, shorts testing
    • G01R31/2813—Checking the presence, location, orientation or value, e.g. resistance, of components or conductors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/09481—Via in pad; Pad over filled via

Definitions

  • the present invention relates to a flexible circuit board.
  • FPDs flat panel displays
  • LCDs liquid crystal displays
  • OLED organic light emitting diode
  • a conductive wiring pattern for transmitting an electrical signal may be formed on the flexible circuit board.
  • a separate test pad or a probe in electrical contact with a via land surrounding a via may be used on the substrate.
  • the present invention has been made in an effort to provide a flexible circuit board capable of inspecting whether a short circuit is opened or not, without causing a terminal defect in a via land.
  • a flexible circuit board for achieving the above technical problem, is electrically connected to a base substrate, a test area is defined on one surface, a first wiring pattern formed on the one surface of the base substrate, respectively At least one or more first connection pads disposed on the one surface of the base substrate, each of the at least one second connection pads electrically connected to a second wiring pattern formed on the other surface of the base substrate on the other surface And a test pattern extending from the second connection pad onto the test area.
  • the test pattern includes a first test pattern extending from the first connection pad onto the test region and a second test pattern extending from the second connection pad onto the test region. can do.
  • the first test pattern and the second test pattern may be disposed to intersect in the test area.
  • the test region may include a first test region in which a first test pattern is disposed and a second test region in which the second test pattern is disposed.
  • the first test area or the second test area may be disposed between the first connection pad and the second connection pad.
  • the first test area or the second test area may be disposed between an end of the flexible circuit board and the first connection pad or the second connection pad.
  • the test pattern may be 45 degrees to 135 degrees with respect to the probe scanning progress direction.
  • the second connection pad may be electrically connected to the second wiring pattern and may vertically overlap with a via passing through the base substrate.
  • the flexible circuit board since a separate test pad is not provided to test whether the wiring pattern is shorted or open, it may have an advantageous effect on the miniaturization of the board.
  • FIG. 1 is a diagram of a flexible circuit board in accordance with one embodiment of the present invention.
  • FIG. 2 is a cross-sectional view taken along line AA ′ of FIG. 1.
  • FIG 3 is an enlarged view of a test area of a flexible circuit board according to an exemplary embodiment of the present invention.
  • FIGS. 4-5 are diagrams of flexible circuit boards in accordance with another embodiment of the present invention.
  • spatially relative terms below “, “ beneath “, “ lower”, “ above “, “ upper” It may be used to easily describe the correlation of a device or components with other devices or components. Spatially relative terms are to be understood as including terms in different directions of the device in use or operation in addition to the directions shown in the figures. For example, when flipping a device shown in the figure, a device described as “below” or “beneath” of another device may be placed “above” of another device. Thus, the exemplary term “below” can encompass both an orientation of above and below. The device can also be oriented in other directions, so that spatially relative terms can be interpreted according to orientation.
  • first, second, etc. are used to describe various elements or components, these elements or components are of course not limited by these terms. These terms are only used to distinguish one element or component from another element or component. Therefore, the first device or component mentioned below may be a second device or component within the technical idea of the present invention.
  • FIG. 1 is a diagram of a flexible circuit board according to an embodiment of the present invention
  • FIG. 2 is a cross-sectional view taken along line AA ′ of FIG. 1.
  • a flexible circuit board 1 may include a base substrate 10, a first wiring pattern 15 formed on one surface of the base substrate, and a first connection pad 50. ), A second connection pad 30, a first test pattern 40, a second test pattern 20, and a second wiring pattern 16 formed on the other surface of the base substrate.
  • the base substrate 10 may be formed of a flexible material and may be included as the substrate in the flexible circuit board 1 to allow the flexible circuit board 1 to be bent or folded.
  • the base substrate 10 may be, for example, a polyimide film.
  • the base substrate 10 may be a PET film, polyethylene naphthalate film, polycarbonate film or insulating metal foil.
  • the base substrate 10 is described as being a polyimide film.
  • the first wiring pattern 15 may be formed on one surface of the base substrate 10.
  • a surface on the base substrate 10 on which the first wiring pattern 15, the first test pattern 40, and the like are disposed is called one surface, and the base substrate on which the second wiring pattern 16 is disposed ( The surface of 10) is described as the other surface.
  • the first wiring pattern 15 may be a plurality of wiring patterns spaced apart from each other with a predetermined width and interval.
  • the first wiring pattern 15 may include, for example, a conductive material such as copper, but the present invention is not limited thereto. Specifically, the first wiring pattern 15 may be made of a material having electrical conductivity, such as gold and aluminum.
  • the first wiring pattern 15 may include at least one subpattern 15_1 and 15_2.
  • the first wiring patterns 15 may be respectively connected to the first connection pads 50 to transmit electrical signals to the first connection pads 50.
  • the first sub pattern 15_1 may be connected to the first sub pad 50_1
  • the second sub pattern 15_2 may be connected to the second sub pad 50_2.
  • first wiring pattern 15 may be electrically connected to the first test pattern 40 through the first connection pad 50.
  • first sub pattern 15_1 may be electrically connected to the first sub test pattern 40_1 through the first sub pad 50_1, and the second sub pattern 15_2 may be the second sub pad 50_2. It may be electrically connected to the second sub test pattern 40_2 through.
  • One end of the first wiring pattern 15 may be connected to the first connection pad 50, and the other end (not shown) may be connected to another pad or connection terminal.
  • the first connection pad 50 may be, for example, an outer lead for connecting to an external device connected to the flexible circuit board 1, and another pad connected to the other end of the first wiring pattern 15 may be It may be an inner lead on which the driving element is mounted.
  • the first wiring pattern 15 since the short / open test using probe scanning is performed on the test patterns 20 and 40 on the test areas 25 and 35, the first wiring pattern 15 ) May not be exposed and may be covered with a protective layer. For example, at least a portion of the first wiring pattern 15 may be covered with a solder resist.
  • the first subpattern 15_1 and the second subpattern 15_2 constituting the first wiring pattern 15 are disposed to extend in the third direction d3, and the first direction ( d1) may be spaced apart from each other, but the present invention is not limited thereto. That is, the arrangement is only one embodiment, and the first subpattern 15_1 and the second subpattern 15_2 extend in the first direction d1 and are spaced apart from each other in the third direction d3, respectively. May be
  • the first connection pad 50 may be formed on one surface of the base substrate 10.
  • the first connection pad 50 may be connected to the first wiring pattern 15 and may have an extended shape of the first wiring pattern 15.
  • the first connection pad 50 may include at least one sub pad. As shown in FIG. 1, the first sub pad 50_1 and the second sub pad 50_2 may be included. The first sub pad 50_1 may electrically connect the first sub pattern 15_1 and the first sub test pattern 40_1, and the second sub pad 50_2 may connect the second sub pattern 15_2 and the second sub pattern 15_1. The sub test pattern 40_2 can be electrically connected.
  • the plurality of first connection pads 50 may be spaced apart from each other at regular intervals to form a first connection pad group 51.
  • the plurality of first connection pads 50 may be arranged side by side in the second direction d2 as illustrated in FIG. 1. Meanwhile, the first connection pads 50 arranged side by side in the second direction d2 may not be overlapped in the first direction d1, but may be disposed to overlap at least a portion in the third direction d3.
  • This arrangement is to minimize the area required for the arrangement of the first connection pads 50 when the first wiring pattern 15 and the first test pattern 40 are arranged to extend in the third direction d3, respectively.
  • the present invention is not limited thereto.
  • the first connection pads 50 may be at least partially in the first direction d1. They may be arranged to overlap each other and not overlap each other in the third direction d3.
  • the first connection pad 50 may include a material having electrical conductivity such as copper, gold, or an alloy thereof.
  • the second wiring pattern 16 may be formed on the other surface of the base substrate 10. That is, the second wiring pattern 16 may be formed on opposite surfaces of the first wiring pattern 15 and the base substrate 10. Similar to the first wiring pattern 15, the second wiring pattern 16 may be a plurality of wiring patterns disposed on the other surface of the base substrate 10 and spaced apart from each other at predetermined widths and intervals.
  • the second wiring pattern 16 may be electrically connected to the second connection pad 30. That is, as shown in FIG. 2, the second wiring pattern 16 may extend on the other surface of the base substrate 10 and be connected to the second connection pad 30. The second wiring pattern 16 may be electrically connected to the second test pattern 20 through the second connection pad 30. Like the first wiring pattern 15, the second wiring pattern 16 may be made of a material having electrical conductivity such as copper, gold, and aluminum.
  • the second connection pad 30 may include an upper pad 36 and a lower pad 37.
  • the upper pad 36 is connected to the second test pattern 20 formed on one surface of the base substrate 10, and the lower pad 37 is formed on the second wiring pattern formed on the other surface of the base substrate 10. 16).
  • At least a portion of the upper pad 36 may vertically overlap with the lower pad 37. Meanwhile, the upper pad 36 and the lower pad 37 may be connected through the via 41.
  • the second connection pads 30 may be disposed to vertically overlap the vias 41. For each of the plurality of second connection pads 30 spaced apart from each other in the second direction d2, vias 41 penetrating the base substrate 10 respectively overlap with the plurality of second connection pads 30, respectively. It may be arranged to.
  • the via 41 may fill the via hole 45 penetrating the base substrate 10 and electrically connect the upper pad 36 and the lower pad 37 to each other.
  • the via 41 filling the via hole 45 is illustrated in FIG. 2 as a single layer, the via 41 may be formed in a multilayer structure having two or more layers in which a metal foil layer is formed on the inner wall of the via hole 45. .
  • the plurality of second connection pads 30 may be spaced apart from each other on one surface of the base substrate 10 at regular intervals to form a second connection pad group 31.
  • the plurality of second connection pads 30 may be arranged side by side in the second direction d2, for example.
  • the plurality of second connection pads 30 may be disposed so as not to overlap each other in the first direction d1 but at least partially overlap the third direction d3.
  • the arrangement of the second connection pads 30 is minimized to minimize the area required for the arrangement of the second connection pads 30. It may be an example of the present invention is not limited.
  • the second connection pads 30 are at least in the first direction d1 to optimize the placement area. Some may overlap and may not be overlapped in the third direction d3.
  • the second connection pad 30 may include an electrically conductive material such as copper, gold, or an alloy thereof.
  • the second connection pad 30 connects the second wiring pattern 16 on the other surface of the base substrate 10 with the second test pattern 20 on the one surface, and the second wiring pattern on the other surface of the base substrate 10.
  • the circuit element connected to 16 may be electrically connected to the second test pattern 20. Accordingly, the open / short test of the circuit element or the second wiring pattern 16 disposed on the other surface of the base substrate 10 may be performed using the second test pattern 20.
  • the first test pattern 40 may extend onto the first test area 35 on one surface of the base substrate 10.
  • the first test pattern 40 may extend between the first connection pad 50 and the second connection pad 30.
  • FIG. 3 is a diagram illustrating an arrangement of test patterns in a test area of a flexible circuit board according to an exemplary embodiment of the present invention.
  • the first test pattern 40 may extend at a predetermined angle with the extension direction d1 of the first test area 35.
  • the first test pattern 40 may form an angle of 45 degrees to 135 degrees with respect to the extension direction d1 of the first test region 35.
  • the first test area 35 may be divided into a portion 40_1a that forms an extension direction d1 of the first test region 35 at 45 degrees and a portion 40_1b which forms 90 degrees.
  • the first test region 35 or the second test region 25 may be probe scanning to perform an open / short test of a circuit element or a wiring pattern.
  • the extension direction d1 of the first test region 35 or the second test region 25 may be a direction in which the probe proceeds in the open / short test. Therefore, when the first or second test patterns 40 and 20 form a predetermined angle with the extending direction d1 of the first or second test areas 35 and 25, the first or second test patterns 40 and 20 may be used. Probe scanning may be performed at an angle with respect to 20).
  • the width w of the first or second test regions 35 and 25 may be 100 ⁇ m or more. That is, the width w of the extending direction of the test area (d1 in FIG. 3) may be 100 ⁇ m or more, which means that the probe scanning is 100 ⁇ m in the open / short test on the first or second test patterns 40, 20. It means that the above proceeds with a wide margin.
  • the first test region 35 may be disposed between the first connection pad 50 and the second connection pad 30, and the second test region 25 may be disposed between an end of the base substrate 10 and the second connection pad 30.
  • a sprocket hole formed to wind the base substrate 10 in a roll-to-roll process is formed at an end of the base substrate 10, and the second test area 25 is a sprocket hole (not shown). And the second connection pad 30 may be disposed.
  • the flexible circuit board 1 does not include a test pad for checking whether the wiring patterns 15 and 16 formed on the base substrate 10 are shorted / open.
  • test patterns 20 and 40 extending over the test areas 25 and 35 of the base substrate 10 where the probe scanning test is performed are provided, thereby reducing the area of the base substrate 10. It may be advantageous to the flexible circuit board (1).
  • probes for the wiring patterns 15 and 16 on both sides of the base substrate 10 are formed by the test patterns 20 and 40 electrically connecting the wiring patterns 15 and 16 on both sides of the base substrate 10. Scanning tests can be performed simultaneously.
  • FIG. 4 is a diagram of a flexible circuit board according to another embodiment of the present invention.
  • a configuration overlapping with the above embodiment will be omitted and the description will be given based on differences.
  • the first test area 35 and the second test area 25 may be adjacent to each other.
  • the flexible circuit board 1 described above with reference to FIG. 1 has been described in the present embodiment if the second test pattern 20 extends in the direction toward the end of the base substrate 10, that is, in the outward direction of the base substrate 10.
  • the flexible circuit board 2 may include a second test pattern 20 extending in the inward direction of the base substrate 10.
  • the first test pattern 40 and the second test pattern may extend between the first connection pad 50 and the second connection pad 30. Therefore, the first and second test areas 35 and 25 may also be disposed between the first connection pad 50 and the second connection pad 30 at a predetermined interval and spaced apart from each other.
  • the first and second test areas 35 and 25 are integrated into one test area, and the first and second test patterns 40 and 20 are included in the integrated test area.
  • the area of the test area may be reduced by intersecting with respect to the probe scanning direction.
  • FIG. 5 is a top view of a flexible circuit board according to another embodiment of the present invention.
  • the flexible circuit board 3 may include a first connection pad 50 and a second connection pad 30 disposed adjacent to each other. That is, the first connection pad group 51 configured by arranging the plurality of first connection pads in the second direction d2 and the second connection pad 30 arranged in the second direction d2 are formed of the first connection pad group 51.
  • the two connection pad groups 31 may be disposed adjacent to each other.
  • the first connection pad group 51 including the plurality of first connection pads 50 and the second connection pad group 31 including the plurality of second connection pads 30 may be provided. Although it may be arranged side by side in the second direction (d2), the present invention is not limited thereto. That is, the first connection pad group 51 and the second connection pad group 31 are disposed between the first test region 35 and the second test region 25, and the first and second connection pad groups are ( 51, 31) Embodiments in which the first direction d1 may be arranged side by side may be possible.
  • the first connection pad 50 may not include the first test pattern 40.
  • a portion of the first wiring pattern 15 connected to the first test pattern 40 may be selected to be set as the first test region 35 and a probe scanning test may be performed.
  • the area of the first test pattern 40 can be reduced, thereby reducing the product size.
  • test area 45 via
  • resist layer 160 protective film

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

L'invention concerne une carte de circuit imprimé flexible. La carte de circuit imprimé flexible comprend : un substrat de base sur un côté duquel est définie une aire d'essai ; une ou plusieurs pastilles de connexion connectées respectivement et électriquement à de premiers motifs de câblage formés sur un côté du substrat de base ; une ou plusieurs deuxièmes pastilles disposées sur un côté du substrat de base et connectées respectivement et électriquement à de deuxièmes motifs de câblage sur l'autre côté du substrat de base, qui est un côté opposé au côté susmentionné du substrat de base ; et des motifs d'essai s'étendant sur l'aire d'essai depuis la ou les deuxièmes pastilles de connexion.
PCT/KR2017/008991 2016-08-18 2017-08-17 Carte de circuit imprimé flexible WO2018034525A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2019503656A JP6918094B2 (ja) 2016-08-18 2017-08-17 フレキシブル回路基板
CN201780050410.9A CN109644550B (zh) 2016-08-18 2017-08-17 柔性印制电路板

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020160104709A KR101896224B1 (ko) 2016-08-18 2016-08-18 연성 회로 기판
KR10-2016-0104709 2016-08-18

Publications (1)

Publication Number Publication Date
WO2018034525A1 true WO2018034525A1 (fr) 2018-02-22

Family

ID=61196861

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/KR2017/008991 WO2018034525A1 (fr) 2016-08-18 2017-08-17 Carte de circuit imprimé flexible

Country Status (5)

Country Link
JP (1) JP6918094B2 (fr)
KR (1) KR101896224B1 (fr)
CN (1) CN109644550B (fr)
TW (1) TWI659680B (fr)
WO (1) WO2018034525A1 (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI744805B (zh) * 2020-02-24 2021-11-01 頎邦科技股份有限公司 電路板
KR20220076177A (ko) 2020-11-30 2022-06-08 삼성전자주식회사 패키지 기판용 필름 및 이를 포함하는 반도체 패키지
CN112954888B (zh) * 2021-02-19 2022-10-28 合肥京东方卓印科技有限公司 一种覆晶薄膜、覆晶薄膜组及显示装置
TWI776631B (zh) * 2021-08-09 2022-09-01 頎邦科技股份有限公司 雙面銅之軟性電路板
CN116525547A (zh) * 2022-01-20 2023-08-01 瑞昱半导体股份有限公司 晶粒封装结构及其制作方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002134644A (ja) * 2000-10-27 2002-05-10 Sharp Corp 半導体集積回路装置搭載用基板
JP2008187074A (ja) * 2007-01-31 2008-08-14 Nitto Denko Corp 配線回路基板およびその製造方法
KR20100000732A (ko) * 2008-06-25 2010-01-06 삼성전자주식회사 테스트 패드 구조물, 반도체 칩 검사용 패드 구조물 및이를 포함하는 테이프 패키지용 배선기판
KR101405328B1 (ko) * 2012-11-27 2014-06-10 스템코 주식회사 연성 회로 기판
KR20160083978A (ko) * 2015-01-02 2016-07-13 삼성전자주식회사 패키지 기판용 필름, 이를 사용한 반도체 패키지 및 반도체 패키지를 포함하는 표시 장치

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09230005A (ja) * 1996-02-22 1997-09-05 Hioki Ee Corp 回路基板検査装置
JPH1167845A (ja) * 1997-08-11 1999-03-09 Oki Electric Ind Co Ltd テープキャリア
JP2006228761A (ja) * 2005-02-15 2006-08-31 Matsushita Electric Ind Co Ltd Ｔａｂテープおよびｔａｂテープの製造方法
JP2006300665A (ja) * 2005-04-19 2006-11-02 Oht Inc 検査装置および導電パターン検査方法
JP2013217841A (ja) * 2012-04-11 2013-10-24 Union Arrow Technologies Inc 導電パターン検査装置
CN204578898U (zh) * 2015-05-06 2015-08-19 深圳市奔强电路有限公司 印刷电路板

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002134644A (ja) * 2000-10-27 2002-05-10 Sharp Corp 半導体集積回路装置搭載用基板
JP2008187074A (ja) * 2007-01-31 2008-08-14 Nitto Denko Corp 配線回路基板およびその製造方法
KR20100000732A (ko) * 2008-06-25 2010-01-06 삼성전자주식회사 테스트 패드 구조물, 반도체 칩 검사용 패드 구조물 및이를 포함하는 테이프 패키지용 배선기판
KR101405328B1 (ko) * 2012-11-27 2014-06-10 스템코 주식회사 연성 회로 기판
KR20160083978A (ko) * 2015-01-02 2016-07-13 삼성전자주식회사 패키지 기판용 필름, 이를 사용한 반도체 패키지 및 반도체 패키지를 포함하는 표시 장치

Also Published As

Publication number Publication date
TWI659680B (zh) 2019-05-11
KR20180020430A (ko) 2018-02-28
JP6918094B2 (ja) 2021-08-11
JP2019522378A (ja) 2019-08-08
CN109644550A (zh) 2019-04-16
TW201808068A (zh) 2018-03-01
CN109644550B (zh) 2022-03-15
KR101896224B1 (ko) 2018-09-11

Similar Documents

Publication Publication Date Title
WO2018034525A1 (fr) Carte de circuit imprimé flexible
WO2016099011A1 (fr) Carte de circuit imprimé souple, dispositif électronique la comprenant et procédé de fabrication de carte de circuit imprimé souple
WO2020009349A1 (fr) Module d'affichage à micro-del
WO2010098558A2 (fr) Bloc sonde
WO2021010769A1 (fr) Structure d'électrode couplée à une antenne et dispositif d'affichage la comprenant
WO2017010834A1 (fr) Module de caméra
KR20190071488A (ko) 반도체 패키지 및 이를 포함하는 반도체 모듈
WO2018159951A1 (fr) Carte de circuit imprimé souple pour dispositif d'affichage
KR20130105163A (ko) 반도체 패키지 및 이를 포함하는 표시 장치
WO2019160240A1 (fr) Carte de circuit imprimé flexible et dispositif électronique la comprenant
WO2019172583A1 (fr) Dispositif d'affichage pourvu d'une fonction tactile et procédé de montage de ligne de signal pour dispositif d'affichage
WO2018056594A1 (fr) Carte de circuit imprimé souple ayant une pastille de trou d'interconnexion
WO2019054668A1 (fr) Carte de circuit imprimé et son procédé de fabrication
CN101738806B (zh) 阵列背板、用以测试阵列背板的探针及液晶显示面板
WO2011087319A2 (fr) Dispositif électroluminescent
WO2019045462A1 (fr) Procédé de fabrication de carte à circuits imprimés flexible et carte à circuits imprimés flexible fabriquée au moyen dudit procédé
WO2015133775A1 (fr) Carte de circuit imprimé
KR101046949B1 (ko) 노이즈 차폐를 위한 다층구조의 인쇄회로기판을 구비한 프로브유닛
WO2020149558A1 (fr) Carte de circuit imprimé souple, son procédé de fabrication, et emballage ayant une carte de circuit imprimé souple
WO2021033951A1 (fr) Carte de circuit imprimé et son procédé de fabrication
WO2022203435A1 (fr) Emballage de substrat et dispositif d'affichage le comprenant
KR20190074101A (ko) 인쇄회로기판 및 그를 이용한 표시장치
WO2018080185A1 (fr) Dispositif à semi-conducteurs ayant une structure multi-puce et module à semi-conducteurs l'utilisant
KR20190081950A (ko) 커버레이와 커버레이를 포함하는 연성회로기판 및 이들을 포함하는 디스플레이 장치
KR20180093533A (ko) 연성 회로 기판

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17841707

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2019503656

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 17841707

Country of ref document: EP

Kind code of ref document: A1