WO2018032928A1 - 移位寄存器单元、驱动方法和栅极驱动电路 - Google Patents

移位寄存器单元、驱动方法和栅极驱动电路 Download PDF

Info

Publication number
WO2018032928A1
WO2018032928A1 PCT/CN2017/093629 CN2017093629W WO2018032928A1 WO 2018032928 A1 WO2018032928 A1 WO 2018032928A1 CN 2017093629 W CN2017093629 W CN 2017093629W WO 2018032928 A1 WO2018032928 A1 WO 2018032928A1
Authority
WO
WIPO (PCT)
Prior art keywords
level
pull
terminal
node
reset
Prior art date
Application number
PCT/CN2017/093629
Other languages
English (en)
French (fr)
Inventor
缪应蒙
高玉杰
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 北京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US15/763,544 priority Critical patent/US20180277052A1/en
Publication of WO2018032928A1 publication Critical patent/WO2018032928A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0283—Arrangement of drivers for different directions of scanning
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking

Definitions

  • the present disclosure relates to the field of display driving technologies, and in particular, to a shift register unit, a driving method, and a gate driving circuit.
  • TV TV
  • different customers have different requirements for scanning the LCD panel. Specifically, some customers want to put the panel forward and scan from the first line; some customers want to flip the panel upside down and scan from the last line.
  • TV products have gradually introduced the concept of two-way scanning.
  • the so-called two-way scanning that is, the liquid crystal display panel can be scanned from the first line or from the first line of the last. In this way, whether the customer puts the liquid crystal display panel up or down to match the whole machine, the erect image can be displayed eventually.
  • the current liquid crystal display panel row drive scanning is driven by COF (Chip On Film), and most of the COF chips of IC (Integrated Circuit) manufacturers provide two-way scanning function.
  • COF Chip On Film
  • IC Integrated Circuit
  • the current TV products are basically designed with GOA (Gate On Array).
  • GOA Gate On Array
  • currently TV GOA drivers have not implemented two-way scanning.
  • a main object of the present disclosure is to provide a shift register unit, a driving method, and a gate driving circuit.
  • an embodiment of the present disclosure provides a shift register unit, including:
  • a gate driving signal output sub-circuit connected to the pull-up node, the gate driving signal output end and the first clock signal end, respectively, and configured to be controlled when a potential of the pull-up node is a first strobe potential
  • the gate drive signal output end is in communication with the first clock signal end;
  • a gate drive signal reset sub-circuit connected to the reset control terminal, the gate drive signal output terminal and the first level terminal, respectively, and configured to control the gate under control of a reset control signal loaded by the reset control terminal
  • the pole drive signal output end is in communication with the first level end
  • the first scan control end is an input end
  • the second scan control end is a reset end
  • the first scan control end is a reset end
  • the second scan The control terminal is an input terminal.
  • the shift register unit of the present disclosure further includes: a first pull-down sub-circuit connected to the pull-up node, the pull-down node, and the first level terminal, respectively, and configured to be Controlling the pull-up node to communicate with the first level terminal when a potential of the pull-down node is at a second level;
  • a pull-down node control sub-circuit connected to the pull-up node, the pull-down node, the second level terminal, and the first level terminal, respectively, and configured to control when the potential of the pull-up node is the second gate potential
  • the pull-down node is in communication with the first level terminal; and when the potential of the pull-up node is at a first level, controlling the pull-down node to communicate with the second level terminal;
  • a second pull-down control sub-circuit which is respectively connected to the pull-down node, the gate driving signal output end and the first level end; and when the potential of the pull-down node is a second level, controlling the gate A drive signal output end is in communication with the first level terminal.
  • the input reset subcircuit includes a first input reset transistor and a second input reset transistor
  • a gate of the first input reset transistor is connected to the first scan control terminal, a first pole of the first input reset transistor is connected to the first scan level terminal, and the first input reset transistor is a second pole is connected to the pull-up node;
  • a gate of the second input reset transistor is connected to the second scan control terminal, a first pole of the second input reset transistor is connected to the pull-up node, and the second A second pole of the input reset transistor is coupled to the second scan level terminal.
  • the gate driving signal output sub-circuit includes:
  • a gate drive signal output transistor having a gate connected to the pull-up node, a first pole connected to the first clock signal end, and a second pole connected to the gate drive signal output end;
  • the storage capacitor has a first end connected to the pull-up node and a second end connected to the gate drive signal output end.
  • the gate drive signal reset sub-circuit includes a gate drive signal reset transistor, wherein
  • the gate of the gate drive signal reset transistor is the reset control terminal
  • the gate of the gate drive signal reset transistor is connected to the second clock signal terminal, the first pole is connected to the gate drive signal output end, and the second pole is connected to the first level terminal;
  • the first clock signal is inverted from the second clock signal input by the second clock signal terminal.
  • the pull-down node control sub-circuit includes:
  • a first pull-down node control transistor having a gate connected to the pull-up node, a first pole connected to the pull-down node, and a second pole connected to the first level terminal;
  • a second pull-down node controls the transistor, the gate and the first pole of which are both connected to the second level terminal;
  • a third pull-down node control transistor having a gate connected to the second pole of the second pull-down node control transistor, a first pole connected to the second level terminal, and a second pole connected to the pull-down node;
  • the fourth pull-down node controls the transistor, the gate of which is connected to the pull-up node, the first pole is connected to the second pole of the second pull-down node control transistor, and the second pole is connected to the first level terminal.
  • the first pull-down sub-circuit includes a first pull-down control transistor having a gate connected to the pull-down node, a first pole connected to the pull-up node, and a second pole First level end connection;
  • the second pull-down control sub-circuit includes a second pull-down control transistor having a gate connected to the pull-down node, a first pole connected to the gate drive signal output terminal, and a second pole connected to the first level terminal .
  • the present disclosure also provides a driving method of a shift register unit for driving the above Shift register unit, the driving method includes:
  • the input reset sub-circuit controls the potential of the pull-up node to be the second level, the first clock signal terminal inputs the first level, the reset control terminal inputs the second level, and the gate drive signal outputs the sub-circuit and the gate.
  • the driving signal reset sub-circuit controls the gate driving signal output end to output the first level
  • the first clock signal terminal inputs a second level
  • the reset control terminal inputs a first level
  • the gate driving signal output sub-circuit controls the bootstrap to pull up the potential of the pull-up node and control the gate driving signal output.
  • the terminal outputs a second level
  • the potential of the input signal is the first level
  • the potential of the reset signal is the second level
  • the input reset sub-circuit controls the potential of the pull-up node to be the first level
  • the first clock signal terminal is input to the first level.
  • the reset control terminal inputs the second level
  • the gate drive signal reset sub-circuit controls the gate drive signal output terminal to output the first level.
  • the step of inputting the reset sub-circuit to control the potential of the pull-up node to the second level comprises: in the input phase, the potential of the input signal accessed by the first scan control terminal is the second level, and second The potential of the reset signal accessed by the scan control terminal is a first level, the first scan level terminal is input with a second level, and the input reset sub-circuit controls the pull-up node to communicate with the first scan level end, thereby controlling the The potential of the pull-up node is a second level;
  • the step of inputting the reset sub-circuit to control the potential of the pull-up node to the first level comprises: in the reset phase, the potential of the input signal is a first level, and the potential of the reset signal is a second Level, the second scan level terminal inputs a first level, and the input reset sub-circuit controls the pull-up node to communicate with the second scan level terminal, thereby controlling the potential of the pull-up node to be a first level.
  • the step of inputting the reset sub-circuit to control the potential of the pull-up node to the second level comprises: in the input phase, the potential of the input signal accessed by the second scan control terminal is the second level, a potential of the reset signal connected to the scan control terminal is a first level, and a second scan level terminal is input to a second level, and the input reset sub-circuit controls the pull-up node to communicate with the second scan level end, thereby controlling The potential of the pull-up node is a second level;
  • the potential of the input signal is a first level
  • the potential of the reset signal is a second level
  • the step of the input reset sub-circuit controlling the potential of the pull-up node to a first level comprises:
  • the potential of the input signal is at the first level
  • the reset signal The potential is a second level
  • the first scan level terminal inputs a first level
  • the input reset sub-circuit controls the pull-up node to communicate with the first scan level terminal, thereby controlling the potential of the pull-up node to be One level.
  • the driving method further includes:
  • the pull-down node control sub-circuit controls the potential of the pull-down node to a first level
  • the pull-down node control sub-circuit controls the potential of the pull-down node to be the second level
  • the first pull-down control sub-circuit controls the potential of the pull-up node to be the first level
  • second The pull-down control sub-circuit controls the gate drive signal output terminal to output a first level
  • the present disclosure also provides a gate driving circuit including a plurality of rows of the above shift register unit, wherein
  • the first scan control terminal of each row of shift register cells is coupled to the gate drive signal output of the adjacent row of shift register cells, except for the last row of shift register cells.
  • the second scan control terminal of each row of shift register cells is connected to the gate drive signal output terminal of the adjacent row of shift register cells.
  • the shift register unit, the driving method, and the gate driving circuit provided by the embodiments of the present disclosure, by connecting the first scan control terminal and the second scan control terminal in the input reset sub-circuit
  • the mode is completely symmetrical, so that in the forward scanning, the first scanning control end is an input end, the second scanning control end is a reset end, and in the reverse scanning, the first scanning control end is a reset end, and the second scanning control is performed.
  • the terminal is an input terminal, so that two-way scanning can be conveniently implemented in the GOA driver of the TV (TV) product.
  • FIG. 1 is a structural diagram of a shift register unit provided by an embodiment of the present disclosure
  • FIG. 2 is a structural diagram of a shift register unit according to another embodiment of the present disclosure.
  • FIG. 3 is a structural diagram of a shift register unit according to still another embodiment of the present disclosure.
  • FIG. 4 is a circuit diagram of a specific embodiment of a shift register unit provided by an embodiment of the present disclosure
  • FIG. 5 is an operational timing diagram of a particular embodiment of the shift register unit of FIG. 4 provided by an embodiment of the present disclosure
  • FIG. 6 is a flowchart of a driving method of a shift register unit according to an embodiment of the present disclosure
  • FIG. 7 is a schematic diagram showing the structure and signal of a gate driving circuit according to an embodiment of the present disclosure during forward scanning;
  • FIG. 8 is a schematic diagram showing the structure and signal of a gate driving circuit in reverse scanning according to an embodiment of the present disclosure
  • FIG. 9 is an operational timing diagram of a gate driving circuit provided by an embodiment of the present disclosure.
  • the shift register unit provided by the embodiment of the present disclosure includes:
  • Input reset sub-circuit 11 connected to first scan control terminal STV_forward, second scan control terminal STV_inversion, first scan level terminal VSD1, second scan level terminal VSD2 and pull-up node PU, respectively, and configured to be Controlling the pull-up node PU and the first scan level terminal VSD1 under control of a first scan control signal accessed by the first scan control terminal STV_forward and a second scan control signal accessed by the second scan control terminal STV_inversion Or the second scan level terminal VSD2 is connected;
  • a gate driving signal output sub-circuit 12 connected to the pull-up node PU, the gate driving signal output terminal OUT and the first clock signal terminal CLK, respectively, and configured to be the first potential of the pull-up node PU Controlling the gate driving signal output terminal OUT to communicate with the first clock signal terminal CLK when the potential is gated;
  • a gate drive signal reset sub-circuit 13 connected to the reset control terminal Ctrl, the gate drive signal output terminal OUT and the first level terminal VD1, respectively, and configured to be under the control of a reset control signal loaded by the reset control terminal Ctrl And controlling the gate driving signal output terminal OUT to communicate with the first level terminal VD1.
  • the first scan control terminal STV_forward is an input terminal
  • the second scan control terminal STV_inversion is a reset terminal
  • the first scan control terminal STV_forward is a reset terminal
  • the second scan control terminal STV_forward is an input terminal.
  • the first gate potential is a potential that enables the gate driving signal output transistor included in the gate driving signal output sub-circuit 12 to be turned on.
  • the connection manner of the first scan control terminal and the second scan control terminal in the input reset sub-circuit in the shift register unit provided by the embodiment of the present disclosure is completely symmetrical.
  • the first scan control end is an input end
  • the second scan control end is an output end
  • the first scan control end is a reset end
  • the second scan control end is an input end.
  • the shift register unit provided by the embodiment of the present disclosure can conveniently implement bidirectional scanning in the GOA drive of a TV (TV) product.
  • the first scan level terminal VSD1 inputs a high level
  • the second scan level terminal VSD2 inputs a low level
  • the first scan level terminal VSD1 inputs a low level
  • the second scan level terminal VSD2 inputs a high level. That is, in the forward scanning and the reverse scanning, the level of the first scanning level terminal VSD1 input and the level of the second scanning level terminal VSD2 are alternately changed to achieve forward and reverse scanning.
  • the first level terminal VD1 can be a low level input terminal, but the first level terminal VD1 can also input other levels according to actual conditions, which is not limited herein.
  • the shift register unit provided by the embodiment of the present disclosure further includes:
  • a first pull-down sub-circuit 14 connected to the pull-up node PU, the pull-down node PD, and the first level terminal VD1, respectively, and configured to control the pull-up when the potential of the pull-down node PD is at a second level
  • the node PU is connected to the first level terminal VD1;
  • a pull-down node control sub-circuit 15 connected to the pull-up node PU, the pull-down node PD, the second level terminal VD2, and the first level terminal VD1, respectively, and configured to be Controlling the pull-down node PD to communicate with the first level terminal VD1 when the potential of the pull-up node PU is the second gate potential; controlling the pull-down node PD when the potential of the pull-up node PU is at the first level The second level terminal VD2 is connected; and,
  • a second pull-down control sub-circuit 16 which is respectively connected to the pull-down node PD, the gate driving signal output terminal OUT and the first level terminal VD1; when the potential of the pull-down node PD is a second level, The gate driving signal output terminal OUT is controlled to communicate with the first level terminal VD1.
  • the second strobe potential is a potential that enables the pull-down node control transistor (ie, M151 in FIG. 4 below) included in the pull-down node control sub-circuit 15 to be turned on, wherein the pull-down node controls the gate of the transistor.
  • the pole is connected to the pull-up node to control the potential of the pull-down node to a first level.
  • the first level terminal VD1 may be a low level input terminal
  • the second level terminal VD2 may be a high level input terminal
  • the first level may be a low level
  • the first The two levels can be high.
  • the level value of the first level and the level value of the second level may be changed according to actual conditions, and are not limited herein.
  • the reset control terminal Ctrl can adopt the second operation in actual operation.
  • the clock signal terminal is in the output cut-off hold phase, not the gate drive signal reset sub-circuit 13 is always operating, but only the second clock signal is at the second level (the second level can be a high level) When the gate drive signal reset sub-circuit 13 resets the gate drive signal.
  • the GOA unit is caused in the GOA unit.
  • An output gate-off signal that should not output an effective gate drive signal outputs an erroneous gate drive signal, causing display failure.
  • the embodiment of the shift register unit shown in FIG. 2 employs a first pull-down control sub-circuit 14, a pull-down node control sub-circuit 15, and a second pull-down control sub-circuit 16.
  • the pull-down node control sub-circuit 15 may control the potential of the pull-down node PD to be a second level when the potential of the pull-up node PU is at a first level (the first level may be a low level) The two levels can be high). Further, the first pull-down control sub-circuit 14 and the second pull-down control sub-circuit 16 can ensure that the potential of the pull-up node PU and the potential of the gate driving signal are at the first level in the output cut-off holding phase (the The first level can be low Flat), which can eliminate display defects.
  • the input reset sub-circuit 11 includes a first input reset transistor MIR1 and a second input reset transistor MIR2.
  • a gate of the first input reset transistor MIR1 is connected to the first scan control terminal STV_forward, a first pole of the first input reset transistor MIR1 is connected to the first scan level terminal VSD1, and the first A second pole of the input reset transistor MIR1 is coupled to the pull-up node PU.
  • a gate of the second input reset transistor MIR2 is connected to the second scan control terminal STV_inversion, a first pole of the second input reset transistor MIR2 is connected to the pull-up node PU, and the second input is reset A second electrode of the transistor MIR2 is connected to the second scan level terminal VSD2.
  • the first scan control terminal STV_forward is an input terminal
  • the second scan control terminal STV_inversion is a reset terminal
  • the first scan control terminal STV_forward is a reset terminal
  • the second scan control terminal STV_inversion is an input terminal.
  • the first input reset transistor MIR1 and the second input reset transistor MIR2 are symmetrically disposed.
  • the gate of MIR1 is connected to the input signal
  • the gate of MIR2 is connected to the reset signal
  • VSD1 is input to the high level
  • VSD2 is input to the low level
  • the gate of MIR1 is connected to the reset signal.
  • the gate of MIR2 is connected to the input signal, VSD1 is input low level, and VSD2 is input high level.
  • the gate driving signal output sub-circuit may include:
  • a gate drive signal output transistor having a gate connected to the pull-up node, a first pole connected to the first clock signal end, and a second pole connected to the gate drive signal output end;
  • the storage capacitor has a first end connected to the pull-up node and a second end connected to the gate drive signal output end.
  • the gate driving signal reset sub-circuit may include a gate driving signal reset transistor.
  • the gate of the gate drive signal reset transistor is the reset control terminal.
  • the gate of the gate driving signal reset transistor is connected to the second clock signal terminal, the first pole is connected to the gate driving signal output end, and the second pole is connected to the first level terminal.
  • the first clock signal is inverted from the second clock signal input by the second clock signal terminal.
  • the pull-down node control sub-circuit may include:
  • a first pull-down node control transistor having a gate connected to the pull-up node, a first pole connected to the pull-down node, and a second pole connected to the first level terminal;
  • a second pull-down node controls the transistor, the gate and the first pole of which are both connected to the second level terminal;
  • a third pull-down node control transistor having a gate connected to the second pole of the second pull-down node control transistor, a first pole connected to the second level terminal, and a second pole connected to the pull-down node;
  • the fourth pull-down node controls the transistor, the gate of which is connected to the pull-up node, the first pole is connected to the second pole of the second pull-down node control transistor, and the second pole is connected to the first level terminal.
  • the first pull-down control sub-circuit may include a first pull-down control transistor having a gate connected to the pull-down node, a first pole connected to the pull-up node, and a second pole and the first Level terminal connection.
  • the second pull-down control sub-circuit includes a second pull-down control transistor having a gate connected to the pull-down node, a first pole connected to the gate drive signal output terminal, and a second pole connected to the first level terminal .
  • the shift register unit provided by the present disclosure is explained below by a specific embodiment.
  • a specific embodiment of the shift register unit includes an input reset sub-circuit 11, a gate drive signal output sub-circuit 12, a gate drive signal reset sub-circuit 13, and a first pull-down control.
  • the input reset sub-circuit 11 includes a first input reset transistor MIR1 and a second input reset transistor MIR2.
  • a gate of the first input reset transistor MIR1 is connected to the first scan control terminal STV_forward, a drain of the first input reset transistor MIR1 is connected to the first scan level terminal VSD1, and the first input is reset.
  • a source of the transistor MIR1 is connected to the pull-up node PU.
  • a gate of the second input reset transistor MIR2 is connected to the second scan control terminal STV_inversion, a drain of the second input reset transistor MIR2 is connected to the pull-up node PU, and the second input reset transistor MIR2 Source and the second sweep The level terminal VSD2 is connected.
  • the gate driving signal output sub-circuit 12 includes:
  • a gate drive signal output transistor M121 having a gate connected to the pull-up node PU, a drain connected to the first clock signal terminal CLK, and a second electrode connected to the gate drive signal output terminal OUT;
  • the storage capacitor Cs has a first end connected to the pull-up node PU and a second end connected to the gate drive signal output terminal OUT.
  • the gate drive signal reset sub-circuit 13 includes a gate drive signal reset transistor M131.
  • the gate of the gate drive signal reset transistor M131 is connected to the second clock signal terminal CLKB, the drain is connected to the gate drive signal output terminal OUT, and the source is connected to the low level terminal VGL.
  • the first clock signal of the CLK input is inverted from the second clock signal of the CLKB input.
  • the pull-down node control sub-circuit 15 may include:
  • the first pull-down node controls the transistor M151, the gate thereof is connected to the pull-up node PU, the drain is connected to the pull-down node PD, and the source is connected to the low-level terminal VGL;
  • the second pull-down node controls the transistor M152, and its gate and drain are both connected to the high level terminal VDD';
  • a third pull-down node control transistor M153 having a gate connected to a source of the second pull-down node control transistor M152, a drain connected to the high-level terminal VDD', and a source connected to the pull-down node PD;
  • the fourth pull-down node controls the transistor M154, the gate of which is connected to the pull-up node PU, the drain is connected to the source of the second pull-down node control transistor M152, and the source is connected to the low-level terminal VGL.
  • the first pull-down control sub-circuit 14 includes a first pull-down control transistor M141 having a gate connected to the pull-down node PD, a drain connected to the pull-up node PU, and a source and the low-level terminal VGL. connection.
  • the second pull-down control sub-circuit 16 includes a second pull-down control transistor M161 having a gate connected to the pull-down node PD, a drain connected to the gate drive signal output terminal, and a source and the low-level terminal VGL. connection.
  • VDD can be connected to 30V and VGL can be connected to -8V.
  • VDD can also be connected to other high levels
  • VGL can also be connected to other low levels.
  • STV_forward accesses the input signal
  • STV_inversion accesses the reset signal
  • VSD1 inputs high level
  • VSD2 inputs low level
  • STV_forward and adjacent upper row shift register The gate drive signal output terminal of the unit is connected, and the STV_inversion is connected to the gate drive signal output terminal of the shift register unit adjacent to the next row.
  • STV_forward accesses the reset signal
  • STV_inversion accesses the input signal
  • VSD1 inputs low level
  • VSD2 inputs high level
  • STV_forward and adjacent next row shift register The gate drive signal output terminal of the unit is connected, and the STV_inversion is connected to the gate drive signal output terminal of the shift register unit of the adjacent upper row.
  • the potential of the input signal accessed by STV_forward is a high level
  • the reset signal accessed by STV_inversion is a low level
  • the CLK input is a low level, CLKB.
  • Input high level MIR1 is turned on
  • MIR2 is turned off
  • the potential of PU is pulled up to high level
  • M121 and M131 are both turned on, so that OUT outputs low level.
  • the potential of the input signal accessed by STV_forward is low
  • the reset signal accessed by STV_inversion is low level
  • CLK is input high level
  • CLKB is input low level.
  • the bootstrap action of Cs further pulls up the potential of the PU, M121 turns on, and M131 turns off, so that OUT outputs a high level.
  • the potential of the input signal accessed by STV_forward is low, and the reset signal accessed by STV_inversion is high (ie, adjacent The gate drive signal output from the shift register unit of the next row is high level), CLK is input low level, CLKB is input high level, MIR1 is turned off, MIR2 is turned on, and the potential of PU is discharged to low level, M121 Disconnected, M131 turns on, so that OUT outputs low.
  • the potential of the input signal accessed by STV_forward is low, and the reset by STV_inversion The signal is low, the CLK interval inputs high level and low level, and the CLKB interval inputs low level and high level.
  • both M151 and M154 are turned off, and M152 is turned on, so that the potential of the gate of M153 is at a high level, thereby controlling the conduction of M153, the potential of the PD It is pulled high to be high, so that both M141 and M161 are turned on, further causing the potential of the PU and the potential of the gate drive signal to be pulled low.
  • CLKB is input to a high level
  • M131 is turned on, and the potential of the gate driving signal is further controlled to be a low level.
  • an embodiment of the present disclosure provides a driving method of a shift register unit for driving the shift register unit described above.
  • the driving method includes:
  • the input reset sub-circuit controls the potential of the pull-up node to be the second level, the first clock signal terminal inputs the first level, the reset control terminal inputs the second level, the gate drive signal output sub-circuit and The gate drive signal reset sub-circuit controls the gate drive signal output end to output a first level;
  • the first clock signal terminal inputs a second level
  • the reset control terminal inputs a first level
  • the gate driving signal output sub-circuit controls the bootstrap to pull up the potential of the pull-up node and control the gate driving The signal output end outputs a second level
  • the potential of the input signal is the first level
  • the potential of the reset signal is the second level
  • the input reset sub-circuit controls the potential of the pull-up node to be the first level
  • the first clock signal end is input to the first level.
  • Level the reset control terminal inputs a second level
  • the gate drive signal reset sub-circuit controls the gate drive signal output terminal to output the first level.
  • the structure of the input reset sub-circuit for input and reset is symmetrical with each other during forward scanning and reverse scanning, thereby making the present disclosure
  • Example of the drive of the shift register unit The method can conveniently realize two-way scanning in the GOA driver of TV (TV) products.
  • the step of inputting the reset sub-circuit to control the potential of the pull-up node to the second level comprises: in the input phase, the potential of the input signal accessed by the first scan control terminal is the second level, and second The potential of the reset signal accessed by the scan control terminal is a first level, the first scan level terminal is input with a second level, and the input reset sub-circuit controls the pull-up node to communicate with the first scan level end, thereby controlling the The potential of the pull-up node is a second level;
  • the step of inputting the reset sub-circuit to control the potential of the pull-up node to the first level comprises: in the reset phase, the potential of the input signal is a first level, and the potential of the reset signal is a second Level, the second scan level terminal inputs a first level, and the input reset sub-circuit controls the pull-up node to communicate with the second scan level terminal, thereby controlling the potential of the pull-up node to be a first level.
  • the step of inputting the reset sub-circuit to control the potential of the pull-up node to the second level comprises: in the input phase, the potential of the input signal accessed by the second scan control terminal is the second level, a potential of the reset signal connected to the scan control terminal is a first level, and a second scan level terminal is input to a second level, and the input reset sub-circuit controls the pull-up node to communicate with the second scan level end, thereby controlling The potential of the pull-up node is a second level;
  • the potential of the input signal is a first level
  • the potential of the reset signal is a second level
  • the step of the input reset sub-circuit controlling the potential of the pull-up node to a first level comprises:
  • the potential of the input signal is the first level
  • the potential of the reset signal is the second level
  • the first scan level terminal is input to the first level
  • the input reset sub-circuit controls the pull-up node and the first scan
  • the level terminals are connected to control the potential of the pull-up node to a first level.
  • the driving method of the shift register unit further includes: after the resetting phase:
  • An output cut-off holding phase in which the reset control terminal inputs a second level every other clock cycle, and the gate drive signal reset sub-circuit controls the gate drive signal output terminal to output the first level .
  • the driving method further includes:
  • the pull-down node control sub-circuit controls the power of the pull-down node Bit is the first level
  • the pull-down node control sub-circuit controls the potential of the pull-down node to be the second level
  • the first pull-down control sub-circuit controls the potential of the pull-up node to be the first level
  • second The pull-down control sub-circuit controls the gate drive signal output terminal to output a first level
  • Embodiments of the present disclosure provide a gate driving circuit including a plurality of rows of the above shift register unit, wherein a first scan control end of each row of shift register units is in addition to the first row of shift register units
  • the gate drive signal output terminal of the adjacent row shift register unit is connected, except for the last row shift register unit, the second scan control terminal of each row of the shift register unit is adjacent to the gate of the adjacent next row shift register unit.
  • the pole drive signal output is connected.
  • the row connection manner of each row of GOA units is: the gate driving signal outputted by the current row GOA unit is used as an input signal of the next row of GOA units, and the gate of the current row of GOA units is output.
  • the drive signal acts as a reset signal for the GOA unit of the previous row.
  • the gate driving circuit provided by the embodiment of the present disclosure requires STV_forward and STV_inversion to be symmetric, and the row bonding mode requires the gate driving circuit to be symmetrical.
  • the STV_forward input frame of the first row of GOA units starts scanning the signal.
  • the STV_inversion of the last line of GOA units inputs an end pulse (ie, a frame end reset signal), thereby resetting the last line of GOA units.
  • the STV_inversion input frame of the last line of the GOA unit starts scanning the signal.
  • the STV_inversion of the first row of GOA units inputs an end pulse (i.e., a frame end reset signal), thereby resetting the first row of GOA units.
  • the GOA requires a row of Dummy signals at the beginning and the end.
  • the gate drive signal output from the gate drive signal output of the first row of shift register cells is only used to provide an input signal to the second row of shift register cells, and is not used to drive the corresponding gate lines.
  • the gate drive signal outputted from the gate drive signal output of the last row of shift register cells is only used to provide an input signal to the adjacent row of shift register cells, and is not used to drive the corresponding gate lines.
  • the first scan control terminal STV_forward of the first row shift register unit G1 inputs the frame start scan signal STV_start, VSD1 is connected to the high level, and VSD2 is connected to the low level.
  • the STV_inversion input frame end reset signal of the last row of shift register cells (not shown in FIG. 7).
  • the STV_forward of the second row shift register unit G2 is connected to the OUT of the first row shift register unit G1, and the STV_inversion of the second row shift register unit G2 is connected to the OUT of the third row shift register unit G3.
  • the STV_forward of the third row shift register unit G3 is connected to the OUT of the second row shift register unit G2.
  • the output of G1 is the dummy signal Dummy1.
  • the output of G2 is the first gate driving scan signal OUT1.
  • the output of G3 is the second gate driving scan signal OUT2.
  • the STV_inversion of the last row shift register unit GN+1 is input to STV_start, VSD1 is input to a low level, and VSD2 is input to a high level.
  • the STV_forward access frame of the first row shift register unit ends the reset signal.
  • the STV_forward of the last row shift register unit G1 is connected to the OUT of the penultimate row shift register unit GN.
  • the STV_forward of the penultimate row shift register unit GN is connected to the OUT of the third-order shift register unit GN-1, the STV_inversion of the second-to-last row shift register unit GN and the OUT of the last row shift register unit GN+1. connection.
  • the GN+1 output is a dummy signal Dummy1.
  • the GN outputs the last row of the gate drive signal OUT_LAST.
  • the GN-1 outputs the penultimate row gate drive signal OUT_SECOND LAST.
  • N is an integer greater than 2.
  • VSD1 and VSD2 are alternately changed to achieve forward and reverse scan control.
  • the frame start scan signal STV_start and the frame end reset signal STV_end may also be interchanged in the forward scan and the reverse scan.

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Shift Register Type Memory (AREA)

Abstract

一种移位寄存器单元、驱动方法和栅极驱动电路。该移位寄存器单元包括：输入复位子电路（11），其分别与第一扫描控制端（STV_forward）、第二扫描控制端（STV_inversion）、第一扫描电平端（VSD1）、第二扫描电平端（VSD2）和上拉节点（PU）连接，并且配置成在由第一扫描控制端（STV_forward）接入的第一扫描控制信号和由第二扫描控制端（STV_inversion）接入的第二扫描控制信号的控制下，控制该上拉节点（PU）与第一扫描电平端（VSD1）或第二扫描电平端（VSD2）连通；栅极驱动信号输出子电路（12）；以及，栅极驱动信号复位子电路（13）。

Description

移位寄存器单元、驱动方法和栅极驱动电路
相关申请
本申请要求享有2016年8月17日提交的中国专利申请No.201610681864.3的优先权，其全部公开内容通过引用并入本文。
技术领域
本公开涉及显示驱动技术领域，尤其涉及一种移位寄存器单元、驱动方法和栅极驱动电路。
背景技术
随着TV(电视)产品的客户数目的不断增加，不同的客户对液晶面板的扫描方式需求不同。具体地，有的客户希望把面板正放，从第一行扫描；有的客户希望把面板倒放，从倒数第一行扫描。为了匹配客户机构设计，满足客户需求，TV产品也渐渐引入了双向扫描的概念。所谓双向扫描，即液晶显示面板可以从第一行扫描，也可以从倒数第一行扫描。这样，不论客户将液晶显示面板正放还是倒放以匹配整机，最终都能显示正立的图像。
现有的液晶显示面板行驱动扫描均为COF(Chip On Film，覆晶薄膜)驱动，并且IC(集成电路)厂家的COF芯片大多都提供双向扫描功能。现在的TV产品为了实现低成本，Gate(栅极)驱动基本都采用GOA(Gate On Array，阵列基板行驱动)设计。然而，目前TV GOA驱动还没有实现双向扫描。
发明内容
本公开的主要目的在于提供一种移位寄存器单元、驱动方法和栅极驱动电路。
为了达到上述目的，本公开的实施例提供了一种移位寄存器单元，包括：
输入复位子电路，其分别与第一扫描控制端、第二扫描控制端、第一扫描电平端、第二扫描电平端和上拉节点连接，并且配置成在由所述第一扫描控制端接入的第一扫描控制信号和由所述第二扫描控制 端接入的第二扫描控制信号的控制下，控制所述上拉节点与第一扫描电平端或所述第二扫描电平端连通；
栅极驱动信号输出子电路，其分别与所述上拉节点、栅极驱动信号输出端和第一时钟信号端连接，并且配置成当所述上拉节点的电位为第一选通电位时控制所述栅极驱动信号输出端与所述第一时钟信号端连通；以及，
栅极驱动信号复位子电路，其分别与复位控制端、所述栅极驱动信号输出端和第一电平端连接，并且配置成在复位控制端加载的复位控制信号的控制下，控制所述栅极驱动信号输出端与所述第一电平端连通；
在正向扫描时，所述第一扫描控制端为输入端，所述第二扫描控制端为复位端；在反向扫描时，所述第一扫描控制端为复位端，所述第二扫描控制端为输入端。
在示例性实施例中，本公开所述的移位寄存器单元还包括：第一下拉子电路，其分别与所述上拉节点、下拉节点和第一电平端连接，并且配置成当所述下拉节点的电位为第二电平时控制所述上拉节点与所述第一电平端连通；
下拉节点控制子电路，其分别与所述上拉节点、所述下拉节点、第二电平端和第一电平端连接，并且配置成当所述上拉节点的电位为第二选通电位时控制所述下拉节点与所述第一电平端连通；当所述上拉节点的电位为第一电平时控制所述下拉节点与所述第二电平端连通；以及，
第二下拉控制子电路，其分别与所述下拉节点、所述栅极驱动信号输出端和所述第一电平端连接；当所述下拉节点的电位为第二电平时，控制所述栅极驱动信号输出端与所述第一电平端连通。
在示例性实施例中，所述输入复位子电路包括第一输入复位晶体管和第二输入复位晶体管；
所述第一输入复位晶体管的栅极与所述第一扫描控制端连接，所述第一输入复位晶体管的第一极与所述第一扫描电平端连接，并且所述第一输入复位晶体管的第二极与所述上拉节点连接；
所述第二输入复位晶体管的栅极与所述第二扫描控制端连接，所述第二输入复位晶体管的第一极与所述上拉节点连接，并且所述第二 输入复位晶体管的第二极与所述第二扫描电平端连接。
在示例性实施例中，栅极驱动信号输出子电路包括：
栅极驱动信号输出晶体管，其栅极与所述上拉节点连接，第一极与所述第一时钟信号端连接，第二极与所述栅极驱动信号输出端连接；以及，
存储电容器，其第一端与所述上拉节点连接，第二端与所述栅极驱动信号输出端连接。
在示例性实施例中，所述栅极驱动信号复位子电路包括栅极驱动信号复位晶体管，其中
所述栅极驱动信号复位晶体管的栅极为所述复位控制端；
所述栅极驱动信号复位晶体管的栅极与第二时钟信号端连接，第一极与所述栅极驱动信号输出端连接，第二极与第一电平端连接；并且
所述第一时钟信号与所述第二时钟信号端输入的第二时钟信号反相。
在示例性实施例中，所述下拉节点控制子电路包括：
第一下拉节点控制晶体管，其栅极与所述上拉节点连接，第一极与所述下拉节点连接，第二极与第一电平端连接；
第二下拉节点控制晶体管，其栅极和第一极都与第二电平端连接；
第三下拉节点控制晶体管，其栅极与所述第二下拉节点控制晶体管的第二极连接，第一极与所述第二电平端连接，第二极与所述下拉节点连接；以及，
第四下拉节点控制晶体管，其栅极与所述上拉节点连接，第一极与所述第二下拉节点控制晶体管的第二极连接，第二极与所述第一电平端连接。
在示例性实施例中，所述第一下拉子电路包括第一下拉控制晶体管，其栅极与所述下拉节点连接，第一极与所述上拉节点连接，第二极与所述第一电平端连接；
所述第二下拉控制子电路包括第二下拉控制晶体管，其栅极与所述下拉节点连接，第一极与所述栅极驱动信号输出端连接，第二极与所述第一电平端连接。
本公开还提供了一种移位寄存器单元的驱动方法，用于驱动上述 的移位寄存器单元，所述驱动方法包括：
在输入阶段，输入复位子电路控制上拉节点的电位为第二电平，第一时钟信号端输入第一电平，复位控制端输入第二电平，栅极驱动信号输出子电路和栅极驱动信号复位子电路都控制栅极驱动信号输出端输出第一电平；
在输出阶段，第一时钟信号端输入第二电平，复位控制端输入第一电平，栅极驱动信号输出子电路控制自举拉升所述上拉节点的电位并控制栅极驱动信号输出端输出第二电平；
在复位阶段，输入信号的电位为第一电平，复位信号的电位为第二电平，输入复位子电路控制上拉节点的电位为第一电平，第一时钟信号端输入第一电平，复位控制端输入第二电平，栅极驱动信号复位子电路控制栅极驱动信号输出端输出第一电平。
在示例性实施例中，在正向扫描时，
所述在输入阶段，输入复位子电路控制上拉节点的电位为第二电平的步骤包括：在输入阶段，由第一扫描控制端接入的输入信号的电位为第二电平，第二扫描控制端接入的复位信号的电位为第一电平，第一扫描电平端输入第二电平，输入复位子电路控制所述上拉节点与所述第一扫描电平端连通，从而控制所述上拉节点的电位为第二电平；
所述在复位阶段，输入复位子电路控制上拉节点的电位为第一电平的步骤包括：在复位阶段，所述输入信号的电位为第一电平，所述复位信号的电位为第二电平，第二扫描电平端输入第一电平，输入复位子电路控制所述上拉节点与所述第二扫描电平端连通，从而控制所述上拉节点的电位为第一电平。
在示例性实施例中，在反向扫描时，
所述在输入阶段，输入复位子电路控制上拉节点的电位为第二电平的步骤包括：在输入阶段，由第二扫描控制端接入的输入信号的电位为第二电平，由第一扫描控制端接入的复位信号的电位为第一电平，第二扫描电平端输入第二电平，输入复位子电路控制所述上拉节点与所述第二扫描电平端连通，从而控制所述上拉节点的电位为第二电平；
所述在复位阶段，所述输入信号的电位为第一电平，所述复位信号的电位为第二电平，输入复位子电路控制上拉节点的电位为第一电平的步骤包括：在复位阶段，输入信号的电位为第一电平，复位信号 的电位为第二电平，第一扫描电平端输入第一电平，输入复位子电路控制所述上拉节点与所述第一扫描电平端连通，从而控制所述上拉节点的电位为第一电平。
在示例性实施例中，在所述复位阶段之后还包括：
输出截止保持阶段，在所述输出截止保持阶段中，每隔一时钟周期，所述复位控制端输入第二电平，并且当所述复位控制端输出第二电平时，栅极驱动信号复位子电路控制栅极驱动信号输出端输出第一电平。
在示例性实施例中，当所述移位寄存器单元包括第一下拉控制子电路、下拉节点控制子电路和第二下拉控制子电路时，所述驱动方法还包括：
在输入阶段和输出阶段，下拉节点控制子电路控制下拉节点的电位为第一电平；
在复位阶段和输出截止保持阶段，下拉节点控制子电路控制所述下拉节点的电位为第二电平，第一下拉控制子电路控制所述上拉节点的电位为第一电平，第二下拉控制子电路控制所述栅极驱动信号输出端输出第一电平。
本公开还提供了一种栅极驱动电路，包括多行上述的移位寄存器单元，其中
除了第一行移位寄存器单元之外，每一行移位寄存器单元的第一扫描控制端都与相邻上一行移位寄存器单元的栅极驱动信号输出端连接，除了最后一行移位寄存器单元之外，每一行移位寄存器单元的第二扫描控制端都与相邻下一行移位寄存器单元的栅极驱动信号输出端连接。
与现有技术相比，在本公开的实施例所提供的移位寄存器单元、驱动方法和栅极驱动电路中，通过使得输入复位子电路中的第一扫描控制端和第二扫描控制端的连接方式完全对称，使得在正向扫描时，所述第一扫描控制端为输入端，第二扫描控制端为复位端，在反向扫描时，第一扫描控制端为复位端，第二扫描控制端为输入端，从而可以在TV(电视)产品的GOA驱动中方便的实现双向扫描。
附图说明
图1是本公开的实施例所提供的移位寄存器单元的结构图；
图2是本公开的另一实施例所提供的移位寄存器单元的结构图；
图3是本公开的又一实施例所提供的移位寄存器单元的结构图；
图4是本公开的实施例所提供的移位寄存器单元的具体实施例的电路图；
图5是本公开的实施例所提供的移位寄存器单元的如图4所示的具体实施例的工作时序图；
图6是本公开实施例所提供的移位寄存器单元的驱动方法的流程图；
图7是本公开实施例所提供的栅极驱动电路在正向扫描时的结构和信号示意图；
图8是本公开实施例所提供的栅极驱动电路在反向扫描时的结构和信号示意图；以及
图9是本公开实施例所提供的栅极驱动电路的工作时序图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本公开的一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
如图1所示，本公开实施例所提供的移位寄存器单元包括：
输入复位子电路11，其分别与第一扫描控制端STV_forward、第二扫描控制端STV_inversion、第一扫描电平端VSD1、第二扫描电平端VSD2和上拉节点PU连接，并且配置成在由所述第一扫描控制端STV_forward接入的第一扫描控制信号和由所述第二扫描控制端STV_inversion接入的第二扫描控制信号的控制下，控制所述上拉节点PU与第一扫描电平端VSD1或所述第二扫描电平端VSD2连通；
栅极驱动信号输出子电路12，其分别与所述上拉节点PU、栅极驱动信号输出端OUT和第一时钟信号端CLK连接，并且配置成当所述上拉节点PU的电位为第一选通电位时控制所述栅极驱动信号输出端OUT与所述第一时钟信号端CLK连通；以及，
栅极驱动信号复位子电路13，其分别与复位控制端Ctrl、所述栅极驱动信号输出端OUT和第一电平端VD1连接，并且配置成在复位控制端Ctrl加载的复位控制信号的控制下，控制所述栅极驱动信号输出端OUT与所述第一电平端VD1连通。
在正向扫描时，所述第一扫描控制端STV_forward为输入端，所述第二扫描控制端STV_inversion为复位端；在反向扫描时，所述第一扫描控制端STV_forward为复位端，所述第二扫描控制端STV_forward为输入端。
在实际操作时，所述第一选通电位为能够使得所述栅极驱动信号输出子电路12包括的栅极驱动信号输出晶体管导通的电位。
本公开实施例所提供的移位寄存器单元中的输入复位子电路中的第一扫描控制端和第二扫描控制端的连接方式完全对称。在正向扫描时，所述第一扫描控制端为输入端，第二扫描控制端为输出端；在反向扫描时，第一扫描控制端为复位端，第二扫描控制端为输入端。作为结果，本公开实施例所提供的移位寄存器单元可以在TV(电视)产品的GOA驱动中方便的实现双向扫描。
在实际操作时，在正向扫描时，所述第一扫描电平端VSD1输入高电平，所述第二扫描电平端VSD2输入低电平；在反向扫描时，所述第一扫描电平端VSD1输入低电平，所述第二扫描电平端VSD2输入高电平。即，在正向扫描和反向扫描时，第一扫描电平端VSD1输入的电平、第二扫描电平端VSD2输入的电平高低交替变化以实现正反向扫描。
在实际操作时，所述第一电平端VD1可以为低电平输入端，但是根据实际情况，该第一电平端VD1也可以输入其他电平，在此并不作限定。
在示例性实施例中，如图2所示，本公开实施例所提供的移位寄存器单元还包括：
第一下拉子电路14，其分别与所述上拉节点PU、下拉节点PD和第一电平端VD1连接，并且配置成当所述下拉节点PD的电位为第二电平时控制所述上拉节点PU与所述第一电平端VD1连通；
下拉节点控制子电路15，其分别与所述上拉节点PU、所述下拉节点PD、第二电平端VD2和第一电平端VD1连接，并且配置成当所述 上拉节点PU的电位为第二选通电位时控制所述下拉节点PD与所述第一电平端VD1连通；当所述上拉节点PU的电位为第一电平时控制所述下拉节点PD与所述第二电平端VD2连通；以及，
第二下拉控制子电路16，其分别与所述下拉节点PD、所述栅极驱动信号输出端OUT和所述第一电平端VD1连接；当所述下拉节点PD的电位为第二电平时，控制所述栅极驱动信号输出端OUT与所述第一电平端VD1连通。
在实际操作时，所述第二选通电位为能够使得下拉节点控制子电路15所包括的下拉节点控制晶体管(也即下图4中的M151)导通的电位，其中下拉节点控制晶体管的栅极与上拉节点连接以控制下拉节点的电位为第一电平。
在实际操作时，所述第一电平端VD1可以为低电平输入端，所述第二电平端VD2可以为高电平输入端，所述第一电平可以为低电平，所述第二电平可以为高电平。但是，所述第一电平的电平值、所述第二电平的电平值可以根据实际情况而改变，在此并不作限定。
在具体实施时，在图1的实施例工作时，在复位阶段之后直至下一帧的该GOA单元的输入阶段之间的输出截止保持阶段，由于复位控制端Ctrl在实际操作时可以采用第二时钟信号端，则在该输出截止保持阶段，并非栅极驱动信号复位子电路13总是在工作，而只是在第二时钟信号为第二电平(所述第二电平可以为高电平)时，所述栅极驱动信号复位子电路13才对栅极驱动信号进行复位。如果此时栅极驱动信号输出子电路12包括的栅极驱动信号输出晶体管和/或栅极驱动信号复位子电路13包括的栅极驱动信号复位晶体管产生漏电等不良现象，则导致在该GOA单元不应输出有效的栅极驱动信号的输出截止保持阶段输出了错误的栅极驱动信号，进而引起显示不良现象。为了解决上述问题，如图2所示的移位寄存器单元的实施例采用了第一下拉控制子电路14、下拉节点控制子电路15和第二下拉控制子电路16。所述下拉节点控制子电路15可以当上拉节点PU的电位为第一电平(所述第一电平可以为低电平)时控制下拉节点PD的电位为第二电平(所述第二电平可以为高电平)。进一步地，通过第一下拉控制子电路14、第二下拉控制子电路16可以保证在输出截止保持阶段中，上拉节点PU的电位、栅极驱动信号的电位为第一电平(所述第一电平可以为低电 平)，从而可以消除显示不良现象。
具体的，如图3所示，所述输入复位子电路11包括第一输入复位晶体管MIR1和第二输入复位晶体管MIR2。
所述第一输入复位晶体管MIR1的栅极与所述第一扫描控制端STV_forward连接，所述第一输入复位晶体管MIR1的第一极与所述第一扫描电平端VSD1连接，并且所述第一输入复位晶体管MIR1的第二极与所述上拉节点PU连接。
所述第二输入复位晶体管MIR2的栅极与所述第二扫描控制端STV_inversion连接，所述第二输入复位晶体管MIR2的第一极与所述上拉节点PU连接，并且所述第二输入复位晶体管MIR2的第二极与所述第二扫描电平端VSD2连接。
在正向扫描时，所述第一扫描控制端STV_forward为输入端，所述第二扫描控制端STV_inversion为复位端；在反向扫描时，所述第一扫描控制端STV_forward为复位端，所述第二扫描控制端STV_inversion为输入端。
由图3可知，在本公开实施例所提供的移位寄存器单元中，所述第一输入复位晶体管MIR1和所述第二输入复位晶体管MIR2是对称设置的。在正向扫描时，MIR1的栅极接入输入信号，MIR2的栅极接入复位信号，VSD1输入高电平，VSD2输入低电平；在反向扫描时，MIR1的栅极接入复位信号，MIR2的栅极接入输入信号，VSD1输入低电平，VSD2输入高电平。
具体的，栅极驱动信号输出子电路可以包括：
栅极驱动信号输出晶体管，其栅极与所述上拉节点连接，第一极与所述第一时钟信号端连接，第二极与所述栅极驱动信号输出端连接；以及，
存储电容器，其第一端与所述上拉节点连接，第二端与所述栅极驱动信号输出端连接。
具体的，所述栅极驱动信号复位子电路可以包括栅极驱动信号复位晶体管。
所述栅极驱动信号复位晶体管的栅极为所述复位控制端。
所述栅极驱动信号复位晶体管的栅极与第二时钟信号端连接，第一极与所述栅极驱动信号输出端连接，第二极与第一电平端连接。
所述第一时钟信号与所述第二时钟信号端输入的第二时钟信号反相。
具体的，所述下拉节点控制子电路可以包括：
第一下拉节点控制晶体管，其栅极与所述上拉节点连接，第一极与所述下拉节点连接，第二极与第一电平端连接；
第二下拉节点控制晶体管，其栅极和第一极都与第二电平端连接；
第三下拉节点控制晶体管，其栅极与所述第二下拉节点控制晶体管的第二极连接，第一极与所述第二电平端连接，第二极与所述下拉节点连接；以及，
第四下拉节点控制晶体管，其栅极与所述上拉节点连接，第一极与所述第二下拉节点控制晶体管的第二极连接，第二极与所述第一电平端连接。
具体的，所述第一下拉控制子电路可以包括第一下拉控制晶体管，其栅极与所述下拉节点连接，第一极与所述上拉节点连接，第二极与所述第一电平端连接。
所述第二下拉控制子电路包括第二下拉控制晶体管，其栅极与所述下拉节点连接，第一极与所述栅极驱动信号输出端连接，第二极与所述第一电平端连接。
下面通过一具体实施例来说明本公开所提供的移位寄存器单元。
如图4所示，本公开所提供的移位寄存器单元的一具体实施例包括输入复位子电路11、栅极驱动信号输出子电路12、栅极驱动信号复位子电路13、第一下拉控制子电路14、下拉节点控制子电路15和第二下拉控制子电路16。
所述输入复位子电路11包括第一输入复位晶体管MIR1和第二输入复位晶体管MIR2。
所述第一输入复位晶体管MIR1的栅极与所述第一扫描控制端STV_forward连接，所述第一输入复位晶体管MIR1的漏极与所述第一扫描电平端VSD1连接，所述第一输入复位晶体管MIR1的源极与所述上拉节点PU连接。
所述第二输入复位晶体管MIR2的栅极与所述第二扫描控制端STV_inversion连接，所述第二输入复位晶体管MIR2的漏极与所述上拉节点PU连接，所述第二输入复位晶体管MIR2的源极与所述第二扫 描电平端VSD2连接。
所述栅极驱动信号输出子电路12包括：
栅极驱动信号输出晶体管M121，其栅极与所述上拉节点PU连接，漏极与所述第一时钟信号端CLK连接，第二极与所述栅极驱动信号输出端OUT连接；以及，
存储电容器Cs，其第一端与所述上拉节点PU连接，第二端与所述栅极驱动信号输出端OUT连接。
所述栅极驱动信号复位子电路13包括栅极驱动信号复位晶体管M131。
所述栅极驱动信号复位晶体管M131的栅极与第二时钟信号端CLKB连接，漏极与所述栅极驱动信号输出端OUT连接，源极与低电平端VGL连接。
CLK输入的第一时钟信号与CLKB输入的第二时钟信号反相。
所述下拉节点控制子电路15可以包括：
第一下拉节点控制晶体管M151，其栅极与所述上拉节点PU连接，漏极与所述下拉节点PD连接，源极与低电平端VGL连接；
第二下拉节点控制晶体管M152，其栅极和漏极都与高电平端VDD′连接；
第三下拉节点控制晶体管M153，其栅极与所述第二下拉节点控制晶体管M152的源极连接，漏极与所述高电平端VDD′连接，源极与所述下拉节点PD连接；以及，
第四下拉节点控制晶体管M154，其栅极与所述上拉节点PU连接，漏极与所述第二下拉节点控制晶体管M152的源极连接，源极与所述低电平端VGL连接。
所述第一下拉控制子电路14包括第一下拉控制晶体管M141，其栅极与所述下拉节点PD连接，漏极与所述上拉节点PU连接，源极与所述低电平端VGL连接。
所述第二下拉控制子电路16包括第二下拉控制晶体管M161，其栅极与所述下拉节点PD连接，漏极与所述栅极驱动信号输出端连接，源极与所述低电平端VGL连接。
在图4中，所有的晶体管都为n型晶体管。
在图4所示的实施例中，VDD可以接入30V，VGL可以接入-8V。 但是，在实际操作时，VDD也可以接入其他的高电平，VGL也可以接入其他的低电平。
如图4所示的移位寄存器单元在正向扫描时，STV_forward接入输入信号，STV_inversion接入复位信号，VSD1输入高电平，VSD2输入低电平，STV_forward与相邻上一行的移位寄存器单元的栅极驱动信号输出端连接，STV_inversion与相邻下一行的移位寄存器单元的栅极驱动信号输出端连接。
如图4所示的移位寄存器单元在反向扫描时，STV_forward接入复位信号，STV_inversion接入输入信号，VSD1输入低电平，VSD2输入高电平，STV_forward与相邻下一行的移位寄存器单元的栅极驱动信号输出端连接，STV_inversion与相邻上一行的移位寄存器单元的栅极驱动信号输出端连接。
下面以如图4所示的移位寄存器单元的具体实施例在正向扫描时的工作过程为例进行说明。
如图5所示，在每一帧时间内的输入阶段T1，由STV_forward接入的输入信号的电位为高电平，由STV_inversion接入的复位信号为低电平，CLK输入低电平，CLKB输入高电平，MIR1导通，MIR2断开，将PU的电位上拉为高电平，M121和M131都导通，以使得OUT输出低电平。
在所述输入阶段T1，由于PU的电位为高电平，因此M151和M154都导通，从而PD的电位被拉低为低电平，M153的栅极电位也被拉低为低电平，M153断开，并且M141和M161断开。
在每一帧时间内的输出阶段T2，由STV_forward接入的输入信号的电位为低电平，由STV_inversion接入的复位信号为低电平，CLK输入高电平，CLKB输入低电平，由Cs的自举作用将PU的电位进一步自举拉升，M121导通，M131断开，以使得OUT输出高电平。
在所述输出阶段T2，由于PU的电位继续为高电平，因此M151和M154继续都导通，从而使得PD的电位继续被拉低为低电平，M153的栅极电位也继续被拉低为低电平，M153断开，M141和M161继续断开。
在每一帧时间内的复位阶段T3，由STV_forward接入的输入信号的电位为低电平，由STV_inversion接入的复位信号为高电平(即相邻 下一行的移位寄存器单元输出的栅极驱动信号为高电平)，CLK输入低电平，CLKB输入高电平，MIR1断开，MIR2导通，将PU的电位放电至低电平，M121断开，M131导通，以使得OUT输出低电平。
在所述复位阶段T3，由于PU的电位为低电平，所以M151和M154都断开，M152导通，以使得M153的栅极的电位为高电平，从而控制M153导通，PD的电位被拉高为高电平，从而M141和M161都导通，进一步使得PU的电位和栅极驱动信号的电位都被拉低。
在输出截止阶段T4(即每一帧时间内的复位阶段T3结束后直至下一帧时间的输入阶段开始之前)，由STV_forward接入的输入信号的电位为低电平，由STV_inversion接入的复位信号为低电平，CLK间隔输入高电平和低电平，CLKB间隔输入低电平和高电平。由于在输出截止阶段T4，PU的电位一直为低电平，所以M151和M154都断开，M152导通，以使得M153的栅极的电位为高电平，从而控制M153导通，PD的电位被拉高为高电平，从而M141和M161都导通，进一步使得PU的电位和栅极驱动信号的电位都被拉低。并且，当CLKB输入高电平时，M131导通，进一步控制栅极驱动信号的电位为低电平。
如图6所示，本公开实施例提供了一种移位寄存器单元的驱动方法，用于驱动上述的移位寄存器单元。所述驱动方法包括：
S1：在输入阶段，输入复位子电路控制上拉节点的电位为第二电平，第一时钟信号端输入第一电平，复位控制端输入第二电平，栅极驱动信号输出子电路和栅极驱动信号复位子电路都控制栅极驱动信号输出端输出第一电平；
S2：在输出阶段，第一时钟信号端输入第二电平，复位控制端输入第一电平，栅极驱动信号输出子电路控制自举拉升所述上拉节点的电位并控制栅极驱动信号输出端输出第二电平；
S3：在复位阶段，输入信号的电位为第一电平，复位信号的电位为第二电平，输入复位子电路控制上拉节点的电位为第一电平，第一时钟信号端输入第一电平，复位控制端输入第二电平，栅极驱动信号复位子电路控制栅极驱动信号输出端输出第一电平。
本公开实施例所提供的移位寄存器单元的驱动方法在工作时，用于输入和复位的输入复位子电路的结构在正向扫描时和反向扫描时是相互对称的，从而使得本公开实施例所提供的移位寄存器单元的驱动 方法可以在TV(电视)产品的GOA驱动中方便的实现双向扫描。
具体的，在正向扫描时，
所述在输入阶段，输入复位子电路控制上拉节点的电位为第二电平的步骤包括：在输入阶段，由第一扫描控制端接入的输入信号的电位为第二电平，第二扫描控制端接入的复位信号的电位为第一电平，第一扫描电平端输入第二电平，输入复位子电路控制所述上拉节点与所述第一扫描电平端连通，从而控制所述上拉节点的电位为第二电平；
所述在复位阶段，输入复位子电路控制上拉节点的电位为第一电平的步骤包括：在复位阶段，所述输入信号的电位为第一电平，所述复位信号的电位为第二电平，第二扫描电平端输入第一电平，输入复位子电路控制所述上拉节点与所述第二扫描电平端连通，从而控制所述上拉节点的电位为第一电平。
具体的，在反向扫描时，
所述在输入阶段，输入复位子电路控制上拉节点的电位为第二电平的步骤包括：在输入阶段，由第二扫描控制端接入的输入信号的电位为第二电平，由第一扫描控制端接入的复位信号的电位为第一电平，第二扫描电平端输入第二电平，输入复位子电路控制所述上拉节点与所述第二扫描电平端连通，从而控制所述上拉节点的电位为第二电平；
所述在复位阶段，所述输入信号的电位为第一电平，所述复位信号的电位为第二电平，输入复位子电路控制上拉节点的电位为第一电平的步骤包括：在复位阶段，输入信号的电位为第一电平，复位信号的电位为第二电平，第一扫描电平端输入第一电平，输入复位子电路控制所述上拉节点与所述第一扫描电平端连通，从而控制所述上拉节点的电位为第一电平。
具体的，所述移位寄存器单元的驱动方法在所述复位阶段之后还包括：
输出截止保持阶段，在所述输出截止保持阶段中，每隔一时钟周期，所述复位控制端输入第二电平，栅极驱动信号复位子电路控制栅极驱动信号输出端输出第一电平。
具体的，当所述移位寄存器单元包括第一下拉控制子电路、下拉节点控制子电路和第二下拉控制子电路时，所述驱动方法还包括：
在输入阶段和输出阶段，下拉节点控制子电路控制下拉节点的电 位为第一电平；
在复位阶段和输出截止保持阶段，下拉节点控制子电路控制所述下拉节点的电位为第二电平，第一下拉控制子电路控制所述上拉节点的电位为第一电平，第二下拉控制子电路控制所述栅极驱动信号输出端输出第一电平。
本公开实施例提供了一种栅极驱动电路，包括多行上述的移位寄存器单元，其中除了第一行移位寄存器单元之外，每一行移位寄存器单元的第一扫描控制端都与相邻上一行移位寄存器单元的栅极驱动信号输出端连接，除了最后一行移位寄存器单元之外，每一行移位寄存器单元的第二扫描控制端都与相邻下一行移位寄存器单元的栅极驱动信号输出端连接。
在本公开实施例所提供的栅极驱动电路中，各行GOA单元的行联方式为：当前行GOA单元输出的栅极驱动信号作为下一行GOA单元的输入信号，当前行GOA单元输出的栅极驱动信号作为上一行GOA单元的复位信号。为使栅极驱动电路支持双向扫描，本公开实施例所提供的栅极驱动电路要求STV_forward和STV_inversion接法对称，行联方式要求栅极驱动电路首尾对称。
在正向扫描时，第一行GOA单元的STV_forward输入帧开始扫描信号。当最后一行GOA单元扫描结束时，最后一行GOA单元的STV_inversion输入一个结束脉冲(即帧结束复位信号)，从而对最后一行GOA单元进行复位。在反向扫描时，最后一行GOA单元的STV_inversion输入帧开始扫描信号。当第一行GOA单元扫描结束时，第一行GOA单元的STV_inversion输入一个结束脉冲(即帧结束复位信号)，从而对第一行GOA单元进行复位。
在实际操作时，在本公开实施例所提供的栅极驱动电路工作时，GOA首尾均需要一行Dummy信号。
在正向扫描时，第一行移位寄存器单元的栅极驱动信号输出端输出的栅极驱动信号仅用于为第二行移位寄存器单元提供输入信号，而不用于驱动相应的栅线。
在反向扫描时，最后一行移位寄存器单元的栅极驱动信号输出端输出的栅极驱动信号仅用于为相邻上一行移位寄存器单元提供输入信号，而不用于驱动相应的栅线。
如图7所示，在正向扫描时，第一行移位寄存器单元G1的第一扫描控制端STV_forward输入帧开始扫描信号STV_start，VSD1接入高电平，VSD2接入低电平。最后一行移位寄存器单元(图7中未示出)的STV_inversion输入帧结束复位信号。
第二行移位寄存器单元G2的STV_forward与第一行移位寄存器单元G1的OUT连接，第二行移位寄存器单元G2的STV_inversion与第三行移位寄存器单元G3的OUT连接。
第三行移位寄存器单元G3的STV_forward与第二行移位寄存器单元G2的OUT连接。
G1输出的为dummy(伪)信号Dummy1。G2输出的为第一栅极驱动扫描信号OUT1。G3输出的为第二栅极驱动扫描信号OUT2。
如图8所示，在反向扫描时，最后一行移位寄存器单元GN+1的STV_inversion输入STV_start，VSD1输入低电平，VSD2输入高电平。第一行移位寄存器单元(图8中未示出)的STV_forward接入帧结束复位信号。最后一行移位寄存器单元G1的STV_forward与倒数第二行移位寄存器单元GN的OUT连接。
倒数第二行移位寄存器单元GN的STV_forward与倒数第三行移位寄存器单元GN-1的OUT连接，倒数第二行移位寄存器单元GN的STV_inversion与最后一行移位寄存器单元GN+1的OUT连接。
GN+1输出的为dummy(伪)信号Dummy1。GN输出的为最后一行栅极驱动信号OUT_LAST。GN-1输出的为倒数第二行栅极驱动信号OUT_SECOND LAST。N为大于2的整数。
如图9所示，VSD1、VSD2高低交替变换以实现正反向扫描控制。
在正向扫描和反向扫描时，帧开始扫描信号STV_start和帧结束复位信号STV_end也可以互换。
以上所述是本公开的示例性实施方式。应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (13)

  1. 一种移位寄存器单元，包括：
    输入复位子电路，其分别与第一扫描控制端、第二扫描控制端、第一扫描电平端、第二扫描电平端和上拉节点连接，并且配置成在由所述第一扫描控制端接入的第一扫描控制信号和由所述第二扫描控制端接入的第二扫描控制信号的控制下，控制所述上拉节点与第一扫描电平端或所述第二扫描电平端连通；
    栅极驱动信号输出子电路，其分别与所述上拉节点、栅极驱动信号输出端和第一时钟信号端连接，并且配置成当所述上拉节点的电位为第一选通电位时控制所述栅极驱动信号输出端与所述第一时钟信号端连通；以及，
    栅极驱动信号复位子电路，其分别与复位控制端、所述栅极驱动信号输出端和第一电平端连接，并且配置成在复位控制端加载的复位控制信号的控制下，控制所述栅极驱动信号输出端与所述第一电平端连通，
    其中，在正向扫描时，所述第一扫描控制端为输入端，所述第二扫描控制端为复位端；在反向扫描时，所述第一扫描控制端为复位端，所述第二扫描控制端为输入端。
  2. 如权利要求1所述的移位寄存器单元，其中，
    所述输入复位子电路包括第一输入复位晶体管和第二输入复位晶体管；
    所述第一输入复位晶体管的栅极与所述第一扫描控制端连接，所述第一输入复位晶体管的第一极与所述第一扫描电平端连接，并且所述第一输入复位晶体管的第二极与所述上拉节点连接；
    所述第二输入复位晶体管的栅极与所述第二扫描控制端连接，所述第二输入复位晶体管的第一极与所述上拉节点连接，并且所述第二输入复位晶体管的第二极与所述第二扫描电平端连接。
  3. 如权利要求1或2所述的移位寄存器单元，还包括：
    第一下拉子电路，其分别与所述上拉节点、下拉节点和第一电平端连接，并且配置成当所述下拉节点的电位为第二电平时控制所述上拉节点与所述第一电平端连通；
    下拉节点控制子电路，其分别与所述上拉节点、所述下拉节点、第二电平端和第一电平端连接，并且配置成当所述上拉节点的电位为第二选通电位时控制所述下拉节点与所述第一电平端连通；当所述上拉节点的电位为第一电平时控制所述下拉节点与所述第二电平端连通；以及，
    第二下拉控制子电路，其分别与所述下拉节点、所述栅极驱动信号输出端和所述第一电平端连接；当所述下拉节点的电位为第二电平时控制所述栅极驱动信号输出端与所述第一电平端连通。
  4. 如权利要求1或2所述的移位寄存器单元，其中，栅极驱动信号输出子电路包括：
    栅极驱动信号输出晶体管，其栅极与所述上拉节点连接，第一极与所述第一时钟信号端连接，第二极与所述栅极驱动信号输出端连接；以及，
    存储电容器，其第一端与所述上拉节点连接，第二端与所述栅极驱动信号输出端连接。
  5. 如权利要求4所述的移位寄存器单元，其中，所述栅极驱动信号复位子电路包括栅极驱动信号复位晶体管，其中，
    所述栅极驱动信号复位晶体管的栅极为所述复位控制端；
    所述栅极驱动信号复位晶体管的栅极与第二时钟信号端连接，第一极与所述栅极驱动信号输出端连接，第二极与第一电平端连接；并且
    所述第一时钟信号与所述第二时钟信号端输入的第二时钟信号反相。
  6. 如权利要求2所述的移位寄存器单元，其中，所述下拉节点控制子电路包括：
    第一下拉节点控制晶体管，其栅极与所述上拉节点连接，第一极与所述下拉节点连接，第二极与第一电平端连接；
    第二下拉节点控制晶体管，其栅极和第一极都与第二电平端连接；
    第三下拉节点控制晶体管，其栅极与所述第二下拉节点控制晶体管的第二极连接，第一极与所述第二电平端连接，第二极与所述下拉节点连接；以及，
    第四下拉节点控制晶体管，其栅极与所述上拉节点连接，第一极 与所述第二下拉节点控制晶体管的第二极连接，第二极与所述第一电平端连接。
  7. 如权利要求2所述的移位寄存器单元，其中，所述第一下拉子电路包括第一下拉控制晶体管，其栅极与所述下拉节点连接，第一极与所述上拉节点连接，第二极与所述第一电平端连接；
    所述第二下拉控制子电路包括第二下拉控制晶体管，其栅极与所述下拉节点连接，第一极与所述栅极驱动信号输出端连接，第二极与所述第一电平端连接。
  8. 一种移位寄存器单元的驱动方法，用于驱动如权利要求1至7中任一权利要求所述的移位寄存器单元，其中，所述驱动方法包括：
    在输入阶段，输入复位子电路控制上拉节点的电位为第二电平，第一时钟信号端输入第一电平，复位控制端输入第二电平，栅极驱动信号输出子电路和栅极驱动信号复位子电路都控制栅极驱动信号输出端输出第一电平；
    在输出阶段，第一时钟信号端输入第二电平，复位控制端输入第一电平，栅极驱动信号输出子电路控制自举拉升所述上拉节点的电位并控制栅极驱动信号输出端输出第二电平；
    在复位阶段，输入信号的电位为第一电平，复位信号的电位为第二电平，输入复位子电路控制上拉节点的电位为第一电平，第一时钟信号端输入第一电平，复位控制端输入第二电平，栅极驱动信号复位子电路控制栅极驱动信号输出端输出第一电平。
  9. 如权利要求8所述的移位寄存器单元的驱动方法，其中，在正向扫描时，
    所述在输入阶段，输入复位子电路控制上拉节点的电位为第二电平的步骤包括：在输入阶段，由第一扫描控制端接入的输入信号的电位为第二电平，第二扫描控制端接入的复位信号的电位为第一电平，第一扫描电平端输入第二电平，输入复位子电路控制所述上拉节点与所述第一扫描电平端连通，从而控制所述上拉节点的电位为第二电平；
    所述在复位阶段，输入复位子电路控制上拉节点的电位为第一电平的步骤包括：在复位阶段，所述输入信号的电位为第一电平，所述复位信号的电位为第二电平，第二扫描电平端输入第一电平，输入复位子电路控制所述上拉节点与所述第二扫描电平端连通，从而控制所 述上拉节点的电位为第一电平。
  10. 如权利要求8所述的移位寄存器单元的驱动方法，其中，在反向扫描时，
    所述在输入阶段，输入复位子电路控制上拉节点的电位为第二电平的步骤包括：在输入阶段，由第二扫描控制端接入的输入信号的电位为第二电平，由第一扫描控制端接入的复位信号的电位为第一电平，第二扫描电平端输入第二电平，输入复位子电路控制所述上拉节点与所述第二扫描电平端连通，从而控制所述上拉节点的电位为第二电平；
    所述在复位阶段，所述输入信号的电位为第一电平，所述复位信号的电位为第二电平，输入复位子电路控制上拉节点的电位为第一电平的步骤包括：在复位阶段，输入信号的电位为第一电平，复位信号的电位为第二电平，第一扫描电平端输入第一电平，输入复位子电路控制所述上拉节点与所述第一扫描电平端连通，从而控制所述上拉节点的电位为第一电平。
  11. 如权利要求8至10中任一权利要求所述的移位寄存器单元的驱动方法，其中，在所述复位阶段之后还包括：
    输出截止保持阶段，在所述输出截止保持阶段中，每隔一时钟周期，所述复位控制端输入第二电平，并且当所述复位控制端输出第二电平时，栅极驱动信号复位子电路控制栅极驱动信号输出端输出第一电平。
  12. 如权利要求11所述的移位寄存器单元的驱动方法，其中，当所述移位寄存器单元包括第一下拉控制子电路、下拉节点控制子电路和第二下拉控制子电路时，所述驱动方法还包括：
    在输入阶段和输出阶段，下拉节点控制子电路控制下拉节点的电位为第一电平；
    在复位阶段和输出截止保持阶段，下拉节点控制子电路控制所述下拉节点的电位为第二电平，第一下拉控制子电路控制所述上拉节点的电位为第一电平，第二下拉控制子电路控制所述栅极驱动信号输出端输出第一电平。
  13. 一种栅极驱动电路，包括多行如权利要求1至6中任一权利要求所述的移位寄存器单元，其中
    除了第一行移位寄存器单元之外，每一行移位寄存器单元的第一 扫描控制端都与相邻上一行移位寄存器单元的栅极驱动信号输出端连接，除了最后一行移位寄存器单元之外，每一行移位寄存器单元的第二扫描控制端都与相邻下一行移位寄存器单元的栅极驱动信号输出端连接。
PCT/CN2017/093629 2016-08-17 2017-07-20 移位寄存器单元、驱动方法和栅极驱动电路 WO2018032928A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/763,544 US20180277052A1 (en) 2016-08-17 2017-07-20 Shift register unit, driving method and gate driving circuit

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201610681864.3A CN106098011A (zh) 2016-08-17 2016-08-17 双向扫描goa单元、驱动方法和goa电路
CN201610681864.3 2016-08-17

Publications (1)

Publication Number Publication Date
WO2018032928A1 true WO2018032928A1 (zh) 2018-02-22

Family

ID=58069742

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/093629 WO2018032928A1 (zh) 2016-08-17 2017-07-20 移位寄存器单元、驱动方法和栅极驱动电路

Country Status (3)

Country Link
US (1) US20180277052A1 (zh)
CN (1) CN106098011A (zh)
WO (1) WO2018032928A1 (zh)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106098011A (zh) * 2016-08-17 2016-11-09 京东方科技集团股份有限公司 双向扫描goa单元、驱动方法和goa电路
US20210280108A1 (en) * 2017-05-15 2021-09-09 Shenzhen Royole Technologies Co., Ltd. Goa circuit, array substrate, and display device
CN107331418B (zh) 2017-07-31 2020-06-19 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动电路及显示装置
CN107507591B (zh) 2017-09-04 2019-03-15 深圳市华星光电半导体显示技术有限公司 一种扫描驱动电路以及液晶显示器
CN108172165B (zh) 2018-01-03 2019-12-10 京东方科技集团股份有限公司 移位寄存器电路、驱动方法和显示装置
TWI682379B (zh) * 2018-12-25 2020-01-11 友達光電股份有限公司 閘極驅動電路及其顯示面板
CN109616068A (zh) * 2019-01-04 2019-04-12 深圳市华星光电半导体显示技术有限公司 Goa扫描电路和液晶显示装置
CN111312177B (zh) 2020-03-03 2021-04-02 武汉华星光电技术有限公司 Goa驱动电路、显示面板及显示装置
US11875727B2 (en) 2020-12-22 2024-01-16 Boe Technology Group Co., Ltd. Shift register, gate driving circuit, display panel, and driving method thereof

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101477836A (zh) * 2007-12-31 2009-07-08 乐金显示有限公司 移位寄存器
CN101937718A (zh) * 2010-08-04 2011-01-05 友达光电股份有限公司 双向移位寄存器
CN102629444A (zh) * 2011-08-22 2012-08-08 北京京东方光电科技有限公司 栅极集成驱动电路、移位寄存器及显示屏
JP5078533B2 (ja) * 2007-10-10 2012-11-21 三菱電機株式会社 ゲート線駆動回路
CN202905121U (zh) * 2012-09-13 2013-04-24 北京京东方光电科技有限公司 移位寄存器单元电路、移位寄存器、阵列基板及显示设备
CN103915052A (zh) * 2013-01-05 2014-07-09 北京京东方光电科技有限公司 一种栅极驱动电路、方法及显示装置
CN104078017A (zh) * 2014-06-23 2014-10-01 合肥京东方光电科技有限公司 移位寄存器单元、栅极驱动电路及显示装置
CN105575306A (zh) * 2014-10-09 2016-05-11 群创光电股份有限公司 显示器面板与双向移位寄存器电路
CN106098011A (zh) * 2016-08-17 2016-11-09 京东方科技集团股份有限公司 双向扫描goa单元、驱动方法和goa电路

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101107703B1 (ko) * 2005-05-26 2012-01-25 엘지디스플레이 주식회사 쉬프트 레지스터
JP5090008B2 (ja) * 2007-02-07 2012-12-05 三菱電機株式会社 半導体装置およびシフトレジスタ回路
JP4912186B2 (ja) * 2007-03-05 2012-04-11 三菱電機株式会社 シフトレジスタ回路およびそれを備える画像表示装置
TWI416530B (zh) * 2009-03-25 2013-11-21 Wintek Corp 移位暫存器
CN102012591B (zh) * 2009-09-04 2012-05-30 北京京东方光电科技有限公司 移位寄存器单元及液晶显示器栅极驱动装置
CN101783124B (zh) * 2010-02-08 2013-05-08 北京大学深圳研究生院 栅极驱动电路单元、栅极驱动电路及显示装置
CN104392704A (zh) * 2014-12-15 2015-03-04 合肥京东方光电科技有限公司 移位寄存器单元及其驱动方法、移位寄存器和显示装置
CN104464605B (zh) * 2014-12-30 2017-12-08 上海中航光电子有限公司 一种移位寄存器及其驱动方法、栅极驱动电路及显示屏
CN104732910A (zh) * 2015-04-09 2015-06-24 京东方科技集团股份有限公司 一种阵列基板、其驱动方法及电子纸
CN104867439B (zh) * 2015-06-24 2017-04-05 合肥京东方光电科技有限公司 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置
CN105096902B (zh) * 2015-09-28 2018-09-11 京东方科技集团股份有限公司 一种移位寄存器、其驱动方法、栅极驱动电路及显示装置
CN105609136A (zh) * 2016-01-04 2016-05-25 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路和显示装置
CN106847160B (zh) * 2017-04-01 2019-10-15 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路和显示装置

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5078533B2 (ja) * 2007-10-10 2012-11-21 三菱電機株式会社 ゲート線駆動回路
CN101477836A (zh) * 2007-12-31 2009-07-08 乐金显示有限公司 移位寄存器
CN101937718A (zh) * 2010-08-04 2011-01-05 友达光电股份有限公司 双向移位寄存器
CN102629444A (zh) * 2011-08-22 2012-08-08 北京京东方光电科技有限公司 栅极集成驱动电路、移位寄存器及显示屏
CN202905121U (zh) * 2012-09-13 2013-04-24 北京京东方光电科技有限公司 移位寄存器单元电路、移位寄存器、阵列基板及显示设备
CN103915052A (zh) * 2013-01-05 2014-07-09 北京京东方光电科技有限公司 一种栅极驱动电路、方法及显示装置
CN104078017A (zh) * 2014-06-23 2014-10-01 合肥京东方光电科技有限公司 移位寄存器单元、栅极驱动电路及显示装置
CN105575306A (zh) * 2014-10-09 2016-05-11 群创光电股份有限公司 显示器面板与双向移位寄存器电路
CN106098011A (zh) * 2016-08-17 2016-11-09 京东方科技集团股份有限公司 双向扫描goa单元、驱动方法和goa电路

Also Published As

Publication number Publication date
CN106098011A (zh) 2016-11-09
US20180277052A1 (en) 2018-09-27

Similar Documents

Publication Publication Date Title
WO2018032928A1 (zh) 移位寄存器单元、驱动方法和栅极驱动电路
US10446104B2 (en) Shift register unit, gate line driving device, and driving method
US10146362B2 (en) Shift register unit, a shift register, a driving method, and an array substrate
US9799287B2 (en) Shift register unit and driving method thereof, gate driving circuit and display device
TWI619104B (zh) Shift register unit and driving method thereof, gate driving circuit and display device
KR101143531B1 (ko) 액정 디스플레이 게이트 구동 장치
US9805658B2 (en) Shift register, gate driving circuit and display device
US10235958B2 (en) Gate driving circuits and liquid crystal devices
US10204582B2 (en) Shift register and driving method thereof, gate electrode driving circuit, and display device
US10629151B2 (en) Shift register unit, gate driving circuit, display and gate driving method
US9443462B2 (en) Gate driving circuit, gate line driving method and display device
US9495931B2 (en) Shift register, display device and method for driving display device
US10049636B2 (en) Gate drive circuit and liquid crystal display device
US10121442B2 (en) Driving methods and driving devices of gate driver on array (GOA) circuit
US10566071B2 (en) Shift register unit, method for driving shift register unit, gate driving circuit and display device
WO2016070543A1 (zh) 移位寄存器单元、栅极驱动电路及显示装置
KR101579842B1 (ko) 게이트 라인 구동 방법, 이를 수행하기 위한 게이트 구동회로 및 이를 구비한 표시 장치
US20180047354A9 (en) Shift register unit and driving method thereof, gate driving circuit and display device
WO2020010852A1 (zh) 移位寄存器单元、驱动方法、栅极驱动电路和显示装置
JP2021518030A (ja) シフトレジスタユニット、ゲート駆動回路、表示装置及び駆動方法
WO2016145780A1 (zh) 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置
US9563396B2 (en) Gate driving circuit and display device
US11200825B2 (en) Shift register unit with reduced transistor count and method for driving the same, gate driving circuit and method for driving the same, and display apparatus
US20190130807A1 (en) Display panel and display device
WO2013131425A1 (zh) 移位寄存器、栅极驱动器及显示装置

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 15763544

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17840903

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205 DATED 19/06/2019)

122 Ep: pct application non-entry in european phase

Ref document number: 17840903

Country of ref document: EP

Kind code of ref document: A1