WO2018028298A1 - 阵列基板的制作方法、阵列基板及显示装置 - Google Patents

阵列基板的制作方法、阵列基板及显示装置 Download PDF

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WO2018028298A1
WO2018028298A1 PCT/CN2017/088200 CN2017088200W WO2018028298A1 WO 2018028298 A1 WO2018028298 A1 WO 2018028298A1 CN 2017088200 W CN2017088200 W CN 2017088200W WO 2018028298 A1 WO2018028298 A1 WO 2018028298A1
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layer
film layer
region
opaque
array substrate
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PCT/CN2017/088200
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English (en)
French (fr)
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张斌
刘建宏
詹裕程
孙雪菲
曹占锋
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京东方科技集团股份有限公司
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Priority to US15/736,972 priority Critical patent/US10224252B2/en
Publication of WO2018028298A1 publication Critical patent/WO2018028298A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1462—Coatings
    • H01L27/14623—Optical shielding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method for fabricating an array substrate, an array substrate, and a display device.
  • LTPS Low Temperature Poly-Silicon, low temperature polysilicon
  • a light shielding layer at the bottom.
  • Metal is commonly used as a light shielding layer in TFTs of LTPS or other top gate structures.
  • an unnecessary etching process is usually performed by etching, and a buffer layer of a certain thickness is deposited on the light shielding layer, and then amorphous silicon is deposited and converted into polysilicon. Since the deposited buffer layer generates protrusions at the position of the light shielding layer, a step is formed.
  • the thickness of the buffer layer is usually increased.
  • an excessively thick buffer layer causes a stress mismatch between the buffer layer and the glass substrate, causing various problems such as glass bending or film peeling.
  • the method for fabricating an array substrate, the array substrate and the display device provided by the embodiments of the present invention are intended to alleviate or eliminate one or more of the problems described above.
  • Embodiments of the present invention provide a method for fabricating an array substrate, including:
  • a thin film transistor is formed on the treated film layer.
  • the method for fabricating the array substrate provided by the embodiment of the present invention is to form a thin film transistor Forming a whole layer of opaque film layer and processing the film layer to form a light-transmitting region and an opaque region, so that when another film layer is deposited on a whole layer of the film layer, The other film layers are caused to have a step difference, and thus various other undesirable problems due to the step difference are also avoided.
  • the film layer is treated such that the film layer does not have a light-receiving area corresponding to the channel region of the active layer, including:
  • the film layer on the film layer to be formed into the light-transmitting region is oxidized by using an oxidizing agent, so that the film layer to be formed into the light-transmitting region is transparent;
  • the remaining photoresist is stripped to obtain a light transmissive region and an opaque region on the film layer.
  • the oxidizing agent is hydrogen peroxide.
  • an orthographic projection of a channel region of the active layer on the substrate substrate is within an orthographic projection of the opaque region on the substrate substrate.
  • the material of the entire layer of the opaque film layer is ruthenium.
  • the step of forming a thin film transistor on the processed film layer includes:
  • a pattern of the active layer is formed on the polysilicon layer by one patterning process.
  • An embodiment of the present invention provides an array substrate, including: a substrate, a whole layer of a film layer and a thin film transistor disposed on the substrate;
  • the film layer is provided with a light transmitting region and an opaque region, and the opaque region corresponds to a channel region of the active layer.
  • an orthographic projection of a channel region of the active layer on the substrate substrate is within an orthographic projection of the opaque region on the substrate substrate.
  • the film layer of the light-transmitting region is an oxidized film layer.
  • the material of the opaque region is ruthenium
  • the material of the light-transmitting region is an oxide of ruthenium
  • the thin film transistor is a top gate type structure.
  • the array substrate further includes: a buffer layer disposed between the film layer and the thin film transistor, and the buffer layer has a thickness of 1000 angstroms to 5000 angstroms.
  • Embodiments of the present invention provide a display device including the above array substrate.
  • FIG. 1 is a flowchart of a method for fabricating an array substrate according to an embodiment of the present invention
  • FIGS. 2a, 2b, and 2c are schematic structural views of each step in the method for fabricating an array substrate according to an embodiment of the present invention.
  • FIG. 2 is a schematic structural diagram of a circuit for forming an active layer according to an embodiment of the present invention
  • FIG. 3 is a flow chart of a method for processing a whole layer of an opaque film layer according to an embodiment of the present invention
  • 4a, 4b, and 4c are schematic structural views of each step in a method for processing a whole layer of an opaque film layer according to an embodiment of the present invention
  • FIG. 5 is a flow chart of the overall steps of the method for fabricating the above array substrate according to an embodiment of the present invention.
  • the thickness of the film and the shape of the regions in the drawings do not reflect the true ratio of the array substrate, and the purpose is only to illustrate the contents of the present invention.
  • a method for fabricating an array substrate according to an embodiment of the present invention is based on the method for fabricating an array substrate, and the process for fabricating the light shielding layer is redesigned and optimized, and the structure of the known light shielding layer is changed. The specific production method will be described in detail below.
  • Embodiments of the present invention provide a method of fabricating an array substrate. As shown in Figure 1, the method includes the following steps:
  • Step 101 forming a whole layer of an opaque film layer on the substrate
  • Step 102 processing the film layer to form a light-transmitting region and an opaque region on the film layer, wherein the opaque region corresponds to the channel region of the active layer;
  • Step 103 forming a thin film transistor on the processed film layer.
  • the common LTPS process or other light-shielding layer produced in the top gate structure will form a step difference when depositing the buffer layer, thereby affecting the crystallization property of the polysilicon.
  • increasing the thickness of the buffer layer to reduce the step difference not only the problem of poor crystallization can be effectively improved, but also various other undesirable problems can be caused.
  • an entire opaque film layer is formed before the buffer layer is formed, and the film layer is processed to form a transparent region and is impervious. Light area.
  • This allows a buffer layer to be deposited over a full layer of film without causing a step difference in the buffer layer.
  • the crystallization performance of polycrystalline silicon is not affected during the subsequent excimer laser annealing process.
  • the method of the present invention can effectively eliminate the influence of the step on the crystallization property without increasing the thickness of the buffer layer, thereby avoiding other various disadvantages caused by the buffer layer being too thick.
  • a whole layer of the opaque film layer 20 is first formed on the substrate 10.
  • the opaque film layer 20 is used to form a light shielding film layer of the array substrate. Since a whole layer of the opaque film layer 20 is formed, it must be able to be oxidized into a transparent film layer, and thus the material of the entire opaque film layer may be a base metal.
  • the entire layer of the film layer 20 formed is processed to form a light-transmitting region a and an opaque region b on the film layer.
  • the opaque region b corresponds to the channel region of the active layer. That is, the two regions a of the film layer 20 in the drawing are changed to the light-transmitting regions, and the opaque regions b corresponding to the channel regions of the active layer are not processed, and are still in the form of opaque.
  • step 103 needs to be performed to form a thin film transistor on the processed film layer.
  • the thin film transistor is located above the film layer 20.
  • the gate 50 of the thin film transistor is located above the active layer 40 and is of a top gate type.
  • the method when a thin film transistor is formed on the processed film layer, it is also required to deposit a buffer layer 30 on the processed film layer and form a thin film transistor on the buffer layer 30.
  • the method when performing step 103, the method further includes the steps of: forming an active layer on the buffer layer, specifically The production of the active layer can be achieved in the following manner.
  • an entire layer of amorphous silicon is deposited on the treated film layer 20. Since the buffer layer needs to be deposited on the processed film layer 20 to form an active layer, an entire layer of amorphous silicon layer is actually deposited on the buffer layer 30, and the amorphous silicon layer is subjected to excimer laser annealing treatment. The amorphous silicon layer is crystallized into a polysilicon layer. Then, a pattern of the active layer is formed on the polysilicon layer by a patterning process, as shown in FIG. 2d, which is a schematic structural diagram of the pattern of the active layer provided by the embodiment of the present invention.
  • FIG. 3 is a flow chart of a method for processing a whole layer of an opaque film layer according to an embodiment of the present invention. Specifically, in the method for fabricating the above array substrate provided by the embodiment of the present invention, for example, the processing of the film layer in step 102 can be specifically implemented by the following steps:
  • Step 1021 depositing a photoresist on the film layer
  • Step 1022 using a mask to expose and develop the photoresist, and retaining a photoresist corresponding to the opaque region to be formed;
  • Step 1023 using the retained photoresist as a mask, using an oxidizing agent to oxidize the film layer on the film layer to be formed into the light-transmitting region, so that the film layer to be formed into the light-transmitting region is transparent;
  • step 1024 the remaining photoresist is stripped to obtain a film layer including a light transmitting region and an opaque region.
  • an entire layer of photoresist 60 is deposited on an entire opaque film layer 20.
  • the entire photoresist 40 is exposed, developed, and the like by using a mask, and the photoresist 60 corresponding to the opaque region is left.
  • the remaining photoresist 60 corresponds to the channel region of the active layer.
  • the photoresist 60 retained in the above FIG. 4b is used as a mask, and the opaque portion of the film layer 20 is oxidized by using an oxidizing agent, so that the portion of the film layer to be formed into the light-transmitting region is formed. (ie two areas a) become light transmissive.
  • the above oxidizing agent is selected from hydrogen peroxide.
  • the remaining photoresist 60 is stripped, as shown in Figure 2b, to obtain an entire layer of the film after oxidation treatment.
  • the region b corresponding to the channel region of the active layer is opaque, while the other regions a are transparent.
  • the orthographic projection of the channel region c of the active layer on the substrate substrate 10 is located within the orthographic projection of the opaque region b on the substrate substrate 10.
  • the area of the opaque region b on the film layer is larger than the area of the channel region c of the active layer, that is, the opaque region b can at least completely cover the channel region c of the active layer. This prevents the polysilicon material on the active layer from being exposed to light, resulting in a problem of performance degradation due to light transmission from the edge region of the opaque region.
  • a flowchart of the overall steps of the method for fabricating the array substrate provided by the embodiment of the present invention includes the following steps:
  • Step 501 forming a whole layer of an opaque film layer on the substrate
  • Step 502 depositing a photoresist on the film layer
  • Step 503 using a mask to expose and develop the photoresist, and retaining a photoresist corresponding to the opaque region to be formed;
  • Step 504 using the remaining photoresist as a mask, using an oxidizing agent to oxidize the film layer on the film layer to be formed into a light-transmitting region, so that the film layer to be formed into the light-transmitting region is transparent;
  • Step 505 peeling off the remaining photoresist to obtain a light-transmitting region and an opaque region on the film layer;
  • Step 506 depositing an amorphous silicon layer on the processed film layer, performing an excimer laser annealing treatment on the amorphous silicon layer, and crystallizing the amorphous silicon layer into a polysilicon layer;
  • Step 507 forming a pattern of the active layer on the polysilicon layer by one patterning process
  • Step 508 forming a gate, a source and a drain of the thin film transistor on the active layer.
  • the array substrate includes a base substrate 10, an entire film layer 20 and a thin film transistor disposed on the base substrate 10.
  • a light-transmitting region a and an opaque region b are disposed on the film layer, and the opaque region b corresponds to the channel region c of the active layer of the thin film transistor.
  • the array substrate provided by the embodiment of the invention has a light shielding layer as a whole layer structure and a film layer having a light transmitting region and an opaque region. Since the buffer layer is provided on a whole layer of the film layer, there is no problem of step difference. In the subsequent excimer laser annealing process polycrystalline silicon crystallization, the effect of the step difference on the crystallization effect can be effectively reduced. At the same time, since there is no step, the thickness of the buffer layer can also be adjusted as needed. This can appropriately reduce the thickness of the buffer layer to eliminate other adverse effects caused by stress.
  • the array substrate further includes: a buffer layer disposed between the film layer and the thin film transistor, and buffering The thickness of the layer is from 1000 angstroms to 5,000 angstroms.
  • the film layer of the light-transmitting region (ie, region a) is an oxidized film layer.
  • the oxidation treatment can change the opaque film layer into a transparent oxide film layer.
  • the above-mentioned opaque film layer can be made of base metal.
  • the material of the opaque region is ruthenium
  • the material of the light-transmitting region is an oxide of ruthenium.
  • base metals can be oxidized by hydrogen peroxide to a colorless, transparent cerium oxide (antimony trioxide or antimony pentoxide).
  • the array substrate provided by the embodiment of the present invention has a whole layer structure and a film layer having a transparent region and an opaque region, and actually, It is also possible to not provide a complete layer of the film layer as needed.
  • a film layer capable of covering at least the active layer and having a transmissive region and an opaque region is provided as a light-shielding film layer, as long as the phase difference does not affect the crystallization effect in the subsequent excimer laser annealing process. .
  • a pattern of a film layer formed by using a halftone mask, and a photoresist for oxidizing the film layer can also be formed with a film layer covering at least the active layer without increasing the number of mask layers. And having a light shielding film layer of the transmission region and the opaque region.
  • the above array substrate provided by the embodiment of the present invention is mainly directed to a structure in which a light shielding layer is required.
  • the thin film transistor is a top gate type structure. Since the present invention is mainly directed to improvement of the light shielding layer metal, it is required to be disposed in a thin film transistor having a light shielding layer, such as a thin film transistor of a top gate type structure, or a thin film transistor of low temperature polysilicon or the like.
  • a display device is provided in the embodiment of the present invention, and the display device includes the array substrate provided in the embodiment of the present invention.
  • the display device can be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • the principle of the display device is similar to that of the array substrate of the embodiment of the present invention. Therefore, the implementation of the display device can be referred to the implementation of the array substrate, and the repeated description is omitted.
  • the method for fabricating an array substrate according to an embodiment of the present invention forms a whole layer of an opaque film layer before forming a thin film transistor, and processes the film layer to form a transparent region and is impermeable. Light area. Therefore, depositing a buffer layer on a whole layer of the film layer does not cause a step difference in the buffer layer, and during the subsequent excimer laser annealing process, Will affect the crystallization properties of polysilicon. At the same time, the method of the present invention can effectively eliminate the influence of the step on the crystallization property without increasing the thickness of the buffer layer, thereby avoiding other various disadvantages caused by the buffer layer being too thick.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
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  • Crystallography & Structural Chemistry (AREA)
  • Electromagnetism (AREA)
  • Thin Film Transistor (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

一种阵列基板的制作方法、阵列基板及显示装置。该方法包括：在衬底基板（10）上形成一整层不透光的膜层（20）；对膜层进行处理，使膜层上形成透光区域（a）和不透光区域（b），其中不透光区域与有源层（40）的沟道区域（c）对应；以及在处理后的膜层上形成薄膜晶体管。通过在形成薄膜晶体管之前形成一整层不透光的膜层，使其形成透光区域和不透光区域，因而在一整层的膜层上沉积其它膜层时不会出现段差，因而也避免了由于段差而造成的其它各种不良的问题。

Description

阵列基板的制作方法、阵列基板及显示装置
相关专利申请
本申请主张于2016年8月10日提交的中国专利申请No.201610649679.6的优先权，其全部内容通过引用结合于此。
技术领域
本发明涉及显示器技术领域，尤其涉及一种阵列基板的制作方法、阵列基板及显示装置。
背景技术
目前，LTPS(Low Temperature Poly-Silicon，低温多晶硅)技术成为了中小尺寸显示行业的主流。在LTPS技术中由于多晶硅对背光较为敏感，因而会采用在底部增加遮光层的方式解决这一问题。通常利用金属作为LTPS或其他顶栅结构的TFT中的遮光层。然而在形成遮光层的图形时，通常采用刻蚀工艺将多余的遮光金属刻蚀掉，再在遮光层上沉积一定厚度的缓冲层，然后再沉积非晶硅并将其转换为多晶硅。由于沉积的缓冲层在遮光层的位置处会产生突起，形成段差。这导致在制作有源层时的准分子激光退火工艺过程中，多晶硅结晶性能变差，甚至造成结晶不良的问题。为了减小缓冲层上的段差，通常会增加缓冲层的厚度。但是，过厚的缓冲层会导致缓冲层与玻璃基板的应力不匹配，造成玻璃弯曲或者膜层脱落等各种不良的问题。
发明内容
本发明实施例提供的一种阵列基板的制作方法、阵列基板及显示装置，其旨在减轻或消除前文所述的一个或多个问题。
本发明实施例提供一种阵列基板的制作方法，包括：
在衬底基板上形成一整层不透光的膜层；
对所述膜层进行处理，使所述膜层上形成透光区域和不透光区域，其中所述不透光区域与有源层的沟道区域对应；以及
在处理后的膜层上形成薄膜晶体管。
本发明实施例提供的阵列基板的制作方法，在形成薄膜晶体管之 前形成一整层不透光的膜层，并对该膜层进行处理，使其形成透光区域和不透光区域，因而后续在一整层的膜层上沉积其它膜层时，不会使其它膜层出现段差，进而也避免了由于段差而造成的其它各种不良的问题。
例如，对所述膜层进行处理，使所述膜层上没有与有源层的沟道区域对应的区域透光，包括：
在所述膜层上沉积光刻胶；
使用掩膜板对所述光刻胶曝光显影，保留待形成不透光区域对应的光刻胶；
利用保留的光刻胶作为掩膜，采用氧化剂对所述膜层上待形成透光区域的膜层进行氧化处理，使得所述待形成透光区域的膜层透光；以及
剥离所述保留的光刻胶，得到所述膜层上的透光区域和不透光区域。
例如，所述氧化剂为双氧水。
例如，所述有源层的沟道区域在所述衬底基板上的正投影位于所述不透光区域在所述衬底基板上的正投影内。
例如，所述一整层不透光的膜层的材料为钽。
例如，在处理后的膜层上形成薄膜晶体管的步骤，包括：
在处理后的膜层上沉积非晶硅层，对所述非晶硅层进行准分子激光退火处理，使所述非晶硅层晶化为多晶硅层；以及
通过一次构图工艺在所述多晶硅层上形成有源层的图形。
本发明实施例提供一种阵列基板，包括：衬底基板，设置在所述衬底基板上的一整层的膜层和薄膜晶体管，
其中所述膜层上设置有透光区域和不透光区域，所述不透光区域与有源层的沟道区域对应。
例如，所述有源层的沟道区域在所述衬底基板上的正投影位于所述不透光区域在所述衬底基板上的正投影内。
例如，所述透光区域的膜层为经过氧化处理后的膜层。
例如，所述不透光区域的材料为钽，并且所述透光区域的材料为钽的氧化物。
例如，所述薄膜晶体管为顶栅型结构。
例如，所述阵列基板还包括：设置在所述膜层和所述薄膜晶体管之间的缓冲层，并且所述缓冲层的厚度为1000埃-5000埃。
本发明实施例提供一种显示装置，包括上述阵列基板。
附图说明
图1为本发明实施例提供的阵列基板的制作方法的流程图；
图2a、图2b和图2c分别为本发明实施例提供的阵列基板的制作方法中各步骤执行后的结构示意图；
图2d为本发明实施例提供的制作有源层的图形后的结构示意图；
图3为本发明实施例提供的对一整层不透光的膜层进行处理的方法流程图；
图4a、图4b和图4c分别为本发明实施例提供的对一整层不透光的膜层进行处理的方法中各步骤执行后的结构示意图；以及
图5为本发明实施例提供的上述阵列基板的制作方法的整体步骤流程图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本发明一部分实施例，并不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
附图中各层薄膜厚度和区域形状大小不反映阵列基板的真实比例，目的只是示意说明本发明内容。
本发明实施例提供的一种阵列基板的制作方法，在已知阵列基板的制作方法的基础上，对制作遮光层的工艺进行了重新设计优化，并且改变了已知遮光层的结构。下面对其具体制作方法进行详细的说明。
本发明实施例提供了一种阵列基板的制作方法。如图1所示，该方法包括以下步骤：
步骤101，在衬底基板上形成一整层不透光的膜层；
步骤102，对膜层进行处理，使膜层上形成透光区域和不透光区域，其中不透光区域与有源层的沟道区域对应；以及
步骤103，在处理后的膜层上形成薄膜晶体管。
在本发明实施例提供的上述阵列基板的制作方法中，由于在衬底基板上形成了一整层的遮光膜层，可以避免在遮光膜层上制作其它膜层时出现段差，减少段差带来的不良影响。
目前，常见的LTPS工艺或其他顶栅结构中制作的遮光层，会在沉积缓冲层时形成段差，进而影响多晶硅的结晶性能。通过增加缓冲层的厚度减小段差的方式，不仅无法有效的改善结晶不良的问题，而且甚至会造成其它各种不良的问题。
基于此，本发明实施例提供的阵列基板的制作方法，在形成缓冲层之前，形成了一整层不透光的膜层，并对该膜层进行处理，使其形成透光区域和不透光区域。这使得在一整层的膜层上沉积缓冲层，不会使缓冲层出现段差。此外，在后续准分子激光退火工艺过程中，也不会影响多晶硅的结晶性能。同时，本发明的方法无需增加缓冲层的厚度就可以有效消除段差对结晶性能的影响，因而也避免了由于缓冲层过厚而造成的其它各种不良的问题。
在具体实施时，在实现上述步骤101时，如图2a所示，先在衬底基板10上形成一整层不透光的膜层20。该不透光的膜层20用于制作阵列基板的遮光膜层。由于形成的一整层不透光的膜层20，必须能够被氧化为透明的膜层，因而该一整层不透光的膜层的材料可以为钽金属。
在具体实施时，在实现上述步骤102时，如图2b所示，对上述形成的一整层的膜层20进行处理，使该膜层上形成透光区域a和不透光区域b。不透光区域b与有源层的沟道区域对应。也就是说，使图中膜层20的两个区域a变为透光区域，而与有源层的沟道区域对应的不透光区域b不进行处理，仍为不透光的形式。
在具体实施时，在实现上述步骤101和102之后，需要执行步骤103，即在处理后的膜层上形成薄膜晶体管。如图2c所示，薄膜晶体管位于膜层20上方。薄膜晶体管的栅极50位于有源层40上方，为顶栅型。
在具体实施时，在处理后的膜层上形成薄膜晶体管时，还需要在处理后的膜层上沉积缓冲层30，并在缓冲层30上形成薄膜晶体管。例如，在执行步骤103时，还包括在缓冲层上制作有源层的步骤，具体 制作有源层可以通过下述方式实现。
首先，在处理后的膜层20上沉积一整层的非晶硅层。由于处理后的膜层20上需要先沉积缓冲层再制作有源层，因而实际上是在缓冲层30上沉积一整层的非晶硅层，对非晶硅层进行准分子激光退火处理，使非晶硅层晶化为多晶硅层。然后，再通过一次构图工艺在多晶硅层上形成有源层的图形，如图2d所示，为本发明实施例提供的制作有源层的图形后的结构示意图。
如图3所示，为本发明实施例提供的对一整层不透光的膜层进行处理的方法流程图。具体地，本发明实施例提供的上述阵列基板的制作方法中，例如，步骤102对膜层进行处理，具体可以采用如下步骤实现：
步骤1021，在膜层上沉积光刻胶；
步骤1022，使用掩膜板对光刻胶曝光显影，保留待形成不透光区域对应的光刻胶；
步骤1023，利用保留的光刻胶作为掩膜，采用氧化剂对膜层上待形成透光区域的膜层进行氧化处理，使得待形成透光区域的膜层透光；以及
步骤1024，剥离保留的光刻胶，得到包括透光区域和不透光区域的膜层。
在具体实施时，首先，如图4a所示，在一整层的不透光膜层20上沉积一整层光刻胶60。
其次，如图4b所示，采用掩膜板对上述一整层的光刻胶60进行曝光、显影等操作，保留待形成不透光区域对应的光刻胶60。保留的光刻胶60与有源层的沟道区域对应。
然后，如图4c所示，再利用上述图4b中保留的光刻胶60作为掩膜，采用氧化剂对膜层20的不透光部分进行氧化处理，使得膜层的待形成透光区域的部分(即两个区域a)变得透光。例如，上述氧化剂选用双氧水。
最后，氧化工艺完成以后，剥离保留的光刻胶60，如图2b所示，得到氧化处理后的一整层的膜层。该膜层与有源层的沟道区域对应的区域b不透光，而其它区域a透光。
在具体实施时，为了防止不透光区域漏光，如图2c所示，例如， 有源层的沟道区域c在衬底基板10上的正投影位于不透光区域b在衬底基板10上的正投影内。具体的，膜层上的不透光区域b的面积大于有源层的沟道区域c的面积，即不透光区域b至少能够完全覆盖有源层的沟道区域c。这防止由于不透光区域的边缘区域透光，而造成有源层上的多晶硅材料受光照后导致性能下降的问题。
为了清楚的说明本发明实施例提供的阵列基板的制作方法，如图5所示，为本发明实施例提供的上述阵列基板的制作方法的整体步骤流程图，包括以下步骤：
步骤501，在衬底基板上形成一整层不透光的膜层；
步骤502，在膜层上沉积光刻胶；
步骤503，使用掩膜板对光刻胶曝光显影，保留待形成不透光区域对应的光刻胶；
步骤504，利用保留的光刻胶作为掩膜，采用氧化剂对膜层上待形成透光区域的膜层进行氧化处理，使得待形成透光区域的膜层透光；
步骤505，剥离保留的光刻胶，得到膜层上的透光区域和不透光区域；
步骤506，在处理后的膜层上沉积非晶硅层，对非晶硅层进行准分子激光退火处理，使非晶硅层晶化为多晶硅层；
步骤507，通过一次构图工艺在多晶硅层上形成有源层的图形；以及
步骤508，在有源层上形成薄膜晶体管的栅极、源漏极。
基于同一发明构思，本发明实施例提供的一种阵列基板。如图2c所示，该阵列基板包括：衬底基板10，设置在衬底基板10上的一整层的膜层20和薄膜晶体管。膜层上设置有透光区域a和不透光区域b，不透光区域b与薄膜晶体管的有源层的沟道区域c对应。
在具体实施时，本发明实施例提供的阵列基板，将遮光层设置为一整层结构、且具有透光区域和不透光区域的膜层。由于是在一整层的膜层上设置的缓冲层，因而不会出现段差的问题。在后续准分子激光退火工艺多晶硅结晶时，可以有效减少段差对结晶效果的影响。同时，由于没有段差，缓冲层的厚度也可以根据需要进行调整。这可以适当降低缓冲层的厚度，以消除应力造成的其他不利影响。例如，该阵列基板还包括：设置在膜层和薄膜晶体管之间的缓冲层，并且缓冲 层的厚度为1000埃-5000埃。
为了不影响显示屏的显示效果，除了与有源层的沟道区域c对应的区域b外，膜层的其它区域a需要能够透光。例如，透光区域(即区域a)的膜层为经过氧化处理后的膜层。在具体实施时，氧化处理可以将不透光的膜层变成透明的氧化物膜层。
在具体实施时，由于钽金属耐高温，且能够转换为透明，因而上述不透光的膜层可以采用钽金属制作。例如，不透光区域的材料为钽，并且透光区域的材料为钽的氧化物。例如，钽金属可以被双氧水氧化为无色透明的钽的氧化物(三氧化二钽或五氧化二钽)。
在具体实施时，为了使缓冲层上不会出现段差，因而本发明实施例提供的阵列基板中设置了一整层结构，且具有透过区域和不透光区域的膜层，而实际上，也可以根据需要不设置完全一整层的膜层。例如，设置至少能够覆盖有源层、且具有透过区域和不透光区域的膜层作为遮光膜层，只要是能够保证在后续准分子激光退火工艺多晶硅结晶时，段差不影响结晶效果即可。
例如，采用半色调掩膜板制作膜层的图形，以及对膜层进行氧化的光刻胶，也可以在不增加掩膜板数量的前提下，制作出至少能够覆盖有源层的膜层、且具有透过区域和不透光区域的遮光膜层。
本发明实施例提供的上述阵列基板主要是针对需要设置遮光层的结构，例如，薄膜晶体管为顶栅型结构。由于本发明主要是针对遮光层金属改进，因而需要设置在有遮光层的薄膜晶体管中，如顶栅型结构的薄膜晶体管，或者是低温多晶硅的薄膜晶体管等。
基于同一构思，本发明实施例中还提供了一种显示装置，该显示装置包括本发明实施例中提供的阵列基板。该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。由于该显示装置解决问题的原理与本发明实施例一种阵列基板相似，因此该显示装置的实施可以参见阵列基板的实施，重复之处不再赘述。
综上所述，本发明实施例提供的阵列基板的制作方法，在形成薄膜晶体管之前形成一整层不透光的膜层，并对该膜层进行处理，使其形成透光区域和不透光区域。因而在一整层的膜层上沉积缓冲层，不会使缓冲层出现段差，并且在后续准分子激光退火工艺过程中，也不 会影响多晶硅的结晶性能。同时，本发明的方法无需增加缓冲层的厚度就可以有效消除段差对结晶性能的影响，因而也避免了由于缓冲层过厚而造成的其它各种不良的问题。
显然，本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (13)

  1. 一种阵列基板的制作方法，包括：
    在衬底基板上形成一整层不透光的膜层；
    对所述膜层进行处理，使所述膜层上形成透光区域和不透光区域，其中所述不透光区域与有源层的沟道区域对应；以及
    在处理后的膜层上形成薄膜晶体管。
  2. 如权利要求1所述的方法，其中对所述膜层进行处理，使所述膜层上形成透光区域和不透光区域的步骤，包括：
    在所述膜层上沉积光刻胶；
    使用掩膜板对所述光刻胶曝光显影，保留待形成不透光区域对应的光刻胶；
    利用保留的光刻胶作为掩膜，采用氧化剂对所述膜层上待形成透光区域的膜层进行氧化处理，使得所述待形成透光区域的膜层透光；以及
    剥离所述保留的光刻胶，得到所述膜层上的透光区域和不透光区域。
  3. 如权利要求2所述的方法，其中所述氧化剂为双氧水。
  4. 如权利要求1所述的方法，其中所述有源层的沟道区域在所述衬底基板上的正投影位于所述不透光区域在所述衬底基板上的正投影内。
  5. 如权利要求1所述的方法，其中所述一整层不透光的膜层的材料为钽。
  6. 如权利要求1-5任一项所述的方法，其中在处理后的膜层上形成薄膜晶体管的步骤，包括：
    在处理后的膜层上沉积非晶硅层，对所述非晶硅层进行准分子激光退火处理，使所述非晶硅层晶化为多晶硅层；以及
    通过一次构图工艺在所述多晶硅层上形成有源层的图形。
  7. 一种阵列基板，包括：衬底基板，设置在所述衬底基板上的一整层的膜层和薄膜晶体管，
    其中所述膜层上设置有透光区域和不透光区域，所述不透光区域与有源层的沟道区域对应。
  8. 如权利要求7所述的阵列基板，其中所述有源层的沟道区域在所述衬底基板上的正投影位于所述不透光区域在所述衬底基板上的正投影内。
  9. 如权利要求7所述的阵列基板，其中所述透光区域的膜层为经过氧化处理后的膜层。
  10. 如权利要求9所述的阵列基板，其中所述不透光区域的材料为钽，并且所述透光区域的材料为钽的氧化物。
  11. 如权利要求7所述的阵列基板，其中所述薄膜晶体管为顶栅型结构。
  12. 如权利要求7-11任一项所述的阵列基板，还包括：设置在所述膜层和所述薄膜晶体管之间的缓冲层，其中所述缓冲层的厚度为1000埃-5000埃。
  13. 一种显示装置，包括权利要求7-12任一项所述的阵列基板。
PCT/CN2017/088200 2016-08-10 2017-06-14 阵列基板的制作方法、阵列基板及显示装置 WO2018028298A1 (zh)

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