CN107170806A - 栅电极及其制作方法、阵列基板制作方法 - Google Patents

栅电极及其制作方法、阵列基板制作方法 Download PDF

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CN107170806A
CN107170806A CN201710389075.7A CN201710389075A CN107170806A CN 107170806 A CN107170806 A CN 107170806A CN 201710389075 A CN201710389075 A CN 201710389075A CN 107170806 A CN107170806 A CN 107170806A
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gate electrode
layer
correspondence
electrode region
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张斌
刘建宏
詹裕程
孙雪菲
周婷婷
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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Priority to CN201710389075.7A priority Critical patent/CN107170806A/zh
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Priority to US16/303,959 priority patent/US11133196B2/en
Priority to PCT/CN2018/087970 priority patent/WO2018214899A1/zh
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Abstract

本发明提供一种栅电极及其制作方法、阵列基板制作方法，该栅电极制作方法包括以下步骤：S1，提供一基板，该基板包括栅电极区域和非栅电极区域；S2，在基板上形成栅电极层，该栅电极层包括对应栅电极区域的导电部分和对应非栅电极区域的透明部分。本发明提供的栅电极及其制作方法、阵列基板制作方法的技术方案，可以消除段差，从而在对非晶硅层进行ELA工艺时，可以避免因段差对多晶硅的结晶性能产生的影响，从而可以获得良好的结晶效果。

Description

栅电极及其制作方法、阵列基板制作方法
技术领域
本发明涉及显示技术领域，具体地，涉及一种栅电极及其制作方法、阵列基板制作方法。
背景技术
低温多晶硅技术(Low Temperature Poly-silicon，简称LTPS)以其超薄、超轻、低能耗等优势，在目前市场上成为了中小尺寸显示行业的主流。
图1为现有的LTPS技术中阵列基板的结构示意图，请参阅图1，阵列基板包括基板1、设置在该基板1上的栅电极层2，设置在该栅电极层2上的栅绝缘层3和设置在该栅绝缘层3上的有源层4(多晶硅层)。其中，上述栅电极层2用作底栅电极，在实际应用中存在以下问题：由于在栅电极层2中栅电极所在区域与其他区域的交界存在段差(图1中的A位置)，该段差在后续的对非晶硅层进行ELA(Excimer Laser Annealing，准分子激光退火)工艺中，会导致多晶硅的结晶性能变差，从而影响结晶效果。
发明内容
本发明旨在至少解决现有技术中存在的技术问题之一，提出了一种栅电极及其制作方法、阵列基板制作方法，其可以消除段差，从而在对非晶硅层进行ELA工艺时，可以避免因段差对多晶硅的结晶性能产生的影响，从而可以获得良好的结晶效果。
为实现本发明的目的而提供一种栅电极制作方法，其包括以下步骤：
S1，提供一基板，所述基板包括栅电极区域和非栅电极区域；
S2，在所述基板上形成栅电极层，所述栅电极层包括对应所述栅电极区域的导电部分和对应所述非栅电极区域的透明部分，所述导电部分的厚度与所述透明部分的厚度一致。
优选的，所述步骤S2进一步包括：
S21，在所述基板上形成能够导电，且被氧化形成透明氧化物的特定金属材料层；
S22，在所述特定金属材料层上形成图形掩膜层，所述图形掩膜层覆盖对应所述栅电极区域的所述特定金属材料层；
S23，对对应所述非栅电极区域的所述特定金属材料层进行氧化处理，以使对应所述非栅电极区域的所述特定金属材料层形成透明氧化物层。
优选的，所述特定金属材料层为钽金属层，所述透明氧化物层为透明钽氧化物层。
优选的，所述透明钽氧化物层包括三氧化二钽或者五氧化二钽。
优选的，所述步骤S22进一步包括以下步骤：
S221，在整个所述特定金属材料层上形成掩膜层；
S222，对所述掩膜层进行光刻工艺，以对所述掩膜层图形化，形成所述图形掩膜层。
作为另一个技术方案，本发明还提供一种阵列基板制作方法，其包括以下步骤：
S100，采用本发明提供的上述栅电极制作方法在基板上形成栅电极层。
优选的，在所述步骤S100之后，还包括以下步骤：
S200，在所述栅电极层上形成栅绝缘层；在所述栅绝缘层上形成有源层。
优选的，所述步骤S200进一步包括以下步骤：
S201，在所述栅电极层上一步形成栅绝缘层和非晶硅层，所述非晶硅层形成在所述栅绝缘层上；
S202，对所述非晶硅层进行准分子激光退火工艺，以使所述非晶硅层转变为多晶硅层，所述多晶硅层用作所述有源层。
优选的，所述步骤S200进一步包括以下步骤：
S201，在所述栅电极层上形成栅绝缘层；
S202，在所述栅绝缘层上形成非晶硅层；
S203，对所述非晶硅层进行准分子激光退火工艺，以使所述非晶硅层转变为多晶硅层，所述多晶硅层用作所述有源层。
作为另一个技术方案，本发明还提供一种栅电极，其包括设置在基板上的栅电极层，所述基板包括栅电极区域和非栅电极区域；
所述栅电极层包括对应所述栅电极区域的导电部分和对应所述非栅电极区域的透明部分，所述导电部分的厚度与所述透明部分的厚度一致。
本发明具有以下有益效果：
本发明提供的栅电极及其制作方法、阵列基板制作方法的技术方案中，栅电极层包括对应栅电极区域的导电部分和对应非栅电极区域的透明部分，且导电部分的厚度与透明部分的厚度一致，该透明部分消除了非栅电极区与栅电极区域中的导电部分的交界存在的段差，从而在对非晶硅层进行ELA工艺时，可以避免因段差对多晶硅的结晶性能产生的影响，从而可以获得良好的结晶效果。
附图说明
图1为现有的LTPS技术中阵列基板的结构示意图；
图2为本发明提供的栅电极制作方法的流程框图；
图3为采用本发明提供的栅电极制作方法获得的栅电极的结构图；
图4A为本发明提供的栅电极制作方法的第一个过程图；
图4B为本发明提供的栅电极制作方法的第二个过程图；
图4C为本发明提供的栅电极制作方法的第三个过程图；
图4D为本发明提供的栅电极制作方法的第四个过程图；
图5为采用本发明提供的阵列基板制作方法获得的阵列基板的结构图。
具体实施方式
为使本领域的技术人员更好地理解本发明的技术方案，下面结合附图来对本发明提供的栅电极及其制作方法、阵列基板制作方法进行详细描述。
请一并参阅图2和图3，本发明提供的栅电极制作方法，其包括以下步骤：
S1，提供一基板5，该基板5包括栅电极区域B和非栅电极区域C；
S2，在基板5上形成栅电极层6，该栅电极层6包括对应栅电极区域B的导电部分61和对应非栅电极区域C的透明部分62，导电部分61的厚度与透明部分62的厚度一致。该透明部分消除了非栅电极区C与栅电极区域B中的导电部分61的交界存在的段差，从而在对非晶硅层进行ELA工艺时，可以避免因段差对多晶硅的结晶性能产生的影响，从而可以获得良好的结晶效果。
下面对本发明提供的栅电极制作方法的具体实施方式进行详细描述。具体地，上述步骤S2进一步包括：
S21，在基板1上形成能够导电，且被氧化形成透明氧化物的特定金属材料层7，如图4A所示。
S22，在特定金属材料层7上形成图形掩膜层81，该图形掩膜层81覆盖对应栅电极区域B的特定金属材料层7，如图4C所示。
形成该图形掩膜层81的具体方式可以为：步骤S22进一步包括以下步骤：
S221，在整个特定金属材料层7上形成掩膜层8，如图4B所示；
S222，对该掩膜层8进行光刻工艺，以对掩膜层8图形化，形成上述图形掩膜层81。
S23，对对应非栅电极区域C的特定金属材料层7进行氧化处理，以使对应非栅电极区域C的特定金属材料层7形成透明氧化物层，该透明氧化物层用作上述透明部分62，如图4D所示。
另外，在上述掩膜层8对对应栅电极区域B的特定金属材料层7的遮盖作用下，对应栅电极区域B的特定金属材料层7未被氧化，从而形成上述导电部分61。
上述氧化处理可以采用双氧水氧化对应非栅电极区域C的特定金属材料层7。
优选的，上述特定金属材料层7为钽金属层，该钽金属层可以被氧化形成透明钽氧化物层。该透明钽氧化物层包括三氧化二钽或者五氧化二钽等等。
当然，在实际应用中，也可以采用其他任意方式在栅电极区域B制作钽金属层，而在非栅电极区域C制作透明钽氧化物层。或者，还可以在栅电极区域B制作其他能够导电膜层，而在非栅电极区域C制作其他透明膜层。
作为另一个技术方案，请参阅图5，本发明还提供一种阵列基板制作方法，其包括以下步骤：
S100，采用本发明提供的上述栅电极制作方法在基板5上形成栅电极层6。
上述栅电极层6包括对应栅电极区域B的导电部分61和对应非栅电极区域C的透明部分62，导电部分61的厚度与透明部分62的厚度一致。该透明部分62消除了非栅电极区C与栅电极区域B中的导电部分61的交界存在的段差，从而在对非晶硅层进行ELA工艺时，可以避免因段差对多晶硅的结晶性能产生的影响，从而可以获得良好的结晶效果。
在上述步骤S100之后，还包括以下步骤：
S200，在栅电极层6上形成栅绝缘层7；在该栅绝缘层7上形成有源层8。
优选的，上述步骤S200进一步包括以下步骤：
S201，在栅电极层6上一步形成栅绝缘层7和非晶硅层(a-Si)，该非晶硅层形成在栅绝缘层6上。
S202，对上述非晶硅层进行准分子激光退火工艺(ELA)，以使非晶硅层转变为多晶硅层(p-Si)，该多晶硅层用作上述有源层8。
通过在栅电极层6上一步形成栅绝缘层7和非晶硅层，在完成上述非晶硅层进行准分子激光退火工艺之后，可以减少多晶硅层与栅绝缘层7之间的缺陷态，从而可以提高产品质量。在实际应用中，可以使用沉积腔室，并通过设定指定的工艺参数，来一步形成栅绝缘层7和非晶硅层。该沉积腔室例如可以为PECVD(Plasma Enhanced Chemical VaporDeposition，等离子体增强化学气相沉积)腔室。
当然，在实际应用中，也可以分两步形成栅绝缘层7和非晶硅层。具体地，步骤S200进一步包括以下步骤：
S201，在栅电极层6上形成栅绝缘层7；
S202，在栅绝缘层7上形成非晶硅层；
S203，对非晶硅层进行准分子激光退火工艺，以使非晶硅层转变为多晶硅层，多晶硅层用作有源层8。
另外，在实际应用中，上述阵列基板制作方法还可以在有源层8上依次制作层间介电层、源漏电极、绝缘层、公共电极、保护层和像素电极等等。
作为另一个技术方案，本发明还提供一种栅电极，请参阅图3，该栅电极包括设置在基板5上的栅电极层6。基板5包括栅电极区域B和非栅电极区域C。栅电极层6包括对应栅电极区域B的导电部分961和对应非栅电极区域C的透明部分62，导电部分61的厚度与透明部分62的厚度一致。
本发明提供的栅电极，其通过使栅电极层6包括对应栅电极区域B的导电部分961和对应非栅电极区域C的透明部分62，该透明部分62消除了非栅电极区与栅电极区域中的导电部分的交界存在的段差，从而在对非晶硅层进行ELA工艺时，可以避免因段差对多晶硅的结晶性能产生的影响，从而可以获得良好的结晶效果。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (10)

1.一种栅电极制作方法，其特征在于，包括以下步骤：
S1，提供一基板，所述基板包括栅电极区域和非栅电极区域；
S2，在所述基板上形成栅电极层，所述栅电极层包括对应所述栅电极区域的导电部分和对应所述非栅电极区域的透明部分，所述导电部分的厚度与所述透明部分的厚度一致。
2.根据权利要求1所述的栅电极制作方法，其特征在于，所述步骤S2进一步包括：
S21，在所述基板上形成能够导电，且被氧化形成透明氧化物的特定金属材料层；
S22，在所述特定金属材料层上形成图形掩膜层，所述图形掩膜层覆盖对应所述栅电极区域的所述特定金属材料层；
S23，对对应所述非栅电极区域的所述特定金属材料层进行氧化处理，以使对应所述非栅电极区域的所述特定金属材料层形成透明氧化物层。
3.根据权利要求2所述的栅电极制作方法，其特征在于，所述特定金属材料层为钽金属层，所述透明氧化物层为透明钽氧化物层。
4.根据权利要求3所述的栅电极制作方法，其特征在于，所述透明钽氧化物层包括三氧化二钽或者五氧化二钽。
5.根据权利要求2所述的栅电极制作方法，其特征在于，所述步骤S22进一步包括以下步骤：
S221，在整个所述特定金属材料层上形成掩膜层；
S222，对所述掩膜层进行光刻工艺，以对所述掩膜层图形化，形成所述图形掩膜层。
6.一种阵列基板制作方法，其特征在于，包括以下步骤：
S100，采用权利要求1-5任意一项所述的栅电极制作方法在基板上形成栅电极层。
7.根据权利要求6所述的阵列基板制作方法，其特征在于，在所述步骤S100之后，还包括以下步骤：
S200，在所述栅电极层上形成栅绝缘层；在所述栅绝缘层上形成有源层。
8.根据权利要求7所述的阵列基板制作方法，其特征在于，所述步骤S200进一步包括以下步骤：
S201，在所述栅电极层上一步形成栅绝缘层和非晶硅层，所述非晶硅层形成在所述栅绝缘层上；
S202，对所述非晶硅层进行准分子激光退火工艺，以使所述非晶硅层转变为多晶硅层，所述多晶硅层用作所述有源层。
9.根据权利要求7所述的阵列基板制作方法，其特征在于，所述步骤S200进一步包括以下步骤：
S201，在所述栅电极层上形成栅绝缘层；
S202，在所述栅绝缘层上形成非晶硅层；
S203，对所述非晶硅层进行准分子激光退火工艺，以使所述非晶硅层转变为多晶硅层，所述多晶硅层用作所述有源层。
10.一种栅电极，其包括设置在基板上的栅电极层，其特征在于，所述基板包括栅电极区域和非栅电极区域；
所述栅电极层包括对应所述栅电极区域的导电部分和对应所述非栅电极区域的透明部分，所述导电部分的厚度与所述透明部分的厚度一致。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018214899A1 (zh) * 2017-05-26 2018-11-29 京东方科技集团股份有限公司 栅电极及其制作方法、阵列基板制作方法
CN111477664A (zh) * 2020-04-26 2020-07-31 合肥鑫晟光电科技有限公司 一种显示面板及其制作方法、显示装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH047876A (ja) * 1990-04-25 1992-01-13 Nec Corp 薄膜トランジスタ
JPH09116161A (ja) * 1995-10-18 1997-05-02 Seiko Epson Corp 薄膜半導体装置およびその製造方法
US20100059757A1 (en) * 2008-09-05 2010-03-11 Myung-Hwan Kim Apparatus and method of manufacturing the same
CN106206456A (zh) * 2016-08-10 2016-12-07 京东方科技集团股份有限公司 一种阵列基板的制作方法、阵列基板及显示装置
CN106531746A (zh) * 2016-11-30 2017-03-22 京东方科技集团股份有限公司 一种阵列基板、阵列基板的制作方法、显示面板及显示装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002268082A (ja) 2001-03-07 2002-09-18 Matsushita Electric Ind Co Ltd 液晶表示装置の製造方法
JP2003115496A (ja) 2001-10-02 2003-04-18 Matsushita Electric Ind Co Ltd 薄膜トランジスタおよびその製造方法
CN101957530B (zh) 2009-07-17 2013-07-24 北京京东方光电科技有限公司 Tft-lcd阵列基板及其制造方法
CN104576523A (zh) * 2013-10-16 2015-04-29 北京京东方光电科技有限公司 一种阵列基板及其制作方法和显示装置
CN107170806A (zh) 2017-05-26 2017-09-15 京东方科技集团股份有限公司 栅电极及其制作方法、阵列基板制作方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH047876A (ja) * 1990-04-25 1992-01-13 Nec Corp 薄膜トランジスタ
JPH09116161A (ja) * 1995-10-18 1997-05-02 Seiko Epson Corp 薄膜半導体装置およびその製造方法
US20100059757A1 (en) * 2008-09-05 2010-03-11 Myung-Hwan Kim Apparatus and method of manufacturing the same
CN106206456A (zh) * 2016-08-10 2016-12-07 京东方科技集团股份有限公司 一种阵列基板的制作方法、阵列基板及显示装置
CN106531746A (zh) * 2016-11-30 2017-03-22 京东方科技集团股份有限公司 一种阵列基板、阵列基板的制作方法、显示面板及显示装置

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018214899A1 (zh) * 2017-05-26 2018-11-29 京东方科技集团股份有限公司 栅电极及其制作方法、阵列基板制作方法
US11133196B2 (en) 2017-05-26 2021-09-28 Boe Technology Group Co., Ltd. Gate electrode and method for manufacturing the same, and method for manufacturing array substrate
CN111477664A (zh) * 2020-04-26 2020-07-31 合肥鑫晟光电科技有限公司 一种显示面板及其制作方法、显示装置
CN111477664B (zh) * 2020-04-26 2023-11-24 合肥鑫晟光电科技有限公司 一种显示面板及其制作方法、显示装置

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