Classifications

• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F11/00—Error detection; Error correction; Monitoring
  • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
  • G06F11/0796—Safety measures, i.e. ensuring safe condition in the event of error, e.g. for controlling element
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
  • G06F1/26—Power supply means, e.g. regulation thereof
  • G06F1/32—Means for saving power
  • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
  • G06F1/3234—Power saving characterised by the action undertaken
  • G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
  • G06F1/26—Power supply means, e.g. regulation thereof
  • G06F1/30—Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations
  • G06F1/305—Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations in the event of power-supply fluctuations
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F11/00—Error detection; Error correction; Monitoring
  • G06F11/30—Monitoring
  • G06F11/3058—Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
  • G06F1/26—Power supply means, e.g. regulation thereof
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
  • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
  • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

• a processor typically employs one or more clock signals to synchronize logic operations at modules of the processor, thereby preventing errors such as setup errors, race conditions, and the like.
• the maximum clock frequency that can be applied to a module depends at least in part on a supply voltage provided to the module that governs voltage thresholds for transistors of the module.
• a processor module sometimes experiences temporary reductions, referred to as voltage droops, in the supply voltage. Failure to adjust the clock frequency for the module can cause errors in the overall operation of the processor.
• Some processors account for voltage droop by generating a "spare" clock signal at a reduced frequency relative to a nominal clock frequency of the module clock signal, and in response to detecting a voltage droop temporarily replace the module clock signal with the spare clock signal.
• replacement of the clock signal can cause operational errors during the replacement, and can require complex circuitry to implement.
• FIG. 1 is a block diagram of a processor that adjusts a clock signal in response to a voltage droop by adjusting enable signals used to generate the clock signal in accordance with some embodiments.
• FIG. 2 is a diagram illustrating an example of adjusting a clock signal at the processor of FIG. 1 by adjusting enable signals used to generate the clock signal in accordance with some embodiments.
• FIG. 3 is a block diagram illustrating a portion of a clock generator of the processor of FIG. 1 in accordance with some embodiments.
• FIG. 4 is a flow diagram of a method of adjusting a clock signal at a processor in response to a voltage droop by adjusting enable signals used to generate the clock signal in accordance with some embodiments.
• FIGs. 1 -4 disclose techniques for adjusting frequencies of one or more clock signals at a processor in response to a voltage droop at the processor.
• the processor generates at least one clock signal by generating a plurality of base clock signals, each of the base clock signals having a common frequency but a different phase.
• the processor also generates a plurality of enable signals, wherein each enable signal governs whether a corresponding one of the base clock signals is used to generate the clock signal.
• the enable signals therefore determine the frequency of the clock signal.
• the processor adjusts the enable signals used to generate the clock signal, thereby "stretching", or reducing the frequency of, the clock signal and reducing errors resulting from the voltage droop.
• FIG. 1 illustrates a processor 100 that adjusts a clock signal in response to a voltage droop in accordance with some embodiments.
• the processor 100 can be
• the processor 100 includes a processor core 102, a voltage detector 103, a clock control module 104, a phase-locked loop (PLL) 105, a stretch control module 107, clock generators 1 10 and 1 12, and a digital voltage and frequency scaling (DVFS) module 1 15.
• a processor core 102 a voltage detector 103, a clock control module 104, a phase-locked loop (PLL) 105, a stretch control module 107, clock generators 1 10 and 1 12, and a digital voltage and frequency scaling (DVFS) module 1 15.
• PLL phase-locked loop
• DVFS digital voltage and frequency scaling
• the processor core 102 is generally configured to execute sets of instructions (e.g., computer programs) to carry out operations on behalf of an electronic device.
• the processor core includes one or more modules, such as fetch stages, dispatch stages, execution units, memory controllers, input/output interfaces, caches, and the like that are each composed of synchronous logic elements, logic gates, and other components.
• the processor core 102 employs one or more clock signals.
• the processor core 102 employs two different clock signals, designated "CK1 " and "CK2" to synchronize its operations.
• the clock signals CK1 and CK2 can concurrently be at different frequencies, and can be used to synchronize different modules of the processor core 102, or different operations of a module.
• the processor 100 To generate the clock signals CK1 and CK2, the processor 100 employs the PLL 105 in conjunction with the clock control module 104 and the clock generators 1 10 and 1 12.
• the clock control module 104 is generally configured to identify a frequency for the clock signals CK1 and CK2 based on any of a number of criteria.
• the DVFS module 1 15 is configured to supply frequency information for the clock signals CK1 and CK2 based on operating conditions for the processor 100. For example, in some embodiments the DVFS module 1 15 receives power mode information for the processor 100, the power mode information indicating a selection of one of a plurality of power states.
• the power mode information can, for example, be supplied by an operating system executing at the processor core 102, based on information supplied by a performance monitor (not shown) of the processor 100 based on performance characteristics of the processor core 102, and the like.
• the DVFS module 1 15 selects a voltage to be supplied to the processor core 102 to be used as a reference voltage for one or more modules of the processor core 102.
• the DVFS module 1 15 supplies frequency information to the clock control module 104, indicating the frequencies for the clock signals CK1 and CK2 corresponding to the selected power state.
• the clock control module 104 Based on the frequency information, the clock control module 104 generates enable signals designated E1 [7:0] and E2[7:0] to set the frequencies for the clock signals CK1 and CK2, as described further herein.
• the PLL 105 is configured to receive a reference clock signal (not shown) from a crystal oscillator (not shown) or other clock source and based on the reference clock signal generate a plurality of base clock signals, wherein each base clock signal is out of phase with the others.
• a reference clock signal not shown
• the PLL 105 generates eight base clock signals, designated CO, C45, C90, C135, C180, C225, C270, and C315, and collectively referred to as C0-C315.
• Each of the base clock signals C0-C315 is at least forty-five degrees out of phase with the other base clock signals.
• the base clock signal C45 is forty-five degrees out of phase with the base clock signal CO
• the base clock signal C90 is ninety degrees out of phase with the base clock signal CO
• the base clock signal C135 is one-hundred thirty-five degrees out of phase with the base clock signal CO
• the number in the clock signal designation indicating the number of degrees the clock signal is out of phase with the clock signal CO.
• the clock generators 1 10 and 1 12 are each configured to receive a set of enable signals and the base signals C0-C315 and, based on the received enable signals, combine the base signals C0-C315 to generate the respective output clock signal at a frequency based on the enable signals.
• the clock generator 1 12 is configured to receive the enable signals E1 [7:0] and based on the enable signals combine the base clock signals C0-C315 to generate the clock signal CK1 at a frequency based on the enable signals E1 [7:0].
• each of the enable signals E1 [7:0] corresponds to a different one of the clock signals C0-C315 and the state of the enable signal indicates whether the corresponding clock signal will be applied to one or more logic gates whose output is used to generate the clock.
• the clock generator 1 12 thereby implements a frequency divider with respect to the frequency (referred to as the base frequency) of the base clock signals C0-C315, generating the clock signal C1 to have a frequency that is a fraction of the base frequency, wherein the fraction is controlled, at least in part, by the enable signals E1 [7:0].
• the clock generator 1 10 is configured similarly to generate the clock signal CK2 based on the base clock signals C0-C315, but the frequency of the clock signal is controlled in part by the enable signals E2[7:0].
• the processor 100 employs the voltage detector 103 and the stretch control module 107.
• the voltage detector 103 is configured to monitor a supply voltage at one or more locations in the processor core 102. In response to detecting the monitored voltage has fallen by a specified threshold amount, the voltage detector 103 asserts an output signal designated "DROOP", thereby indicating that a voltage droop has been detected at the processor core 102.
• the stretch control module 107 is configured to generate two sets of signals in response to assertion of the DROOP signal. In particular, in response to assertion of the DROOP signal, the stretch control module 107 asserts a signal designated
• the stretch control module 107 generates a set of stretch enable signals, designated S[7:0].
• each of the stretch enable signals corresponds to either the enable signals E2[7:0] or the enable signals E1 [7:0].
• the clock generator 1 12 replaces the enable signals E1 [7:0] with the stretch enable signals S[7:0], thereby changing the frequency of the clock signal CK1 in response to the detected voltage droop.
• the clock generator 1 10 replaces the enable signals E2[7:0] with the with the stretch enable signals S[7:0], thus changing the frequency of the clock signal CK2.
• the stretch control module 107 is configured to monitor the enable signals E2[7:0] and to generate the stretch enable signals S[7:0] to modify the frequency of the clock signal CK1 by a predetermined amount.
• the stretch control module 107 can generate the stretch enable signals such that the frequency of the clock signal CK1 is divided by two, relative to the nominal frequency of the clock signal as set by the enable signals E2[7:0], in response to a voltage droop.
• the stretch control module changes the frequency of the clock signal CK1 by a variable amount, depending on the size of the voltage droop indicated by the signal DROOP (or by a plurality of control signals represented by the signal DROOP).
• the stretch control module 107 can set the stretch control signals S[7:0] to divide the frequency the clock signal CK1 by 1 .25, relative to the nominal frequency set by the enable signals E1 [7:0] and if the voltage droop at the processor core 102 exceeds a second threshold, the stretch control module 107 can set the stretch control signals S[7:0] to divide the frequency the clock signal CK1 by 1 .25, relative to the nominal frequency.
• the voltage detector 103 continues to monitor the voltage at the processor core 102.
• the voltage detector 103 negates the DROOP signal.
• the stretch control module 107 negates the STRETCH signal, causing the clock generator 1 12 to return to generating the CK1 clock signal based only on the enable signals E1 [7:0], and the clock generator 1 10 to return to generating the CK2 clock signal based only on the enable signals E2[7:0]. That is, the clock signals CK1 and CK2 are returned to their pre-voltage-droop frequencies, as set by the clock control module 104.
• the processor 100 reduces the clock frequencies of clock signals applied to the processor core by modifying the enable signals used to generate the clock signals. This allows the processor 100 to adapt the clock frequencies in response to a voltage droop using the same circuitry used to generate the original clock signals, thereby reducing the amount of circuitry needed to adapt to a voltage droop.
• the processor 100 can ensure that the change in the clock frequency is synchronized with a phase of the original clock signals, allowing the clock frequency to change without requiring suspension of activity at the processor core 102.
• the stretch control module 107 can adjust set the frequency for the clock signals CK1 and CK2 to different frequencies, including stretching one of the clock signals while maintaining the other clock signal in an unstretched state.
• the stretch control module 107 can generate two sets of individually and separately controllable stretch control signals S1 [7:0] and S2[7:0].
• the processor 100 can include multiple voltage detectors to detect voltage droop at different modules of the processor 100, such as one voltage detector to detect a voltage droop at a processor core and a different voltage detector to detect a voltage droop at a cache. Based on signals provided by the different voltage detectors, the stretch control module 107 can individually and selectively adjust the frequency of different clock signals. For example, stretching a clock signal supplied to a cache in response to the
• corresponding voltage detector detecting a voltage droop at the cache, while maintaining a clock signal supplied to the processor core in an unstretched state because no voltage droop has been detected at the processor core.
• FIG. 2 illustrates a diagram 200 depicting an example operation of the clock generator 1 10 in accordance with some embodiments.
• the diagram 200 illustrates waveforms 220-227, each corresponding to a different one of the base clock signals C0-C315.
• waveform 220 represents the base clock signal CO
• waveform 221 represents the base clock signal C45.
• diagram 200 illustrates waveform 230, representing the clock signal CK1 , and waveform 235, representing the signal STRETCH.
• the STRETCH signal is in a negated state, indicating that no voltage droop has been detected at the processor core 102.
• the frequency of the clock signal CK1 is controlled by the enable signals E1 [7:0] generated by the clock control module 104.
• the clock control module 104 sets the E1 [7:0] enable signals to the value 000001 1 1 .
• the clock generator 1 10 generates the CK1 clock signal as the logical "OR" combination of the base clock signals CK0, CK45, and CK90.
• the clock control module 104 sets the E1 [7:0] enable signals to the value 1 1 100000.
• the clock generator 1 10 generates the CK1 clock signal as the logical "OR" combination of the base clock signals CK180, CK225, and CK270.
• the clock control module 104 sets the E1 [7:0] enable signals to the value 00000000, so that the CK1 clock signal is negated.
• the net effect of the enable signals E1 [7:0] as generated by the clock control module 104 between times 240 and 244 is to cause the clock generator 1 10 to generate the CK1 clock signal to have a frequency equal to the frequency of the base clock signals divided by 1 .75.
• the clock generator 1 10 operates as a frequency divider, wherein it generates the CK1 clock to have a frequency equal to the frequency of the base clock signals divided by a divisor, with the divisor set by the sequence of enable signals generated by the clock generator 1 10.
• the clock generator 1 10 can adjust the divisor by adjusting the sequence of enable signals, in order to set the CK1 clock signal to a frequency indicated by the DVFS module 1 15 (FIG. 1 ).
• the STRETCH signal is asserted, indicating that the voltage detector 103 (FIG. 1 ) has detected a voltage droop at the processor core 102.
• the clock generator 1 10 stops employing the E1 [7:0] enable signals to generate the clock signal CK1 , and begins using the stretch enable signals S[7:0].
• the stretch control module 107 generates the stretch enable signals S[7:0] to reduce the frequency of the clock signal CK1 relative to its frequency prior to time 244, thereby adjusting for the voltage droop.
• the stretch control module 107 generates the stretch enable signals S[7:0] to have a value of 0001 1 1 1 1 .
• the clock generator 1 10 generates the CK1 clock signal as the logical "OR" combination of the base clock signals CK0, CK45, CK90, CK135, and CK180.
• the stretch control module 107 generates the stretch enable signals S[7:0] to have a value of 00000000, thereby causing the clock generator 1 10 to negate the clock signal CK1 for this period of the base clock signal 180.
• the stretch control module 107 alternates the value of the stretch enable signals S[7:0] between 0001 1 1 1 1 and 0000000.
• This sequencing of values for the stretch enable signals results in the clock generator 1 10 generating the clock signal CK1 to have a frequency that is half of the frequency of the base clock signals. That is, the sequence of values for the stretch enable signals S[7:0] establishes the divisor for the clock generator 1 10 to have a value of two.
• the clock control module 104 continues to generate values for the enable signals E1 [7:0] while the STRETCH signal is asserted. That is, the clock control module 104 generates the enable signals E1 [7:0] independently of the state of the STRETCH signal. This allows the processor 100 to quickly switch between clock frequencies, in response to the initiation or cessation of voltage droop, by switching which enable signals are employed by the clock generator 1 10 to generate the clock signal CK1 . Further, it allows the clock generator 1 10 to synchronize any change in frequency with a period of the clock signal CK1 , thereby allowing the processor core 102 to continue operation during the change in
• the clock generator 1 10 can change the period at a falling edge of the clock signal CK1 , so that the first stretched phase of the clock signal CK1 is during a negated phase.
• changing the period of the clock signal during a falling edge can allow the clock generator 1 10 to begin the stretched period of the clock signal CK1 more quickly, thereby saving additional power.
• the stretch control module 107 when the STRETCH signal is negated, the stretch control module 107 provides the S[7:0] signals that are phase-aligned with the clock signal CK1 .
• the clock control module 104 when the STRETCH signal is asserted, the clock control module 104 provides the E1 [7:0] signals as phase-aligned signals to the stretched clock signal CK1 .
• the period of the clock signal CK1 can transition at a clock edge, thereby reducing errors resulting from the change in the clock signal CK1 .
• FIG. 3 illustrates a block diagram of a portion 300 of the clock generator 1 10 in accordance with some embodiments.
• the portion 300 includes a clock sub-circuit 350, NAND gate 355 and 356, and a NOR gate 357.
• the sub-circuit 350 includes a latch 351 , a multiplexer 352, a latch 353, and a NAND gate 354.
• the latch 351 includes a data input to receive the enable signal E1 [1 ], a clock input to receive the base clock signal C180, and an output.
• the multiplexer 352 includes a data input connected to the output of the latch 351 , a data input to receive the stretch enable signal S[1 ], and a control input to receive the STRETCH signal, and an output.
• the latch 353 includes a data input connected to the output of the multiplexer 352, an enable input to receive the base clock signal C225, and an output.
• the NAND gate 354 includes an input connected to the output of the latch 353, an input to receive the clock signal C45, and an output.
• the sub-circuit 350 is generally configured to select one of the enable signal E1 [1 ] or the stretch enable signal S[1 ] as the applicable enable signal for the sub-circuit 350, and to select whether the base clock signal C45 is to be used to as one of the bases of the clock signal CK1 .
• the latch 351 is generally configured to latch the value of the enable signal E1 [1 ] in response to assertion of the base clock signal C180.
• the multiplexer 352 is configured to select the applicable enable signal based on the state of the STRETCH signal. In particular, in response to the STRETCH signal being negated, the multiplexer 352 applies the output of the latch 351 at its output.
• the multiplexer 352 applies the stretch enable signal S[1 ] to the input of the latch 353.
• the NAND gate 354 is configured to selectively apply the base clock signal C45 at its output based on the state of the applicable enable signal as latched at the latch 353. Thus, if the value of the latched applicable enable signal is negated, indicating the base clock signal C45 is not to be used as a basis of the CK1 clock signal, the NAND gate 354 maintains its output in an asserted state. If the value of the latched applicable enable signal is asserted, the output of the NAND gate will be an inverted representation of the base clock signal C45.
• the clock generator 1 10 includes additional sub-circuits similar to the sub-circuit 350 and are not illustrated at the portion 300 for clarity.
• the clock generator 1 10 includes a corresponding sub-circuit for each base clock signal C0-C315, with each sub-circuit receiving a different one of the enable signals E1 [7:0] and a different corresponding one of the stretch enable signals S[7:0].
• Each sub-circuit operates similarly to the sub-circuit 350 by selecting the applicable enable signal based on the state of the STRETCH signal, and by selecting, based on the state of the
• the NAND gate 355 includes a plurality of inputs each connected to a different one of the sub-circuits for the base clock signals CO, C45, C90, and C135, and an output.
• the NAND gate 356 includes a plurality of inputs each connected to a different one of the sub-circuits for the base clock signals C180, C225, C270, and C315.
• the NOR gate 357 includes an input connected to the output of the NAND gate 355, an input connected to the output of the NAND gate 356, and an output to provide the clock signal CK1 .
• the CK1 clock signal is generated based on the state of the applicable enable signals, as indicated by the state of the STRETCH signal, and based on the base clock signals selected by the applicable enable signals.
• FIG. 4 illustrates a flow diagram of a method 400 of adjusting a frequency of a clock signal in response to detecting a voltage droop at a processor core in accordance with at least one embodiment.
• the method 400 is described with respect to an example implementation at the processor 100 of FIG. 1 .
• the clock control module 104 identifies, based on information received from the DVFS module 1 15, the nominal frequency setting for the clock signals CK1 and CK2.
• the clock control module 104 generates the E2[7:0] and E1 [7:0] enable signals to set the CK2 and CK1 clock signals to their respective nominal frequency settings.
• the stretch control module 107 generates the stretch enable signals S[7:0] to set the CK1 and CK2 clock signals to a lower frequency relative to their nominal frequencies.
• the voltage detector 103 monitors the voltage at one or more points of the processor core 102 to identify whether a voltage droop is present. If not, the voltage detector 103 maintains the DROOP signal in a negated state and the stretch control module 107 in turn maintains the STRETCH signal in a negated state. In response, the method flow moves to block 410, and the clock generators 1 10 and 1 12 generate the CK2 and CK1 clock signals based on the E2[7:0] and E1 [7:0] enable signals, thereby generating the clock signals at their respective nominal frequencies. The method flow then returns to block 408 as the voltage detector 103 continues to monitor the voltage at the processor core 102.
• the voltage detector 103 in response to detecting a voltage droop the voltage detector 103 asserts the DROOP signal, thereby causing the stretch control module 107 to assert the STRETCH signal.
• the method flow moves to block 412 and the clock generators 1 10 and 1 12 generate the CK2 and CK1 clock signals based on the S[7:0] stretch enable signals, thus generating the clock signals at their slower frequencies.
• the method flow proceeds to block 414 and the voltage detector 103 monitors whether the voltage at the processor core 102 has returned to its nominal level or range. If not, the method returns to block 412 as the clock generators 1 10 and 1 12 maintain the CK2 and CK1 clock signals at their slower frequencies.
• the method flow proceeds to block 410, where the stretch control module 107 negates the STRETCH signal, causing the clock generators 1 10 and 1 12 to return to generating the CK2 and CK1 clock signals based on the E2[7:0] and E1 [7:0] enable signals.
• the stretch control module 107 negates the STRETCH signal, causing the clock generators 1 10 and 1 12 to return to generating the CK2 and CK1 clock signals based on the E2[7:0] and E1 [7:0] enable signals.
• certain aspects of the techniques described above can implemented by one or more processors of a processing system executing software.
• the software comprises one or more sets of executable instructions stored or otherwise tangibly embodied on a non-transitory computer readable storage medium.
• the software can include the instructions and certain data that, when executed by the one or more processors, manipulate the one or more processors to perform one or more aspects of the techniques described above.
• the non-transitory computer readable storage medium can include, for example, a magnetic or optical disk storage device, solid state storage devices such as Flash memory, a cache, random access memory (RAM) or other non-volatile memory device or devices, and the like.
• the executable instructions stored on the non-transitory computer readable storage medium may be in source code, assembly language code, object code, or other instruction format that is interpreted or otherwise executable by one or more processors.

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