JP6940585B2 - 電圧降下のためのクロック調整 - Google Patents

電圧降下のためのクロック調整 Download PDF

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Publication number
JP6940585B2
JP6940585B2 JP2019500873A JP2019500873A JP6940585B2 JP 6940585 B2 JP6940585 B2 JP 6940585B2 JP 2019500873 A JP2019500873 A JP 2019500873A JP 2019500873 A JP2019500873 A JP 2019500873A JP 6940585 B2 JP6940585 B2 JP 6940585B2
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Prior art keywords
clock
frequency
clock signal
signals
enable signals
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JP2019500873A
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Japanese (ja)
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JP2019527884A5 (enExample
JP2019527884A (ja
Inventor
コムルシュ スティーヴン
コムルシュ スティーヴン
メーラ アミタブ
メーラ アミタブ
マーティン ボーン リチャード
マーティン ボーン リチャード
ディー． ヤング ボビー
ディー． ヤング ボビー
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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Publication of JP2019527884A5 publication Critical patent/JP2019527884A5/ja
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0796—Safety measures, i.e. ensuring safe condition in the event of error, e.g. for controlling element
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/30—Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations
    • G06F1/305—Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations in the event of power-supply fluctuations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/3058—Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Computing Systems (AREA)
  • Power Sources (AREA)
  • Pulse Circuits (AREA)
  • Manipulation Of Pulses (AREA)
JP2019500873A 2016-07-12 2016-09-15 電圧降下のためのクロック調整 Active JP6940585B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/208,388 2016-07-12
US15/208,388 US10642336B2 (en) 2016-07-12 2016-07-12 Clock adjustment for voltage droop
PCT/US2016/051814 WO2018013156A1 (en) 2016-07-12 2016-09-15 Clock adjustment for voltage droop

Publications (3)

Publication Number Publication Date
JP2019527884A JP2019527884A (ja) 2019-10-03
JP2019527884A5 JP2019527884A5 (enExample) 2019-11-14
JP6940585B2 true JP6940585B2 (ja) 2021-09-29

Family

ID=60940594

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2019500873A Active JP6940585B2 (ja) 2016-07-12 2016-09-15 電圧降下のためのクロック調整

Country Status (5)

Country Link
US (1) US10642336B2 (enExample)
JP (1) JP6940585B2 (enExample)
KR (1) KR102340679B1 (enExample)
CN (1) CN109478157B (enExample)
WO (1) WO2018013156A1 (enExample)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11177811B2 (en) * 2017-09-28 2021-11-16 Intel Corporation Clock synthesis for frequency scaling in programmable logic designs
US10627883B2 (en) * 2018-02-28 2020-04-21 Advanced Micro Devices, Inc. Onboard monitoring of voltage levels and droop events
US10310549B1 (en) * 2018-06-21 2019-06-04 Nanya Technology Corporation Clock signal generating circuit and operating method thereof
US11487341B2 (en) * 2018-08-09 2022-11-01 Nvidia Corporation Techniques for configuring a processor to execute instructions efficiently
US10928886B2 (en) 2019-02-25 2021-02-23 Intel Corporation Frequency overshoot and voltage droop mitigation apparatus and method
GB2590660B (en) * 2019-12-23 2022-01-05 Graphcore Ltd Reactive droop limiter
US11442082B2 (en) 2019-12-23 2022-09-13 Graphcore Limited Droop detection
KR102827935B1 (ko) 2020-07-03 2025-07-01 삼성전자주식회사 전자 장치 및 그 전자 장치의 제어 방법
US12353266B2 (en) 2020-07-27 2025-07-08 Google Llc Adaptive frequency control in integrated circuits
US11835998B2 (en) * 2021-06-29 2023-12-05 Advanced Micro Devices, Inc. System and method for enabling clock stretching during overclocking in response to voltage droop
US12189415B2 (en) * 2021-09-08 2025-01-07 International Business Machines Corporation Providing deterministic frequency and voltage enhancements for a processor
US12353235B2 (en) 2021-10-01 2025-07-08 Intel Corporation Adaptive clock modulation
US12422883B2 (en) * 2022-12-13 2025-09-23 Skyechip Sdn Bhd System and a method for aligning a programmable clock or strobe

Family Cites Families (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5124571A (en) * 1991-03-29 1992-06-23 International Business Machines Corporation Data processing system having four phase clocks generated separately on each processor chip
JPH0573166A (ja) * 1991-09-11 1993-03-26 Matsushita Electric Ind Co Ltd コンピユータシステム
JP2959657B2 (ja) * 1993-05-13 1999-10-06 キヤノン株式会社 電子機器
JP2000207381A (ja) * 1999-01-20 2000-07-28 Mitsubishi Electric Corp マイクロコンピュ―タのリセット装置
DE10119051B4 (de) * 2001-04-18 2006-12-28 Infineon Technologies Ag Schaltungsanordnung zur Freigabe eines Taktsignals in Abhängigkeit von einem Freigabesignal
JP2002328744A (ja) * 2001-04-27 2002-11-15 Fujitsu Ltd 半導体集積回路装置
US7114038B2 (en) * 2001-12-28 2006-09-26 Intel Corporation Method and apparatus for communicating between integrated circuits in a low power mode
JP4119152B2 (ja) * 2002-04-17 2008-07-16 株式会社ルネサステクノロジ 半導体集積回路装置
DE10249886B4 (de) * 2002-10-25 2005-02-10 Sp3D Chip Design Gmbh Verfahren und Vorrichtung zum Erzeugen eines Taktsignals mit vorbestimmten Taktsingaleigenschaften
US6922111B2 (en) * 2002-12-20 2005-07-26 Intel Corporation Adaptive frequency clock signal
US6882238B2 (en) 2003-03-21 2005-04-19 Intel Corporation Method and apparatus for detecting on-die voltage variations
US7007188B1 (en) 2003-04-29 2006-02-28 Advanced Micro Devices, Inc. Precision bypass clock for high speed testing of a data processor
US7225349B2 (en) * 2003-07-25 2007-05-29 Intel Corporation Power supply voltage droop compensated clock modulation for microprocessors
US7076679B2 (en) * 2003-10-06 2006-07-11 Hewlett-Packard Development Company, L.P. System and method for synchronizing multiple variable-frequency clock generators
DE10354215B4 (de) * 2003-11-20 2010-02-25 Infineon Technologies Ag Taktregulierungsvorrichtung sowie Schaltungsanordnung
US7068081B2 (en) * 2004-05-04 2006-06-27 Hewlett-Packard Development Company, L.P. Frequency synthesizer with digital phase selection
JP4492394B2 (ja) * 2005-03-08 2010-06-30 株式会社デンソー マイクロコンピュータ
US8037340B2 (en) * 2007-11-28 2011-10-11 International Business Machines Corporation Apparatus and method for micro performance tuning of a clocked digital system
DE102008061034B3 (de) * 2008-12-08 2010-04-08 Fujitsu Siemens Computers Gmbh Anordnung umfassend wenigstens zwei Stromversorgungseinheiten und wenigstens eine Strom verbrauchende Komponente, Computersystem sowie Verfahren zur Steuerung einer Anordnung
WO2011118012A1 (ja) * 2010-03-25 2011-09-29 富士通株式会社 マルチコアプロセッサシステム、制御プログラム、および制御方法
US8384435B2 (en) 2011-01-05 2013-02-26 Texas Instruments Incorporated Clock switching circuit with priority multiplexer
US20120187991A1 (en) 2011-01-25 2012-07-26 Advanced Micro Devices, Inc. Clock stretcher for voltage droop mitigation
US8937511B2 (en) 2011-11-22 2015-01-20 Marvell World Trade Ltd. Frequency scaling of variable speed systems for fast response and power reduction
US9317342B2 (en) * 2011-12-23 2016-04-19 Intel Corporation Characterization of within-die variations of many-core processors
US9164563B2 (en) * 2012-05-24 2015-10-20 International Business Machines Corporation Processor noise mitigation using differential critical path monitoring
US10020931B2 (en) 2013-03-07 2018-07-10 Intel Corporation Apparatus for dynamically adapting a clock generator with respect to changes in power supply
US8933737B1 (en) * 2013-06-28 2015-01-13 Stmicroelectronics International N.V. System and method for variable frequency clock generation
GB2525864B (en) * 2014-05-06 2021-04-07 Advanced Risc Mach Ltd Clock frequency reduction for an electronic device
US9753525B2 (en) 2014-12-23 2017-09-05 Intel Corporation Systems and methods for core droop mitigation based on license state
US9798376B2 (en) 2015-08-03 2017-10-24 Qualcomm Incorporated Power distribution network (PDN) droop/overshoot mitigation
US9778676B2 (en) 2015-08-03 2017-10-03 Qualcomm Incorporated Power distribution network (PDN) droop/overshoot mitigation in dynamic frequency scaling
US9915968B2 (en) 2016-04-19 2018-03-13 Qualcomm Incorporated Systems and methods for adaptive clock design
US10148258B2 (en) 2016-09-28 2018-12-04 Mellanox Technologies, Ltd. Power supply voltage monitoring and high-resolution adaptive clock stretching circuit
US10009016B1 (en) * 2016-12-28 2018-06-26 Qualcomm Incorporated Dynamically adaptive voltage-frequency guardband control circuit
US10171081B1 (en) * 2017-07-28 2019-01-01 International Business Machines Corporation On-chip supply noise voltage reduction or mitigation using local detection loops in a processor core

Also Published As

Publication number Publication date
WO2018013156A1 (en) 2018-01-18
KR20190018171A (ko) 2019-02-21
CN109478157B (zh) 2023-07-28
KR102340679B1 (ko) 2021-12-17
JP2019527884A (ja) 2019-10-03
US10642336B2 (en) 2020-05-05
US20180018009A1 (en) 2018-01-18
CN109478157A (zh) 2019-03-15

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