WO2018008537A1 - Dispositif de communication en duplex intégral - Google Patents

Dispositif de communication en duplex intégral Download PDF

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Publication number
WO2018008537A1
WO2018008537A1 PCT/JP2017/024079 JP2017024079W WO2018008537A1 WO 2018008537 A1 WO2018008537 A1 WO 2018008537A1 JP 2017024079 W JP2017024079 W JP 2017024079W WO 2018008537 A1 WO2018008537 A1 WO 2018008537A1
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WIPO (PCT)
Prior art keywords
full
duplex communication
data
signal
sensor
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PCT/JP2017/024079
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English (en)
Japanese (ja)
Inventor
敏明 中村
和夫 小埜
都留　康隆
雅秀 林
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日立オートモティブシステムズ株式会社
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Publication of WO2018008537A1 publication Critical patent/WO2018008537A1/fr

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    • G—PHYSICS
    • G08—SIGNALLING
    • G08C—TRANSMISSION SYSTEMS FOR MEASURED VALUES, CONTROL OR SIMILAR SIGNALS
    • G08C15/00—Arrangements characterised by the use of multiplexing for the transmission of a plurality of signals over a common path
    • G—PHYSICS
    • G08—SIGNALLING
    • G08C—TRANSMISSION SYSTEMS FOR MEASURED VALUES, CONTROL OR SIMILAR SIGNALS
    • G08C19/00—Electric signal transmission systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received

Definitions

  • the present invention relates to a full-duplex communication device.
  • Full-duplex communication is a communication method that can send and receive data from both sides simultaneously in bidirectional communication, and full-duplex communication devices that employ such a communication method are used in various fields. Yes.
  • the full-duplex communication device is applied, for example, when performing vehicle control and measurement.
  • full-duplex communication is executed between a master on the ECU (electronic control unit) side and a slave on the measuring instrument side, and a sensor output of the sensor type indicated by the master is returned from the slave as a response.
  • the sensor type in this case is a sensor for vehicle acceleration and angular velocity, and is transmitted from the sensor side to the ECU, which is the main device, and used depending on the purpose of use such as prevention of skidding and safe driving assistance.
  • Patent Document 1 As a known example that is applied to a vehicle and performs full-duplex communication of inertial sensor output, devices as described in Patent Document 1 and Patent Document 2 are known.
  • Patent Document 1 discloses a “first signal that is a physical quantity measuring device that detects a predetermined physical quantity, detects the predetermined physical quantity, and is a signal according to the detected magnitude of the predetermined physical quantity.
  • a sensor element that outputs a signal, a detection circuit that generates a second signal according to the predetermined physical quantity based on the first signal, a drive signal, and a drive signal that is supplied to the sensor element
  • a third signal that is an internal signal from at least one of the drive circuit, the detection circuit, and the drive circuit, and a failure diagnosis for at least one of the detection circuit and the drive circuit based on the third signal
  • a failure diagnosis unit that outputs a fourth signal that is a signal corresponding to the result of the failure diagnosis, and receives a command and generates command request data that is data requested by the command
  • An interface unit that serially transmits response data including the command request data, and the interface unit is configured to transmit the command request data based on at least one of the second signal and the fourth signal.
  • Patent Document 2 includes “a transmission / reception function for performing bidirectional communication with a host, and a synchronization control unit, a frequency generator that generates a transmission signal, and a reference signal generation source that generates a reference signal.
  • the control unit detects a frequency error of the transmission signal with respect to the reception signal received from the host and outputs a frequency adjustment signal that reduces the error with respect to the reception signal, and the frequency generator is based on the reference signal.
  • the transmission / reception apparatus is characterized in that the frequency of the transmission signal is determined and the frequency of the transmission signal is adjusted by the frequency adjustment signal.
  • the sensor that detects the angular velocity, acceleration, etc. of the vehicle while traveling determines the type and number of sensor data to be transmitted from the sensor side to the main ECU, according to the purpose of use such as prevention of skidding and safe driving assistance. It is desirable that it can be appropriately changed.
  • the main device side outputs a communication clock, and the sensor side transmits the requested data and the communication error detection code in synchronization therewith.
  • the sensor side needs to transmit an error detection code at the end of communication. Therefore, it is necessary to fix the number of clocks for each communication with the main device in advance. For example, if the number of clocks for each communication is fixed to 32 clocks, for example, if the error detection code is 8 bits, the sensor side may transmit the error detection code at the 25th clock to the 32nd clock every time.
  • the main apparatus side cannot receive a plurality of sensor outputs at the same time at a time.
  • the main apparatus side must receive unnecessary data, and there is a problem that it takes time for communication.
  • Patent Document 1 shows an example in which the data length of full-duplex communication is always constant, and the output timing of CRC (error detection code: cyclic redundancy code) added to the end of communication data is always constant. ing.
  • CRC error detection code: cyclic redundancy code
  • Patent Document 2 shows an example in which the slave side has a function of counting the number of clocks output from the master side for the purpose of detecting the clock frequency.
  • the present invention has been made in view of such circumstances, and makes it possible to vary the data length or the number of communication clocks for each communication, and to transmit an error detection code at the end of communication even when the data length is variable. It is an object of the present invention to provide a full-duplex communication device.
  • a transmission signal including a clock signal and a command signal is given from the master unit to the slave unit, and the slave unit returns a response signal including the data type specified by the command signal to the master unit
  • a full-duplex communication device that continuously performs full-duplex communication in which a signal and a response signal are transmitted and received in both directions at the same time, and the command signal transmitted from the master unit is the data type and the length of the full-duplex communication
  • the slave unit determines the range of the clock for transmitting error detection data for detecting a communication error based on the received information for determining the period length for performing full-duplex communication, and inputs from the master unit In synchronization with a clock signal to be transmitted, data of a specified data type and error detection data are transmitted as a response signal
  • the present invention also provides a transmission signal including a clock signal and a command signal from the ECU to the sensor unit, and the sensor unit returns a response signal including the sensor type specified by the command signal to the ECU, and the command signal and the response signal are simultaneously transmitted.
  • a full-duplex communication device that continuously performs full-duplex communication that is transmitted and received in both directions, and a command signal transmitted from the ECU includes information that defines a sensor type and a period length for performing full-duplex communication.
  • the unit determines a clock range for transmitting error detection data for detecting a communication error based on the information for determining a period length for performing full-duplex communication, and synchronizes with a clock signal input from the master unit.
  • the data of the specified sensor type and error detection data are transmitted as a response signal.
  • full-duplex communication that makes it possible to change the data length or the number of communication clocks for each communication, and to send an error detection code at the end of communication even when the data length is variable. Can do.
  • FIG. 3 is a block diagram illustrating a specific configuration example of a command receiving unit 112.
  • FIG. 9 is a block diagram illustrating a specific circuit configuration example of a clock number storage unit 113 according to the second embodiment.
  • the block diagram which shows the specific circuit structural example of the CRC output period calculation part 114.
  • FIG. The figure explaining the view of full-duplex communication between the master part 106 and the slave part 105.
  • FIG. The time chart which shows a specific SPI communication format.
  • FIG. 1 is a block diagram of a full-duplex communication apparatus according to an embodiment of the present invention.
  • the full-duplex communication apparatus can be roughly classified into the master unit 106, the slave unit 105, and the sensor unit 100. However, when simply classifying the master and the slave, it can be called the slave unit including the sensor unit 100. .
  • the master unit 106 is a main device, or an ECU (electronic control unit) corresponds to this in the case of vehicle control.
  • ECU electronic control unit
  • the master unit 106 as an ECU in the case of vehicle control.
  • the master unit 106 which is an ECU, transmits and receives signals to and from the slave unit 105, which is a sensor unit, through SPI communication.
  • the master unit 106 provides the slave unit 105 with a transmission signal SS composed of a chip select signal SS1, a clock signal SS2, and a command signal SS3.
  • the master unit 106 includes a clock number setting unit 122 and a command transmission unit 121 in order to generate the transmission signal SS.
  • the master unit 106 also includes a response receiving unit 123 for receiving the response signal SR from the slave unit 105.
  • the clock number setting unit 122 sets the clock number of the response signal SR to, for example, 16, 32, 64, etc., and the command transmission unit 121 incorporates information on the number of clocks into the command signal SS3 and transmits it.
  • the sensor unit 100 includes a control unit 104 and a plurality of sensors 101, 102, and 103.
  • the angular velocity sensor (Yaw sensor) 101 detects an angular velocity (a changing speed of the rotation angle in the turning direction) when the rotation occurs around the vertical axis or the horizontal axis of the vehicle.
  • the acceleration sensor (xG sensor) 102 detects the acceleration when movement occurs in the left-right direction of the vehicle.
  • the acceleration sensor (yG sensor) 103 detects acceleration when movement occurs in the front-rear direction of the vehicle.
  • the control unit 104 corrects and diagnoses the operations of the three sensors 101 to 103 of different types and the temperature and noise of each sensor output.
  • the control unit 104 sends sensor data S2 to the slave unit 105 in response to the sensor type designation signal S1 from the slave unit 105.
  • the slave unit 105 is a core part of the present invention, and a sensor type designation signal S1 is sent to the sensor unit 100 in accordance with a transmission signal SS (chip select signal SS1, clock signal SS2, command signal SS3) from the master unit 106.
  • the response signal SR created by processing the sensor data S2 obtained from the sensor unit 100 is sent to the master unit 106.
  • the sensor output and the diagnostic output corrected by the control unit 104 are input as sensor data S2, processed according to a command received from the master unit 106, and output to the master unit 106 as a response signal SR. is doing.
  • FIG. 5 is a diagram for explaining the concept of full-duplex communication between the master unit 106 and the slave unit 105.
  • a chip select signal SS1, a clock signal SS2, a command signal SS3, and a response signal SR are described in order from the top.
  • the chip select signal SS1, the clock signal SS2, and the command signal SS3 are transmission signals SS given from the master unit 106 to the slave unit 105
  • the response signal SR is given from the slave unit 105 to the master unit 106.
  • a clock signal SS2 having a predetermined number of clocks is given in the periods TN, TN + 1, and TN + 2 determined by the chip select signal SS1, and the command signal SS3 and the response are sent in the periods TN, TN + 1, and TN + 2.
  • Signal SR is bidirectionally communicated. However, in bidirectional communication, the response signal SR in the current period TN + 1 is sensor data S2 formed in response to an instruction from the command signal SS3 in the previous period TN (sensor output and diagnostic output corrected by the control unit 104). It is supposed to reflect.
  • the response signal SR in the current period TN + 1 shows the output of the angular velocity sensor 101 obtained according to the instruction. Is included.
  • the response signal SR is transmitted from the slave unit 105 to the master unit 106 in accordance with the content of the command signal SS3.
  • the response signal SR is synchronized with the clock output from the master unit 106. Is output.
  • the command signal SS3 and the response signal SR are simultaneously transmitted and received with the same clock.
  • the response signal SR is returned after interpreting the contents of the command signal SS3, the response to the command N is the response N + 1 as the next communication. Will be output.
  • the slave unit 105 is configured and functions as follows in order to achieve the above-described bidirectional communication.
  • the chip select signal SS1 and the clock signal SS2 from the master unit 106 are taken into the counter 111.
  • the counter 111 counts the number of clocks of the clock signal SS2 input during a period (for example, TN, TN + 1, TN + 2) where the chip select signal SS1 input from the master unit 106 is L (low) level.
  • the chip is in a reset state while the chip select signal SS1 is at the H (high) level.
  • the clock number Sg1 is given to the comparison unit 115 described later.
  • the command receiving unit 112 receives the command signal SS3 input in synchronization with the clock signal SS2 from the master unit 116, distributes it to the control unit 104 and the clock number storage unit 113, and outputs it.
  • the command signal SS3 specifies at least the sensor type to be transmitted and the number of clocks at that time, and the sensor type to be transmitted is sent to the control unit 104 as the sensor type designation signal S1, and the number of clocks at that time Sg2 is distributed and sent to the clock number storage unit 113.
  • FIG. 2 is a block diagram illustrating a specific configuration example of the command receiving unit 112.
  • the command receiving unit 112 includes the serial / parallel conversion unit 201 as a main component.
  • a 16-bit signal from the head of the serial signal input as the command signal SS3 is output to the control unit 104 as 16-bit parallel information (sensor type designation signal S1) indicating the requested sensor type.
  • the subsequent 4-bit signal is output to the control unit 104 as 4-bit parallel information (clock number Sg2) indicating the clock number.
  • the clock number storage unit 113 is a register that stores the clock number Sg ⁇ b> 2 output from the command reception unit 112. The stored data is retained until the next input.
  • the clock number Sg2 given as 4-bit parallel information is normally designated as 16, 32, or 64 bits.
  • a CRC output period calculation unit 114 calculates a period for outputting a CRC, which is an error detection code, from the value of the number of input clocks.
  • FIG. 4 shows a specific circuit configuration example of the CRC output period calculation unit 114.
  • the CRC data length (for example, 8 bits) given by the constant setting unit 402 is subtracted by the subtraction unit 402 from the input clock number Sg2 (usually 16, 32, 64 bits).
  • the CRC output period calculation unit 114 outputs 25 as the clock number.
  • the comparison unit 115 counts the actual number of clocks Sg1 using the number of clocks 25 given by the CRC output period calculation unit 114 as a set value.
  • the output of the comparator 115 is given to the selector 118 of FIG.
  • the output of the CRC generator 117 is given to the output terminal Y when “1” is given as the output of the output, and the output of the response transmitter 116 is given the output terminal Y when “0” is given as the output of the comparator 115.
  • the comparison unit 115 compares the output of the counter 111 and the output of the CRC output period calculation unit 114, and sets “0” when the output of the counter 111 is equal to or less than the output of the CRC output period calculation unit 114.
  • the output of the counter 111 is larger than the output of the CRC output period calculation unit 114, “1” is output. In this way, for example, when the number of clocks is 32, “1” is output during a period from 25 to 32 count outputs.
  • the response transmission unit 116 selects output information from the three sensor outputs and diagnostic information according to the sensor type designation signal S1 from the control unit 104, converts the output information into serial data, and holds a part of the response signal. Yes.
  • the CRC generation unit 117 calculates the transmission data input from the response transmission unit 116 in order from the first clock to the 24th clock, and generates and holds 8-bit CRC data.
  • the held data of the response transmission unit 116 and the CRC generation unit 117 are given to the selector 118, and the selector 118 uses the period from the falling point of the chip select signal SS1 in FIG.
  • the output of the transmission unit 116 is sent out.
  • the CRC data of the CRC generation unit 117 is serially output sequentially during the period from the 25th clock to the 32nd clock.
  • the selector 118 switches between the input from the response transmission unit 116 and the input from the CRC generation unit 117 and outputs the result.
  • the response signal SR selects and outputs the input from the control unit 104 from the first clock to the 24th clock, but switches from the 25th clock to the output of the CRC code. It is said.
  • FIG. 6 is a time chart showing a specific SPI communication format. Specific examples of the command signal SS3 and the response signal SR are shown.
  • the first to fourth bits of the command signal SS3 are data types indicating which output of the three sensor outputs and the diagnostic output is desired to be transmitted.
  • the next 5th to 8th bits are the number of clocks of the current communication. Since the number of clocks is information necessary for the slave unit 105 to determine the timing to start outputting the CRC, it needs to be received before outputting the CRC. In the figure, since the 25th and subsequent bits of 32 bits are allocated to the CRC, the number of clocks of the current communication is set using the 5th to 8th bits having sufficient margin with respect to the time of the 25th bit. Giving.
  • the clock number storage unit 113 holds this information until the end of the current communication at the time after the 9th bit.
  • the CRC output period calculation unit 114 outputs 24, and the comparison unit 115 outputs “1” from the 25th clock to the 32nd clock. As a result, a CRC output is transmitted through the selector 118 during that period.
  • the response signal SR is formed in a form reflecting the command of the previous command signal SS3.
  • the first to fourth bits of the response signal SR are information on the designated data type.
  • the 5th to 20th bits are information about the designated sensor output and diagnostic output.
  • the data to be returned can use up to the 24th bit including the data type information, but here shows the case where the 20th bit is completed, up to the 25th bit when CRC output is started Is all “0”.
  • FIG. 7 is a time chart showing the operation of individually transmitting the sensor data S2.
  • “individual transmission” means performing data transmission of sensor types that differ for each period.
  • the command signal SS3 instructs transmission of the output Yaw of the angular velocity sensor 101 in the period TN, instructs transmission of the output xG of the acceleration sensor 102 in the period TN + 1, and outputs the output yG of the acceleration sensor 103 in the period TN + 2.
  • the transmission is instructed, and in the period TN + 3, the transmission of the diagnosis output is instructed.
  • the length of each period T is 32 bits.
  • This communication is an example in the case of realizing the conventional communication with a constant number of clocks. Communication of one sensor data is enabled by one communication.
  • the clock output from the master unit 106 is constant at 32 clocks per communication.
  • the head is the angular velocity (Yaw)
  • the next is the acceleration in the left-right direction (xG)
  • the next is the acceleration in the front-rear direction (yG)
  • the next is the diagnosis result.
  • the number of clocks in each command signal SS3 is 32. Therefore, the response signal SR transmitted from the slave unit 105 outputs data corresponding to the data type for each communication with a delay of one communication, and outputs a CRC every 25th clock to 32nd clock.
  • the data portion of the response signal SR is all “0”.
  • FIG. 8 is a time chart showing an operation of transmitting sensor data at a time.
  • “transmission at a time” is to perform all the prepared data transmission for each period T.
  • the command signal SS3 gives Yaw meaning all prepared data transmissions in any of the periods TN, TN + 1, and TN + 2, and as a result, prepared as the response signal SR in the next period. All the data (the output Yaw of the angular velocity sensor 101, the output xG of the acceleration sensor 102, the output yG of the acceleration sensor 103, and the diagnosis output) are transmitted. Note that the length of each period T is 64 clocks, but only the first is set to the shortest 16 clocks.
  • the master unit 106 can acquire three sensor data at the same time.
  • the first number of clocks output from the master unit 106 is 16 bits. This is to minimize the number of clocks since the first response signal SR is indefinite. Communication after the next is always constant at 64 clocks.
  • the head data type of the command signal SS3 is an angular velocity (Yaw), thereby instructing all communications.
  • the number of clocks in each command signal SS3 is all 64. Therefore, the response signal SR transmitted from the communication unit 105 outputs data corresponding to the data type for each communication with one communication delay, and outputs a CRC at the 57th clock to the 64th clock every time.
  • FIG. 9 is a time chart showing an operation of transmitting sensor data separately.
  • “separate transmission” means that a part of all data is transmitted every period T.
  • all the data are the output Yaw of the angular velocity sensor 101, the output xG of the acceleration sensor 102, the output yG of the acceleration sensor 103, and the diagnosis output.
  • the command signal SS3 gives Yaw in the period TN, and the next time In the period TN + 1, xG is given, and in the next period TN + 2, diagnosis is given.
  • the number of clocks is designated as the number of clocks in the current period, and is set to a variable number of clocks according to the length of data transmitted every period T.
  • the period TN + 1 only Yaw is used, so that it is 32 bits.
  • xG and yG are included, and therefore 48 bits.
  • only the first period TN is set to the shortest 16 clocks.
  • This communication is an embodiment in which the number of clocks is different for each communication.
  • the number of clocks output from the master unit 106 is 16 for the first time. This is to minimize the number of clocks since the first response is indefinite.
  • the number of clocks for the next communication is 32, and Yaw data and CRC data, which are requests in the previous communication, are output at 32 clocks. Further, the number of clocks for the next communication is 48, and xG data, yG data, and CRC data are output at 48 clocks.
  • the number of clocks in the period is obtained from the information on the number of clocks included in the command signal SS3.
  • the information on the number of clocks here uses a portion transmitted using 4 bits from the 5th bit to the 8th bit of the waveform of FIG.
  • the second embodiment is a method of obtaining the number of clocks in the period from the data type information from the first bit to the fourth bit. As a result, the grasping of the number of clocks can be completed at an earlier timing than in the first embodiment.
  • FIG. 3 is a block diagram showing a specific circuit configuration example of the clock number storage unit 113.
  • the request data number m included in the sensor type designation signal S1 is converted into the clock number.
  • the requested data number m is 1 for Yaw only, 2 for xG and yG, 1 for diagnosis only, 4 for all designations, and so on. This value is input as the number of data m that is input in FIG.
  • Example 2 a value obtained by multiplying the result of adding 1 to the number of data m by 16 is stored as the number of clocks.
  • the adder 301 adds the output “1” of the constant setting unit 302 to the input data number m.
  • the multiplier 303 multiplies the input (m + 1) from the adder 301 by the output “16” of the constant setting unit 304.
  • the register 305 holds the output of the multiplier 303 until the next data number is input.
  • 101 angular velocity sensor, 102, 103: acceleration sensor, 104: control unit, 105: slave unit, 106: master unit, 111: counter, 112: command receiving unit, 113: clock number storage unit, 114: CRC output period calculation , 115: comparison unit, 116: response transmission unit, 117: CRC generation unit, 118: selector, 121: command transmission unit, 122: clock number setting unit, 123: response reception unit, 201: serial / parallel conversion unit, 301 : Addition unit, 302: constant setting unit, 303: multiplication unit, 304: constant setting unit, 305: register, 401: subtraction unit, 402: constant setting unit

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  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Arrangements For Transmission Of Measured Signals (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

La présente invention concerne un dispositif de communication en duplex intégral permettant de modifier une longueur de données ou un compte d'horloge de communication pour chaque communication et de transmettre un code de correction d'erreur à la fin de la communication même lorsque la longueur de données est variable. La présente invention concerne un dispositif de communication en duplex intégral permettant d'effectuer en continu une communication en duplex intégral, un signal de transmission comprenant un signal d'horloge et un signal de commande étant transmis d'une unité maîtresse à une unité esclave, et un signal de réponse comprenant un type de données spécifié par le signal de commande étant renvoyé à l'unité maîtresse à partir de l'unité esclave de telle manière que le signal de commande et le signal de réponse ont l'autorisation d'être échangés dans les deux sens en même temps, et se caractérise en ce que le signal de commande transmis à partir de l'unité maîtresse comprend des informations permettant de définir le type de données et une durée de communication en duplex intégral à effectuer, et l'unité esclave, lors de la détermination d'une plage d'horloge pendant laquelle des données de détection d'erreur permettant de détecter une erreur de communication doivent être transmises en fonction des informations reçues définissant la durée de communication en duplex intégral à effectuer, transmet des données du type de données spécifié et des données de détection d'erreur sous forme de signal de réponse d'une manière synchronisée avec le signal d'horloge entré à partir de l'unité maîtresse.
PCT/JP2017/024079 2016-07-08 2017-06-30 Dispositif de communication en duplex intégral WO2018008537A1 (fr)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014086876A (ja) * 2012-10-23 2014-05-12 Seiko Epson Corp シリアル通信回路、集積回路装置、物理量測定装置、電子機器、移動体およびシリアル通信方法
JP2015226117A (ja) * 2014-05-27 2015-12-14 横河電機株式会社 同期制御装置および同期制御方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014086876A (ja) * 2012-10-23 2014-05-12 Seiko Epson Corp シリアル通信回路、集積回路装置、物理量測定装置、電子機器、移動体およびシリアル通信方法
JP2015226117A (ja) * 2014-05-27 2015-12-14 横河電機株式会社 同期制御装置および同期制御方法

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