WO2018006738A1 - 封装结构以及封装方法 - Google Patents

封装结构以及封装方法 Download PDF

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Publication number
WO2018006738A1
WO2018006738A1 PCT/CN2017/090508 CN2017090508W WO2018006738A1 WO 2018006738 A1 WO2018006738 A1 WO 2018006738A1 CN 2017090508 W CN2017090508 W CN 2017090508W WO 2018006738 A1 WO2018006738 A1 WO 2018006738A1
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WIPO (PCT)
Prior art keywords
substrate
semiconductor chip
blocking structure
barrier
area
Prior art date
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PCT/CN2017/090508
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English (en)
French (fr)
Inventor
王之奇
沈志杰
耿志明
张坚
Original Assignee
苏州晶方半导体科技股份有限公司
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Publication date
Priority claimed from CN201610516699.6A external-priority patent/CN105977225B/zh
Priority claimed from CN201620692372.XU external-priority patent/CN206098376U/zh
Application filed by 苏州晶方半导体科技股份有限公司 filed Critical 苏州晶方半导体科技股份有限公司
Priority to US16/314,833 priority Critical patent/US20190259634A1/en
Publication of WO2018006738A1 publication Critical patent/WO2018006738A1/zh

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Definitions

  • the present application relates to semiconductor packaging technology, and in particular to a package structure and a packaging method.
  • An image sensor is a sensor that senses external light and converts it into an electrical signal. After the image sensor chip is completed, a series of packaging processes are performed on the image sensing chip, and the package structure is formed as part of an image sensor or an image sensor for various electronic devices such as a digital camera and a digital video camera. device.
  • Wafer level packaging gradually replaces wire bond packaging as a more common packaging method.
  • Wafer-level packaging technology has the following advantages: it can process the entire wafer at the same time, and the packaging efficiency is high; the whole wafer is tested before cutting, which reduces the testing process in the packaging process and reduces the testing cost; the package structure is light, Small, thin advantage.
  • the problem to be solved by the present application is to provide a package structure and a packaging method to avoid contamination of the functional area and improve the performance of the package structure.
  • the present application provides a package structure including: a substrate; a circuit wiring layer disposed on the substrate; a conductive bump on the circuit wiring layer; and a semiconductor chip flipped over the substrate
  • the semiconductor chip is provided with a functional area on the first surface of the substrate and a discrete pad surrounding the functional area, and the pad is electrically connected to the conductive bump; a sealing layer on the substrate, the sealing layer surrounding the semiconductor chip; and being located on the substrate a blocking structure surrounding the functional area to block material leakage of the sealing layer into the functional area.
  • a top of the circuit wiring layer is higher than a top of the substrate; or a top of the circuit wiring layer is flush with a top of the substrate; or a top of the circuit wiring layer is lower than the substrate top.
  • the conductive bumps enclose a designated area, and the blocking structure is located in the designated area.
  • the blocking structure is located between the conductive bump and the functional region; and the top surface of the blocking structure is in contact with the first surface of the semiconductor chip, the bottom surface of the blocking structure is The substrates are in contact.
  • the top surface width dimension of the blocking structure is less than or equal to the bottom surface width dimension in a direction parallel to the top surface of the substrate.
  • the conductive bump surrounds a designated area, and the blocking structure is located outside the designated area; and the blocking structure is further located between the semiconductor chip and the substrate.
  • the area of the semiconductor chip projected on the substrate is a projection area
  • the blocking structure is located in the projection area; and the top surface of the blocking structure is in contact with the first surface of the semiconductor chip, the blocking The bottom surface of the structure is in contact with the substrate.
  • the blocking structure comprises: a first blocking structure, a second blocking structure on a side of the first blocking structure and next to the first blocking structure, wherein a region of the semiconductor chip projected on the substrate is a projection a region, the first blocking structure is located outside the projection area, the second blocking structure is located in the projection area; and a top surface of the second blocking structure is in contact with the first surface of the semiconductor chip.
  • the thickness of the second blocking structure on the substrate is a first thickness, and a distance between the first surface of the semiconductor chip and the substrate is equal to the first thickness.
  • the thickness of the first blocking structure on the substrate is a second thickness, and the second thickness is greater than or equal to the first thickness.
  • the sealing layer is also located on top of the first blocking structure.
  • the area of the semiconductor chip projected on the substrate is a projection area
  • the blocking structure is located outside the projection area; and the top of the blocking structure is higher than the first surface of the semiconductor chip.
  • the gap has a width dimension of from 2 micrometers to 10 micrometers in a direction parallel to a top surface of the substrate.
  • the distance between the top surface of the blocking structure and the front surface of the semiconductor chip is from 2 micrometers to 10 micrometers in a direction perpendicular to a top surface of the substrate.
  • the sealing layer is also located on top of the blocking structure.
  • the shape of the blocking structure is a closed ring shape.
  • the blocking structure is in contact with the sidewall of the conductive bump; and the material of the blocking structure is an insulating material.
  • the blocking structure and the conductive bump are separated from each other; and the material of the blocking structure is an insulating material or a conductive material.
  • the insulating material is a photosensitive adhesive.
  • the blocking structure is a stacked structure, comprising: an underlying barrier layer in contact with the substrate and the circuit wiring layer, and a top barrier layer in contact with the first surface of the semiconductor chip, wherein
  • the material of the underlying barrier layer is an insulating material
  • the material of the top barrier layer is a conductive material or an insulating material.
  • the substrate comprises a substrate, the substrate is a light transmissive substrate or a PCB substrate; when the substrate is a PCB substrate, a through hole penetrating the PCB substrate is formed in the PCB substrate, the functional region Located above the through hole; when the substrate is a transparent substrate, the transparent substrate is provided with a buffer layer, and the circuit wiring layer is located on the buffer layer, and is disposed at a position corresponding to the functional region on the buffer layer There is an opening, and the bottom of the opening exposes the light transmissive substrate.
  • the material of the buffer layer is an organic polymer photoresist.
  • the package structure further includes: a solder bump on the substrate, the solder bump is electrically connected to the circuit wiring layer; the solder bump is located on the substrate and located in the semiconductor The outside of the chip.
  • the semiconductor chip is an image sensing chip; and the functional area is a photosensitive area.
  • the present application also provides a packaging method comprising: providing a plurality of individual semiconductor chips, a first surface of the semiconductor chip having a functional area and a pad surrounding the functional area; providing a substrate, the substrate including a flip-chip and a scribe line region between adjacent flip-chip regions; a circuit wiring layer is disposed on the flip-chip region of the substrate; the semiconductor chip is flipped over the substrate flip-chip region, and the pad is The circuit wiring layer is electrically connected by a conductive bump; a sealing layer is formed on the substrate, and the sealing layer surrounds the semiconductor chip; after the sealing layer is formed, the substrate is cut along the scribe line region Forming a plurality of single package structures; wherein, before forming the sealing layer, further comprising: forming a barrier structure on the substrate, the barrier structure surrounding the functional region to block a material overflowing functional region of the sealing layer .
  • the conductive bumps are formed on the pads before the semiconductor chip is flipped over the substrate flip-chip regions.
  • the conductive bumps are formed on the circuit wiring layer before the semiconductor chip is flipped over the substrate flip-chip region.
  • the method for forming the barrier structure comprises: forming a barrier film on the substrate; performing exposure processing and development processing on the barrier film to form the barrier structure; or engraving the barrier film Etching to form the barrier structure.
  • the step of flipping the semiconductor chip over the flip chip area of the substrate comprises: placing the semiconductor chip on the flip chip area of the substrate, and the pad passes through the conductive bump The circuit wiring layers are connected; the conductive bumps are subjected to a solder bonding process such that the pads are electrically connected to the circuit wiring layer through the conductive bumps.
  • the conductive bump encloses a designated area, and the blocking structure is located in the designated area; or the blocking structure Located outside the designated area, and the blocking structure is located in a projection area of the semiconductor chip projected on the substrate; forming the blocking structure before flipping the semiconductor chip over the substrate flip-chip area; After the semiconductor chip is flipped over the substrate flip-chip region, the top surface of the blocking structure is in contact with the first surface of the semiconductor chip.
  • a thickness of the conductive bump between the substrate and the first surface of the semiconductor chip is greater than or equal to a thickness of the blocking structure; and in the soldering During the bonding process, the thickness of the conductive bump between the substrate and the first surface of the semiconductor chip is reduced such that the top surface of the blocking structure is in contact with the first surface of the semiconductor chip.
  • the blocking structure comprises: a first blocking structure, a second blocking structure on one side of the first blocking structure and next to the first blocking structure; and flipping the semiconductor chip on the substrate
  • the area of the semiconductor chip projected on the substrate is a projection area
  • the first blocking structure is located outside the projection area
  • the second blocking structure is located in the projection area
  • the packaging method is further The method includes: forming the blocking structure before flipping the semiconductor chip over the substrate flip-chip region; and after flipping the semiconductor chip over the substrate flip-chip region, the second blocking A top surface of the structure is in contact with the first surface of the semiconductor chip.
  • the thickness of the conductive bump between the substrate and the first surface of the semiconductor chip is reduced, such that the top surface of the second blocking structure and the semiconductor chip The first surface is in contact and the first barrier structure covers a sidewall of the semiconductor chip portion.
  • a region of the semiconductor chip projected on the substrate is a projection area
  • the blocking structure is located outside the projection area, and the blocking a top of the structure being higher than the first surface of the semiconductor chip; forming the blocking structure before flipping the semiconductor chip over the flip-chip area of the substrate; or, flipping the semiconductor chip in the The barrier structure is formed after the substrate flip-chip area is over.
  • the packaging method further includes forming a solder bump on the substrate, and the solder bump is electrically connected to the circuit wiring layer.
  • the sealing layer is formed by a dispensing process or a plastic sealing process.
  • a blocking structure is disposed on the substrate, and the blocking structure surrounds the functional area to block the material of the sealing layer from overflowing into the functional area, thereby preventing the functional area from being contaminated. Thereby improving the performance of the package structure.
  • the blocking structure, the semiconductor chip, the substrate and the circuit wiring layer enclose a closed region, so that the barrier structure blocks the material of the sealing layer from overflowing into the functional region, and the performance of the package structure is further improved.
  • the top surface width dimension of the blocking structure is less than or equal to the bottom surface width dimension in a direction parallel to the top surface of the substrate, such that the blocking structure and the semiconductor chip front side The area of the contact is small, so the space on the front side of the semiconductor chip to be reserved for the barrier structure is small, so that the size of the semiconductor chip can be made smaller.
  • the blocking structure when the blocking structure is located outside the semiconductor chip, there is a gap between the blocking structure and the semiconductor chip in a direction parallel to a top surface of the substrate, and the gap has a width dimension of 2 micrometers. ⁇ 10 ⁇ m, because the width dimension of the gap is small, thereby preventing the material of the sealing layer from entering the functional region through the pore, and ensuring that the barrier structure has a strong function of blocking the overflow of the sealing layer material.
  • 1 and 2 are schematic structural views of a package structure
  • FIG. 3 to FIG. 5 are schematic structural diagrams of a package structure according to an embodiment of the present application.
  • FIG. 6 to FIG. 9 are schematic structural diagrams of a package structure according to another embodiment of the present application.
  • FIG. 10 and FIG. 11 are schematic structural diagrams of a package structure according to another embodiment of the present application.
  • FIG. 12 to FIG. 15 are schematic structural diagrams showing a process of forming a package structure according to an embodiment of the present application.
  • FIG. 16 to FIG. 19 are schematic structural diagrams showing a process of forming a package structure according to another embodiment of the present application.
  • FIG. 20 and FIG. 21 are schematic structural diagrams showing a process of forming a package structure according to still another embodiment of the present application.
  • orientation words above, below, left and right are defined on the basis of the view shown in FIG. 1. It should be understood that the use of the orientation words should not limit the protection requested by the application. range.
  • FIG. 1 is a schematic plan view of a package structure
  • FIG. 2 is a schematic cross-sectional view of the structure taken along line AA1 of FIG. It should be noted that, for convenience of illustration and description, the top view of the package structure is not fully illustrated in FIG.
  • the package structure includes: a substrate 107 having a circuit wiring layer 106 having an opening 109 exposing the substrate 107; a conductive bump 103 on the circuit wiring layer 106; and flipping on the substrate 107
  • the image sensing chip 100 on the front side of the image sensing chip 100 has a photosensitive area a field 101 and a pad 102 surrounding the photosensitive region 101, and the pad 102 is electrically connected to the conductive bump 103; a glue located on the circuit wiring layer 106 and covering the sidewall of the image sensing chip 100 Layer 104; solder bumps 105 on the circuit wiring layer 106.
  • the material of the dispensing layer 104 easily overflows into the photosensitive region of the image sensing chip 100 through the slit during the process of forming the dispensing layer 104.
  • the material of the dispensing layer 104 causes contamination of the photosensitive region 101, which in turn results in poor performance of the package structure, affecting the performance and yield of the package structure.
  • the present application provides a package structure including a barrier structure on a substrate and surrounding the functional region, the barrier structure being adapted to block a material of the sealing layer from overflowing into a functional region, thereby avoiding material overflow of the sealing layer
  • the in-function area pollutes the functional area and improves the performance of the package structure.
  • FIG. 3 is a schematic top view of a package structure according to an embodiment of the present invention
  • FIG. 4 is a cross-sectional structural view of FIG. 3 along a direction of BB1
  • the package structure includes:
  • circuit wiring layer 203 disposed on the substrate
  • a semiconductor chip 205 flipped over the substrate, the semiconductor chip 205 is disposed on a first surface of the substrate with a functional region 206 and a pad 207 surrounding the functional region 206, and the pad 207 is The conductive bumps 204 are electrically connected;
  • sealing layer 210 on the substrate, the sealing layer 210 surrounding the semiconductor chip 205;
  • a blocking structure 208 is disposed on the substrate and on the circuit wiring layer 203, and the blocking structure 208 surrounds the functional region 206 to block the material of the sealing layer 210 from overflowing into the functional region 206.
  • the substrate includes a substrate 201 and a buffer layer 202 on the substrate 201, and the buffer layer 202 has an opening 209 extending through the buffer layer 202.
  • the functional area 206 is located above the opening 209.
  • the functional area 206 can receive external light through the opening 209;
  • the substrate 201 is a light-transmitting substrate or a PCB substrate.
  • the substrate 201 is a light-transmitting substrate.
  • the substrate is a PCB substrate
  • the PCB substrate is formed through the PCB substrate. a through hole, and the functional area is located above the through hole.
  • the substrate may also be a single layer structure including a substrate that is a light transmissive substrate or a PCB substrate.
  • the buffer layer 202 is advantageous for improving the adhesion between the circuit wiring layer 203 and the substrate 201, which in turn improves the adhesion between the substrate 201 and the semiconductor chip 205.
  • the material of the buffer layer 202 is an organic polymer photoresist, for example, an epoxy resin or an acrylic resin.
  • the circuit wiring layer 203 protrudes from the surface of the substrate.
  • the circuit wiring layer may also be located in the substrate, that is, the top of the circuit wiring layer is flush with the top of the substrate, or the top of the circuit wiring layer is lower than the substrate. top.
  • the circuit wiring layer 203 is located on the buffer layer 202; the position and number of the circuit wiring layer 203 correspond to the position and number of the pads 207.
  • the openings 209 have a plurality of discrete circuit wiring layers 203 on four sides, and each of the discrete circuit wiring layers 203 is electrically connected to one of the pads 202.
  • the circuit wiring layer 203 is electrically connected to the pad 207 through the conductive bumps 204.
  • the side of the opening has the same number of discrete circuit wiring layers.
  • the material of the circuit wiring layer 203 is Cu, Al, W, Sn, Au or Sn-Au alloy; the material of the conductive bump 204 is Au, Sn or Sn alloy, and the Sn alloy may be tin silver, tin Lead, tin-silver-copper, tin-silver-zinc or tin-zinc.
  • the conductive bumps 204 are square or spherical in shape. In this embodiment, the shape of the conductive bump 204 is square as an example.
  • the front surface of the semiconductor chip 205 has a functional area 206 and a pad 207 surrounding the functional area 206.
  • the functional area 206 is formed with a functional unit and an associated circuit connected to the functional unit.
  • the semiconductor chip 205 is an image sensing chip.
  • the functional area 206 is a photosensitive area, and the functional area 206 receives external light and converts the received light into an electrical signal, and the An electrical signal is transmitted to the external circuit through the pad 207 and the circuit wiring layer 203.
  • a region in which the semiconductor chip 205 is projected onto the substrate is referred to as a projection region.
  • the functional area 206 is located at an intermediate position of the semiconductor chip 205, the pad 207 is located at an edge position of the semiconductor chip 205, and the pad 207 is located on four sides of the functional area 206.
  • a rectangular distribution is formed, and a plurality of pads 207 are formed on each side, and the number of the pads 207 depends on the type of the semiconductor chip 205.
  • the pad 207 is connected to the circuit wiring layer 203, and the semiconductor chip 205 is connected to an external circuit through the circuit wiring layer 203.
  • the positions of the pads and functional regions may be flexibly adjusted according to actual needs.
  • the pads may be located on one side, two sides, or three sides of the functional area. .
  • the function of the conductive bumps 204 includes: on one hand, electrical connection between the circuit wiring layer 203 and the pads 207; on the other hand, since the conductive bumps 204 are disposed between the pads 207 and the circuit wiring layer 203, The distance between the functional region 206 and the circuit wiring layer 203 in the direction perpendicular to the surface of the substrate 201 is made larger, and the functional region 206 is prevented from touching the circuit wiring layer 203, thereby preventing the functional region 206 from being damaged. In this embodiment, the thickness of the conductive bump 204 is greater than the thickness of the photosensitive element in the functional region 206.
  • the package structure further includes: a solder bump 211 on the substrate, the solder bump 211 being electrically connected to the circuit wiring layer 203.
  • the solder bumps 211 are located on the circuit wiring layer 203, and the solder bumps 211 electrically connect the pads 207 to external circuits, thereby allowing the semiconductor chip 205 to operate normally.
  • the material of the solder bump 211 is gold, tin or tin alloy.
  • the shape of the top surface of the solder bump 211 is curved.
  • the function of the sealing layer 210 is that, on the one hand, the sealing layer 210 places the semiconductor chip 205 in a closed environment, preventing the semiconductor chip 205 from being ineffective under the influence of the external environment, preventing moisture from intruding from the outside, and External electrical insulation; on the other hand, the sealing layer 210 functions to support the semiconductor chip 205, and the semiconductor chip 205 is fixed for circuit connection.
  • the material of the sealing layer 210 is a resin or a solder resist ink material such as an epoxy resin or an acrylic resin.
  • the sealing layer 210 is located on the sidewall of the semiconductor chip 205, the sealing layer 210 is also located on the substrate and the circuit wiring layer 203, and the top of the sealing layer 210 is lower than the bottom surface of the semiconductor chip 205. Or, the top of the sealing layer 210 is flush with the bottom surface of the semiconductor chip 205. It should be noted that the bottom surface refers to the surface opposite to the front surface of the semiconductor chip 205.
  • the sealing layer 210 and the solder bumps 211 are separated from each other.
  • the solder bumps may also be located within the sealing layer and through the sealing layer, in other words, the solder bumps are located on the substrate and outside the semiconductor chip.
  • the sealing layer 210 covers the substrate outside the projection area and the circuit wiring layer 203, and also covers the sidewall surface of the semiconductor chip 205 and the bottom surface; the solder bump 211 is located in the sealing The sealing layer 210 is penetrated in the layer 210.
  • the blocking structure 208 is located on the substrate and on the circuit wiring layer 203, and also surrounds the functional area 206.
  • the blocking structure 208, the semiconductor chip 205, the substrate, and the circuit wiring layer 203 enclose a closed area, so that the sealing layer 210 material is difficult to enter the enclosed area, thereby effectively blocking the material of the sealing layer 210 from entering the functional area 206, thereby avoiding the function.
  • Area 206 causes pollution.
  • the conductive bumps 204 on the substrate or circuit wiring layer 203 enclose a designated area, and the blocking structure 208 is located in the designated area; it is also considered that the blocking structure 208 is located in the aforementioned projection area. And also between the conductive bump 204 and the functional area 206.
  • the top surface of the blocking structure 208 is in contact with the front surface of the semiconductor chip 205, and the bottom surface of the blocking structure 208 is in contact with the circuit wiring layer 203 and the substrate.
  • the blocking structure 208 is located on the circuit wiring layer 203 and the buffer layer 202; the top surface of the blocking structure 208 is The front surface of the semiconductor chip 205 is in contact with the bottom surface of the blocking structure 208 in contact with the circuit wiring layer 203 and the buffer layer 202.
  • the thickness of the blocking structure 208 on the circuit wiring layer 203 is a first thickness, and a distance between the front surface of the semiconductor chip 205 and the circuit wiring layer 203 is equal to the first thickness; on the substrate
  • the thickness of the blocking structure 208 is a second thickness, and a distance between the front surface of the semiconductor chip 205 and the substrate is equal to the second thickness.
  • the thickness of the blocking structure 208 on the buffer layer 202 is a second thickness, and the distance between the front surface of the semiconductor chip 205 and the buffer layer 202 is equal to the second thickness.
  • the distance between the front surface of the semiconductor chip 205 and the circuit wiring layer 203 refers to the minimum distance between the front surface of the semiconductor chip 205 and the surface of the circuit wiring layer 203; the semiconductor chip The distance between the buffer layers 202 on the front side of the 205 refers to the minimum distance between the front surface of the semiconductor chip 205 and the surface of the buffer layer 202.
  • the top surface width dimension of the blocking structure 208 is equal to the bottom surface width dimension in a direction parallel to the substrate surface.
  • the top surface width dimension of the blocking structure may also be smaller than the bottom surface width dimension, so that the area of the blocking structure contacting the front surface of the semiconductor chip is small. Thereby saving the volume of the semiconductor chip.
  • the shape of the blocking structure 208 is a closed loop.
  • the cross-sectional shape of the barrier structure 208 is a square ring shape, a circular ring shape, an elliptical ring shape or an irregular shape ring shape in a direction parallel to the surface of the substrate.
  • the cross-sectional shape of the blocking structure 208 is a square ring shape as an example.
  • the shape of the blocking structure 208 may also match the shape of the designated area surrounded by the conductive bumps 204.
  • the shape of the area surrounded by the conductive bumps 204 is square.
  • the cross-sectional shape of the conductive bump 208 is a square ring shape; when the shape of the region surrounded by the conductive bump 204 is a circular shape, the cross-sectional shape of the conductive bump 208 is a circular ring shape.
  • the blocking structure 208 and the circuit wiring layer 203 are electrically insulated from each other.
  • the blocking structure 208 is a single layer structure, and the material of the blocking structure is an insulating material.
  • the barrier structure may also be a laminate structure.
  • the barrier structure having a stacked structure may include: an underlying barrier layer in contact with the substrate and the circuit wiring layer, and a top barrier layer in contact with the front surface of the semiconductor chip, wherein the material of the underlying barrier layer is an insulating material
  • the material of the top barrier layer is a conductive material or an insulating material.
  • the conductive material comprises copper, aluminum, tungsten or tin
  • the insulating material is a photosensitive adhesive
  • the photosensitive adhesive comprises epoxy resin, acrylic resin, polyimide glue or benzocyclobutene glue.
  • the blocking structure 208 and the conductive bumps 204 are separated from each other, and a sidewall of the blocking structure 208 and the sidewall of the conductive bump 204 have a certain distance, so that the blocking structure 208 does not interfere with the electrical connection properties of the conductive bumps 204.
  • the material of the barrier structures 208 can be an insulating material, and the material of the barrier structures 208 can also include conductive materials.
  • the sidewall of the barrier structure is in contact with the sidewall of the conductive bump, since the shape of the barrier structure is a closed loop, in order to prevent the barrier structure from connecting the mutually separated conductive bumps This results in an unnecessary electrical connection of the conductive bumps, the material of which is an insulating material.
  • the blocking structure 208 is located in the conductive bump 204 Within the designated area, that is, the blocking structure 208 is located between the conductive bump 204 and the functional area 206 such that the blocking structure 208 provides protection to the functional area 206, preventing the sealing layer 210 material or other materials.
  • the function area 206 is prevented from being contaminated by the gap between the adjacent conductive bumps 204, thereby improving the yield and electrical properties of the package structure.
  • the conductive bumps 204 correspond to the locations of the pads 207 on the semiconductor chip 205, since the blocking structures 208 are located between the conductive bumps 204 and the functional regions 206, corresponding to the blocking The structure 208 is located between the pad 207 and the functional region 206, so there is no need to increase the distance between the pad 207 and the sidewall of the semiconductor chip 205 for placing the blocking structure 208, so that the semiconductor chip 205 has a small volume. Meet the development trend of miniaturization and miniaturization of package structure.
  • FIG. 6 to FIG. 9 are schematic structural diagrams of a package structure according to another embodiment of the present application, wherein FIG. 6 is a schematic top view of the package structure, and FIG. 7 is a cross-sectional structural view of FIG. 6 along the CC1 direction.
  • the package structure includes:
  • circuit wiring layer 303 disposed on the substrate
  • a semiconductor chip 305 flipped over the substrate, the semiconductor chip 305 being disposed on a first surface of the substrate with a functional region 306 and a pad 307 surrounding the functional region 306, and the pad 307 and the The conductive bumps 304 are electrically connected;
  • sealing layer 310 on the substrate, the sealing layer 310 surrounding the semiconductor chip 305;
  • a blocking structure 308 is disposed on the circuit wiring layer 303 and on the substrate, and the blocking structure 308 surrounds the functional region 306 to block the material of the sealing layer 310 from overflowing into the functional region 306.
  • the substrate 301 includes a substrate 301 and a buffer layer 302 on the substrate 301, and the buffer layer 302 has an opening 309 extending through the buffer layer 302.
  • the substrate 301 For a description of the substrate 301, the buffer layer 302, the opening 309, the circuit wiring layer 303, the conductive bump 304, the semiconductor chip 305, the functional region 306, and the pad 307, please refer to the description of the previous embodiment, and details are not described herein again.
  • the blocking structure 308, the semiconductor chip 305, the substrate, and the circuit wiring layer 303 enclose a closed region.
  • the conductive layer on the circuit wiring layer 303 The bump 304 encloses a designated area
  • the blocking structure 308 is located outside the designated area
  • the blocking structure 308 is also located between the semiconductor chip 305 and the circuit wiring layer 303.
  • the sealing layer 310 is located on the buffer layer 302 and on the sidewall of the semiconductor chip 305, and on the substrate and the circuit wiring layer 303.
  • the area of the semiconductor chip 305 projected on the substrate is a projection area
  • the blocking structure 308 is located in the projection area.
  • the top of the blocking structure 308 is in contact with the front surface of the semiconductor chip 305
  • the bottom surface of the blocking structure 308 is in contact with the circuit wiring layer 303 and the substrate. Since the substrate includes the substrate 301 and the buffer layer 302, in the embodiment, the bottom surface of the blocking structure 308 is in contact with the circuit wiring layer 303 and the buffer layer 302.
  • the material and structure of the blocking structure 308 can be referred to the description of the previous embodiment, and will not be described herein.
  • the blocking structure 308 and the conductive bump 304 are separated from each other; in other embodiments, the blocking structure may also be in contact with the sidewall of the conductive bump, and the blocking structure
  • the material is an insulating material.
  • the package structure further includes: a solder bump 311 on the substrate, the solder bump 311 being electrically connected to the circuit wiring layer 303.
  • the solder bump 311 is located on the circuit wiring layer 303, and the sealing layer 310 and the solder bump 311 are separated from each other.
  • the solder bumps 311 may also be located on the substrate and on the outside of the semiconductor chip.
  • the blocking structure 308 can not only block the material of the sealing layer 310 or other materials from entering the functional area 306, but also prevent the functional area 306 from being contaminated; the blocking structure 308 can also be used for the conductive bumps 304.
  • the sealing layer 310 material or other materials are prevented from contaminating the conductive bumps 304, and the conductive properties of the conductive bumps 304 are prevented from being damaged, thereby further improving the performance of the package structure.
  • the conductive bumps 304 on the circuit wiring layer 303 enclose a designated area, and the blocking structure 308 is located outside the designated area;
  • the blocking structure includes: a first blocking structure 318 and a side of the first blocking structure 318 and immediately adjacent to the first a second blocking structure 328 of the blocking structure 318, wherein a region of the semiconductor chip 305 projected on the substrate is a projection area, and the first blocking structure 318 is located outside the projection area.
  • the second blocking structure 328 is located within the projection area.
  • a top surface of the second blocking structure 328 is in contact with a front surface of the semiconductor chip 305, and a bottom surface of the second blocking structure 328 is in contact with the circuit wiring layer 303 and the substrate. Specifically, a bottom surface of the second blocking structure 328 is in contact with the circuit wiring layer 303 and the buffer layer 302.
  • the thickness of the second blocking structure 328 on the substrate is a first thickness
  • the semiconductor chip 305 a distance between the front surface and the substrate is equal to the first thickness
  • a thickness of the second blocking structure 328 on the circuit wiring layer 303 is a third thickness
  • a front surface of the semiconductor chip 305 and the circuit wiring layer The distance between 303 is equal to the third thickness.
  • the thickness of the second blocking structure 328 on the buffer layer 302 is a first thickness
  • the distance between the front surface of the semiconductor chip 305 and the buffer layer 302 is equal to the first thickness.
  • the sealing layer 310 is located on the first blocking structure 318 in addition to the sidewall of the semiconductor chip 305.
  • the sealing layer 310 is located not only on the top and sidewalls of the first barrier structure 318 but also on the circuit wiring layer 303 and on the buffer layer 302.
  • the first blocking structure 318 may function as a sealing layer as compared to a solution that does not have the first blocking structure, such that the first blocking structure 318 occupies a portion of the sealing layer spatial position, thereby further reducing the The sealing layer 310 material contaminates the functional region 306 and also correspondingly further prevents the sealing layer 310 material from contaminating the conductive bumps 304, further improving the performance of the package structure.
  • the thickness of the first blocking structure 318 on the substrate is a second thickness
  • the thickness of the second blocking structure 328 on the substrate is a first thickness
  • the first The second thickness is equal to the first thickness. That is, the top of the first blocking structure 318 on the substrate is flush with the top of the second blocking structure 328, and correspondingly, the top of the first blocking structure 318 on the circuit wiring layer 303 and the first The top of the second blocking structure 328 is flush.
  • the sealing layer 319 is located on the top of the first blocking structure 318 and on the side of the semiconductor chip 305. In other embodiments, the sealing layer may be located on the circuit wiring layer and on the substrate in addition to the top of the first blocking structure and the sidewall of the semiconductor chip.
  • the thickness of the first blocking structure 318 on the substrate For a second thickness, the thickness of the second barrier structure 328 on the substrate is a first thickness and the second thickness is greater than the first thickness. That is, the top of the first blocking structure 318 on the substrate is higher than the top of the second blocking structure 328, and correspondingly, the top of the first blocking structure 318 on the circuit wiring layer 303 is higher than the second blocking structure 328.
  • the top portion causes the first blocking structure 318 to cover a portion of the sidewall of the semiconductor chip 305.
  • the sealing layer 310 is located on top of the first blocking structure 318 and on sidewalls of the semiconductor chip 305. In other embodiments, the sealing layer may also be on the circuit wiring layer and on the substrate. Since the first blocking structure 318 covers a portion of the sidewall of the semiconductor chip 305, the ability of the first blocking structure 318 to block the material of the sealing layer 310 from spilling into the functional region 306 is further improved.
  • the blocking structure 308 by disposing the blocking structure 308 outside the designated area surrounded by the conductive bumps 304, it is not necessary to protect the functional area 306 from contamination while between the conductive bumps 304 and the functional areas 306.
  • the spatial position is reserved for the blocking structure 308, and thus the distance between the conductive bump 304 and the functional region 306 can be reduced.
  • the distance between the blocking structure 308 and the functional area 306 is far away, thereby preventing the blocking structure 308 from causing pollution or damage to the functional area 306, and further improving the performance of the packaging structure.
  • the first blocking structure 318 located outside the projection area occupies a partial spatial position of the sealing layer 310, further reducing the possibility of the sealing layer 310 material spilling into the functional area 306; and, the first blocking structure 318 and the The two barrier structures 328 can all function to block the material of the sealing layer 310 from overflowing into the functional region 306. Therefore, the functional region 306 in the package structure provided by the embodiment can be better protected.
  • FIG. 10 and FIG. 11 are schematic structural diagrams of a package structure according to another embodiment of the present application, where the package structure includes:
  • circuit wiring layer 403 disposed on the substrate
  • a semiconductor chip 405 flipped over the substrate the semiconductor chip 405 is disposed on a first surface of the substrate with a functional region 406 and a pad 407 surrounding the functional region 406, and the pad 407 is The conductive bumps 404 are electrically connected;
  • sealing layer 410 on the substrate, the sealing layer 410 surrounds the semiconductor chip 405;
  • a blocking structure 408 is disposed on the substrate and on the circuit wiring layer 403, and the blocking structure 408 surrounds the functional region 406 to block the material of the sealing layer 410 from overflowing into the functional region 406.
  • the substrate includes a substrate 401 and a buffer layer 402 on the substrate 401, and the buffer layer 402 has an opening 409 penetrating the buffer layer 402.
  • the area of the semiconductor chip 405 projected on the substrate is a projection area
  • the blocking structure 408 is located outside the projection area.
  • the blocking structure 408 is located in the The semiconductor chip 405 is outside and surrounds the semiconductor chip 405.
  • the top of the blocking structure 408 is higher than the first surface of the semiconductor chip 405. Also, the distance between the top surface of the blocking structure 408 and the first surface of the semiconductor chip 405 is not too small in a direction perpendicular to the surface of the substrate. If the distance is too small, the sealing layer 410 material is more likely to overflow into the functional region 406 via the void between the barrier structure 408 and the semiconductor chip 405, such that the barrier structure 408 blocks the leakage of the sealing layer 410 material from being weak.
  • the distance between the top surface of the blocking structure 408 and the first surface of the semiconductor chip 405 is 2 micrometers to 10 micrometers in a direction perpendicular to the surface of the substrate.
  • the barrier structure 408 has a gap with the sidewall of the semiconductor chip 405 in a direction parallel to the surface of the substrate. If the width dimension of the gap is too large, the material of the sealing layer 410 tends to overflow into the functional region 406 via the gap. To this end, the gap has a width dimension equal to 2 micrometers to 10 micrometers in a direction parallel to the surface of the substrate.
  • the blocking structure 408 may also cover the sidewall of the semiconductor chip 405, that is, the gap may have a width dimension of zero.
  • the sealing layer 410 is located on the top of the blocking structure 408 in addition to the sidewalls of the semiconductor chip 405. In addition, the sealing layer 410 may also be located on the circuit wiring layer 403 and on the buffer layer 402.
  • the package structure further includes: a solder bump 411 on the substrate, the solder bump 411 being electrically connected to the circuit wiring layer 403.
  • the solder bumps 411 are located on the circuit wiring layer 403.
  • the blocking structure 408 covers the circuit wiring layer 403 to And a buffer layer 402, the solder bump 411 is located in the blocking structure 408 and penetrates the blocking structure 408, and the sealing layer 410 is located at the top of the blocking structure 408 portion.
  • the sealing layer may also cover the entire top of the barrier structure, and the solder bumps also penetrate the sealing layer.
  • the blocking structure 408 is located on a portion of the circuit wiring layer 403 and on a portion of the substrate, the solder bumps 411 and the blocking structure 408 are separated from each other, and the sealing layer 410 is located on top of the blocking structure 408.
  • the sealing layer may also cover the circuit wiring layer and the substrate, the solder bumps being located within the sealing layer and penetrating the sealing layer.
  • the shape of the blocking structure 408 is a closed shape, and the material of the blocking structure 408 is an insulating material or a conductive material.
  • the material and structure of the blocking structure 408 reference may be made to the corresponding description of the foregoing embodiment, and no longer Narration.
  • the top of the blocking structure is higher than the first surface of the semiconductor chip, so that the blocking structure can block the material of the sealing layer from overflowing into the functional area, thereby preventing the functional area from being contaminated, so that the package
  • the structure has higher performance and the yield of the package structure is improved.
  • the blocking structure 408 is located outside the projection area on which the semiconductor chip 405 is projected on the substrate, there is no need to reserve a spatial position in the semiconductor chip 405 for the blocking structure 408; and the blocking structure 408 is opposite to the substrate and the The flip-chip between the semiconductor chips 405 has no effect, so the blocking structure 408 does not affect the spatial layout between the substrate and the semiconductor chip 405.
  • the present application further provides a packaging method for forming the foregoing package structure, comprising: providing a plurality of individual semiconductor chips, the first surface of the semiconductor chip having a functional area and a pad surrounding the functional area; providing a substrate, The substrate includes a flip-chip region and a scribe line region between adjacent flip-chip regions; a plurality of discrete circuit wiring layers are disposed on the flip-chip region of the substrate; and the semiconductor chip is flipped on the substrate Above the flip-chip region, and the pad and the circuit wiring layer are electrically connected by conductive bumps; a sealing layer is formed on the substrate, and the sealing layer surrounds the semiconductor chip; and the sealing layer is formed Thereafter, the substrate is cut along the scribe line region to form a plurality of single package structures; wherein, before forming the sealing layer, further comprising: at the base A barrier structure is formed on the board, the barrier structure surrounding the functional area to block the material of the sealing layer from overflowing into the functional area.
  • the barrier structure since a barrier structure is formed on the substrate before forming the sealing layer, the barrier structure surrounds the functional region and is adapted to block the material of the sealing layer from overflowing into the functional region; therefore, in forming the sealing layer During the process, the barrier structure protects the functional area and prevents the sealing layer material from overflowing into the functional area, so that the performance and yield of the formed package structure are improved.
  • FIG. 12 to FIG. 15 are schematic diagrams showing the structure of a package structure formed according to an embodiment of the present application.
  • a number of individual semiconductor chips 205 are provided having a functional area 206 on the front side and pads 207 surrounding the functional area 206.
  • the semiconductor chip 205 is an image sensing chip, and the corresponding functional area 206 is a photosensitive area; the semiconductor chip 205 is formed by cutting a wafer to be packaged, and the wafer to be packaged has a plurality of A semiconductor chip 205 arranged in a matrix.
  • conductive bumps 204 are formed on the pads 207.
  • the position and number of the conductive bumps 204 correspond to the position and number of the pads 207; the shape of the conductive bumps 204 is square or spherical.
  • the conductive bumps 204 have a square shape, and the conductive bumps 204 are formed by a screen printing process.
  • the conductive bumps may also have a spherical shape, and the conductive bumps may be formed by a ball bonding process.
  • the conductive bumps may also be formed by a combination of a screen printing process and a reflow process.
  • the conductive bumps may not be formed on the pads, and the conductive bumps may be formed on circuit wirings of the subsequently provided substrate.
  • a substrate which includes a flip-chip region I and a dicing street region II between adjacent flip-chip regions I, on which a circuit wiring layer 203 is disposed.
  • the area of the flip-chip area I and the scribe line area II can be set according to actual packaging process requirements.
  • the substrate includes a substrate 201 and a buffer layer 202 on the substrate 201.
  • An opening 209 penetrating the buffer layer 202 is formed in the buffer layer 202.
  • the material of the substrate 201 reference may be made to the corresponding description in the foregoing package structure.
  • the material of the buffer layer 202 is an organic polymer photoresist
  • the process of forming the buffer layer 202 includes: forming a buffer film on the substrate 201; exposing the buffer film and The development process forms a buffer layer 202 having the opening 209.
  • the circuit wiring layer 203 protrudes from the surface of the substrate.
  • the step of forming the circuit wiring layer 203 includes: forming a circuit layer on the buffer layer 202 and at the bottom and sidewalls of the opening 209; patterning the circuit layer to remove the circuit layer on the bottom and sidewalls of the opening 209, A plurality of discrete circuit wiring layers 203 are formed on the buffer layer 202.
  • the circuit wiring layer may also be located in the substrate, that is, the top of the circuit wiring layer is flush with the top of the substrate, or the top of the circuit wiring layer is lower than the top of the substrate.
  • a blocking structure 208 is formed on the circuit wiring layer 203 and on the substrate.
  • the blocking structure 208 is formed on the circuit wiring layer 203 and the buffer layer 202.
  • the shape of the blocking structure 208 is a closed loop.
  • the cross-sectional shape of the barrier structure 208 is a square ring shape, a circular ring shape, an elliptical ring shape or an irregular shape ring shape in a cross section parallel to the surface direction of the substrate.
  • the semiconductor chip 205 (refer to FIG. 12) is flipped over the substrate flip-chip region I, and the pad 207 is electrically connected to the circuit wiring layer 203 through the conductive bump 204; After the chip 205 is flipped over the substrate flip-chip area I, the conductive bumps 204 enclose a designated area, and the blocking structure 208 is located in the designated area.
  • the process step of forming the barrier structure 208 includes: forming a barrier film on the circuit wiring layer 203 and on the substrate; exposing and developing the barrier film to form the blocking structure 208; or The barrier film is etched to form the barrier structure 208.
  • the blocking structure 208 is a single layer structure, and the material of the blocking structure 208 is an insulating material.
  • the blocking structure may further be a laminated structure including an underlying barrier layer in contact with the circuit wiring layer and the substrate, and a front surface of the semiconductor chip The top barrier layer of the touch, wherein the material of the underlying barrier layer is an insulating material, and the material of the top barrier layer is an insulating material or a conductive material, and the insulating material is a photosensitive adhesive.
  • the blocking structure 208 and the conductive bump 204 are separated from each other, the material of the blocking structure 208 includes an insulating material, and the material of the blocking structure 208 may further include a conductive material.
  • the material of the barrier structures when the sidewalls of the barrier structure are in contact with the sidewalls of the conductive bumps, the material of the barrier structures is an insulating material in order to ensure electrical insulation properties between adjacent conductive bumps.
  • the semiconductor chip 205 is flipped over the substrate flip-chip region I, and the pad 207 and the circuit wiring layer 203 are electrically connected by the conductive bumps 204.
  • each of the pads 207 corresponds to a discrete conductive bump 204. It is also considered that each of the pads 207 corresponds to a discrete circuit wiring layer 203.
  • the step of flipping the semiconductor chip 205 over the substrate flip-chip region I includes: placing the semiconductor chip 205 on the substrate flip-chip region I, and the pad 207 passes the conductive bump 204 is connected to the circuit wiring layer 203; the conductive bump 204 is soldered such that the pad 207 is electrically connected to the circuit wiring layer 203 through the conductive bump 204.
  • the process used in the solder bonding process is a eutectic bonding process, an ultrasonic thermocompression bonding process or a thermocompression bonding process.
  • the thickness of the conductive bumps 204 between the substrate and the front surface of the semiconductor chip 205 is greater than or equal to the thickness of the barrier structure 208; and during the solder bonding process, The thickness of the conductive bump 204 between the substrate and the front surface of the semiconductor chip 205 is reduced such that the top surface of the blocking structure 208 is in contact with the front surface of the semiconductor chip 205.
  • the conductive bump 204 After flipping the semiconductor chip 205 over the substrate flip-chip area I, the conductive bump 204 encloses a designated area, and the blocking structure 208 is located in the designated area; After the processing, the blocking structure 208, the semiconductor chip 205, the circuit wiring layer 203, and the substrate enclose a closed region, thereby preventing the subsequently formed sealing layer material from overflowing into the functional region 206.
  • the difference between the thicknesses of 208 should not be too large. If the difference is too large, after the solder bonding process, there is an aperture between the blocking structure 208 and the front side of the semiconductor chip 205 through which the subsequently formed sealing layer diffuses into the functional region 206.
  • a sealing layer 210 is formed on the substrate, and the sealing layer 210 surrounds the semiconductor chip 205.
  • the sealing layer 210 is used to seal the semiconductor chip 205 to prevent the external environment from adversely affecting the semiconductor chip 205.
  • the sealing layer 210 is also located on a portion of the circuit wiring layer 203.
  • the sealing layer may also cover the back surface of the semiconductor chip, and further, the sealing layer may cover the entire substrate surface exposed by the semiconductor chip.
  • the sealing layer 210 is formed by a dispensing process.
  • the sealing layer may also be formed using a molding process, wherein the molding process is a transfer molding or an injection molding process.
  • the blocking structure 210 is adapted to block material of the sealing layer 210 from overflowing into the functional region 206, avoiding the sealing layer 210 material from passing through adjacent conductive bumps 204. The gap between them enters the functional area 206, preventing the functional area 206 from being contaminated, thereby improving the performance and yield of the formed package structure.
  • a step further includes forming solder bumps 211 on the substrate, the solder bumps 211 being electrically connected to the circuit wiring layer 203.
  • a solder bump 211 is formed on the circuit wiring layer 203, and the solder bump 211 electrically connects the pad 207 to an external circuit, thereby causing the semiconductor chip 205 to operate normally.
  • solder bumps 211 and the sealing layer 210 are separated from each other. In other embodiments, the solder bumps may also be located within the sealing layer and through the sealing layer.
  • the subsequent process steps further include cutting the substrate along the scribe line region II to form a plurality of individual package structures as shown in Figure 4.
  • FIG. 16 to FIG. 19 are schematic structural diagrams of a package structure forming process according to another embodiment of the present application.
  • the conductive bumps on the circuit wiring layer enclose a designated area
  • the formed blocking structure is located outside the designated area and surrounds the conductive bumps
  • the The blocking structure is also located between the semiconductor chip and the circuit wiring layer.
  • a substrate including a flip-chip region I and a dicing region II between adjacent flip-chip regions I having a circuit wiring layer 303 thereon; formed on the circuit wiring layer 303 a conductive bump 304; forming a blocking structure 308 on the substrate, the blocking structure 308 surrounding the guiding Electrical bumps 304.
  • the substrate includes a substrate 301 and a buffer layer 302 on the substrate 301 having an opening 309 extending through the buffer layer 302.
  • the conductive bumps 304 on the circuit wiring layer 303 enclose a designated area, and the formed blocking structure 308 is located outside the designated area.
  • the material and structure of the blocking structure 308 reference may be made to the corresponding description of the foregoing embodiments, and details are not described herein again.
  • the conductive bump may be formed after the barrier structure is formed.
  • conductive bumps may not be formed on the circuit wiring layer, and the conductive bumps may be formed on pads of the subsequently provided semiconductor chip.
  • a semiconductor chip 305 is provided, the front surface of the semiconductor chip 305 having a functional area 306 and a pad 307 surrounding the functional area 306; the semiconductor chip 305 is flipped over the substrate flip-chip area I, The electrical connection between the pad 307 and the circuit wiring layer 303 is performed by the conductive bumps 304.
  • the step of flipping the semiconductor chip 305 over the substrate flip-chip region I includes: placing the semiconductor chip 305 on the substrate flip-chip region I, and the pad 307 passes through the conductive bump 304 is connected to the circuit wiring layer 303; the conductive bump 304 is subjected to a solder bonding process such that the pad 307 is electrically connected to the circuit wiring layer 303 through the conductive bump 304.
  • the thickness of the conductive bump 304 between the substrate and the front surface of the semiconductor chip 305 is greater than or equal to the thickness of the blocking structure 306; and in the solder bonding During processing, the thickness of the conductive bumps 304 between the substrate and the front side of the semiconductor chip 305 is reduced such that the top surface of the blocking structure 308 is in contact with the front surface of the semiconductor chip 305.
  • the top surface of the blocking structure 308 is in contact with the front surface of the semiconductor chip 305, and thus the blocking structure 308
  • the semiconductor chip 305, the substrate, and the circuit wiring layer 303 enclose a closed region.
  • the conductive bumps 304 enclose a designated area, and the blocking structure 308 is located outside the designated area, and The blocking structure 308 is located in the projection area of the semiconductor chip 305 projected on the substrate.
  • the blocking structure 308 is located outside the designated area, and the blocking structure 308 includes: a first blocking structure 318 and a side of the first blocking structure 318 and next to the a second blocking structure 328 of the first blocking structure 318; after the semiconductor chip 305 is flipped over the substrate flip-chip area I, the area of the semiconductor chip 305 projected on the substrate is a projection area, the first a blocking structure 318 is located outside the projection area, and the second blocking structure 328 is located in the projection area; correspondingly, the semiconductor chip 305 is formed before being flipped over the substrate flip-chip area I a blocking structure 308; and after flipping the semiconductor chip 305 over the substrate flip-chip region I, a top surface of the second blocking structure 328 is in contact with a front surface of the semiconductor chip 305; During processing, the thickness of the conductive bumps 304 between the substrate and the front surface of the semiconductor chip 305 is reduced, such that the top surface of the second blocking structure 328 is in contact with the front
  • the first blocking structure 318 when the thickness of the first blocking structure 318 is equal to the thickness of the second blocking structure 328, the top of the first blocking structure 318 is flush with the front surface of the semiconductor chip 305; when the second blocking structure When the thickness of 328 is greater than the thickness of the first barrier structure 318, the first barrier structure 318 also covers a portion of the sidewall of the semiconductor chip 305 after the solder bonding process.
  • a sealing layer 310 is formed on the substrate, the sealing layer 310 surrounding the shadow semiconductor chip 305; a solder bump 311 is formed on the substrate, the solder bump 311 and the circuit wiring layer 303 electrical connection.
  • the sealing layer 310 is further located on the circuit wiring layer 303 and a side surface of the semiconductor chip 305; the sealing layer 310 is formed by a dispensing process or a plastic sealing process.
  • solder bump 311 and the sealing layer 310 are separated from each other, and the solder bump 311 is located on the substrate and located outside the semiconductor chip 305. In other embodiments, the solder bumps may also be located within the sealing layer and through the sealing layer.
  • the blocking structure 308 blocks the material of the sealing layer 310 such that the material of the sealing layer 310 cannot overflow into the functional region 306, thereby avoiding the functional region 306.
  • the blocking structure 308 also protects the conductive bumps 304 from the contamination of the conductive bumps 304 by the sealing layer 310 material, and prevents the sealing layer 310 material from interfering with the conductive properties of the conductive bumps 304.
  • the blocking structure 308 includes a first blocking structure 318 to And a second blocking structure 328 next to the first blocking structure 318.
  • the top surface of the second blocking structure 328 is in contact with the front surface of the semiconductor chip 305, and the top of the first blocking structure 318 is flush with the front surface of the semiconductor chip 305; or the top of the first blocking structure 318 is higher than the front surface of the semiconductor chip 305.
  • the first blocking structure 318 also covers the sidewall of the semiconductor chip 305.
  • the sealing layer 310 is formed on the top of the first blocking structure 318, and the sealing layer 310 may also be located on the circuit wiring layer.
  • the first barrier structure 318 can function as the sealing layer 310 such that the first barrier structure 318 occupies a spatial location where the sealing layer 310 should otherwise be formed, thereby further reducing the risk of the sealing layer 310 material spilling into the functional region 306.
  • the subsequent process steps further include cutting the substrate along the scribe line region II to form a plurality of single package structures as shown in Figures 7 and 9.
  • FIG. 20 and FIG. 21 are schematic structural diagrams showing a process of forming a package structure according to another embodiment of the present application.
  • the difference from the foregoing embodiment is that, in this embodiment, the area where the semiconductor chip is projected on the substrate is a projection area, the formed blocking structure is located outside the projection area, and the top of the blocking structure is higher than the front surface of the semiconductor chip.
  • a substrate including a flip-chip region I and a dicing street region II between adjacent flip-chip regions I having a circuit wiring layer 403 thereon;
  • a conductive bump 404 is formed on the layer 403;
  • a blocking structure 408 is formed on the circuit wiring layer 403 and on the substrate; and
  • a semiconductor chip 405 is provided.
  • the front surface of the semiconductor chip 405 has a functional region 406 and a pad surrounding the functional region 406.
  • the semiconductor chip 405 is flipped over the substrate flip-chip area I, and the pad 407 and the circuit wiring layer 403 are electrically connected by the conductive bumps 404.
  • the substrate includes a substrate 401 and a buffer layer 402 on the substrate 401.
  • An opening 409 is formed in the buffer layer 420 through the buffer layer 402.
  • the area projected by the semiconductor chip 405 on the substrate is a projection area
  • the blocking structure 408 is located outside the projection area.
  • the top of the blocking structure 408 is higher than the front surface of the semiconductor chip 405.
  • the barrier structure 408 and the sidewall of the semiconductor chip 405 have a gap; since a sealing layer covering the sidewall of the semiconductor chip 405 is formed on the barrier structure 408, if If the width dimension of the gap is too large, the material of the sealing layer can easily escape into the functional area 406 via the gap.
  • the gap has a width dimension of 2 ⁇ m to 10 ⁇ m in a direction parallel to the surface of the substrate.
  • the top of the blocking structure 408 is higher than the front surface of the semiconductor chip 405.
  • the distance between the top of the blocking structure 408 and the front surface of the semiconductor chip 405 should not be too small.
  • the distance between the top surface of the blocking structure 406 and the front surface of the semiconductor chip 405 is 2 micrometers to 10 micrometers in a direction perpendicular to the surface of the substrate.
  • the gap width between the barrier structure and the sidewall of the semiconductor chip may also be 0, that is, the barrier structure covers the sidewall of the semiconductor chip.
  • the barrier structure 408 is formed as an example before the semiconductor chip 405 is flipped over the substrate flip-chip region I, and the process of the barrier structure 408 is avoided from being introduced into the semiconductor chip 405. Unnecessary damage.
  • the blocking structure may also be formed after flipping the semiconductor chip over the substrate flip-chip region.
  • the area of the blocking structure 408 covering the circuit wiring layer 403 can be flexibly adjusted according to requirements.
  • a sealing layer 410 is formed on the substrate, the sealing layer 410 surrounding the semiconductor chip 405; a solder bump 411 is formed on the substrate, the solder bump 411 and the circuit wiring layer 403 Electrical connection.
  • the sealing layer 410 is also located on top of the blocking structure 408, and the blocking structure 408 is adapted to block the material overflowing functional area of the sealing layer 410 during the process of forming the sealing layer 410. Within 406, functional area 406 is protected from contamination.
  • the sealing layer may also be located on the sidewall of the blocking structure, and may also be on the circuit wiring layer and on the substrate.
  • the blocking structure 408 and the soldering protrusions 411 are separated from each other.
  • the weld projections may also be located within the barrier structure and extend through the barrier structure.
  • the subsequent process steps include cutting the substrate along the scribe line region II to form a plurality of single package structures as shown in Figure 11.
  • the encapsulation method provided by the present application forms a barrier structure for protecting the functional region before forming the sealing layer, and the barrier structure is adapted to block the material of the sealing layer from overflowing into the functional region, thereby preventing the functional region from being affected. Contamination increases the performance and yield of the resulting package structure.

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Abstract

一种封装结构以及封装方法，封装结构包括：基板（201，202）；设置在所述基板（201，202）上的电路布线层（203）；位于所述电路布线层（203）上的导电凸块（204）；倒装在所述基板（201，202）上方的半导体芯片（205），所述半导体芯片（205）朝向所述基板（201，202）的第一表面上设置有功能区域（206）以及环绕所述功能区域（206）的分立的焊盘（207），且所述焊盘（207）与所述导电凸块（204）电连接；位于所述基板（201，202）上的密封层（210），所述密封层（210）包围所述半导体芯片（205）；位于所述基板（201，202）上的阻挡结构（208），所述阻挡结构（208）环绕所述功能区域（206），以阻挡所述密封层（210）的材料溢入功能区域（206），从而避免功能区域（206）受到污染，提高封装结构的性能和良率。

Description

封装结构以及封装方法
本申请要求于2016年7月4日提交中国专利局，申请号为201610516699.6，发明名称为“封装结构以及封装方法”的中国专利申请的优先权，以及于2016年7月4日提交中国专利局，申请号为201620692372.X，发明名称为“封装结构”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体封装技术，特别涉及一种封装结构以及封装方法。
背景技术
影像传感器是一种能够感受外部光线并将其转换成电信号的传感器。在影像传感芯片制作完成后，再通过对影像传感芯片进行一系列封装工艺，形成的封装结构用于作为影像传感器或者影像传感器的一部分，以用于诸如数码相机、数码摄像机等各种电子设备。
传统的封装方法通常是采用引线键合(wire bonding)进行封装，但随着集成电路的飞速发展，较长的引线使得产品尺寸难以达到理想的要求，因此，晶圆级封装(WLP，Wafer Lever Package)逐渐取代引线键合封装成为一种较为常用的封装方法。晶圆级封装技术具有以下优点：能够对整个晶圆同时加工，封装效率高；在切割前进行整片晶圆的测试，减少了封装过程中的测试过程，降低测试成本；封装结构具有轻、小、薄的优势。
然而，现有技术形成的封装结构的性能有待提高。
发明内容
本申请解决的问题是提供一种封装结构以及封装方法，避免功能区域受到污染，提高封装结构的性能。
为解决上述问题，本申请提供一种封装结构，包括：基板；设置在基板上的电路布线层；位于所述电路布线层上的导电凸块；倒装在所述基板上方的半导体芯片，所述半导体芯片朝向基板的第一表面上设置有功能区域以及 环绕所述功能区域的分立的焊盘，且所述焊盘与所述导电凸块电连接；位于所述基板上的密封层，所述密封层包围所述半导体芯片；以及位于所述基板上的阻挡结构，所述阻挡结构环绕所述功能区域，以阻挡所述密封层的材料溢入功能区域。
可选的，所述电路布线层的顶部高于所述基板的顶部；或者所述电路布线层的顶部与所述基板的顶部平齐；或者所述电路布线层的顶部低于所述基板的顶部。
可选的，所述导电凸块围成指定区域，且所述阻挡结构位于所述指定区域内。
可选的，所述阻挡结构位于所述导电凸块与所述功能区域之间；且所述阻挡结构顶部表面与所述半导体芯片的第一表面相接触，所述阻挡结构底部表面与所述基板相接触。
可选的，在平行于所述基板顶面的方向上，所述阻挡结构的顶部表面宽度尺寸小于或等于底部表面宽度尺寸。
可选的，所述导电凸块围成指定区域，所述阻挡结构位于所述指定区域外侧；且所述阻挡结构还位于所述半导体芯片与所述基板之间。
可选的，所述半导体芯片投影于基板的区域为投影区域，所述阻挡结构位于所述投影区域内；且所述阻挡结构顶部表面与所述半导体芯片的第一表面相接触，所述阻挡结构底部表面与所述基板相接触。
可选的，所述阻挡结构包括：第一阻挡结构、位于第一阻挡结构一侧且紧挨所述第一阻挡结构的第二阻挡结构，其中，所述半导体芯片投影于基板的区域为投影区域，所述第一阻挡结构位于所述投影区域外侧，所述第二阻挡结构位于所述投影区域内；且所述第二阻挡结构顶部表面与所述半导体芯片的第一表面相接触。
可选的，位于所述基板上的第二阻挡结构的厚度为第一厚度，且所述半导体芯片的第一表面与所述基板之间的距离等于所述第一厚度。
可选的，位于所述基板上的第一阻挡结构的厚度为第二厚度，且所述第二厚度大于或等于所述第一厚度。
可选的，所述密封层还位于所述第一阻挡结构顶部上。
可选的，所述半导体芯片投影于基板的区域为投影区域，所述阻挡结构位于所述投影区域外侧；且所述阻挡结构顶部高于所述半导体芯片的第一表面。
可选的，在平行于所述基板顶面的方向上，所述阻挡结构与所述半导体芯片侧壁之间具有间隙。
可选的，在平行于所述基板顶面的方向上，所述间隙的宽度尺寸为2微米～10微米。
可选的，在垂直于所述基板顶面的方向上，所述阻挡结构顶部表面与所述半导体芯片正面之间的距离为2微米～10微米。
可选的，所述密封层还位于所述阻挡结构顶部上。
可选的，所述阻挡结构的形状为封闭环形。
可选的，所述阻挡结构与所述导电凸块侧壁相接触；且所述阻挡结构的材料为绝缘材料。
可选的，所述阻挡结构与所述导电凸块相互分离；且所述阻挡结构的材料为绝缘材料或导电材料。
可选的，所述绝缘材料为感光胶。
可选的，所述阻挡结构为叠层结构，包括：与所述基板以及电路布线层相接触的底层阻挡层、以及与所述半导体芯片的第一表面相接触的顶层阻挡层，其中，所述底层阻挡层的材料为绝缘材料，所述顶层阻挡层的材料为导电材料或绝缘材料。
可选的，所述基板包括基底，所述基底为透光基底或PCB基底；当所述基底为PCB基底时，所述PCB基板内形成有贯穿所述PCB基底的通孔，所述功能区域位于所述通孔上方；当所述基底为透光基底时，所述透光基底上设置有缓冲层，所述电路布线层位于所述缓冲层上，在缓冲层上对应功能区域的位置设置有开口，所述开口底部暴露所述透光基底。
可选的，所述缓冲层的材料为有机高分子光刻胶。
可选的，所述封装结构还包括：位于所述基板上的焊接凸起，所述焊接凸起与所述电路布线层电连接；所述焊接凸起位于所述基板上且位于所述半导体芯片的外侧。
可选的，所述半导体芯片为影像传感芯片；所述功能区域为感光区域。
本申请还提供一种封装方法，包括：提供若干单个的半导体芯片，所述半导体芯片的第一表面具有功能区域以及环绕所述功能区域的焊盘；提供基板，所述基板包括倒装区以及位于相邻倒装区之间的切割道区域；在所述基板的倒装区上设置有电路布线层；将所述半导体芯片倒装在所述基板倒装区上方，且所述焊盘与所述电路布线层通过导电凸块电连接；在所述基板上形成密封层，且所述密封层包围所述半导体芯片；在形成所述密封层之后，沿所述切割道区域切割所述基板，形成若干单颗封装结构；其中，在形成所述密封层之前，还包括：在所述基板上形成阻挡结构，所述阻挡结构环绕功能区域，以阻挡所述密封层的材料溢入功能区域。
可选的，在将所述半导体芯片倒装在所述基板倒装区上方之前，在所述焊盘上形成所述导电凸块。
可选的，在将所述半导体芯片倒装在所述基板倒装区上方之前，在所述电路布线层上形成所述导电凸块。
可选的，形成所述阻挡结构的方法包括：在所述基板上形成阻挡膜；对所述阻挡膜进行曝光处理以及显影处理，以形成所述阻挡结构；或者，对所述阻挡膜进行刻蚀，以形成所述阻挡结构。
可选的，所述将半导体芯片倒装在所述基板倒装区上方的步骤包括：将所述半导体芯片放置在所述基板倒装区上，且所述焊盘通过所述导电凸块与所述电路布线层相连接；对所述导电凸块进行焊接键合处理，使得所述焊盘通过导电凸块与所述电路布线层电连接。
可选的，在将所述半导体芯片倒装在所述基板倒装区上方之后，所述导电凸块围成指定区域，且所述阻挡结构位于所述指定区域内；或者，所述阻挡结构位于所述指定区域外侧，且阻挡结构位于所述半导体芯片投影于基板的投影区域内；在将所述半导体芯片倒装在所述基板倒装区上方之前，形成所述阻挡结构；且在将所述半导体芯片倒装在所述基板倒装区上方之后，所述阻挡结构顶部表面与所述半导体芯片的第一表面相接触。
可选的，在进行所述焊接键合处理之前，所述基板与半导体芯片的第一表面之间的导电凸块的厚度大于或等于所述阻挡结构的厚度；且在所述焊接 键合处理过程中，所述基板与所述半导体芯片的第一表面之间的导电凸块的厚度减小，使得所述阻挡结构顶部表面与所述半导体芯片的第一表面相接触。
可选的，所述阻挡结构包括：第一阻挡结构、位于第一阻挡结构一侧且紧挨所述第一阻挡结构的第二阻挡结构；在将所述半导体芯片倒装在所述基板倒装区上方之后，所述半导体芯片投影于基板的区域为投影区域，所述第一阻挡结构位于所述投影区域外侧，所述第二阻挡结构位于所述投影区域内；以及所述封装方法还包括：在将所述半导体芯片倒装在所述基板倒装区上方之前，形成所述阻挡结构；以及在将所述半导体芯片倒装在所述基板倒装区上方之后，所述第二阻挡结构顶部表面与所述半导体芯片的第一表面相接触。
可选的，在所述焊接键合处理过程中，所述基板与半导体芯片的第一表面之间的导电凸块的厚度减小，使得所述第二阻挡结构顶部表面与所述半导体芯片的第一表面相接触，且所述第一阻挡结构覆盖半导体芯片部分侧壁。
可选的，在将所述半导体芯片倒装在所述基板倒装区上方之后，所述半导体芯片投影于基板的区域为投影区域，所述阻挡结构位于所述投影区域外侧，且所述阻挡结构顶部高于所述半导体芯片的第一表面；在将所述半导体芯片倒装在所述基板倒装区上方之前，形成所述阻挡结构；或者，在将所述半导体芯片倒装在所述基板倒装区上方之后，形成所述阻挡结构。
可选的，所述封装方法还包括，在所述基板上形成焊接凸起，所述焊接凸起与所述电路布线层电连接。
可选的，采用点胶工艺或者塑封工艺，形成所述密封层。
与现有技术相比，本申请的技术方案具有以下优点：
本申请提供的封装结构的技术方案中，在基板上设置有阻挡结构，所述阻挡结构环绕所述功能区域，以阻挡密封层的材料溢入功能区域内，从而避免所述功能区域受到污染，从而提高封装结构的性能。
可选方案中，所述阻挡结构、半导体芯片、基板以及电路布线层围成封闭区域，从而使得阻挡结构阻挡密封层的材料溢入功能区域内的效果更好，进一步提高封装结构的性能。
可选方案中，在平行于所述基板顶面的方向上，所述阻挡结构的顶部表面宽度尺寸小于或等于底部表面宽度尺寸，使得阻挡结构与半导体芯片正面 相接触的面积较小，因此半导体芯片正面需为阻挡结构预留的空间位置较小，使得半导体芯片的尺寸可以做的较小。
可选方案中，当所述阻挡结构位于半导体芯片外侧时，在平行于基板顶面的方向上，所述阻挡结构与所述半导体芯片之间具有间隙，且所述间隙的宽度尺寸为2微米～10微米，由于间隙的宽度尺寸较小，从而防止密封层的材料经由所述孔隙进入功能区域内，保证阻挡结构具有较强的阻挡密封层材料溢入的作用。
附图说明
图1及图2为一种封装结构的结构示意图；
图3至图5为本申请一实施例提供的封装结构的结构示意图；
图6至图9为本申请另一实施例提供的封装结构的结构示意图；
图10及图11为本申请又一实施例提供的封装结构的结构示意图；
图12至图15为本申请一实施例提供的封装结构形成过程的结构示意图；
图16至图19为本申请另一实施例提供的封装结构形成过程的结构示意图；
图20及图21为本申请又一实施例提供的封装结构形成过程的结构示意图。
具体实施方式
由背景技术可知，现有技术形成的封装结构的性能有待进一步提高。
这里需要说明的是，文中所述方位词上、下、左和右均是以图1所示的视图为基准定义的，应当理解，所述方位词的使用不应限制本申请所请求的保护范围。
参考图1及图2，图1为封装结构的俯视示意图，图2为图1中沿AA1方向的剖面结构示意图。需要说明的是，为方便图示和说明，图1中未将封装结构的俯视示意图完全示出。
所述封装结构包括：具有电路布线层106的基板107，所述电路布线层106中具有暴露出基板107的开口109；位于所述电路布线层106上的导电凸块103；倒装在基板107上的影像传感芯片100，所述影像传感芯片100正面具有感光区 域101以及环绕所述感光区域101的焊盘102，且所述焊盘102与所述导电凸块103电连接；位于所述电路布线层106上且覆盖影像传感芯片100侧壁的点胶层104；位于所述电路布线层106上的焊接凸起105。
经分析，由于相邻导电凸块103之间存在缝隙，因此在形成点胶层104的工艺过程中，所述点胶层104的材料易经由所述缝隙溢入影像传感芯片100的感光区域101内，点胶层104的材料对感光区域101造成污染，进而导致封装结构的性能差，影响封装结构的性能和良率。
为解决上述问题，本申请提供一种封装结构，包括位于基板上且环绕所述功能区域的阻挡结构，所述阻挡结构适于阻挡密封层的材料溢入功能区域，从而避免密封层的材料溢入功能区域对功能区域造成污染，提高封装结构的性能。
为使本申请的上述目的、特征和优点能够更为明显易懂，下面结合附图对本申请的具体实施例做详细的说明。
参考图3及图4，图3为本申请一实施例提供的封装结构的俯视示意图，图4为图3沿BB1方向的剖面结构示意图，所述封装结构包括：
基板；
设置在所述基板上的电路布线层203；
位于所述电路布线层203上的导电凸块204；
倒装在所述基板上方的半导体芯片205，所述半导体芯片205朝向所述基板的第一表面上设置具有功能区域206以及环绕所述功能区域206的焊盘207，且所述焊盘207与所述导电凸块204电连接；
位于所述基板上的密封层210，所述密封层210包围所述半导体芯片205；以及
位于所述基板上以及电路布线层203上的阻挡结构208，所述阻挡结构208环绕所述功能区域206，以阻挡所述密封层210的材料溢入功能区域206。
以下将结合附图对本实施例提供的封装结构进行详细说明。
本实施例中，所述基板包括基底201以及位于基底201上的缓冲层202，且所述缓冲层202内具有贯穿所述缓冲层202的开口209，所述功能区域206位于所述开口209上方，功能区域206可通过所述开口209接收外界光线；其中，所 述基底201为透光基底或PCB基底，本实施例中所述基底201为透光基底；在其他实施例中，所述基底为PCB基底时，所述PCB基底内形成有贯穿所述PCB基底的通孔，且所述功能区域位于所述通孔上方。
在其他实施例中，所述基板还可以为包括基底的单层结构，所述基底为透光基底或PCB基底。
所述缓冲层202有利于提高电路布线层203与基底201之间的粘附性，继而提高基底201与半导体芯片205之间的粘合性。所述缓冲层202的材料为有机高分子光刻胶，例如，为环氧树脂或丙烯酸树脂。
本实施例中，所述电路布线层203凸出于所述基板表面。在其他实施例中，所述电路布线层还可以位于所述基板内，也就是说，所述电路布线层顶部与所述基板顶部齐平，或者，所述电路布线层顶部低于所述基板顶部。
本实施例中，所述电路布线层203位于缓冲层202上；所述电路布线层203的位置和数量与焊盘207的位置和数量相对应。具体的，当功能区域206四侧均具有若干焊盘207时，则开口209四侧均具有若干分立的电路布线层203，且每一个分立的电路布线层203对应与一个焊盘202电连接，且所述电路布线层203通过导电凸块204与焊盘207电连接。在其他实施例中，所述功能区域一侧具有若干焊盘时，则所述开口一侧具有相同数量的分立的电路布线层。
所述电路布线层203的材料为Cu、Al、W、Sn、Au或Sn-Au合金；所述导电凸块204的材料为Au、Sn或Sn合金，所述Sn合金可以为锡银、锡铅、锡银铜、锡银锌或锡锌。
所述导电凸块204的形状为方形或球形。本实施例中，以所述导电凸块204的形状为方形作为示例。
所述半导体芯片205正面具有功能区域206以及环绕所述功能区域206的焊盘207，其中，所述功能区域206内形成有功能单元以及与所述功能单元相连接的关联电路。本实施例中，所述半导体芯片205为影像传感芯片，相应的，所述功能区域206为感光区域，所述功能区域206接收外界光线并将接收的光线转换成电信号，并将所述电信号通过所述焊盘207以及电路布线层203，传送给外部电路。本实施例中，将所述半导体芯片205投影于所述基板的区域称为投影区域。
本实施例中，为了便于布线，功能区域206位于半导体芯片205的中间位置，所述焊盘207位于所述半导体芯片205的边缘位置，且所述焊盘207位于所述功能区域206的四侧，呈矩形分布，每一个侧边形成有若干个焊盘207，且焊盘207的数量取决于半导体芯片205的类型。将所述焊盘207与电路布线层203相连接，通过电路布线层203使所述半导体芯片205与外部电路连接。
需要说明的是，在其他实施例中，所述焊盘和功能区域的位置可以根据实际需求灵活调整，例如，在其他实施例中，焊盘可以位于功能区域的一侧、两侧或三侧。
所述导电凸块204的作用包括：一方面，实现电路布线层203与焊盘207之间的电连接；另一方面，由于焊盘207与电路布线层203之间设置有导电凸块204，使得功能区域206与电路布线层203在垂直于基底201表面方向上的距离较大，防止功能区域206触碰到电路布线层203，进而避免功能区域206受到损伤。本实施例中，所述导电凸块204的厚度大于功能区域206内感光元件的厚度。
所述封装结构还包括：位于所述基板上的焊接凸起211，所述焊接凸起211与所述电路布线层203电连接。本实施例中，所述焊接凸起211位于所述电路布线层203上，所述焊接凸起211使焊盘207与外部电路电连接，从而使半导体芯片205正常工作。所述焊接凸起211的材料为金、锡或锡合金。本实施例中，所述焊接凸起211顶部表面形状为弧形。
所述密封层210的作用为：一方面，所述密封层210将半导体芯片205置于封闭环境内，防止在外界环境的影响下造成的半导体芯片205性能失效，防止湿气由外部侵入、与外部电气绝缘；另一方面，所述密封层210起到支撑半导体芯片205的作用，将半导体芯片205固定好以便电路连接。
所述密封层210的材料为树脂或防焊油墨材料，例如，环氧树脂或丙烯酸树脂。
本实施例中，所述密封层210除位于半导体芯片205侧壁上外，所述密封层210还位于基板上以及电路布线层203上，且所述密封层210顶部低于半导体芯片205底部表面，或者密封层210顶部与半导体芯片205底部表面齐平，需要说明的是，所述底部表面指的是与半导体芯片205正面相对的面。
本实施例中，所述密封层210与所述焊接凸起211之间相互分离。在其他实施例中，所述焊接凸起还可以位于所述密封层内且贯穿所述密封层，换句话说，所述焊接凸起位于基板上且位于半导体芯片的外侧。具体的，参考图5，所述密封层210覆盖投影区域之外的基板上以及电路布线层203上，且还覆盖半导体芯片205侧壁表面以及底部表面；所述焊接凸起211位于所述密封层210内且贯穿所述密封层210。
本实施例中，所述阻挡结构208位于基板上以及电路布线层203上，且还环绕所述功能区域206。阻挡结构208、半导体芯片205、基板以及电路布线层203围成封闭区域，使得所述密封层210材料难以进入封闭区域内，从而有效的阻挡密封层210的材料进入功能区域206内，避免对功能区域206造成污染。
具体的，位于所述基板或电路布线层203上的导电凸块204围成指定区域，且所述阻挡结构208位于所述指定区域内；也可以认为，所述阻挡结构208位于前述的投影区域内，且还位于导电凸块204与所述功能区域206之间。其中，所述阻挡结构208顶部表面与所述半导体芯片205正面相接触，所述阻挡结构208底部表面与所述电路布线层203以及基板相接触。
本实施例中，由于所述基板包括基底201以及缓冲层202，相应的，所述阻挡结构208位于所述电路布线层203上、以及缓冲层202上；所述阻挡结构208顶部表面与所述半导体芯片205正面相接触，所述阻挡结构208底部表面与所述电路布线层203以及缓冲层202相接触。
位于所述电路布线层203上的阻挡结构208的厚度为第一厚度，且所述半导体芯片205正面与所述电路布线层203之间的距离等于所述第一厚度；位于所述基板上的阻挡结构208的厚度为第二厚度，且所述半导体芯片205正面与所述基板之间的距离等于所述第二厚度。本实施例中，位于所述缓冲层202上的阻挡结构208的厚度为第二厚度，且所述半导体芯片205正面与所述缓冲层202之间的距离等于所述第二厚度。需要说明的是，所述半导体芯片205正面与所述电路布线层203之间的距离指的是，所述半导体芯片205正面与所述电路布线层203表面之间的最小距离；所述半导体芯片205正面所述缓冲层202之间的距离指的是，所述半导体芯片205正面与所述缓冲层202表面之间的最小距离。
本实施例中，在平行于所述基板表面方向上，所述阻挡结构208的顶部表面宽度尺寸等于底部表面宽度尺寸。在其他实施例中，为了减小阻挡结构占据半导体芯片正面的空间尺寸，所述阻挡结构的顶部表面宽度尺寸还可以小于底部表面宽度尺寸，使得阻挡结构与半导体芯片正面相接触的面积较小，从而节约半导体芯片的体积。
所述阻挡结构208的形状为封闭环形。在平行于所述基板表面方向上，所述阻挡结构208的剖面形状为方形环形、圆形环形、椭圆形环形或不规则形状环形。本实施例中，以所述阻挡结构208的剖面形状为方形环形作为示例。
此外，还需要说明的是，所述阻挡结构208的形状还可以与所述导电凸块204围成的指定区域的形状相匹配，例如，所述导电凸块204围成的区域的形状为方形，所述导电凸块208的剖面形状为方形环形；所述导电凸块204围成的区域的形状为圆形时，所述导电凸块208的剖面形状为圆形环形。为了避免所述阻挡结构208对封装结构电连接性能造成不良影响，本实施例中，所述阻挡结构208与所述电路布线层203之间相互电绝缘。
本实施例中，所述阻挡结构208为单层结构，且所述阻挡结构的材料为绝缘材料。在其他实施例中，所述阻挡结构还可以为叠层结构。该具有叠层结构的阻挡结构可以包括：与基板以及电路布线层相接触的底层阻挡层、以及与所述半导体芯片正面相接触的顶层阻挡层，其中，所述底层阻挡层的材料为绝缘材料，所述顶层阻挡层的材料为导电材料或绝缘材料。其中，所述导电材料包括铜、铝、钨或锡，所述绝缘材料为感光胶，所述感光胶包括环氧树脂、丙烯酸树脂、聚酰亚胺胶或苯并环丁烯胶。
此外，本实施例中，所述阻挡结构208与所述导电凸块204相互分离，所述阻挡结构208侧壁与所述导电凸块204侧壁之间具有一定的距离，使得所述阻挡结构208不会对导电凸块204的电连接性能造成干扰，所述阻挡结构208的材料可以为绝缘材料，所述阻挡结构208的材料还可以包括导电材料。在其他实施例中，所述阻挡结构侧壁与所述导电凸块侧壁相接触时，由于所述阻挡结构的形状为封闭环形，为了避免所述阻挡结构将相互分立的导电凸块相连而导致导电凸块发生不必要的电连接，所述阻挡结构的材料为绝缘材料。
本实施例提供的封装结构，所述阻挡结构208位于所述导电凸块204围成 的指定区域内，即，所述阻挡结构208位于所述导电凸块204与所述功能区域206之间，使得所述阻挡结构208对功能区域206提供保护作用，防止密封层210材料或者其他材料经由相邻导电凸块204之间的缝隙进入功能区域206内，避免功能区域206受到污染，从而提高封装结构的良率以及电性能。
此外，所述导电凸块204与所述半导体芯片205上的焊盘207位置相对应，由于所述阻挡结构208位于所述导电凸块204与所述功能区域206之间，相应的所述阻挡结构208位于所述焊盘207与所述功能区域206之间，因此无需为放置阻挡结构208而增加焊盘207到半导体芯片205侧壁之间的距离，使得半导体芯片205具有较小的体积，满足封装结构小型化微型化的发展趋势。
图6至图9为本申请另一实施例提供的封装结构的结构示意图，其中，图6为封装结构的俯视结构示意图，图7为图6中沿CC1方向的剖面结构示意图。所述封装结构包括：
基板；
设置在基板上的电路布线层303；
位于所述电路布线层303上的导电凸块304；
倒装在所述基板上方的半导体芯片305，所述半导体芯片305朝向基板的第一表面上设置有功能区域306以及环绕所述功能区域306的焊盘307，且所述焊盘307与所述导电凸块304电连接；
位于所述基板上的密封层310，所述密封层310包围所述半导体芯片305；
位于所述电路布线层303上以及基板上的阻挡结构308，所述阻挡结构308环绕所述功能区域306，以阻挡所述密封层310的材料溢入功能区域306。
以下将结合附图对本实施例提供的封装结构进行详细说明。
本实施例中，以所述基板包括基底301以及位于基底301上的缓冲层302为例，且所述缓冲层302内具有贯穿所述缓冲层302的开口309。
有关基底301、缓冲层302、开口309、电路布线层303、导电凸块304、半导体芯片305、功能区域306以及焊盘307的描述请相应参考前一实施例的说明，在此不再赘述。
所述阻挡结构308、半导体芯片305、基板以及电路布线层303围成封闭区域。与前一实施例不同的是，本实施例中，位于所述电路布线层303上的导电 凸块304围成指定区域，所述阻挡结构308位于所述指定区域外侧，且所述阻挡结构308还位于所述半导体芯片305与所述电路布线层303之间。相应的，所述密封层310除位于缓冲层302上以及半导体芯片305侧壁上之外，还位于所述基板上以及电路布线层303上。
参考图7，本实施例中，所述半导体芯片305投影于基板的区域为投影区域，且所述阻挡结构308位于所述投影区域内。所述阻挡结构308顶部与所述半导体芯片305正面相接触，所述阻挡结构308底部表面与所述电路布线层303以及基板相接触。由于所述基板包括基底301以及缓冲层302，本实施例中，所述阻挡结构308底部表面与所述电路布线层303以及缓冲层302相接触。
有关阻挡结构308的材料和结构可相应参考前一实施例的说明，在此不再赘述。本实施例中，所述阻挡结构308与所述导电凸块304相互分离；在其他实施例中，所述阻挡结构还可以与所述导电凸块的侧壁相接触，且所述阻挡结构的材料为绝缘材料。
所述封装结构还包括：位于所述基板上的焊接凸起311，所述焊接凸起311与所述电路布线层303电连接。本实施例中，所述焊接凸起311位于所述电路布线层303上，且所述密封层310与所述焊接凸起311相互分立，相应可参考前一实施例的描述。在其他实施例中，所述焊接凸起311还可以位于所述基板上且位于所述半导体芯片的外侧。
本实施例中提供的封装结构中，所述阻挡结构308不仅可以阻挡密封层310材料或其他材料进入功能区域306，避免功能区域306受到污染；所述阻挡结构308还可以对导电凸块304起到保护作用，防止密封层310材料或其他材料对导电凸块304造成污染，防止所述导电凸块304的导电性能受到损伤，从而进一步改善封装结构的性能。
还需要说明的是，在其他实施例中，参考图8及图9，位于所述电路布线层303上的导电凸块304围成指定区域，所述阻挡结构308位于所述指定区域外侧；且所述阻挡结构308还位于所述半导体芯片305与所述电路布线层303之间时，所述阻挡结构包括：第一阻挡结构318以及位于第一阻挡结构318一侧且紧挨所述第一阻挡结构318的第二阻挡结构328，其中，所述半导体芯片305投影于基板的区域为投影区域，所述第一阻挡结构318位于所述投影区域外侧， 所述第二阻挡结构328位于所述投影区域内。
并且，所述第二阻挡结构328顶部表面与所述半导体芯片305正面相接触，所述第二阻挡结构328底部表面与所述电路布线层303以及基板相接触。具体的，所述第二阻挡结构328底部表面与所述电路布线层303以及缓冲层302相接触。
由于所述阻挡结构308、半导体芯片305、基板以及电路布线层303之间围成封闭区域，因此，位于所述基板上的第二阻挡结构328的厚度为第一厚度，且所述半导体芯片305正面与所述基板之间的距离等于所述第一厚度；位于所述电路布线层303上的第二阻挡结构328的厚度为第三厚度，且所述半导体芯片305正面与所述电路布线层303之间的距离等于所述第三厚度。具体到本实施例中，位于所述缓冲层302上的第二阻挡结构328的厚度为第一厚度，且所述半导体芯片305正面与所述缓冲层302之间的距离等于所述第一厚度。
相应的，所述密封层310除位于半导体芯片305侧壁上外，还位于所述第一阻挡结构318上。或者，所述密封层310不仅位于所述第一阻挡结构318顶部和侧壁上，且还位于电路布线层303上以及缓冲层302上。
与不具有所述第一阻挡结构的方案相比，所述第一阻挡结构318可以起到密封层的效果，因此所述第一阻挡结构318占据密封层部分空间位置，从而进一步的降低所述密封层310材料污染功能区域306的可能性，并且也相应的进一步防止密封层310材料对导电凸块304造成污染，进一步改善封装结构的性能。
在一实施例中，参考图8，位于所述基板上的第一阻挡结构318的厚度为第二厚度，位于所述基板上的第二阻挡结构328的厚度为第一厚度，且所述第二厚度等于所述第一厚度。也就是说，位于所述基板上的第一阻挡结构318顶部与所述第二阻挡结构328顶部齐平，相应的，位于所述电路布线层303上的第一阻挡结构318顶部与所述第二阻挡结构328顶部齐平。所述密封层319位于所述第一阻挡结构318顶部以及半导体芯片305侧边上。在其他实施例中，所述密封层除位于第一阻挡结构顶部以及半导体芯片侧壁上外，还可以位于电路布线层上以及基板上。
在另一实施例中，参考图9，位于所述基板上的第一阻挡结构318的厚度 为第二厚度，位于所述基板上的第二阻挡结构328的厚度为第一厚度，且所述第二厚度大于所述第一厚度。也就是说，位于所述基板上的第一阻挡结构318顶部高于第二阻挡结构328顶部，相应的，位于所述电路布线层303上的第一阻挡结构318顶部高于第二阻挡结构328顶部，使得所述第一阻挡结构318覆盖半导体芯片305部分侧壁。所述密封层310位于所述第一阻挡结构318顶部以及半导体芯片305侧壁上。在其他实施例中，所述密封层还可以位于电路布线层上以及基板上。由于所述第一阻挡结构318覆盖半导体芯片305部分侧壁，使得第一阻挡结构318阻挡密封层310材料溢入功能区域306的能力进一步得到提高。
本实施例中，通过将所述阻挡结构308设置在导电凸块304围成的指定区域外，在保护所述功能区域306不受到污染的同时，无需在导电凸块304与功能区域306之间为阻挡结构308预留空间位置，因此能够减小导电凸块304与功能区域306之间的距离。
同时，所述阻挡结构308与所述功能区域306之间的距离较远，从而避免所述阻挡结构308对所述功能区域306造成污染或损伤，进一步提高封装结构的性能。
此外，位于所述投影区域外侧的第一阻挡结构318占据密封层310的部分空间位置，进一步降低了密封层310材料溢入功能区域306的可能性；并且，所述第一阻挡结构318和第二阻挡结构328均可以起到阻挡密封层310材料溢入功能区域306的作用，因此本实施例提供的封装结构中功能区域306能够得到更好的保护。
本申请又一实施例还提供一种封装结构，图10及图11为本申请又一实施例提供的封装结构的结构示意图，所述封装结构包括：
基板；
设置在基板上的电路布线层403；
位于所述电路布线层403上的导电凸块404；
倒装在所述基板上方的半导体芯片405，所述半导体芯片405朝向所述基板的第一表面上设置有功能区域406以及环绕所述功能区域406的焊盘407，且所述焊盘407与所述导电凸块404电连接；
位于所述基板上的密封层410，所述密封层410包围所述半导体芯片405；
位于所述基板上以及电路布线层403上的阻挡结构408，所述阻挡结构408环绕所述功能区域406，以阻挡所述密封层410的材料溢入功能区域406。
以下将结附图对本实施例提供的封装结构进行详细说明。
所述基板包括基底401以及位于所述基底401上的缓冲层402，且所述缓冲层402具有贯穿所述缓冲层402的开口409。
与前述实施例不同的是，本实施例中，所述半导体芯片405投影于基板的区域为投影区域，所述阻挡结构408位于所述投影区域外侧，相应的，所述阻挡结构408位于所述半导体芯片405外侧且环绕所述半导体芯片405。
为保证所述阻挡结构408具有阻挡密封层410材料溢入功能区域306的能力，所述阻挡结构408顶部高于所述半导体芯片405的第一表面。并且，在垂直于所述基板表面方向上，所述阻挡结构408顶部表面与所述半导体芯片405的第一表面之间的距离不宜过小。若所述距离过小，则密封层410材料较易经由阻挡结构408与半导体芯片405之间的孔隙溢入功能区域406内，使得阻挡结构408阻挡密封层410材料溢入的能力较弱。
为此，本实施例中，在垂直于所述基板表面方向上，所述阻挡结构408顶部表面与所述半导体芯片405的第一表面之间的距离为2微米～10微米。
在平行于所述基板表面方向上，所述阻挡结构408与所述半导体芯片405侧壁之间具有间隙。若所述间隙的宽度尺寸过大，则密封层410的材料易经由所述间隙溢入功能区域406内。为此，在平行于所述基板表面方向上，所述间隙的宽度尺寸为等于2微米～10微米。
还需要说明的是，所述阻挡结构408还可以覆盖所述半导体芯片405侧壁，也就是说，所述间隙的宽度尺寸可以为0。
所述密封层410除位于半导体芯片405侧壁上外，还位于所述阻挡结构408顶部上。此外，所述密封层410还可以位于电路布线层403上以及缓冲层402上。
所述封装结构还包括：位于所述基板上的焊接凸起411，所述焊接凸块411与电路布线层403电连接。本实施例中，所述焊接凸起411位于所述电路布线层403上。
在一实施例中，参考图10，所述阻挡结构408覆盖所述电路布线层403以 及缓冲层402，所述焊接凸起411位于所述阻挡结构408内且贯穿所述阻挡结构408，且所述密封层410位于阻挡结构408部分顶部。需要说明的是，在其他实施例中，所述密封层还可以覆盖阻挡结构的整个顶部，且所述焊接凸起还贯穿所述密封层。
在另一实施例中，参考图11，所述阻挡结构408位于部分电路布线层403上以及部分基板上，所述焊接凸起411与所述阻挡结构408之间相互分离，且所述密封层410位于所述阻挡结构408顶部上。在其他实施例中，所密封层还可以覆盖电路布线层以及基板上，所述焊接凸起位于所述密封层内且贯穿所述密封层。
所述阻挡结构408的形状为封闭形状，所述阻挡结构408的材料为绝缘材料或导电材料，有关所述阻挡结构408的材料和结构的描述可参考前述实施例的相应描述，在此不再赘述。
本申请提供的封装结构中，所述阻挡结构顶部高于所述半导体芯片的第一表面，使得所述阻挡结构可以阻挡密封层的材料溢入功能区域内，从而防止功能区域受到污染，使得封装结构具有较高的性能，所述封装结构的良率得到提高。
此外，由于阻挡结构408位于半导体芯片405投影于基板上的投影区域外侧，因此所述半导体芯片405中无需为阻挡结构408预留空间位置；并且，所述阻挡结构408对所述基板与所述半导体芯片405之间的倒装无影响，因此所述阻挡结构408不会对所述基板以及半导体芯片405之间的空间布局产生影响。
相应的，本申请还提供一种形成前述封装结构的封装方法，包括：提供若干单个的半导体芯片，所述半导体芯片的第一表面具有功能区域以及环绕所述功能区域的焊盘；提供基板，所述基板包括倒装区以及位于相邻倒装区之间的切割道区域；在所述基板的倒装区上设置有若干分立的电路布线层；将所述半导体芯片倒装在所述基板倒装区上方，且所述焊盘与所述电路布线层通过导电凸块实现电连接；在所述基板上形成密封层，且所述密封层包围所述半导体芯片；在形成所述密封层之后，沿所述切割道区域切割所述基板，形成若干单颗封装结构；其中，在形成所述密封层之前，还包括：在所述基 板上形成阻挡结构，所述阻挡结构环绕功能区域，以阻挡所述密封层的材料溢入功能区域。
本申请中，由于在形成密封层之前，在所述基板上形成有阻挡结构，所述阻挡结构环绕所述功能区域且适于阻挡密封层的材料溢入功能区域；因此，在形成密封层的工艺过程中，所述阻挡结构对功能区域起到保护作用，防止密封层材料溢入功能区域内，使得形成的封装结构的性能和良率得到改善。
以下将结合附图对本申请提供的封装方法进行详细说明。
图12至图15为本申请一实施例提供的封装结构形成过程的结构示意图。
参考图12，提供若干单个的半导体芯片205，所述半导体芯片205正面具有功能区域206以及环绕所述功能区域206的焊盘207。
本实施例中，所述半导体芯片205为影像传感芯片，相应的所述功能区域206为感光区域；所述半导体芯片205为切割待封装晶圆形成的，所述待封装晶圆中具有若干矩阵排列的半导体芯片205。
有关功能区域206以及焊盘207的描述请相应参考前述封装结构中的描述，在此不再赘述。
继续参考图12，在所述焊盘207上形成导电凸块204。
所述导电凸块204的位置和数量与所述焊盘207的位置和数量相对应；所述导电凸块204的形状为方形或球形。
本实施例中，所述导电凸块204的形状为方形，采用网板印刷工艺形成所述导电凸块204。
在其他实施例中，所述导电凸块的形状还可以为球形，采用植球工艺形成所述导电凸块，还可以采用网板印刷工艺和回流工艺相结合的工艺形成所述导电凸块。
还需要说明的是，在其他实施例中，还可以不在所述焊盘上形成所述导电凸块，在后续提供的基板的电路布线上形成所述导电凸块。
参考图13，提供基板，所述基板包括倒装区I以及位于相邻倒装区I之间的切割道区域II，所述基板倒装区I上设置有电路布线层203。
所述倒装区I和切割道区域II的面积可根据实际封装工艺需求设定。
本实施例中，所述基板包括基底201以及位于基底201上的缓冲层202，所 述缓冲层202内形成有贯穿所述缓冲层202的开口209。有关基底201的材料可参考前述封装结构中的相应描述。
本实施例中，所述缓冲层202的材料为有机高分子光刻胶，形成所述缓冲层202的工艺步骤包括：在所述基底201上形成缓冲膜；对所述缓冲膜进行曝光处理以及显影处理，形成具有所述开口209的缓冲层202。
本实施例中，所述电路布线层203凸出于所述基板表面。形成所述电路布线层203的步骤包括：在所述缓冲层202上以及开口209底部和侧壁形成电路层；图形化所述电路层，以去除位于开口209底部和侧壁上的电路层，在所述缓冲层202上形成若干分立的电路布线层203。
在其他实施例中，所述电路布线层还可以位于所述基板内，即，所述电路布线层顶部与所述基板顶部齐平，或者，所述电路布线层顶部低于所述基板顶部。
继续参考图13，在所述电路布线层203上以及基板上形成阻挡结构208。
本实施例中，在所述电路布线层203以及缓冲层202上形成所述阻挡结构208。
所述阻挡结构208的形状为封闭环形。在平行于所述基板表面方向的剖面上，所述阻挡结构208的剖面形状为方形环形、圆形环形、椭圆形环形或不规则形状环形。
本实施例中，后续会将半导体芯片205(参考图12)倒装在基板倒装区I上方，且焊盘207通过导电凸块204与所述电路布线层203电连接；在将所述半导体芯片205倒装在所述基板倒装区I上方之后，所述导电凸块204围成指定区域，且所述阻挡结构208位于所述指定区域内。
形成所述阻挡结构208的工艺步骤包括：在所述电路布线层203上以及基板上形成阻挡膜；对所述阻挡膜进行曝光处理以及显影处理，形成所述阻挡结构208；或者，对所述阻挡膜进行刻蚀，形成所述阻挡结构208。
本实施例中，为了避免所述电路布线层203与所述阻挡结构208发生不必要的电连接，所述阻挡结构208为单层结构，且所述阻挡结构208的材料为绝缘材料。在其他实施例中，所述阻挡结构还可以为叠层结构，其包括与所述电路布线层以及基板相接触的底层阻挡层、以及与所述半导体芯片正面相接 触的顶层阻挡层，其中，所述底层阻挡层的材料为绝缘材料，所述顶层阻挡层的材料为绝缘材料或导电材料，所述绝缘材料为感光胶。
此外，本实施例中，所述阻挡结构208与所述导电凸块204相互分离，所述阻挡结构208的材料包括绝缘材料，所述阻挡结构208的材料还可以包括导电材料。在其他实施例中，所述阻挡结构侧壁与所述导电凸块侧壁相接触时，为了保证相邻导电凸块之间的电绝缘性能，所述阻挡结构的材料为绝缘材料。
参考图14，将所述半导体芯片205倒装在基板倒装区I上方，且所述焊盘207与所述电路布线层203通过导电凸块204实现电连接。
具体的，每一个焊盘207对应于一个分立的导电凸块204，也可以认为，每一个焊盘207对应于一个分立的电路布线层203。
将所述半导体芯片205倒装在所述基板倒装区I上方的步骤包括：将所述半导体芯片205放置在所述基板倒装区I上，且所述焊盘207通过所述导电凸块204与所述电路布线层203相连接；对所述导电凸块204进行焊接处理，使得所述焊盘207通过所述导电凸块204与所述电路布线层203电连接。
所述焊接键合处理采用的工艺为共晶键合工艺、超声热压键合工艺或者热压焊接工艺。
在进行所述焊接键合处理之前，所述基板与半导体芯片205正面之间的导电凸块204的厚度大于或等于所述阻挡结构208的厚度；且在所述焊接键合处理过程中，所述基板与半导体芯片205正面之间的导电凸块204的厚度减小，使得所述阻挡结构208顶部表面与所述半导体芯片205正面相接触。
在将所述半导体芯片205倒装在所述基板倒装区I上方之后，所述导电凸块204围成指定区域，且所述阻挡结构208位于所述指定区域内；在进行所述焊接键合处理之后，所述阻挡结构208、半导体芯片205、电路布线层203以及基板之间围成封闭区域，从而防止后续形成的密封层材料溢入功能区域206内。
此外，还需要说明的是，在将所述半导体芯片205放置在基板上后、进行焊接键合处理之前，位于所述基板与半导体芯片205之间的导电凸块204的厚度与所述阻挡结构208厚度之间的差值不宜过大。若所述差值过大，则在焊接键合处理之后，所述阻挡结构208与所述半导体芯片205正面之间具有孔隙，后续形成的密封层会经由所述孔隙扩散进入功能区域206内。
参考图15，在所述基板上形成密封层210，且所述密封层210包围所述半导体芯片205。
所述密封层210用于使所述半导体芯片205处于密封状态，防止外界环境对半导体芯片205造成不良影响。本实施例中，所述密封层210还位于部分电路布线层203上。在其他实施例中，所述密封层还可以覆盖半导体芯片背面，此外，所述密封层还可以覆盖被半导体芯片暴露出的整个基板表面。
本实施例中，采用点胶工艺形成所述密封层210。在其他实施例中，还可以采用塑封工艺(molding)形成所述密封层，其中，所述塑封工艺为转塑工艺(transfer molding)或注塑工艺(injection molding)。
在形成所述密封层210的工艺过程中，所述阻挡结构210适于阻挡所述密封层210的材料溢入所述功能区域206内，避免所述密封层210材料经由相邻导电凸块204之间的缝隙进入功能区域206内，防止功能区域206受到污染，从而提高形成的封装结构的性能和良率。
继续参考图15，还包括步骤：在所述基板上形成焊接凸起211，所述焊接凸起211与所述电路布线层203电连接。
本实施例中，在所述电路布线层203上形成焊接凸起211，所述焊接凸起211使焊盘207与外部电路电连接，从而使半导体芯片205正常工作。
本实施例中，所述焊接凸起211与所述密封层210之间相互分立。在其他实施例中，所述焊接凸起还可以位于所述密封层内且贯穿所述密封层。
结合参考图15和图4，后续的工艺步骤还包括：沿所述切割道区域II切割所述基板，形成若干单颗如图4所示的封装结构。
本申请另一实施例还提供一种封装方法，图16至图19为本申请另一实施例提供的封装结构形成过程的结构示意图。
与前一实施例不同之处在于，本实施例中，位于电路布线层上的导电凸块围成指定区域，形成的阻挡结构位于所述指定区域外侧且环绕所述导电凸块，且所述阻挡结构还位于半导体芯片与电路布线层之间。
参考图16，提供基板，所述基板包括倒装区I以及位于相邻倒装区I之间的切割道区域II，所述基板上具有电路布线层303；在所述电路布线层303上形成导电凸块304；在所述基板上形成阻挡结构308，所述阻挡结构308环绕所述导 电凸块304。
所述基底包括基底301以及位于基底301上的缓冲层302，所述缓冲层302内具有贯穿所述缓冲层302的开口309。
本实施例中，位于所述电路布线层303上的导电凸块304围成指定区域，且形成的所述阻挡结构308位于所述指定区域外侧。有关阻挡结构308的材料和结构可参考前述实施例的相应说明，在此不再赘述。
需要说明的是，在其他实施例中，还可以先形成所述阻挡结构后形成所述导电凸块。
此外，还可以不在所述电路布线层上形成导电凸块，在后续提供的半导体芯片的焊盘上形成所述导电凸块。
参考图17，提供半导体芯片305，所述半导体芯片305正面具有功能区域306以及环绕所述功能区域306的焊盘307；将所述半导体芯片305倒装在所述基板倒装区I上方，所述焊盘307与电路布线层303之间通过导电凸块304实现电连接。
将所述半导体芯片305倒装在所述基板倒装区I上方的步骤包括：将所述半导体芯片305放置在所述基板倒装区I上，且所述焊盘307通过所述导电凸块304与电路布线层303相连接；对所述导电凸块304进行焊接键合处理，使得所述焊盘307通过导电凸块304与电路布线层303电连接。
有关焊接键合处理可参考前一实施例的相应描述，在此不再赘述。本实施例中，在进行所述焊接键合处理之前，所述基板与半导体芯片305正面之间的导电凸块304的厚度大于或等于所述阻挡结构306的厚度；且在所述焊接键合处理过程中，所述基板与半导体芯片305正面之间的导电凸块304的厚度减小，使得所述阻挡结构308顶部表面与所述半导体芯片305正面相接触。
因此，本实施例中，在将所述半导体芯片305倒装在所述基板倒装区I上方之后，所述阻挡结构308顶部表面与所述半导体芯片305正面相接触，因此所述阻挡结构308、半导体芯片305、基板以及电路布线层303围成封闭区域。本实施例中，在将所述半导体芯片305倒装在所述基板倒装区I上方之后，所述导电凸块304围成指定区域，所述阻挡结构308位于所述指定区域外侧，且所述阻挡结构308位于所述半导体芯片305投影于基板的投影区域内。
在其他实施例中，结合参考图19，所述阻挡结构308位于所述指定区域外侧，且所述阻挡结构308包括：第一阻挡结构318以及位于第一阻挡结构318一侧且紧挨所述第一阻挡结构318的第二阻挡结构328；在将所述半导体芯片305倒装在所述基板倒装区I上方之后，所述半导体芯片305投影于基板的区域为投影区域，所述第一阻挡结构318位于所述投影区域外侧，所述第二阻挡结构328位于所述投影区域内；相应的，在将所述半导体芯片305倒装在所述基板倒装区I上方之前，形成所述阻挡结构308；且在将所述半导体芯片305倒装在所述基板倒装区I上方之后，所述第二阻挡结构328顶部表面与所述半导体芯片305正面相接触；在所述焊接键合处理过程中，所述基板与半导体芯片305正面之间的导电凸块304的厚度减小，使得所述第二阻挡结构328顶部表面与所述半导体芯片305正面相接触。
此外，当所述第一阻挡结构318的厚度与所述第二阻挡结构328的厚度相等时，所述第一阻挡结构318顶部与所述半导体芯片305正面齐平；当所述第二阻挡结构328的厚度大于所述第一阻挡结构318的厚度时，在所述焊接键合处理之后，所述第一阻挡结构318还覆盖半导体芯片305部分侧壁。
参考图18，在所述基板上形成密封层310，所述密封层310包围所述影半导体芯片305；在所述基板上形成焊接凸起311，所述焊接凸起311与所述电路布线层303电连接。
本实施例中，所述密封层310还位于所述电路布线层303上以及半导体芯片305部分侧边表面；采用点胶工艺或者塑封工艺，形成所述密封层310。
本实施例中，所述焊接凸起311与所述密封层310相互分立，所述焊接凸起311位于所述基板上且位于所述半导体芯片305的外侧。在其他实施例中，所述焊接凸起还可以位于所述密封层内且贯穿所述密封层。
在形成所述密封层310的工艺过程中，所述阻挡结构308对所述密封层310的材料起到阻挡作用，使得密封层310的材料无法溢入功能区域306内，从而避免对功能区域306造成污染；此外，所述阻挡结构308还对导电凸块304起到保护作用，避免密封层310材料对导电凸块304造成污染，防止密封层310材料对导电凸块304的导电性能造成干扰。
在其他实施例中，参考图19，所述阻挡结构308包括第一阻挡结构318以 及紧挨所述第一阻挡结构318的第二阻挡结构328。其中，所述第二阻挡结构328顶部表面与所述半导体芯片305正面相接触，且第一阻挡结构318顶部与半导体芯片305正面齐平；或者，第一阻挡结构318顶部高于半导体芯片305正面，且第一阻挡结构318还覆盖半导体芯片305侧壁。相应的，形成的所述密封层310位于所述第一阻挡结构318顶部上，所述密封层310还可以位于电路布线层上。所述第一阻挡结构318可以起到密封层310的作用，使得第一阻挡结构318占据原本应形成密封层310的空间位置，从而进一步的降低了密封层310材料溢入功能区域306的风险。
结合参考图18和图7、以及图19和图9，后续的工艺步骤还包括：沿切割道区域II切割所述基板，形成若干如图7以及图9所示的单颗封装结构。
本申请又一实施例还提供一种封装方法，图20及图21为本申请又一实施例提供的封装结构形成过程的结构示意图。
与前述实施例不同之处在于，本实施例中，半导体芯片投影于基板的区域为投影区域，形成的阻挡结构位于所述投影区域外侧，且所述阻挡结构顶部高于所述半导体芯片正面。
参考图20，提供基板，所述基板包括倒装区I以及位于相邻倒装区I之间的切割道区域II，所述基板倒装区I上具有电路布线层403；在所述电路布线层403上形成导电凸块404；在所述电路布线层403上以及基板上形成阻挡结构408；提供半导体芯片405，所述半导体芯片405正面具有功能区域406以及环绕所述功能区域406的焊盘407；将所述半导体芯片405倒装在基板倒装区I上方，所述焊盘407与所述电路布线层403通过导电凸块404实现电连接。
本实施例中，所述基板包括基底401以及位于基底401上的缓冲层402，所述缓冲层420内形成有贯穿所述缓冲层402的开口409。
有关阻挡结构408的材料和结构请相应参考前述说明，在此不再赘述。
本实施例中，在将所述半导体芯片405倒装在所述基板倒装区I上方之后，所述半导体芯片405投影于基板的区域为投影区域，所述阻挡结构408位于所述投影区域外侧，且所述阻挡结构408顶部高于所述半导体芯片405正面。
本实施例中，所述阻挡结构408与所述半导体芯片405侧壁之间具有间隙；由于后续会在所述阻挡结构408上形成覆盖半导体芯片405侧壁的密封层，若 所述间隙的宽度尺寸过大，则所述密封层的材料易经由所述间隙溢入功能区域406内。为此，本实施例中，在平行于所述基板表面方向上，所述间隙的宽度尺寸为2微米～10微米。
本实施例中，所述阻挡结构408顶部高于所述半导体芯片405正面。为保证阻挡结构408具有较强的阻挡密封层材料溢入的能力，所述阻挡结构408顶部与所述半导体芯片405正面之间的距离不宜过小。为此，本实施例中，在垂直于所述基板表面方向上，所述阻挡结构406顶部表面与所述半导体芯片405正面之间的距离为2微米～10微米。
还需要说明的是，在其他实施例中，所述阻挡结构与所述半导体芯片侧壁之间的间隙宽度尺寸还可以为0，也就是说，所述阻挡结构覆盖所述半导体芯片侧壁。
此外，本实施例中，以在将所述半导体芯片405倒装在所述基板倒装区I上方之前，形成所述阻挡结构408为例，避免了阻挡结构408的工艺过程对半导体芯片405引入不必要的损伤。在其他实施例中，还可以在将所述半导体芯片倒装在所述基板倒装区上方之后，形成所述阻挡结构。
有关形成所述阻挡结构408的工艺步骤可参考前述实施例的描述，在此不再赘述。所述阻挡结构408覆盖电路布线层403的面积可以根据需求进行灵活调整。
参考图21，在所述基板上形成密封层410，所述密封层410包围所述半导体芯片405；在所述基板上形成焊接凸起411，所述焊接凸起411与所述电路布线层403电连接。
本实施例中，所述密封层410还位于阻挡结构408顶部上，且在形成所述密封层410的工艺过程中，所述阻挡结构408适于阻挡所述密封层410的材料溢入功能区域406内，避免功能区域406受到污染。
在其他实施例中，所述密封层还可以位于阻挡结构侧壁上，且还可以位于所述电路布线层上以及基板上。
还需要说明的是，本实施例中，所述阻挡结构408与所述焊接凸起411相互分立。在其他实施例中，所述焊接凸起还可以位于所述阻挡结构内且贯穿所述阻挡结构。
结合参考图21和11，后续的工艺步骤包括，沿切割道区域II切割所述基板，形成若干如图11所示的单颗封装结构。
本申请提供的封装方法，由于在形成密封层之前，先形成了对功能区域起到保护作用的阻挡结构，所述阻挡结构适于阻挡密封层的材料溢入功能区域内，从而防止功能区域受到污染，使得形成的封装结构的性能和良率得到提高。
虽然本申请披露如上，但本申请并非限定于此。任何本领域技术人员，在不脱离本申请的精神和范围内，均可作各种更动与修改，因此本申请的保护范围应当以权利要求所限定的范围为准。

Claims (37)

  1. 一种封装结构，其特征在于，包括：
    基板；
    设置在所述基板上的电路布线层；
    位于所述电路布线层上的导电凸块；
    倒装在所述基板上方的半导体芯片，所述半导体芯片朝向所述基板的第一表面上设置有功能区域以及环绕所述功能区域的分立的焊盘，且所述焊盘与所述导电凸块电连接；
    位于所述基板上的密封层，所述密封层包围所述半导体芯片；以及
    位于所述基板上的阻挡结构，所述阻挡结构环绕所述功能区域，以阻挡所述密封层的材料溢入功能区域。
  2. 如权利要求1所述的封装结构，其特征在于，所述电路布线层的顶部高于所述基板的顶部；或者
    所述电路布线层的顶部与所述基板的顶部平齐；或者
    所述电路布线层的顶部低于所述基板的顶部。
  3. 如权利要求1所述的封装结构，其特征在于，所述导电凸块围成指定区域，且所述阻挡结构位于所述指定区域内。
  4. 如权利要求3所述的封装结构，其特征在于，所述阻挡结构位于所述导电凸块与所述功能区域之间；且所述阻挡结构顶部表面与所述半导体芯片的第一表面相接触，所述阻挡结构底部表面与所述基板相接触。
  5. 如权利要求3所述的封装结构，其特征在于，在平行于所述基板顶面的方向上，所述阻挡结构的顶部表面宽度尺寸小于或等于底部表面宽度尺寸。
  6. 如权利要求1所述的封装结构，其特征在于，所述导电凸块围成指定区域，所述阻挡结构位于所述指定区域外侧；且所述阻挡结构还位于所述半导体芯片与所述基板之间。
  7. 如权利要求6所述的封装结构，其特征在于，所述半导体芯片投影于基板的区域为投影区域，所述阻挡结构位于所述投影区域内；且所述阻挡结构顶部表面与所述半导体芯片的第一表面相接触，所述阻挡结构底部表面与所述基板相接触。
  8. 如权利要求6所述的封装结构，其特征在于，所述阻挡结构包括：第一阻挡结构、位于第一阻挡结构一侧且紧挨所述第一阻挡结构的第二阻挡结构，其中，所述半导体芯片投影于基板的区域为投影区域，所述第一阻挡结构位于所述投影区域外侧，所述第二阻挡结构位于所述投影区域内；且所述第二阻挡结构顶部表面与所述半导体芯片的所述第一表面相接触。
  9. 如权利要求8所述的封装结构，其特征在于，位于所述基板上的第二阻挡结构的厚度为第一厚度，且所述半导体芯片的所述第一表面与所述基板之间的距离等于所述第一厚度。
  10. 如权利要求9所述的封装结构，其特征在于，位于所述基板上的第一阻挡结构的厚度为第二厚度，其中，所述第二厚度大于或等于所述第一厚度。
  11. 如权利要求8所述的封装结构，其特征在于，所述密封层还位于所述第一阻挡结构顶部上。
  12. 如权利要求1所述的封装结构，其特征在于，所述半导体芯片投影于基板的区域为投影区域，所述阻挡结构位于所述投影区域外侧；且所述阻挡结构顶部高于所述半导体芯片的第一表面。
  13. 如权利要求12所述的封装结构，其特征在于，在平行于所述基板顶面的方向上，所述阻挡结构与所述半导体芯片侧壁之间具有间隙。
  14. 如权利要求13所述的封装结构，其特征在于，在平行于所述基板顶面的方 向上，所述间隙的宽度尺寸为2微米～10微米。
  15. 如权利要求13所述的封装结构，其特征在于，在垂直于所述基板顶面的方向上，所述阻挡结构顶部表面与所述半导体芯片的所述第一表面之间的距离为2微米～10微米。
  16. 如权利要求12所述的封装结构，其特征在于，所述密封层位于所述阻挡结构顶部上。
  17. 如权利要求1所述的封装结构，其特征在于，所述阻挡结构的形状为封闭环形。
  18. 如权利要求1所述的封装结构，其特征在于，所述阻挡结构与所述导电凸块侧壁相接触；且所述阻挡结构的材料为绝缘材料。
  19. 如权利要求1所述的封装结构，其特征在于，所述阻挡结构与所述导电凸块相互分离；且所述阻挡结构的材料为绝缘材料或导电材料。
  20. 如权利要求18或19所述的封装结构，其特征在于，所述绝缘材料为感光胶。
  21. 如权利要求1所述的封装结构，其特征在于，所述阻挡结构为叠层结构，包括：与所述基板以及电路布线层相接触的底层阻挡层、以及与所述半导体芯片的所述第一表面相接触的顶层阻挡层，其中，所述底层阻挡层的材料为绝缘材料，所述顶层阻挡层的材料为导电材料或绝缘材料。
  22. 如权利要求1所述的封装结构，其特征在于，所述基板包括基底，所述基底为透光基底或PCB基底；
    当所述基底为PCB基底时，所述PCB基板内形成有贯穿所述PCB基底的通孔，所述功能区域位于所述通孔上方；以及
    当所述基底为透光基底时，所述透光基底上设置有缓冲层，所述电路布线层位于所述缓冲层上，在缓冲层上对应功能区域的位置设置有开口，所述开 口底部暴露所述透光基底。
  23. 如权利要求22所述的封装结构，其特征在于，所述缓冲层的材料为有机高分子光刻胶。
  24. 如权利要求1所述的封装结构，其特征在于，所述封装结构还包括：位于所述基板上的焊接凸起，所述焊接凸起与所述电路布线层电连接；且所述焊接凸起位于所述半导体芯片的外侧。
  25. 如权利要求1所述的封装结构，其特征在于，所述半导体芯片为影像传感芯片；以及所述功能区域为感光区域。
  26. 一种封装方法，其特征在于，包括：
    提供若干单个的半导体芯片，所述半导体芯片的第一表面具有功能区域以及环绕所述功能区域的焊盘；
    提供基板，所述基板包括倒装区以及位于相邻倒装区之间的切割道区域；
    在所述基板的倒装区上设置有电路布线层；
    将所述半导体芯片倒装在所述基板倒装区上方，且所述焊盘与所述电路布线层通过导电凸块电连接；
    在所述基板上形成密封层，且所述密封层包围所述半导体芯片；以及
    在形成所述密封层之后，沿所述切割道区域切割所述基板，形成若干单颗封装结构；
    其中，在形成所述密封层之前，还包括：在所述基板上形成阻挡结构，所述阻挡结构环绕功能区域，以阻挡所述密封层的材料溢入功能区域。
  27. 如权利要求26所述的封装方法，其特征在于，在将所述半导体芯片倒装在所述基板倒装区上方之前，在所述焊盘上形成所述导电凸块。
  28. 如权利要求26所述的封装方法，其特征在于，在将所述半导体芯片倒装在所述基板倒装区上方之前，在所述电路布线层上形成所述导电凸块。
  29. 如权利要求26所述的封装方法，其特征在于，形成所述阻挡结构的方法包括：
    在所述基板上形成阻挡膜；以及
    对所述阻挡膜进行曝光处理以及显影处理，以形成所述阻挡结构；或者，对所述阻挡膜进行刻蚀，以形成所述阻挡结构。
  30. 如权利要求26所述的封装方法，其特征在于，所述将半导体芯片倒装在所述基板倒装区上方的步骤包括：
    将所述半导体芯片放置在所述基板倒装区上，且所述焊盘通过所述导电凸块与所述电路布线层相连接；以及
    对所述导电凸块进行焊接键合处理，使得所述焊盘通过导电凸块与所述电路布线层电连接。
  31. 如权利要求30所述的封装方法，其特征在于，在将所述半导体芯片倒装在所述基板倒装区上方之后，所述导电凸块围成指定区域，且所述阻挡结构位于所述指定区域内；或者，所述阻挡结构位于所述指定区域外侧，且阻挡结构位于所述半导体芯片投影于基板的投影区域内；
    在将所述半导体芯片倒装在所述基板倒装区上方之前，形成所述阻挡结构；以及
    在将所述半导体芯片倒装在所述基板倒装区上方之后，所述阻挡结构顶部表面与所述半导体芯片的第一表面相接触。
  32. 如权利要求31所述的封装方法，其特征在于，在进行所述焊接键合处理之前，所述基板与所述半导体芯片的第一表面之间的导电凸块的厚度大于或等于所述阻挡结构的厚度；且在所述焊接键合处理过程中，所述基板与所 述半导体芯片的第一表面之间的导电凸块的厚度减小，使得所述阻挡结构顶部表面与所述半导体芯片的第一表面相接触。
  33. 如权利要求30所述的封装方法，其特征在于，所述阻挡结构包括：第一阻挡结构、位于第一阻挡结构一侧且紧挨所述第一阻挡结构的第二阻挡结构；在将所述半导体芯片倒装在所述基板倒装区上方之后，所述半导体芯片投影于基板的区域为投影区域，所述第一阻挡结构位于所述投影区域外侧，所述第二阻挡结构位于所述投影区域内；以及所述封装方法还包括：
    在将所述半导体芯片倒装在所述基板倒装区上方之前，形成所述阻挡结构；以及
    在将所述半导体芯片倒装在所述基板倒装区上方之后，所述第二阻挡结构顶部表面与所述半导体芯片的第一表面相接触。
  34. 如权利要求33所述的封装方法，其特征在于，在所述焊接键合处理过程中，所述基板与半导体芯片的第一表面之间的导电凸块的厚度减小，使得所述第二阻挡结构顶部表面与所述半导体芯片的第一表面相接触，且所述第一阻挡结构覆盖半导体芯片部分侧壁。
  35. 如权利要求26或30所述的封装方法，其特征在于，在将所述半导体芯片倒装在所述基板倒装区上方之后，所述半导体芯片投影于基板的区域为投影区域，所述阻挡结构位于所述投影区域外侧，且所述阻挡结构顶部高于所述半导体芯片的第一表面；
    在将所述半导体芯片倒装在所述基板倒装区上方之前，形成所述阻挡结构；或者，
    在将所述半导体芯片倒装在所述基板倒装区上方之后，形成所述阻挡结构。
  36. 如权利要求26所述的封装方法，其特征在于，所述封装方法还包括，在所述基板上形成焊接凸起，所述焊接凸起与所述电路布线层电连接。
  37. 如权利要求26所述的封装方法，其特征在于，采用点胶工艺或者塑封工艺，形成所述密封层。
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