WO2018006447A1 - 液晶显示面板的数据驱动系统 - Google Patents

液晶显示面板的数据驱动系统 Download PDF

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Publication number
WO2018006447A1
WO2018006447A1 PCT/CN2016/090891 CN2016090891W WO2018006447A1 WO 2018006447 A1 WO2018006447 A1 WO 2018006447A1 CN 2016090891 W CN2016090891 W CN 2016090891W WO 2018006447 A1 WO2018006447 A1 WO 2018006447A1
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Prior art keywords
data driving
signal
data
chip
turned
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English (en)
French (fr)
Inventor
熊志
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US15/127,393 priority Critical patent/US10417986B2/en
Publication of WO2018006447A1 publication Critical patent/WO2018006447A1/zh
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/08—Details of image data interface between the display device controller and the data line driver circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/14—Use of low voltage differential signaling [LVDS] for display data communication

Definitions

  • the present invention generally relates to the field of liquid crystal display, and more particularly to a data driving system for a liquid crystal display panel.
  • Liquid crystal display (LCD) data drive system uses different voltages to change the arrangement direction of liquid crystal molecules, and then different light transmittances of each pixel to form different gray scales of the screen, so the new generation display While the resolution, brightness and reaction time are continuously optimized, the data drive system also needs higher frequency and higher voltage to meet the requirements of high scanning frequency and fast update. Therefore, the number of chips in the data drive system will also increase according to demand. .
  • the function of the X-circuit board is to transmit the signal of the control board to the liquid crystal display panel.
  • the data driver chip source driver IC.
  • the size of the X-circuit board becomes longer and longer, causing the remote data driving chip to be too far away from the near-end data driving chip, thereby causing the impedance discontinuity to be received by the data driving chip. The signal is getting worse and worse.
  • the method of setting the terminating resistor at the terminal of the transmission line is generally adopted to improve the quality of the received signal.
  • the timing control chip (TCON IC) on the control board and the data driving chip communicate using a mini-LVDS differential signal mode, and the transmitting end (TX) inside the timing control chip transmits a data signal ( Data signal), the data signal is a current signal, and the terminating resistor disposed inside the data driving chip can convert the current signal into a voltage signal.
  • a terminal resistor is required inside each of the data driving chips.
  • the existing data driving system includes a plurality of data driving chips
  • the differential current signals input to the data driving system flow to the plurality of data driving chips, and therefore, the current of the differential signals received by each of the data driving chips is reduced. This will cause the output data drive voltage to drop, resulting in an abnormal display.
  • the present invention provides a data driving system for a liquid crystal display panel, comprising: a timing control chip; a plurality of data driving chips; and a plurality of first signal lines for using a predetermined data signal from the timing control chip Transmitting to the plurality of data driving chips, wherein each first signal line is disposed between the timing control chip and a data driving chip for transmitting the predetermined data signal from the timing control chip to The one data driving chip; the plurality of first transmission gates, wherein each of the first transmission gates is disposed on a first signal line.
  • the plurality of first transmission gates are not turned on at the same time.
  • the plurality of first transmission gates are sequentially turned on, and when each of the first transmission gates is turned on, The other first transmission gates are closed.
  • One of the plurality of data driving chips controls the first transmission gate on the first signal line connected to itself to be turned on in response to receiving the predetermined signal, thereby receiving the predetermined data signal.
  • the data driving chip receiving the predetermined data signal controls the first transmission gate of the first signal line connected to itself to be turned off, and outputs the control signal to one or more data driving chips in the data driving chip that does not receive the predetermined data signal
  • the data driving chip receiving the control signal controls the first transmission gate on the first signal line connected to itself to be turned on.
  • the data driving system further includes: a plurality of second signal lines for transmitting a clock control signal from the timing control chip to the plurality of data driving chips, wherein each second signal line is set at the timing a control chip and a data driving chip for transmitting the clock control signal to the one data driving chip; a plurality of second transmission gates, wherein each second transmission gate is disposed on a second signal line on.
  • the first transmission gate connected to the first signal line of any one of the data driving chips is turned on or off simultaneously with the second transmission gate connected to the second signal line of the arbitrary one of the data driving chips.
  • N is an integer greater than zero.
  • One of the plurality of data driving chips controls the second transmission gate on the second signal line connected to itself to be turned on in response to receiving the predetermined signal.
  • the clock control signal and the predetermined data signal are respectively transmitted as differential signals.
  • the invention provides a data driving system for a liquid crystal display panel, which controls whether a signal provided by a chip is transmitted to a data driving chip through a turn-on and turn-off control timing of a transmission gate, thereby realizing time-division opening of a plurality of data driving chips, and timing control chip
  • the provided signals are sequentially transmitted in the data driving chip, thereby avoiding a decrease in current of the data signal received by each data driving chip due to the flow of the data signal provided by the timing control chip to the plurality of data driving chips, and a voltage drop after the conversion.
  • the problem is that the quality of the signal received by the data driving chip is significantly improved, and the signal receiving error is effectively avoided.
  • FIG. 1 is a schematic view showing a data driving system of a liquid crystal display panel of an embodiment of the present invention.
  • FIG. 2 is a timing chart showing a data driving system of the liquid crystal display panel of FIG. 1.
  • a data driving system of a liquid crystal display panel according to an embodiment of the present invention will be described below with reference to FIGS. 1 and 2.
  • the liquid crystal embodiment of the present invention proposes a display panel driving data system comprising: a timing control chip 100, a plurality of data driving chips SD1, SD2, whil, SDi, a plurality of first signal lines L 11, L 21 , ..., L i1 , a plurality of first transmission gates TG 11 , TG 21 , ..., TG i1 .
  • i is a positive integer.
  • the timing control chip 100 is formed on a control board for providing a predetermined data signal and a clock signal required for the liquid crystal display panel to display an image.
  • the predetermined data signal and the clock control signal are respectively transmitted as differential signals, it being understood that, in this case, the signal lines transmitting the differential signals respectively include a positive line and a negative line.
  • the plurality of first signal lines are for transmitting a predetermined data signal from the timing control chip 100 to the plurality of data driving chips.
  • Each of the first signal lines is disposed between the timing control chip 100 and a data driving chip for transmitting the predetermined data signal to the one data driving chip.
  • the first signal line L 11 is disposed between the timing control chip 100 and the first data driving chip SD1 for transmitting the predetermined data signal to the first data driving chip SD1.
  • Each of the first transmission gates is disposed on a first signal line.
  • each of the first transmission gates controls whether the first signal line on which it is located transmits a predetermined data signal to the data driving chip to which the first signal line is connected.
  • a first transfer gate TG 11 is disposed on a first signal line L 11, when the first transfer gate TG 11 is turned on, the first signal line L 11 to a predetermined data signal to a first signal line L 11 is connected a first data driving chip SD1; SD1 when the first data driving chip is turned off when the first transfer gate TG 11, the first signal line L 11 is not the predetermined data signal to a first signal line L 11 is connected.
  • the first transmission gate is a CMOS transmission gate
  • two control terminals of the CMOS transmission gate are connected to an internal circuit of the data driving chip
  • an input end and an output end of the CMOS transmission gate are connected to the first signal line.
  • the first transmission gate in this embodiment is merely exemplary and can also be implemented by other transmission gates.
  • the plurality of first transmission gates are sequentially turned on, and when each of the first transmission gates is turned on, the other The first transmission gate is turned off. In other words, only one first transmission gate is turned on, so that the first signal line where the first transmission gate is located transmits the predetermined data signal to the data driving chip to which it is connected, in which case only the data driving chip receives The predetermined data signal provided by the timing control chip 100, then the predetermined data signal flows all the way to the data driving chip, which significantly improves the quality of the signal received by the data driving chip. It should be understood that the predetermined data signal received by each data driving chip is the same data signal provided by the timing control chip 100 during the sequential conduction of the plurality of first transmission gates.
  • the present invention is not limited thereto, and it should be understood that in the process of transmitting the predetermined data signal from the timing control chip 100 to the plurality of data driving chips, the plurality of first transmission gates may not be turned on at the same time.
  • the process of transmitting the predetermined data signal from the timing control chip 100 to the plurality of data driving chips only part of the first transmission gates are turned on, that is, not all of the first transmission gates are turned on, thereby Not all of the data driving chips receive the predetermined data signal provided by the timing control chip 100, and the current of the predetermined data signal received by each data driving chip caused by the predetermined data signal flowing to all the data driving chips can be prevented from being reduced and converted.
  • the problem of voltage reduction It should be understood that when the plurality of first transmission gates are not turned on at the same time, the predetermined data signals received by the partial data driving chips are the same data signals provided by the timing control chip 100.
  • one of the plurality of data driving chips controls the first transmission gate on the first signal line connected to itself to be turned on in response to receiving the predetermined signal, thereby receiving the predetermined data signal.
  • the predetermined signal is a direct current voltage DC.
  • the data driving chip that receives the predetermined signal first receives the predetermined data signal supplied from the timing control chip.
  • the data driving chip controls the first transmission gate of the first signal line connected to itself to be turned off, and outputs the control signal to a data driving chip of the data driving chip that does not receive the predetermined data signal; receiving The data driving chip of the control signal controls the first transmission gate on the first signal line connected to itself to be turned on. This is done in sequence until the last data drive chip receives the predetermined data signal.
  • the first data driving chip SD1 controls the first transmission gate TG 11 on the first signal line L 11 connected to itself to be turned on in response to receiving the predetermined signal, thereby receiving the predetermined data signal; the first data driving chip SD1 a first control signal line connected to the connection L on the first transfer gate 11 TG 11 is turned off, and outputs a control signal P 1 to a predetermined data signal is not received second data driving chip SD2, SD2 second data driving chip controlling their a first signal line L on the first transfer gate 21 is connected to the TG 21 is turned on, to receive a predetermined data signal; a second control of the first data driving signal SD2 chip connected to the connection line L 21 on the first transfer gate TG 21 is turned off And outputting the control signal P 2 to a third data driving chip (not shown) that has not received the predetermined data signal; the third data driving chip controls the first transmission on the first signal line (not shown) to which it is connected A gate (not shown) is turned on to receive a predetermined data signal.
  • the last data driving chip i.e., the i-th data driving chip SDi
  • the first transmission gate TG i1 on the first signal line L i1 to which it is connected to be turned on, thereby receiving the predetermined data signal.
  • the signal transmission process between the plurality of data driving chips provided by the embodiment is merely exemplary, and the present invention is not limited thereto.
  • the data driving chip that receives the predetermined data signal controls the first transmission gate of the first signal line connected to itself to be turned off, and may also output the control signal to the signal that the predetermined data signal is not received.
  • a plurality of data driving chips in the data driving chip; and the plurality of data driving chips receiving the control signals respectively control the first transmission gate of the first signal line connected to the first transmission gate to be turned on. This is done in sequence until all data drive chips receive the predetermined data signal.
  • the data driving chip receiving the predetermined data signal outputs a control signal to a partial data driving chip in the data driving chip that does not receive the predetermined data signal, and the partial driving chip controls the first transmission on the first signal line connected to itself.
  • the gate is turned on to transfer the predetermined data signal from the timing control chip 100 to a portion of the data driving chip.
  • a part of the data driving chip that receives the predetermined data signal by the control signal and a part of the data driving chips of the plurality of data driving chips that do not receive the predetermined data signal are sequentially turned on until all the data driving chips receive the reservation. Data signal.
  • the received data signal a first predetermined data driving chip SD1 and SD2 second data driving chips, respectively, a first control signal P 1 and P 2 outputs a second control signal to a predetermined data signal is not received third data driving chip
  • the SD3 (not shown) and the fourth data driving chip SD4 (not shown) respectively control the first transmission gate of the first signal line connected thereto to be simultaneously turned on. And thereby receiving the predetermined data signal provided by the timing control chip 100.
  • the third data driving chip SD3 and the fourth data driving chip SD4 respectively control the first transmission gates on the first signal line connected by themselves to be simultaneously turned off, and respectively respectively control the third control signal P 3 (not shown) and the fourth control signal.
  • P 4 (not shown) is output to the fifth data driving chip SD5 (not shown) and the sixth data driving chip SD6 (not shown) that have not received the predetermined data signal, and the fifth data driving chip SD5 and the sixth data.
  • the driving chip SD6 controls the first transmission gate on the first signal line connected to itself to be simultaneously turned on, thereby receiving the predetermined data signal provided by the timing control chip 100. This is done in sequence until all data drive chips receive the predetermined data signal. It should be understood that the signal transmission process of sequentially turning on two data driving chips simultaneously in this embodiment is merely exemplary, and the present invention is not limited thereto.
  • the data driving system further includes: a plurality of second signal lines L 12 , L 22 , . . . , L i2 and a plurality of second transmission gates TG 12 , TG 22 , . . . , TG i2 .
  • i is a positive integer.
  • the plurality of second signal lines are for transmitting a clock control signal from the timing control chip 100 to the plurality of data driving chips.
  • Each of the second signal lines is disposed between the timing control chip and a data driving chip for transmitting the clock control signal to the one data driving chip.
  • the second signal line L 12 is disposed between the timing control chip and the first data driving chip SD1 for transmitting the clock control signal to the first data driving chip SD1.
  • Each of the second transmission gates is disposed on a second signal line.
  • each of the second transmission gates controls whether the second signal line on which it is located transmits a clock control signal to the data driving chip to which the second signal line is connected.
  • the second transfer gate TG 12 is provided on the second signal line L 12, when the second transfer gate TG 12 is turned on, the second clock signal line L 12 a control signal to the second signal line L 12 is connected.
  • the second transmission gate is a CMOS transmission gate, and the two control ends of the CMOS transmission gate are connected to an internal circuit of the data driving chip, and the input end and the output end of the CMOS transmission gate are connected to the second signal line.
  • the second transmission gate in this embodiment is merely exemplary and can also be implemented by other transmission gates.
  • the first transmission gate connected to the first signal line of any one of the data driving chips is simultaneously turned on or off with the second transmission gate connected to the second signal line of the any one of the data driving chips.
  • any one of the data driving chips controls the first transmission gate on the first signal line and the second transmission gate on the second signal line that are connected to each other to be turned on or off at the same time, thereby receiving the predetermined data signal provided by the timing control chip 100 and A clock control signal of N clock cycles, where N is an integer greater than zero.
  • One of the plurality of data driving chips controls the second transmission gate on the second signal line connected to itself to be turned on in response to receiving the predetermined signal.
  • the data driving chip that receives the predetermined signal first receives the predetermined data signal and the clock control signal supplied from the timing control chip 100.
  • the timing control chip 100 provides a clock control signal, and the time corresponding to the N clock cycles of the clock control signal is to receive the N
  • the data of the clock control signal of one clock cycle drives the time when the chip is turned on, and when the clock control signal of the Nth clock cycle is received, the data drive chip is turned off.
  • the data driving chip receiving the clock control signal outputs a control signal to a data driving chip in the data driving chip that does not receive the clock control signal when receiving the clock control signal of the Mth clock cycle.
  • the data driving chip receiving the control signal controls the first transmission gate of the first signal line connected to itself to be turned on. This is done in sequence until the last data drive chip receives the predetermined data signal and the clock control signal.
  • the data driving chip that receives the clock control signal can output the control signal to the data driving that does not receive the clock control signal when receiving the clock control signal of the Mth clock cycle.
  • M is a positive integer smaller than N; and the plurality of data driving chips receiving the control signal respectively control the second transmission gate delay on the second signal line connected to the NM clock cycle Passing, so that when the data driving chip receiving the clock control signal controls the first transmission gate of the first signal line connected to itself to be turned off, the plurality of data driving chips receiving the control signal control the first signal line connected by itself The first transmission gate is turned on.
  • FIG. 2 is a timing chart showing a data driving system of the liquid crystal display panel of FIG. 1.
  • a first data driving chip SD1 in response to receiving the DC to DC voltage, a first control signal line connected to the connection L on the first transfer gate 11 TG 11 and the second signal line L on the second transfer gate TG 12 12 is simultaneously turned on, thereby receiving the predetermined data signal and the clock control signal CLK of N clock cycles, and controlling the first signal line L 11 connected thereto when the clock control signal of the Nth clock cycle is received.
  • the first transmission gate TG 11 is turned off.
  • First Off transfer gate TG 21 and outputs a control signal P 2 to a predetermined data signal is not received third data driving chip (not shown); a third data driving chip to control the first signal line connected to the connection (not shown)
  • the upper first transmission gate (not shown) is turned on. It should be understood that each data driving chip simultaneously receives a predetermined data signal and a clock control signal.
  • the data driving system of the liquid crystal display panel whether the signal provided by the chip is transmitted to the data driving chip by the turn-on and turn-off control timing of the transmission gate, thereby realizing time-sharing to turn on the plurality of data driving chips, thereby enabling
  • the signal provided by the timing control chip is sequentially transmitted in the data driving chip, thereby avoiding the current reduction of the data signal received by each data driving chip caused by the data signal provided by the timing control chip flowing to the plurality of data driving chips, and the converted
  • the problem of voltage reduction significantly improves the quality of the signal received by the data driving chip and effectively avoids signal reception errors.

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Abstract

一种液晶显示面板的数据驱动系统，包括：时序控制芯片（100）；多个数据驱动芯片（SD1、SD2、……、SDi）；多个第一信号线（L 11、L 21、……、L i1），用于将预定数据信号从时序控制芯片（100）传输至多个数据驱动芯片（SD1、SD2、……、SDi），其中，每个第一信号线（L 11、L 21、……、L i1）设置在时序控制芯片（100）与一个数据驱动芯片（SD1、SD2、……、SDi）之间，以用于将预定数据信号从时序控制芯片（100）传输至一个数据驱动芯片（SD1、SD2、……、SDi）；多个第一传输门（TG 11、TG 21、……、TG i1），其中，每个第一传输门（TG 11、TG 21、……、TG i1）设置在一个第一信号线（L 11、L 21、……、L i1）上。数据驱动系统通过传输门（TG 11、TG 21、……、TG i1）的导通和截止控制时序控制芯片（100）提供的信号是否向数据驱动芯片（SD1、SD2、……、SDi）传输，进而实现分时逐个开启数据驱动芯片（SD1、SD2、……、SDi），使时序控制芯片（100）提供的信号依次在数据驱动芯片（SD1、SD2、……、SDi）中传递，从而显著提高数据驱动芯片（SD1、SD2、……、SDi）接收信号的质量，且有效避免信号接收错误。

Description

液晶显示面板的数据驱动系统 技术领域
本发明总体说来涉及液晶显示领域，更具体地讲，涉及一种液晶显示面板的数据驱动系统。
背景技术
液晶显示器(Liquid Crystal Display，LCD)的数据驱动系统是利用输出不同的电压来改变液晶分子的排列方向，再透过每个像素不同的透光程度来构成画面不同的灰阶，故新一代显示器在分辨率、亮度与反应时间不断优化的同时，数据驱动系统也需要更高频与更高电压才能满足高扫描频率与快速更新的需求，因此，数据驱动系统的芯片数量也将依据需求而提高。
在现有的液晶显示器的X-电路板(X board)和控制板(Control board)分离的面板驱动架构中，X-电路板的作用是将控制板的信号传递到设于液晶显示面板上的数据驱动芯片(source driver IC)内部。随着数据驱动芯片数量的增加，X-电路板的尺寸越来越长，导致远端的数据驱动芯片与近端的数据驱动芯片距离过远，进而引起阻抗不连续，使数据驱动芯片接收的信号变得越来越差。
目前，通常采用在传输线终端设置终端电阻的方式，提高接收信号的质量。另外，控制板上的时序控制芯片(Timing control IC，TCON IC)与数据驱动芯片之间采用mini-LVDS的差分信号方式进行通信，时序控制芯片内部的发射端(TX)传输的是数据信号(data signal)，该数据信号是一种电流信号，设置在数据驱动芯片内部的终端电阻可以将电流信号转换为电压信号。为了避免差分信号(例如数据电流信号)在传输时，由于信号在传输线传输在终端形成反射波，干扰原信号，每个数据驱动芯片的内部均需设置一个终端电阻。然而，由于现有的数据驱动系统包括多个数据驱动芯片，输入数据驱动系统的差分电流信号会流向多个数据驱动芯片，因此，每个数据驱动芯片接收到的差分信号的电流将减小，这样就会导致输出的数据驱动电压降低，从而导致画面显示异常。
因此，亟需开发一种新型的液晶显示面板的数据驱动系统，以解决上述存在的问题。
发明内容
本发明的目的在于提供一种液晶显示面板的数据驱动系统，可以显著提高数据驱动芯片接收信号的质量，且有效避免信号接收错误。
为实现上述发明目的，本发明提供一种液晶显示面板的数据驱动系统，包括：时序控制芯片；多个数据驱动芯片；多个第一信号线，用于将预定数据信号从所述时序控制芯片传输至所述多个数据驱动芯片，其中，每个第一信号线设置在所述时序控制芯片与一个数据驱动芯片之间，以用于将所述预定数据信号从所述时序控制芯片传输至所述一个数据驱动芯片；多个第一传输门，其中，每个第一传输门设置在一个第一信号线上。
在将所述预定数据信号从所述时序控制芯片传输至所述多个数据驱动芯片的过程中，所述多个第一传输门不同时导通。
在将所述预定数据信号从所述时序控制芯片传输至所述多个数据驱动芯片的过程中，所述多个第一传输门依次导通，并且在每个第一传输门导通时，其他第一传输门截止。
所述多个数据驱动芯片中的一个数据驱动芯片响应于接收到预定信号，控制自己连接的第一信号线上的第一传输门导通，从而接收所述预定数据信号。
接收到预定数据信号的数据驱动芯片控制自己连接的第一信号线上的第一传输门截止，并将控制信号输出到未接收到预定数据信号的数据驱动芯片中的一个或多个数据驱动芯片；接收到控制信号的数据驱动芯片控制自己连接的第一信号线上的第一传输门导通。
所述数据驱动系统还包括：多个第二信号线，用于将时钟控制信号从所述时序控制芯片传输至所述多个数据驱动芯片，其中，每个第二信号线设置在所述时序控制芯片与一个数据驱动芯片之间，以用于将所述时钟控制信号传输至所述一个数据驱动芯片；多个第二传输门，其中，每个第二传输门设置在一个第二信号线上。
连接到任意一个数据驱动芯片的第一信号线上的第一传输门与连接到所述任意一个数据驱动芯片的第二信号线上的第二传输门同时导通或截止。
每当一个数据驱动芯片在完成第N个时钟周期的时钟控制信号的接收时，控制自己连接的第一信号线上的第一传输门截止，其中，N为大于0的整数。
接收到时钟控制信号的数据驱动芯片在完成第M个时钟周期的时钟控制信号的接收时，将控制信号输出到未接收到时钟控制信号的数据驱动芯片中的一个或多个数据驱动芯片，其中，M为小于N的正整数；接收到控制信号的数据驱动芯片控制自己连接的第二信号线上的第二传输门延迟N-M个时钟周期导通，从而当接收到时钟控制信号的数据驱动芯片控制自己连接的第一信号线上的第一传输门截止时，接收到控制信号的数据驱动芯片控制自己连接的第一信号线上的第一传输门导通。
所述多个数据驱动芯片中的一个数据驱动芯片响应于接收到预定信号，控制自己连接的第二信号线上的第二传输门导通。
所述时钟控制信号和所述预定数据信号分别以差分信号的方式来传输。
本发明提供一种液晶显示面板的数据驱动系统，通过传输门的导通和截止控制时序控制芯片提供的信号是否向数据驱动芯片传输，进而实现分时开启多个数据驱动芯片，使时序控制芯片提供的信号依次在数据驱动芯片中传递，避免由于时序控制芯片提供的数据信号流向多个数据驱动芯片而导致的每个数据驱动芯片接收到的数据信号的电流减小、转换后的电压降低的问题，显著提高数据驱动芯片接收信号的质量，且有效避免信号接收错误。
附图说明
图1示出本发明实施例的液晶显示面板的数据驱动系统的示意图。
图2示出图1的液晶显示面板的数据驱动系统的时序图。
具体实施方式
下面参照图1和图2描述根据本发明的实施例的液晶显示面板的数据驱动系统。
图1示出根据本发明实施例的液晶显示面板的数据驱动系统的示意图。参照图1，本发明的实施例中提出的液晶显示面板的数据驱动系统包括：时序控 制芯片100、多个数据驱动芯片SD1、SD2、……、SDi、多个第一信号线L11、L21、……、Li1、多个第一传输门TG11、TG21、……、TGi1。其中，i为正整数。
这里，时序控制芯片100制作于控制板(Control board)上，用于提供液晶显示面板显示影像所需的预定数据信号和时钟控制信号(clock signal)。优选地，所述预定数据信号和时钟控制信号分别以差分信号的方式来传输，应当理解，在此情况下，传输差分信号的信号线分别包括正极线和负极线。
所述多个第一信号线用于将预定数据信号从时序控制芯片100传输至所述多个数据驱动芯片。每个第一信号线设置在时序控制芯片100与一个数据驱动芯片之间，以用于将所述预定数据信号传输至所述一个数据驱动芯片。例如，第一信号线L11设置在时序控制芯片100与第一数据驱动芯片SD1之间，以用于将所述预定数据信号传输至所述第一数据驱动芯片SD1。
每个第一传输门设置在一个第一信号线上。这里，每个第一传输门控制自己所在的第一信号线是否将预定数据信号传输至该第一信号线所连接的数据驱动芯片。例如，第一传输门TG11设置在第一信号线L11上，当第一传输门TG11导通时，该第一信号线L11将预定数据信号传输至第一信号线L11所连接的第一数据驱动芯片SD1；当第一传输门截止TG11时，该第一信号线L11不能将预定数据信号传输至第一信号线L11所连接的第一数据驱动芯片SD1。
优选地，第一传输门为CMOS传输门，该CMOS传输门的两个控制端连接至数据驱动芯片的内部电路，CMOS传输门的输入端和输出端连接在第一信号线上。应当理解，本实施例中的第一传输门仅是示例性的，还可通过其他的传输门来实现。
在将所述预定数据信号从时序控制芯片100传输至所述多个数据驱动芯片的过程中，所述多个第一传输门依次导通，并且在每个第一传输门导通时，其他第一传输门截止。换言之，仅有一个第一传输门导通，从而该第一传输门所在的第一信号线将预定数据信号传输至自己所连接的数据驱动芯片，在此情况下，仅有该数据驱动芯片接收时序控制芯片100提供的预定数据信号，那么，所述预定数据信号全部流向该数据驱动芯片，显著提高数据驱动芯片接收信号的质量。应当理解，在多个第一传输门依次导通的过程中，每个数据驱动芯片接收的预定数据信号为时序控制芯片100提供的同一数据信号。
然而，本发明不限于此，应当理解，在将所述预定数据信号从时序控制芯片100传输至所述多个数据驱动芯片的过程中，所述多个第一传输门可以不同时导通。换言之，在将所述预定数据信号从时序控制芯片100传输至所述多个数据驱动芯片的过程中，仅部分第一传输门导通，即，不是所有的第一传输门都导通，从而不是所有的数据驱动芯片都接收时序控制芯片100提供的预定数据信号，可以避免该预定数据信号流向全部数据驱动芯片而导致的每个数据驱动芯片接收到的预定数据信号的电流减小、转换后的电压降低的问题。应当理解，当所述多个第一传输门不同时导通时，部分数据驱动芯片接收的预定数据信号为时序控制芯片100提供的同一数据信号。
在本实施例中，所述多个数据驱动芯片中的一个数据驱动芯片响应于接收到预定信号，控制自己连接的第一信号线上的第一传输门导通，从而接收所述预定数据信号。优选地，所述预定信号为直流电压DC。换言之，接收到预定信号的数据驱动芯片最先接收时序控制芯片提供的预定数据信号。
接收到预定数据信号的数据驱动芯片控制自己连接的第一信号线上的第一传输门截止，并将控制信号输出到未接收到预定数据信号的数据驱动芯片中的一个数据驱动芯片；接收到控制信号的数据驱动芯片控制自己连接的第一信号线上的第一传输门导通。依次如此进行，直至最后一个数据驱动芯片接收到预定数据信号。
例如，第一数据驱动芯片SD1响应于接收到预定信号，控制自己连接的第一信号线L11上的第一传输门TG11导通，从而接收所述预定数据信号；第一数据驱动芯片SD1控制自己连接的第一信号线L11上的第一传输门TG11截止，并将控制信号P1输出到未接收到预定数据信号的第二数据驱动芯片SD2，第二数据驱动芯片SD2控制自己连接的第一信号线L21上的第一传输门TG21导通，以接收预定数据信号；第二数据驱动芯片SD2控制自己连接的第一信号线L21上的第一传输门TG21截止，并将控制信号P2输出到未接收到预定数据信号的第三数据驱动芯片(未示出)；第三数据驱动芯片控制自己连接的第一信号线(未示出)上的第一传输门(未示出)导通，以接收预定数据信号。依次如此进行，直至最后一个数据驱动芯片(即第i数据驱动芯片SDi)控制自己连接的第一信号线Li1上的第一传输门TGi1导通，从而接收到预定数据信号。应当理解，本实施例提供的多个数据驱动芯片之间的信号传递过程仅是示例性的， 本发明不限于此。
然而，本发明不限于此，应当理解，接收到预定数据信号的数据驱动芯片控制自己连接的第一信号线上的第一传输门截止，还可以将控制信号输出到未接收到预定数据信号的数据驱动芯片中的多个数据驱动芯片；接收到控制信号的多个数据驱动芯片均控制自己连接的第一信号线上的第一传输门导通。依次如此进行，直至全部数据驱动芯片均接收到预定数据信号。换言之，接收到预定数据信号的数据驱动芯片将控制信号输出到未接收到预定数据信号的数据驱动芯片中的部分数据驱动芯片，该部分驱动芯片控制自己连接的第一信号线上的第一传输门导通，从而将所述预定数据信号从时序控制芯片100传输至部分数据驱动芯片。依次如此进行，通过控制信号实现接收到预定数据信号的部分数据驱动芯片与未接收到预定数据信号的多个数据驱动芯片中的部分数据驱动芯片依次导通，直至全部数据驱动芯片均接收到预定数据信号。
例如，接收到预定数据信号的第一数据驱动芯片SD1和第二数据驱动芯片SD2分别将第一控制信号P1和第二控制信号P2输出至未接收到预定数据信号的第三数据驱动芯片SD3(未示出)和第四数据驱动芯片SD4(未示出)，第三数据驱动芯片SD3和第四数据驱动芯片SD4分别控制自己连接的第一信号线上的第一传输门同时导通，从而接收时序控制芯片100提供的所述预定数据信号。第三数据驱动芯片SD3和第四数据驱动芯片SD4分别控制自己连接的第一信号线上的第一传输门同时截止，并分别将第三控制信号P3(未示出)和第四控制信号P4(未示出)输出到未接收到预定数据信号的第五数据驱动芯片SD5(未示出)和第六数据驱动芯片SD6(未示出)，第五数据驱动芯片SD5和第六数据驱动芯片SD6分别控制自己连接的第一信号线上的第一传输门同时导通，从而接收时序控制芯片100提供的所述预定数据信号。依次如此进行，直至全部数据驱动芯片均接收到预定数据信号。应当理解，本实施例提供的依次同时导通两个数据驱动芯片的信号传递过程仅是示例性的，本发明不限于此。
下面详细描述本发明提供的数据驱动系统中分时逐个开启数据驱动芯片以接收时序控制芯片提供的信号的具体过程。
在本实施例中，所述数据驱动系统还包括：多个第二信号线L12、L22、……、 Li2和多个第二传输门TG12、TG22、……、TGi2。其中，i为正整数。
所述多个第二信号线用于将时钟控制信号从时序控制芯片100传输至所述多个数据驱动芯片。每个第二信号线设置在时序控制芯片与一个数据驱动芯片之间，以用于将所述时钟控制信号传输至所述一个数据驱动芯片。例如，第二信号线L12设置在时序控制芯片与第一数据驱动芯片SD1之间，以用于将所述时钟控制信号传输至所述第一数据驱动芯片SD1。
每个第二传输门设置在一个第二信号线上。这里，每个第二传输门控制自己所在的第二信号线是否将时钟控制信号传输至该第二信号线所连接的数据驱动芯片。例如，第二传输门TG12设置在第二信号线L12上，当第二传输门TG12导通时，该第二信号线L12将时钟控制信号传输至第二信号线L12所连接的第一数据驱动芯片SD1；当第二传输门截止TG12时，该第二信号线L12不能将时钟控制信号传输至第二信号线L12所连接的第一数据驱动芯片SD1。
优选地，第二传输门为CMOS传输门，该CMOS传输门的两个控制端连接至数据驱动芯片的内部电路，CMOS传输门的输入端和输出端连接在第二信号线上。应当理解，本实施例中的第二传输门仅是示例性的，还可通过其他的传输门来实现。
在本实施例中，连接到任意一个数据驱动芯片的第一信号线上的第一传输门与连接到所述任意一个数据驱动芯片的第二信号线上的第二传输门同时导通或截止。换言之，任意一个数据驱动芯片控制自己连接的第一信号线上的第一传输门和第二信号线上的第二传输门同时导通或截止，从而接收时序控制芯片100提供的预定数据信号和N个时钟周期的时钟控制信号，其中，N为大于0的整数。
所述多个数据驱动芯片中的一个数据驱动芯片响应于接收到预定信号，控制自己连接的第二信号线上的第二传输门导通。换言之，接收到预定信号的数据驱动芯片最先接收时序控制芯片100提供的预定数据信号和时钟控制信号。
每当一个数据驱动芯片在完成第N个时钟周期的时钟控制信号的接收时，控制自己连接的第一信号线上的第一传输门截止。换言之，时序控制芯片100提供时钟控制信号，该时钟控制信号的N个时钟周期对应的时间为接收该N 个时钟周期的时钟控制信号的数据驱动芯片开启的时间，当完成第N个时钟周期的时钟控制信号的接收时，该数据驱动芯片关闭。
在本实施例中，接收到时钟控制信号的数据驱动芯片在完成第M个时钟周期的时钟控制信号的接收时，将控制信号输出到未接收到时钟控制信号的数据驱动芯片中的一个数据驱动芯片，其中，M为小于N的正整数；接收到控制信号的数据驱动芯片控制自己连接的第二信号线上的第二传输门延迟N-M个时钟周期导通，从而当接收到时钟控制信号的数据驱动芯片控制自己连接的第一信号线上的第一传输门截止时，接收到控制信号的数据驱动芯片控制自己连接的第一信号线上的第一传输门导通。依次如此进行，直至最后一个数据驱动芯片接收到预定数据信号和时钟控制信号。换言之，当一个接收预定数据信号的数据驱动芯片关闭时，另一个未接收预定数据信号的数据驱动芯片立即开启，从而实现多个数据驱动芯片的分时逐个依次开启，并且，当一个数据驱动芯片开启时，其他数据驱动芯片均关闭。
然而，本发明不限于此，应当理解，接收到时钟控制信号的数据驱动芯片在完成第M个时钟周期的时钟控制信号的接收时，可以将控制信号输出到未接收到时钟控制信号的数据驱动芯片中的多个数据驱动芯片，其中，M为小于N的正整数；接收到控制信号的多个数据驱动芯片均控制自己连接的第二信号线上的第二传输门延迟N-M个时钟周期导通，从而当接收到时钟控制信号的数据驱动芯片控制自己连接的第一信号线上的第一传输门截止时，接收到控制信号的多个数据驱动芯片均控制自己连接的第一信号线上的第一传输门导通。依次如此进行，直至全部数据驱动芯片均接收到预定数据信号和时钟控制信号。换言之，接收到时钟控制信号的数据驱动芯片在完成第M个时钟周期的时钟控制信号的接收时，将控制信号输出到未接收到时钟控制信号的数据驱动芯片中的部分数据驱动芯片，该部分驱动芯片控制自己连接的第二信号线上的第二传输门延迟N-M个时钟周期导通。依次如此进行，通过控制信号实现当接收到时钟控制信号的部分数据驱动芯片关闭时，未接收到时钟控制信号的部分数据驱动芯片开启，直至全部数据驱动芯片均接收到预定数据信号和时钟控制信号。
图2示出图1的液晶显示面板的数据驱动系统的时序图。
参照图2，第一数据驱动芯片SD1响应于接收到直流电压DC，控制自己连接的第一信号线L11上的第一传输门TG11和第二信号线L12上的第二传输门TG12同时导通，从而接收所述预定数据信号和N个时钟周期的时钟控制信号CLK，并在完成第N个时钟周期的时钟控制信号的接收时，控制自己连接的第一信号线L11上的第一传输门TG11截止。第一数据驱动芯片SD1在完成第M个时钟周期的时钟控制信号的接收时(此时，还有N-M个时钟周期的时钟控制信号未接收，该N-M个时钟周期记为T1)，将控制信号P1输出到未接收到时钟控制信号的第二数据驱动芯片SD2；第二数据驱动芯片SD2控制自己连接的第二信号线L22上的第二传输门TG22延迟N-M个时钟周期导通(延迟的N-M个周期记为T2，且T1＝T2)，从而当第一数据驱动芯片完成第N个时钟周期的时钟控制信号的接收时(即第一数据驱动芯片SD1控制自己连接的第一信号线L11上的第一传输门TG11截止时)，接收到控制信号P1的第二数据驱动芯片SD2控制自己连接的第一信号线L21上的第一传输门TG21导通，从而接收所述预定数据信号和N个时钟周期的时钟控制信号CLK，并在完成第N个时钟周期的时钟控制信号的接收时，第二数据驱动芯片SD2控制自己连接的第一信号线L21上的第一传输门TG21截止，并将控制信号P2输出到未接收到预定数据信号的第三数据驱动芯片(未示出)；第三数据驱动芯片控制自己连接的第一信号线(未示出)上的第一传输门(未示出)导通。应当理解，每个数据驱动芯片同时接收预定数据信号和时钟控制信号。
依次如此进行，直至最后一个数据驱动芯片SDi接收到预定数据信号和时钟控制信号，进而实现分时逐个开启数据驱动芯片，以显著提高数据驱动芯片接收信号的质量，且有效避免信号接收错误。
采用上述根据本发明实施例的液晶显示面板的数据驱动系统，通过传输门的导通和截止控制时序控制芯片提供的信号是否向数据驱动芯片传输，进而实现分时开启多个数据驱动芯片，使时序控制芯片提供的信号依次在数据驱动芯片中传递，避免由于时序控制芯片提供的数据信号流向多个数据驱动芯片而导致的每个数据驱动芯片接收到的数据信号的电流减小、转换后的电压降低的问题，显著提高数据驱动芯片接收信号的质量，且有效避免信号接收错误。
上面已经结合具体实施例描述了本发明，但是本发明的实施不限于此。在本发明的精神和范围内，本领域技术人员可以进行各种修改和变型，这些修改 和变型将落入权利要求限定的保护范围之内。

Claims (20)

  1. 一种液晶显示面板的数据驱动系统，其中，包括：
    时序控制芯片；
    多个数据驱动芯片；
    多个第一信号线，用于将预定数据信号从所述时序控制芯片传输至所述多个数据驱动芯片，其中，每个第一信号线设置在所述时序控制芯片与一个数据驱动芯片之间，以用于将所述预定数据信号从所述时序控制芯片传输至所述一个数据驱动芯片；
    多个第一传输门，其中，每个第一传输门设置在一个第一信号线上。
  2. 如权利要求1所述的液晶显示面板的数据驱动系统，其中，在将所述预定数据信号从所述时序控制芯片传输至所述多个数据驱动芯片的过程中，所述多个第一传输门不同时导通。
  3. 如权利要求2所述的液晶显示面板的数据驱动系统，其中，在将所述预定数据信号从所述时序控制芯片传输至所述多个数据驱动芯片的过程中，所述多个第一传输门依次导通，并且在每个第一传输门导通时，其他第一传输门截止。
  4. 如权利要求3所述的液晶显示面板的数据驱动系统，其中，所述多个数据驱动芯片中的一个数据驱动芯片响应于接收到预定信号，控制自己连接的第一信号线上的第一传输门导通，从而接收所述预定数据信号。
  5. 如权利要求1所述的液晶显示面板的数据驱动系统，其中，接收到预定数据信号的数据驱动芯片控制自己连接的第一信号线上的第一传输门截止，并将控制信号输出到未接收到预定数据信号的数据驱动芯片中的一个或多个数据驱动芯片，
    接收到控制信号的数据驱动芯片控制自己连接的第一信号线上的第一传输门导通。
  6. 如权利要求2所述的液晶显示面板的数据驱动系统，其中，接收到预定数据信号的数据驱动芯片控制自己连接的第一信号线上的第一传输门截止，并将控制信号输出到未接收到预定数据信号的数据驱动芯片中的一个或多个数据驱动芯片，
    接收到控制信号的数据驱动芯片控制自己连接的第一信号线上的第一传输门导通。
  7. 如权利要求3所述的液晶显示面板的数据驱动系统，其中，接收到预定数据信号的数据驱动芯片控制自己连接的第一信号线上的第一传输门截止，并将控制信号输出到未接收到预定数据信号的数据驱动芯片中的一个或多个数据驱动芯片，
    接收到控制信号的数据驱动芯片控制自己连接的第一信号线上的第一传输门导通。
  8. 如权利要求5所述的液晶显示面板的数据驱动系统，其中，所述数据驱动系统还包括：
    多个第二信号线，用于将时钟控制信号从所述时序控制芯片传输至所述多个数据驱动芯片，其中，每个第二信号线设置在所述时序控制芯片与一个数据驱动芯片之间，以用于将所述时钟控制信号传输至所述一个数据驱动芯片；
    多个第二传输门，其中，每个第二传输门设置在一个第二信号线上。
  9. 如权利要求6所述的液晶显示面板的数据驱动系统，其中，所述数据驱动系统还包括：
    多个第二信号线，用于将时钟控制信号从所述时序控制芯片传输至所述多个数据驱动芯片，其中，每个第二信号线设置在所述时序控制芯片与一个数据驱动芯片之间，以用于将所述时钟控制信号传输至所述一个数据驱动芯片；
    多个第二传输门，其中，每个第二传输门设置在一个第二信号线上。
  10. 如权利要求7所述的液晶显示面板的数据驱动系统，其中，所述数据驱动系统还包括：
    多个第二信号线，用于将时钟控制信号从所述时序控制芯片传输至所述多个数据驱动芯片，其中，每个第二信号线设置在所述时序控制芯片与一个数据驱动芯片之间，以用于将所述时钟控制信号传输至所述一个数据驱动芯片；
    多个第二传输门，其中，每个第二传输门设置在一个第二信号线上。
  11. 如权利要求8所述的液晶显示面板的数据驱动系统，其中，连接到任意一个数据驱动芯片的第一信号线上的第一传输门与连接到所述任意一个数据驱动芯片的第二信号线上的第二传输门同时导通或截止。
  12. 如权利要求9所述的液晶显示面板的数据驱动系统，其中，连接到任意一个数据驱动芯片的第一信号线上的第一传输门与连接到所述任意一个数据驱动芯片的第二信号线上的第二传输门同时导通或截止。
  13. 如权利要求10所述的液晶显示面板的数据驱动系统，其中，连接到任意一个数据驱动芯片的第一信号线上的第一传输门与连接到所述任意一个数据驱动芯片的第二信号线上的第二传输门同时导通或截止。
  14. 如权利要求11所述的液晶显示面板的数据驱动系统，其中，每当一个数据驱动芯片在完成第N个时钟周期的时钟控制信号的接收时，控制自己连接的第一信号线上的第一传输门截止，其中，N为大于0的整数。
  15. 如权利要求12所述的液晶显示面板的数据驱动系统，其中，每当一个数据驱动芯片在完成第N个时钟周期的时钟控制信号的接收时，控制自己连接的第一信号线上的第一传输门截止，其中，N为大于0的整数。
  16. 如权利要求13所述的液晶显示面板的数据驱动系统，其中，每当一个数据驱动芯片在完成第N个时钟周期的时钟控制信号的接收时，控制自己连接的第一信号线上的第一传输门截止，其中，N为大于0的整数。
  17. 如权利要求14所述的液晶显示面板的数据驱动系统，其中，接收到时钟控制信号的数据驱动芯片在完成第M个时钟周期的时钟控制信号的接收时，将控制信号输出到未接收到时钟控制信号的数据驱动芯片中的一个或多个数据驱动芯片，其中，M为小于N的正整数，
    接收到控制信号的数据驱动芯片控制自己连接的第二信号线上的第二传输门延迟N-M个时钟周期导通，从而当接收到时钟控制信号的数据驱动芯片控制自己连接的第一信号线上的第一传输门截止时，接收到控制信号的数据驱动芯片控制自己连接的第一信号线上的第一传输门导通。
  18. 如权利要求15所述的液晶显示面板的数据驱动系统，其中，接收到时钟控制信号的数据驱动芯片在完成第M个时钟周期的时钟控制信号的接收时，将控制信号输出到未接收到时钟控制信号的数据驱动芯片中的一个或多个数据驱动芯片，其中，M为小于N的正整数，
    接收到控制信号的数据驱动芯片控制自己连接的第二信号线上的第二传输门延迟N-M个时钟周期导通，从而当接收到时钟控制信号的数据驱动芯片控制自己连接的第一信号线上的第一传输门截止时，接收到控制信号的数据驱动芯片控制自己连接的第一信号线上的第一传输门导通。
  19. 如权利要求17所述的液晶显示面板的数据驱动系统，其中，所述多个数据驱动芯片中的一个数据驱动芯片响应于接收到预定信号，控制自己连接的第二信号线上的第二传输门导通。
  20. 如权利要求8所述的液晶显示面板的数据驱动系统，其中，所述时钟控制信号和所述预定数据信号分别以差分信号的方式来传输。
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