WO2017222061A1 - Procédé de fabrication d'une carte de circuit imprimé isolée, carte de circuit imprimé isolée et module de conversion thermoélectrique - Google Patents

Procédé de fabrication d'une carte de circuit imprimé isolée, carte de circuit imprimé isolée et module de conversion thermoélectrique Download PDF

Info

Publication number
WO2017222061A1
WO2017222061A1 PCT/JP2017/023272 JP2017023272W WO2017222061A1 WO 2017222061 A1 WO2017222061 A1 WO 2017222061A1 JP 2017023272 W JP2017023272 W JP 2017023272W WO 2017222061 A1 WO2017222061 A1 WO 2017222061A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
aluminum
titanium
circuit board
ceramic substrate
Prior art date
Application number
PCT/JP2017/023272
Other languages
English (en)
Japanese (ja)
Inventor
伸幸 寺▲崎▼
東洋 大橋
Original Assignee
三菱マテリアル株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP2017121741A external-priority patent/JP6904094B2/ja
Application filed by 三菱マテリアル株式会社 filed Critical 三菱マテリアル株式会社
Priority to CN201780034318.3A priority Critical patent/CN109219878B/zh
Priority to US16/306,708 priority patent/US10798824B2/en
Priority to EP20180726.0A priority patent/EP3734654B1/fr
Priority to EP17815526.3A priority patent/EP3477695B1/fr
Publication of WO2017222061A1 publication Critical patent/WO2017222061A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0055—After-treatment, e.g. cleaning or desmearing of holes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H05K3/061—Etching masks
    • H05K3/062—Etching masks consisting of metals or alloys or metallic inorganic compounds
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N10/00—Thermoelectric devices comprising a junction of dissimilar materials, i.e. devices exhibiting Seebeck or Peltier effects
    • H10N10/80—Constructional details
    • H10N10/81—Structural details of the junction
    • H10N10/817—Structural details of the junction the junction being non-separable, e.g. being cemented, sintered or soldered
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/83447—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0341—Intermediate metal, e.g. before reinforcing of conductors by plating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10219—Thermoelectric component

Definitions

  • the present invention relates to a method for manufacturing an insulated circuit board, a insulated circuit board, and a thermoelectric conversion module including a ceramic substrate and a circuit layer having a circuit pattern disposed on one surface of the ceramic substrate.
  • the present application claims priority based on Japanese Patent Application No. 2016-124667 filed in Japan on June 23, 2016, and Japanese Patent Application No. 2017-121741 filed in Japan on June 21, 2017. The contents are incorporated herein.
  • thermoelectric conversion modules have a structure in which a semiconductor element or a thermoelectric element is bonded on a circuit layer made of a conductive material.
  • a semiconductor element or a thermoelectric element is bonded on a circuit layer made of a conductive material.
  • the amount of heat generated is large. Therefore, for example, AlN (aluminum nitride), Al 2.
  • an insulating circuit board including a ceramic substrate made of 2 O 3 (alumina) and a circuit layer formed by bonding a metal plate having excellent conductivity to one surface of the ceramic substrate has been widely used. It has been.
  • a ceramic substrate having a metal layer formed on the other surface is also provided.
  • the power module shown in Patent Document 1 is bonded to an insulating circuit board in which a circuit layer and a metal layer made of Al are formed on one surface and the other surface of a ceramic substrate, and a solder material is bonded to the circuit layer. And a semiconductor device that has been manufactured. A heat sink is bonded to the other surface side of the insulating circuit board, and the heat transmitted from the semiconductor element to the insulating circuit board side is dissipated to the outside through the heat sink.
  • Patent Document 1 discloses a technique for joining a circuit layer and a semiconductor element, and a metal layer and a heat sink by using a silver oxide paste containing silver oxide particles and a reducing agent made of an organic substance as an alternative to a solder material. Has been proposed.
  • Patent Document 4 proposes an insulated circuit board in which the circuit layer has a laminated structure of an aluminum layer and a metal member layer made of copper, nickel, or silver.
  • This insulated circuit board has a structure in which an aluminum layer and a metal member layer are bonded via a titanium layer.
  • thermoelectric conversion module when the circuit layer is made of aluminum or the like, aluminum diffuses into the thermoelectric element, which may deteriorate the characteristics of the thermoelectric element. For this reason, in order to prevent aluminum from diffusing into the thermoelectric element, it is conceivable to form a titanium layer as a diffusion preventing layer on the surface of the circuit layer.
  • an etching process may be performed to form a circuit pattern in the circuit layer.
  • ferric chloride is used as an etchant used when etching copper or aluminum.
  • the above-mentioned etching agent cannot etch the titanium layer, there is a problem that the circuit pattern having the titanium layer cannot be etched to form a circuit pattern.
  • the present invention has been made in view of the circumstances described above, and includes an aluminum layer disposed on one surface of a ceramic substrate and titanium formed on the surface of the aluminum layer opposite to the ceramic substrate.
  • An object of the present invention is to provide an insulating circuit board manufacturing method, an insulating circuit board, and a thermoelectric conversion module capable of forming a circuit pattern with high accuracy and efficiency with respect to a circuit layer having a layer.
  • an insulating circuit board manufacturing method includes an insulating circuit board including a ceramic substrate and a circuit layer having a circuit pattern disposed on one surface of the ceramic substrate.
  • the circuit layer includes an aluminum layer disposed on one surface of the ceramic substrate, and a titanium layer formed on a surface of the aluminum layer opposite to the ceramic substrate.
  • a titanium layer forming step of forming the titanium layer is characterized in that the aluminum layer wherein the titanium layer is formed and a, and an etching process for etching the circuit pattern.
  • the titanium layer can be formed in a circuit pattern on the surface of the aluminum layer.
  • the aluminum layer having the titanium layer formed into a circuit pattern is provided with an etching process step, the titanium layer acts as a resist material, and the aluminum layer is etched into a circuit pattern. be able to.
  • the resist material application process, the curing process and the peeling process can be omitted, and the etching process process can be performed efficiently.
  • the circuit pattern is accurately applied to the circuit layer having the aluminum layer disposed on one surface of the ceramic substrate and the titanium layer formed on the surface of the aluminum layer opposite to the ceramic substrate. And can be formed efficiently.
  • the circuit layer includes a metal member layer made of copper, nickel, or silver laminated on a surface of the titanium layer opposite to the aluminum layer. And a metal member layer forming step of forming the metal member layer on the surface of the titanium layer formed in a circuit pattern after the etching treatment step.
  • the metal member layer is made of copper or copper alloy, nickel or nickel alloy, or silver or silver alloy.
  • the metal member which consists of copper, nickel, or silver on a titanium layer A layer can be formed.
  • the circuit pattern can be formed with high accuracy and efficiency with respect to the circuit layer having.
  • the metal member layer can be reliably formed on the titanium layer by cleaning the surface of the titanium layer.
  • a titanium layer can be formed in a circuit pattern on the aluminum layer.
  • the manufacturing method of the insulated circuit board of this invention you may implement the said ceramics / aluminum joining process after the said titanium layer formation process.
  • the aluminum plate and the ceramic substrate can be joined after the titanium layer is formed in a circuit pattern on the aluminum plate.
  • the titanium layer forming step and the ceramic / aluminum bonding step may be performed simultaneously.
  • an insulated circuit board having a circuit pattern can be efficiently manufactured by simultaneously performing the titanium layer forming step and the ceramic / aluminum bonding step.
  • the aluminum washing process which wash
  • the aluminum layer or the aluminum material and the titanium material can be reliably bonded to form a titanium layer.
  • Si is added to Al 3 Ti at the interface between the titanium layer and the aluminum layer by forming the Si enriched layer on the surface of the aluminum layer or the aluminum material on the side where the titanium layer is formed. can be dissolved, hard Al 3 Ti can suppress the is formed more than necessary, it is possible to suppress the occurrence of cracks at the bonding interface between the titanium layer and an aluminum layer.
  • the insulated circuit board of the present invention is an insulated circuit board comprising a ceramic substrate and a circuit layer having a circuit pattern disposed on one surface of the ceramic substrate, wherein the circuit layer is the ceramic substrate. It has the aluminum layer arrange
  • the titanium layer since the titanium layer is formed on the surface of the aluminum layer opposite to the ceramic substrate, the titanium layer can function as a diffusion preventing layer. Therefore, diffusion of aluminum in the aluminum layer into the element mounted on the circuit layer can be suppressed.
  • thermoelectric conversion module of the present invention is characterized in that a thermoelectric element is mounted on the circuit layer of the above-described insulated circuit board.
  • thermoelectric conversion module having this configuration since the thermoelectric element is mounted on the circuit layer formed with the titanium layer formed on the surface of the aluminum layer opposite to the ceramic substrate, the aluminum of the aluminum layer is the thermoelectric element. And the deterioration of the thermoelectric element characteristics can be suppressed.
  • a circuit for a circuit layer having an aluminum layer disposed on one surface of a ceramic substrate and a titanium layer formed on the surface of the aluminum layer opposite to the ceramic substrate. It is possible to provide an insulating circuit board manufacturing method, an insulating circuit board, and a thermoelectric conversion module that can form a pattern with high accuracy and efficiency.
  • brazing filler material is not necessarily limited to a material containing lead.
  • FIG. 1 the power module 1 using the insulated circuit board 10 which is 1st embodiment of this invention is shown.
  • the power module 1 includes an insulating circuit board 10, a semiconductor element 3 bonded to one surface (the upper surface in FIG. 1) of the insulating circuit board 10 via a first solder layer 2, and a bottom of the insulating circuit board 10. And a heat sink 41 joined via a second solder layer 42 to the side.
  • the semiconductor element 3 is made of a semiconductor material such as Si.
  • the first solder layer 2 that joins the insulating circuit board 10 and the semiconductor element 3 is, for example, a Sn—Ag, Sn—Cu, Sn—In, or Sn—Ag—Cu solder material (so-called lead-free solder). Material).
  • the heat sink 41 is for dissipating heat on the insulated circuit board 10 side.
  • the heat sink 41 is made of copper or a copper alloy, and is made of oxygen-free copper in this embodiment.
  • the second solder layer 42 that joins the insulating circuit board 10 and the heat sink 41 is, for example, a Sn—Ag, Sn—Cu, Sn—In, or Sn—Ag—Cu solder material (so-called lead-free solder material). ).
  • the insulated circuit board 10 As shown in FIGS. 1 and 2, the insulated circuit board 10 according to the present embodiment is disposed on the ceramic substrate 11 and one surface (the upper surface in FIGS. 1 and 2) of the ceramic substrate 11. A circuit layer 20 and a metal layer 30 disposed on the other surface (the lower surface in FIGS. 1 and 2) of the ceramic substrate 11 are provided.
  • the ceramic substrate 11 is made of highly insulating AlN (aluminum nitride), Si 3 N 4 (silicon nitride), Al 2 O 3 (alumina), or the like. In the present embodiment, it is composed of Si 3 N 4 excellent in strength (silicon nitride). In addition, the thickness of the ceramic substrate 11 is set within a range of 0.2 to 1.5 mm, and in this embodiment is set to 0.32 mm.
  • the circuit layer 20 is laminated with an aluminum layer 21 disposed on one surface of the ceramic substrate 11 and a titanium layer 25 on one surface of the aluminum layer 21. And a copper layer 22 (metal member layer).
  • the thickness of the aluminum layer 21 in the circuit layer 20 is set within a range of 0.1 mm or more and 1.0 mm or less, and is set to 0.4 mm in the present embodiment.
  • the thickness of the copper layer 22 in the circuit layer 20 is set within a range of 0.1 mm or more and 6.0 mm or less, and is set to 1.0 mm in the present embodiment.
  • a circuit pattern is formed as shown in FIG.
  • the metal layer 30 is laminated with an aluminum layer 31 disposed on the other surface of the ceramic substrate 11 and a titanium layer 35 on the other surface of the aluminum layer 31. And a copper layer 32 (metal member layer).
  • the thickness of the aluminum layer 31 in the metal layer 30 is set within a range of 0.1 mm to 3.0 mm, and is set to 0.4 mm in the present embodiment.
  • the thickness of the copper layer 32 in the metal layer 30 is set within a range of 0.1 mm or more and 6.0 mm or less, and is set to 1.0 mm in the present embodiment.
  • the aluminum layers 21 and 31 are formed by bonding aluminum plates 51 and 61 to one surface and the other surface of the ceramic substrate 11.
  • the aluminum plates 51 and 61 to be the aluminum layers 21 and 31 are made of aluminum (2N aluminum) having a purity of 99 mass% or more. Note that the Si content is in the range of 0.03 mass% to 1.0 mass%.
  • the copper layers 22 and 32 are formed by bonding a copper plate (metal member) made of copper or a copper alloy to one surface and the other surface of the aluminum layers 21 and 31 via the titanium layers 25 and 35. Yes.
  • the copper plates (metal members) constituting the copper layers 22 and 32 are oxygen-free copper rolled plates.
  • Al—Ti—Si layers 26 and 36 are formed at the bonding interfaces between the aluminum layers 21 and 31 and the titanium layers 25 and 35.
  • the Al—Ti—Si layers 26, 36 are formed on Al 3 Ti formed by mutual diffusion of Al atoms in the aluminum layers 21, 31 and Ti atoms in the titanium layers 25, 35. This is formed by solid solution of Si.
  • the thickness of the Al—Ti—Si layers 26 and 36 is set to 0.5 ⁇ m or more and 10 ⁇ m or less, and is 3 ⁇ m in this embodiment.
  • the Al—Ti—Si layers 26, 36 are formed on the first Al—Ti—Si layers 26 A, 36 A formed on the titanium layers 25, 35 side and the aluminum layers 21, 31 side.
  • Second Al—Ti—Si layers 26B and 36B That is, at the junction between the aluminum layers 21 and 31 and the copper layers 22 and 32, the titanium layers 25 and 35, the first Al—Ti—Si layers 26A and 36A, the second Al—Ti—Si layers 26B and 36B, Is formed.
  • the first Al—Ti—Si layers 26A and 36A and the second Al—Ti—Si layers 26B and 36B are made of an Al—Ti—Si phase in which Si is dissolved in Al 3 Ti as described above.
  • the Si concentration of the Ti—Si layers 26B and 36B is lower than the Si concentration of the first Al—Ti—Si layers 26A and 36A.
  • Si contained in the first Al—Ti—Si layers 26A and 36A and the second Al—Ti—Si layers 26B and 36B is composed of Si diffused in the aluminum layers 21 and 31 as described later. Diffusion and concentration in the Ti-Si layers 26 and 36.
  • the Si concentration of the first Al—Ti—Si layers 26A and 36A is 10 at% or more and 30 at% or less, and is 20 at% in the present embodiment.
  • the Si concentration of the second Al—Ti—Si layers 26B and 36B is 1 at% or more and 10 at% or less, and is 3 at% in this embodiment.
  • titanium materials 55 and 65 are disposed on the surfaces of the aluminum plates 51 and 61.
  • the titanium material 55 is arranged in a circuit pattern on the surface of the aluminum plate 51 to be the circuit layer 20.
  • a film forming method such as vapor deposition or ion plating may be applied.
  • the titanium material 55 can be arranged in a circuit pattern by forming a titanium film using a metal mask.
  • the titanium foil may be arranged in a circuit pattern.
  • the thickness of the titanium materials 55 and 65 is preferably in the range of 7 ⁇ m to 20 ⁇ m.
  • an aluminum plate 51 and a titanium material 55 are disposed on one surface of the ceramic substrate 11, and an aluminum plate 61 and a titanium material 65 are disposed on the other surface of the ceramic substrate 11.
  • an Al—Si brazing material is interposed between the aluminum plate 51 and the ceramic substrate 11 and between the aluminum plate 61 and the ceramic substrate 11. These are placed in a vacuum heating furnace in a state where they are pressurized in the stacking direction (load: 3 to 20 kgf / cm 2 (0.29 to 1.96 MPa)) and heated.
  • the pressure in the vacuum heating furnace is set in the range of 10 ⁇ 6 Pa to 10 ⁇ 3 Pa
  • the heating temperature is set to 600 ° C. to 640 ° C.
  • the holding time is set in the range of 30 minutes to 180 minutes. It is preferable.
  • the aluminum plate 51 and the ceramic substrate 11 and the ceramic substrate 11 and the aluminum plate 61 are joined (ceramic / aluminum joining step).
  • the aluminum plate 51 and the titanium material 55, the aluminum plate 61, and the titanium material 65 are joined, and the titanium layers 25 and 35 are formed (titanium layer formation process).
  • Al 3 Ti is formed at the bonding interface between the aluminum plate 51 and the titanium material 55 and between the aluminum plate 61 and the titanium material 65. Since the aluminum plates 51 and 61 contain Si in the range of 0.03 mass% to 1.0 mass%, Si is dissolved in Al 3 Ti, and the Al—Ti—Si layers 26, 36 described above are dissolved. Is formed.
  • a titanium layer 25 is formed in a circuit pattern on the aluminum plate 51 to be the circuit layer 20.
  • an etching process is performed on the aluminum layer 21 in which the titanium layer 25 is formed in a circuit pattern.
  • ferric chloride is used as an etching agent.
  • the concentration of ferric chloride in the etching agent (etching solution) is 35 wt% to 60 wt%, and etching can be performed at an etching temperature of 40 ° C. to 60 ° C. for 2 minutes to 20 minutes.
  • the titanium layer 25 since the titanium layer 25 is hardly etched by ferric chloride, the titanium layer 25 acts as a resist material. That is, the portion where the titanium layer 25 is formed is not etched, and only the portion where the titanium layer 25 is not formed is etched. Thereby, the aluminum layer 21 is also formed in a circuit pattern.
  • Tianium layer cleaning step S04 Next, as shown in FIG. 4, the surfaces of the titanium layers 25 and 35 on which the copper layers 22 and 32 are disposed are cleaned.
  • a mixed liquid of ammonia and hydrogen peroxide is used for cleaning the titanium layers 25 and 35.
  • an aqueous solution of 10 wt% ammonia, 3 wt% hydrogen peroxide, and 12 wt% EDTA (ethylenediaminetetraacetic acid) can be used.
  • the cleaning may be performed at a temperature of 40 ° C. to 50 ° C. for 10 minutes to 30 minutes.
  • a copper plate (metal member) is joined to the surfaces of the titanium layers 25 and 35 to form the copper layers 22 and 32.
  • a solid phase diffusion bonding method may be applied or a brazing material may be used for bonding.
  • titanium layers 25 and 35 and a copper plate (metal member) are stacked and pressed in the stacking direction (load 3 to 20 kgf / cm 2 ) in a vacuum heating furnace.
  • the pressure is in the range of 10 ⁇ 6 Pa to 10 ⁇ 3 Pa
  • the heating temperature is 600 ° C. to 650 ° C., more preferably 620 ° C. to 643 ° C.
  • the holding time is 30 minutes to 180 minutes, more preferably It is good to join within the range of 60 minutes or more and 120 minutes or less.
  • a Cu—P—Sn brazing material When joining using a brazing material, a Cu—P—Sn brazing material, a Cu—P—Sn—Ni based brazing material, a Cu—P—Sn—Fe based brazing material, a Cu—P—Sn—Mn based brazing material, A brazing foil such as a Cu—P—Sn—Cr brazing filler metal was disposed between the titanium layers 25 and 35 and the copper plate (metal member) and pressed in the stacking direction (load 3 to 20 kgf / cm 2 ).
  • the pressure in the vacuum heating furnace is in the range of 10 ⁇ 6 Pa to 10 ⁇ 3 Pa, the heating temperature is 600 ° C. to 650 ° C., more preferably 620 ° C.
  • a copper plate (metal member) is disposed and bonded on the titanium layer 25 formed in a circuit pattern.
  • a circuit pattern is formed on the circuit layer 20 in which the aluminum layer 21, the titanium layer 25, and the copper layer 22 are laminated, and the insulated circuit board 10 according to this embodiment is manufactured.
  • the titanium material arrangement in which the titanium material 55 to be the titanium layer 25 is arranged in a circuit pattern on the surface of the aluminum plate 51 Since the process S01 is provided, the titanium layer 25 can be formed in a circuit pattern on the surface of the aluminum layer 21 by the subsequent titanium layer forming process and the ceramic / aluminum bonding process S02.
  • the etching process step S03 for performing an etching process on the aluminum layer 21 on which the titanium layer 25 is formed the titanium layer 25 acts as a resist material, and the aluminum layer 21 is etched into a circuit pattern. be able to. That is, by using the titanium layer 25 as a resist material, the resist material application process, the curing process, and the peeling process can be omitted, and the etching process S03 can be performed efficiently.
  • the copper layer formation process S05 which joins a copper plate (metal member) on the titanium layer 25 formed in the circuit pattern shape, and forms the copper layer 22, it is a copper layer on the titanium layer 25. 22 can be formed in a circuit pattern. As described above, the circuit pattern can be accurately and efficiently formed on the circuit layer 20 in which the aluminum layer 21, the titanium layer 25, and the copper layer 22 are laminated.
  • the insulated circuit board which has a circuit pattern 10 can be manufactured efficiently.
  • the titanium layer cleaning process S04 which cleans the surface of the titanium layer 25 is provided before the copper layer formation process S05, the titanium layer 25 and the copper plate (Metal member) can be reliably joined, and the copper layer 22 can be reliably formed.
  • the aluminum plates 51 and 61 contain Si within the range of 0.03 mass% or more and 1.0 mass% or less, the titanium layers 25 and 35 are included. Si is dissolved in Al 3 Ti at the bonding interface between the aluminum layers 21 and 31 and the Al—Ti—Si layers 26 and 36 described above are formed. Since the Al—Ti—Si layers 26 and 36 are relatively low in hardness, the occurrence of cracks in the circuit layer 20 and the metal layer 30 when a heat cycle is applied can be suppressed.
  • the Si concentration of the first Al—Ti—Si layers 26A, 36A formed on the titanium layers 25, 35 side is the Si concentration of the second Al—Ti—Si layers 26B, 36B formed on the aluminum layers 21, 31 side. Therefore, the first Al—Ti—Si layers 26A and 36A having a high Si concentration suppress the Ti atoms from diffusing toward the aluminum layers 21 and 31, thereby reducing the thickness of the Al—Ti—Si layers 26 and 36. Can be thinned. Further, by reducing the thickness of the Al—Ti—Si layers 26 and 36 in this way, cracks occur at the joints between the aluminum layers 21 and 31 and the copper layers 22 and 32 when a heat cycle is applied. This can be suppressed.
  • the Si concentration contained in the second Al—Ti—Si layers 26B and 36B formed on the aluminum layers 21 and 31 side is 1 at% or more and 10 at% or less, Al atoms are on the titanium layers 25 and 35 side. Excessive diffusion is suppressed, and the thickness of the second Al—Ti—Si layers 26B and 36B can be reduced.
  • the Si concentration in the second Al—Ti—Si layers 26B and 36B is more preferably 1 at% or more and 10 at% or less, but is not limited thereto.
  • the Si concentration contained in the first Al—Ti—Si layers 26A and 36A formed on the titanium layers 25 and 35 side is 10 at% or more and 30 at% or less, Ti atoms are on the aluminum layers 21 and 31 side. Therefore, the first Al—Ti—Si layers 26A and 36A can be reduced in thickness.
  • the Si concentration in the first Al—Ti—Si layers 26A and 36A is more preferably 10 at% or more and 30 at% or less, but is not limited thereto.
  • the copper layers 22 and 32 having a relatively large deformation resistance are formed on the surface of the circuit layer 20 and the metal layer 30, the circuit layer 20 and the metal layer when the heat cycle is applied. 30, the deformation of the surface of the first solder layer 2 that joins the semiconductor element 3 and the circuit layer 20 and the second solder layer 42 that joins the heat sink 41 and the metal layer 30 can be prevented from cracking. , The bonding reliability can be improved. Further, since the copper layers 22 and 32 having good thermal conductivity are formed on the surface of the circuit layer 20 and the metal layer 30, the heat from the semiconductor element 3 is spread in the surface direction and efficiently transmitted to the heat sink 41 side. can do.
  • FIG. 6 shows a power module 101 including an insulated circuit board 110 according to the second embodiment of the present invention.
  • the power module 101 includes an insulating circuit board 110, a semiconductor element 3 bonded to one surface (upper surface in FIG. 6) of the insulating circuit board 110 via a solder layer 2, and a lower side of the insulating circuit board 110.
  • a heat sink 141 bonded thereto.
  • the heat sink 141 is for dissipating heat on the insulated circuit board 110 side.
  • the heat sink 141 is made of aluminum or an aluminum alloy, and in this embodiment is made of an A6063 alloy.
  • the insulated circuit board 110 and the heat sink 141 are joined using a brazing material.
  • the insulating circuit substrate 110 is disposed on the ceramic substrate 11, the circuit layer 120 disposed on one surface of the ceramic substrate 11, and the other surface of the ceramic substrate 11. And a metal layer 130.
  • the circuit layer 120 is laminated with an aluminum layer 121 disposed on one surface of the ceramic substrate 11 and a titanium layer 125 on one surface of the aluminum layer 121. And a copper layer 122 (metal member layer).
  • the thickness of the aluminum layer 121 in the circuit layer 120 is set within a range of 0.1 mm or more and 1.0 mm or less, and is set to 0.6 mm in the present embodiment.
  • the thickness of the copper layer 122 in the circuit layer 120 is set within a range of 0.1 mm or more and 6.0 mm or less, and is set to 1.5 mm in the present embodiment.
  • a circuit pattern is formed as shown in FIG.
  • the aluminum layer 121 is formed by joining an aluminum plate 151 to one surface of the ceramic substrate 11.
  • the aluminum plate 151 to be the aluminum layer 121 is made of aluminum (2N aluminum) having a purity of 99 mass% or more.
  • the Si content is in the range of 0.03 mass% to 1.0 mass%.
  • the copper layer 122 is formed by bonding a copper plate (metal member) made of copper or a copper alloy to one surface of the aluminum layer 121 via a titanium layer 125.
  • the copper plate (metal member) constituting the copper layer 122 is an oxygen-free copper rolled plate.
  • Al—Ti—Si layer in which Si is dissolved in Al 3 Ti is formed as in the first embodiment.
  • Al 3 Ti is formed by the mutual diffusion of Al atoms in the aluminum layer 121 and Ti atoms in the titanium layer 125, and the Si in the aluminum layer 121 is formed by the Al 3 Ti. It is formed by solid solution.
  • the metal layer 130 is formed by bonding an aluminum plate 161 to one surface of the ceramic substrate 11 as shown in FIG.
  • the metal layer 130 is formed by joining rolled sheets of aluminum (4N aluminum) having a purity of 99.99 mass% or more.
  • the thickness of the aluminum plate 161 to be joined is set within a range of 0.1 mm to 1.0 mm, and is set to 0.6 mm in the present embodiment.
  • an aluminum plate 151 is laminated on one surface of the ceramic substrate 11 via an Al—Si based brazing foil (not shown). Further, an aluminum plate 161 is laminated on the other surface of the ceramic substrate 11 via a brazing material foil (not shown).
  • the laminated aluminum plate 151, ceramic substrate 11 and aluminum plate 161 are placed in a vacuum heating furnace and heated in a state of being pressurized (load 3 to 20 kgf / cm 2 ) in the lamination direction. As a result, the aluminum plate 151 and the ceramic substrate 11 and the ceramic substrate 11 and the aluminum plate 161 are joined to form the aluminum layer 121 and the metal layer 130.
  • the aluminum layer 121 can be cleaned, for example, using a 5 wt% to 10 wt% sulfuric acid aqueous solution or a 5 wt% to 10 wt% nitric acid aqueous solution at a temperature of 20 ° C. to 30 ° C. for a time of 30 seconds to 60 seconds.
  • a titanium material 155 is arranged in a circuit pattern on the surface of the aluminum layer 121.
  • a film forming method such as vapor deposition or ion plating may be applied.
  • the titanium material 155 can be arranged in a circuit pattern by forming a titanium film using a metal mask.
  • the titanium foil may be arranged in a circuit pattern.
  • the thickness of the titanium material 155 is preferably in the range of 7 ⁇ m or more and 20 ⁇ m or less.
  • Tianium layer forming step S104 Next, as shown in FIG. 8 and FIG. 9, with the titanium material 155 disposed on the surface of the aluminum layer 121, vacuum heating is performed in a state where these are pressed in the stacking direction (load 3 to 20 kgf / cm 2 ). Place in the furnace and heat.
  • the pressure in the vacuum heating furnace is set in the range of 10 ⁇ 6 Pa to 10 ⁇ 3 Pa
  • the heating temperature is set to 600 ° C. to 640 ° C.
  • the holding time is set in the range of 30 minutes to 180 minutes. It is preferable.
  • the aluminum layer 121 and the titanium material 155 are joined, and the titanium layer 125 is formed in a circuit pattern.
  • the Al—Ti—Si layer described above is formed at the bonding interface between the aluminum layer 121 and the titanium layer 125.
  • Tianium layer cleaning step S106 Next, as shown in FIG. 8, the surface of the titanium layer 125 on which the copper layer 122 is disposed is cleaned.
  • the cleaning of the titanium layer 125 can be performed as in the first embodiment.
  • a copper plate (metal member) is bonded to the surface of the titanium layer 125 formed in a circuit pattern to form the copper layer 122.
  • the solid phase diffusion bonding method may be applied or the brazing material may be bonded as in the first embodiment. .
  • a circuit pattern is formed on the circuit layer 120 in which the aluminum layer 121, the titanium layer 125, and the copper layer 122 are laminated, and the insulated circuit board 110 according to this embodiment is manufactured.
  • the titanium material disposing step S103, the titanium layer forming step S104, and the etching process step S105 as in the first embodiment.
  • the copper layer forming step S107 the circuit pattern can be accurately and efficiently formed on the circuit layer 120 in which the aluminum layer 121, the titanium layer 125, and the copper layer 122 are laminated. Can do.
  • the titanium layer 125 is used as a resist material in the etching process S105, the resist material application process and the peeling process can be omitted, and the etching process S105 can be performed efficiently.
  • thermoelectric conversion module 201 provided with the insulated circuit board 210 which concerns on 3rd embodiment of this invention is shown.
  • the thermoelectric conversion module 201 includes a thermoelectric element 203 and an insulating circuit board 210 disposed on one end side and the other end side of the thermoelectric element 203.
  • the thermoelectric element 203 is bonded to the circuit layer 220 of the insulating circuit board 210 via the bonding layer 202.
  • the bonding layer 202 is a fired body of silver paste containing silver particles.
  • the insulated circuit board 210 includes a ceramic substrate 11 and a circuit layer 220 disposed on one surface of the ceramic substrate 11.
  • the circuit layer 220 includes an aluminum layer 221 disposed on one surface of the ceramic substrate 11 and a titanium layer 225 formed on one surface of the aluminum layer 221.
  • the thickness of the aluminum layer 221 in the circuit layer 220 is set within a range of 0.1 mm to 1.0 mm, and is set to 0.6 mm in the present embodiment.
  • a circuit pattern is formed as shown in FIG.
  • the aluminum layer 221 is formed by bonding an aluminum plate 251 to one surface of the ceramic substrate 11.
  • the aluminum plate 251 serving as the aluminum layer 221 is made of aluminum (4N aluminum) having a purity of 99.99 mass% or more. Note that a Si concentrated layer in which the Si content is in the range of 0.03 mass% to 1.0 mass% is formed at the interface of the aluminum layer 221 on the titanium layer 225 side.
  • an Al—Ti—Si layer in which Si is dissolved in Al 3 Ti is formed at the bonding interface between the aluminum layer 221 and the titanium layer 225. Yes.
  • the Al-Ti-Si layer, and the Al atoms of the aluminum layer 221, together with the Al 3 Ti is formed by and the Ti atoms in the titanium layer 225 to interdiffusion, Si of Si concentrated layer, the Al 3 It is formed by dissolving in Ti.
  • Si concentrated layer forming step S201 First, a Si concentrated layer containing Si within a range of 0.03 mass% to 1.0 mass% on one surface of an aluminum plate 251 made of aluminum (4N aluminum) having a purity of 99.99 mass% or higher. Form. Specifically, a Si material 252 containing Si (for example, an Al—Si brazing material) is disposed on one surface of the aluminum plate 251 and heat-treated, so that Si of the Si material is moved to the aluminum plate 251 side. And the above-described Si concentrated layer is formed.
  • the Si concentration was obtained by measuring five points on the surface on which the titanium layer is formed by quantitative analysis using EPMA (electron beam microanalyzer), and taking the average value.
  • the Si concentration is the concentration when the total amount of Al and Si is 100.
  • a titanium material 255 is arranged in a circuit pattern on one surface of the aluminum plate 151 (the surface on which the Si concentrated layer is formed).
  • a film forming method such as vapor deposition or ion plating may be applied.
  • the titanium material 255 can be arranged in a circuit pattern.
  • the titanium foil may be arranged in a circuit pattern.
  • the thickness of the titanium material 255 is preferably in the range of 7 ⁇ m to 20 ⁇ m.
  • a titanium material 255 is disposed on the surface of the aluminum plate 251, and is placed in a vacuum heating furnace in a state of being pressurized in the stacking direction (load 3 to 20 kgf / cm 2 ). And heat.
  • the pressure in the vacuum heating furnace is set in the range of 10 ⁇ 6 Pa to 10 ⁇ 3 Pa
  • the heating temperature is set to 600 ° C. to 640 ° C.
  • the holding time is set in the range of 30 minutes to 180 minutes. It is preferable.
  • the aluminum plate 251 and the titanium material 255 are joined, and the titanium layer 225 is formed in a circuit pattern.
  • the Al—Ti—Si layer described above is formed at the bonding interface between the aluminum plate 251 and the titanium layer 225.
  • an aluminum plate 251 on which a titanium layer 225 is formed is laminated on one surface of the ceramic substrate 11 with an Al—Si based brazing foil (not shown). To do.
  • the laminated aluminum plate 251 and the ceramic substrate 11 are placed in a vacuum heating furnace and heated while being pressurized (load 3 to 20 kgf / cm 2 ) in the lamination direction. Thereby, the aluminum plate 251 and the ceramic substrate 11 are joined, and the aluminum layer 221 is formed.
  • a circuit pattern is formed on the circuit layer 220 in which the aluminum layer 221 and the titanium layer 225 are laminated, and the insulated circuit board 210 according to this embodiment is manufactured.
  • thermoelectric conversion module 201 shown in FIG. 10 is manufactured.
  • the aluminum layer A circuit pattern can be accurately and efficiently formed on the circuit layer 220 in which the layer 221 and the titanium layer 225 are stacked. Further, since the titanium layer 225 is used as a resist material in the etching process S205, the resist material application process and the peeling process can be omitted, and the etching process S205 can be performed efficiently.
  • the aluminum layer 221 of the circuit layer 220 is made of aluminum (4N aluminum) having a purity of 99.99 mass% or more.
  • an Al—Ti—Si layer can be formed between the aluminum layer 221 and the titanium layer 225 as in the first embodiment and the second embodiment.
  • the titanium layer 225 is formed on the surface of the aluminum layer 221 opposite to the ceramic substrate 11, so that the titanium layer 225 is diffused. It can function as a prevention layer. Therefore, diffusion of aluminum in the aluminum layer 221 into the thermoelectric element 203 mounted on the circuit layer 211 can be suppressed. Thereby, deterioration of the characteristics of the thermoelectric element 203 can be suppressed.
  • the solderability is good and the bonding reliability with a semiconductor element or a heat sink can be improved.
  • the nickel layer is formed by solid phase diffusion bonding, the masking process performed when forming the Ni plating film by electroless plating or the like is unnecessary, and thus the manufacturing cost can be reduced.
  • the thickness of the nickel layer be 1 ⁇ m or more and 30 ⁇ m or less. If the thickness of the nickel layer is less than 1 ⁇ m, the effect of improving the reliability of bonding to the semiconductor element or the heat sink may be lost. If the thickness exceeds 30 ⁇ m, the nickel layer becomes a thermal resistor and efficiently transfers heat. There is a risk that it will not be possible.
  • the nickel layer is formed by solid phase diffusion bonding, the solid phase diffusion bonding can be formed under the same conditions as when the copper layer is formed.
  • the silver oxide is reduced.
  • the silver layer are connected, that is, the same kind of metal is bonded to each other, so that the bonding reliability can be improved.
  • the thickness of the silver layer is desirably 1 ⁇ m or more and 20 ⁇ m or less. If the thickness of the silver layer is less than 1 ⁇ m, the effect of improving the bonding reliability with the semiconductor element or the heat sink may be lost.
  • the thickness exceeds 20 ⁇ m, the effect of improving the bonding reliability is not observed, and the cost is reduced. Incurs an increase.
  • the solid phase diffusion bonding can be formed under the same conditions as when the copper layer is formed.
  • an aluminum plate used as an aluminum layer it is 2N aluminum whose purity is 99 mass% or more, and Si content is the range of 0.03 mass% or more and 1.0 mass% or less.
  • the present invention is not limited to this, and other aluminum materials may be used.
  • an aluminum material that does not contain Si such as 4N aluminum having a purity of 99.99 mass% or more
  • a titanium layer is formed in advance in the aluminum material.
  • the surface Si concentration may be adjusted to 0.03 mass% to 1.0 mass%.
  • the Si concentration is an average value obtained by measuring the surface on which the titanium layer is formed at five points by quantitative analysis of EPMA.
  • the Si concentration is the concentration when the total amount of Al and Si is 100.
  • a circuit pattern can be accurately and efficiently formed on a circuit layer.
  • the insulated circuit board of this invention is suitable for semiconductor devices, such as LED and a power module, and a thermoelectric conversion module.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Inorganic Chemistry (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)

Abstract

La présente invention concerne un procédé de fabrication d'une carte de circuit imprimé isolée comprenant : une étape de liaison céramique/aluminium servant à former une couche d'aluminium par liaison d'un matériau d'aluminium à un substrat céramique; une étape d'agencement de matériau de titane servant à disposer un matériau de titane sur la surface de la couche d'aluminium ou du matériau d'aluminium selon une forme de motif de circuit; une étape de formation de couche de titane servant à former une couche de titane en réalisant un traitement thermique lorsque le matériau de titane est empilé sur la surface de la couche d'aluminium ou du matériau d'aluminium; et une étape de gravure servant à graver la couche d'aluminium sur laquelle la couche de titane a été formée en une forme de motif de circuit.
PCT/JP2017/023272 2016-06-23 2017-06-23 Procédé de fabrication d'une carte de circuit imprimé isolée, carte de circuit imprimé isolée et module de conversion thermoélectrique WO2017222061A1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CN201780034318.3A CN109219878B (zh) 2016-06-23 2017-06-23 绝缘电路基板的制造方法、绝缘电路基板及热电转换模块
US16/306,708 US10798824B2 (en) 2016-06-23 2017-06-23 Method for manufacturing insulated circuit board, insulated circuit board, and thermoelectric conversion module
EP20180726.0A EP3734654B1 (fr) 2016-06-23 2017-06-23 Procédé de fabrication d'une carte de circuit imprimé isolée, carte de circuit imprimé isolée et module de conversion thermoélectrique
EP17815526.3A EP3477695B1 (fr) 2016-06-23 2017-06-23 Procédé de fabrication d'une carte de circuit imprimé isolée

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2016124667 2016-06-23
JP2016-124667 2016-06-23
JP2017-121741 2017-06-21
JP2017121741A JP6904094B2 (ja) 2016-06-23 2017-06-21 絶縁回路基板の製造方法

Publications (1)

Publication Number Publication Date
WO2017222061A1 true WO2017222061A1 (fr) 2017-12-28

Family

ID=60783869

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2017/023272 WO2017222061A1 (fr) 2016-06-23 2017-06-23 Procédé de fabrication d'une carte de circuit imprimé isolée, carte de circuit imprimé isolée et module de conversion thermoélectrique

Country Status (2)

Country Link
CN (1) CN109219878B (fr)
WO (1) WO2017222061A1 (fr)

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5725060B2 (fr) 1975-12-12 1982-05-27
JPH07142858A (ja) * 1993-11-15 1995-06-02 Toshiba Corp セラミックス配線基板の製造方法
JP3171234B2 (ja) 1997-03-26 2001-05-28 三菱マテリアル株式会社 ヒートシンク付セラミック回路基板
JP2003078086A (ja) * 2001-09-04 2003-03-14 Kubota Corp 半導体素子モジュール基板の積層構造
JP2003309294A (ja) * 2002-02-12 2003-10-31 Komatsu Ltd 熱電モジュール
JP2004172378A (ja) 2002-11-20 2004-06-17 Mitsubishi Materials Corp パワーモジュール用基板の製造方法並びにパワーモジュール用基板及びパワーモジュール
JP2008208442A (ja) 2007-02-28 2008-09-11 Hitachi Ltd 金属化合物粒子を用いた接合方法
JP2012248697A (ja) * 2011-05-27 2012-12-13 Showa Denko Kk 絶縁基板用積層材の製造方法
JP2015233063A (ja) * 2014-06-09 2015-12-24 トヨタ自動車株式会社 熱電変換システム
JP2016124667A (ja) 2014-12-29 2016-07-11 ニスカ株式会社 給紙装置
JP2017121741A (ja) 2016-01-07 2017-07-13 キヤノンファインテック株式会社 記録装置および記録方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW369672B (en) * 1997-07-28 1999-09-11 Hitachi Ltd Wiring board and its manufacturing process, and electrolysis-free electroplating method
JP5431598B2 (ja) * 2010-12-28 2014-03-05 株式会社トクヤマ メタライズド基板、金属ペースト組成物、および、メタライズド基板の製造方法
KR102130868B1 (ko) * 2013-03-14 2020-07-08 미쓰비시 마테리알 가부시키가이샤 접합체, 파워 모듈용 기판, 및 히트 싱크가 부착된 파워 모듈용 기판
JP6146242B2 (ja) * 2013-09-27 2017-06-14 三菱マテリアル株式会社 パワーモジュール用基板の製造方法

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5725060B2 (fr) 1975-12-12 1982-05-27
JPH07142858A (ja) * 1993-11-15 1995-06-02 Toshiba Corp セラミックス配線基板の製造方法
JP3171234B2 (ja) 1997-03-26 2001-05-28 三菱マテリアル株式会社 ヒートシンク付セラミック回路基板
JP2003078086A (ja) * 2001-09-04 2003-03-14 Kubota Corp 半導体素子モジュール基板の積層構造
JP2003309294A (ja) * 2002-02-12 2003-10-31 Komatsu Ltd 熱電モジュール
JP2004172378A (ja) 2002-11-20 2004-06-17 Mitsubishi Materials Corp パワーモジュール用基板の製造方法並びにパワーモジュール用基板及びパワーモジュール
JP2008208442A (ja) 2007-02-28 2008-09-11 Hitachi Ltd 金属化合物粒子を用いた接合方法
JP2012248697A (ja) * 2011-05-27 2012-12-13 Showa Denko Kk 絶縁基板用積層材の製造方法
JP2015233063A (ja) * 2014-06-09 2015-12-24 トヨタ自動車株式会社 熱電変換システム
JP2016124667A (ja) 2014-12-29 2016-07-11 ニスカ株式会社 給紙装置
JP2017121741A (ja) 2016-01-07 2017-07-13 キヤノンファインテック株式会社 記録装置および記録方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3477695A4

Also Published As

Publication number Publication date
CN109219878A (zh) 2019-01-15
CN109219878B (zh) 2022-06-03

Similar Documents

Publication Publication Date Title
KR102154889B1 (ko) 접합체의 제조 방법 및 파워 모듈용 기판의 제조 방법
JP5725060B2 (ja) 接合体、パワーモジュール用基板、及びヒートシンク付パワーモジュール用基板
JP5067187B2 (ja) ヒートシンク付パワーモジュール用基板及びヒートシンク付パワーモジュール
KR20170044105A (ko) 접합체, 히트 싱크가 부착된 파워 모듈용 기판, 히트 싱크, 접합체의 제조 방법, 히트 싱크가 부착된 파워 모듈용 기판의 제조 방법, 및 히트 싱크의 제조 방법
WO2014157178A1 (fr) Module d'alimentation
JP2008235852A (ja) セラミックス基板及びこれを用いた半導体モジュール
KR20170046649A (ko) 접합체, 히트 싱크가 부착된 파워 모듈용 기판, 히트 싱크, 접합체의 제조 방법, 히트 싱크가 부착된 파워 모듈용 기판의 제조 방법, 및 히트 싱크의 제조 방법
JP6904094B2 (ja) 絶縁回路基板の製造方法
JP2019081690A (ja) 接合体、及び、絶縁回路基板
KR20200083455A (ko) 접합체, 및, 절연 회로 기판
JP6750422B2 (ja) 絶縁回路基板の製造方法、及び、絶縁回路基板、パワーモジュール、ｌｅｄモジュール、熱電モジュール
JP6432373B2 (ja) ヒートシンク付パワーモジュール用基板、パワーモジュール、及び、ヒートシンク付パワーモジュール用基板の製造方法
JP2012191004A (ja) パワーモジュール用基板の製造方法及びパワーモジュール用基板
JP2017063126A (ja) 抵抗器の製造方法、抵抗器
WO2017222061A1 (fr) Procédé de fabrication d'une carte de circuit imprimé isolée, carte de circuit imprimé isolée et module de conversion thermoélectrique
JP6428327B2 (ja) ヒートシンク付パワーモジュール用基板、パワーモジュール、及び、ヒートシンク付パワーモジュール用基板の製造方法
JP2005050886A (ja) 複合基板及びその製造方法
WO2016167217A1 (fr) Corps lié, substrat pour module d'alimentation pourvu d'un dissipateur thermique, dissipateur thermique, procédé de fabrication de corps lié, procédé de fabrication de substrat pour module d'alimentation pourvu d'un dissipateur thermique, et procédé de fabrication de dissipateur thermique
JP6327058B2 (ja) ヒートシンク付パワーモジュール用基板、接合体の製造方法、パワーモジュール用基板の製造方法、及び、ヒートシンク付パワーモジュール用基板の製造方法
JP2018046106A (ja) 銅／チタン／アルミニウム接合体、絶縁回路基板、ヒートシンク付き絶縁回路基板、パワーモジュール、ｌｅｄモジュール、熱電モジュール
WO2020044594A1 (fr) Corps assemblé en cuivre/céramique, carte de circuit imprimé isolée, procédé de production de corps assemblé en cuivre/céramique, et procédé de fabrication de carte de circuit imprimé isolée
JP6439489B2 (ja) パワーモジュール用基板の製造方法及びパワージュールの製造方法
JP6390481B2 (ja) めっき付きパワーモジュール用基板の製造方法
JP6287681B2 (ja) 接合体の製造方法、パワーモジュール用基板の製造方法、及び、ヒートシンク付パワーモジュール用基板の製造方法
JP5303936B2 (ja) パワーモジュール用基板及びパワーモジュール並びにパワーモジュール用基板の製造方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17815526

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

ENP Entry into the national phase

Ref document number: 2017815526

Country of ref document: EP

Effective date: 20190123