WO2017215138A1 - 共平面型双栅电极氧化物薄膜晶体管及其制备方法 - Google Patents

共平面型双栅电极氧化物薄膜晶体管及其制备方法 Download PDF

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WO2017215138A1
WO2017215138A1 PCT/CN2016/099064 CN2016099064W WO2017215138A1 WO 2017215138 A1 WO2017215138 A1 WO 2017215138A1 CN 2016099064 W CN2016099064 W CN 2016099064W WO 2017215138 A1 WO2017215138 A1 WO 2017215138A1
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gate electrode
contact region
oxide semiconductor
substrate
semiconductor layer
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French (fr)
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谢应涛
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6723—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device having light shields
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6733—Multi-gate TFTs
    • H10D30/6734—Multi-gate TFTs having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H10D30/6756—Amorphous oxide semiconductors
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/213—Channel regions of field-effect devices
    • H10D62/221—Channel regions of field-effect devices of FETs
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    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0212—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or coating of substrates
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    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
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    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0241—Manufacture or treatment of multiple TFTs using liquid deposition, e.g. printing
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    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
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    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00—Bonding of wafers, substrates or parts of devices
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/46—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a liquid
    • H10P14/47—Electrolytic deposition, i.e. electroplating; Electroless plating

Definitions

  • the invention relates to the field of display technology, in particular to a coplanar double gate electrode oxide thin film transistor and a preparation method thereof.
  • the carrier mobility of an oxide semiconductor is 20-30 times that of amorphous silicon, which can greatly increase the charge and discharge rate of the TFT electrode, improve the response speed of the pixel, achieve a faster refresh rate, and have a faster response.
  • the line scan rate of the pixels is increased, making ultra-high resolution possible in the TFT-LCD. Therefore, oxide thin film transistor technology is gradually becoming a strong competitor of the next generation display technology.
  • oxide thin film transistor technology is gradually becoming a strong competitor of the next generation display technology.
  • the object of the present invention is to provide a coplanar double gate electrode oxide thin film transistor and a preparation method thereof, which are improved by optimizing and improving the structure and preparation method of the oxide thin film transistor.
  • the device performance stability of the thin film transistor structure accelerates the response speed of the thin film transistor, optimizes the process flow, and reduces the production cost.
  • the present invention includes two aspects.
  • a coplanar double gate electrode oxide thin film transistor comprising: a substrate; a bottom gate electrode formed on an upper surface of the substrate; and a bottom gate formed on the bottom gate a first gate insulating layer on the electrode; an oxide semiconductor layer formed on the first gate insulating layer; a source contact region and a drain contact region formed on both sides of the oxide semiconductor layer; a second gate insulating layer on the oxide semiconductor layer; a top gate electrode formed on the second gate insulating layer; wherein the upper surface of the substrate is recessed toward the interior thereof to form a recess, the bottom gate An electrode is formed in the recess such that an upper surface of the bottom gate electrode is at the same level as an upper surface of the substrate.
  • an upper surface of the source contact region, an upper surface of the drain contact region, and the oxygen are all in the same horizontal plane.
  • the source contact region and/or the drain contact region are formed by plasma processing the oxide semiconductor layer.
  • the plasma treatment uses a gas in which one or a mixture of Ar, H 2 or a mixture of the two is used.
  • the coplanar double gate electrode oxide thin film transistor further includes an interconnection layer formed over the top gate electrode, and a contact hole is formed in the interconnection layer, the contact The hole exposes an upper surface of the source contact region and an upper surface portion of the drain contact region.
  • the coplanar double gate electrode oxide thin film transistor further includes a source and a drain formed on the interconnect layer, and the source passes through the contact hole and the source The contact regions are in contact, and the drain contacts the drain contact region through the contact holes.
  • the coplanar double gate electrode oxide thin film transistor further includes a planarization layer formed on the interconnect layer, the source, and the drain.
  • the coplanar double gate electrode oxide thin film transistor further includes an ITO film layer formed on the planarization layer.
  • the bottom gate electrode is a patterned bottom gate electrode.
  • the top gate electrode is a patterned top gate electrode.
  • the oxide semiconductor layer is a patterned oxide semiconductor layer.
  • the ITO film layer is a patterned ITO film layer.
  • the first gate insulating layer is made of a SiOx or aluminum oxide film.
  • the second gate insulating layer is made of a SiOx or aluminum oxide film.
  • the oxide semiconductor layer is made of an amorphous IGZO film.
  • the interconnect layer is one or a combination of two of a SiOx film, a SiNx film.
  • planarization layer is an organic photoresist film.
  • the present invention also provides a method for fabricating the above-described coplanar double gate electrode oxide thin film transistor, comprising the following steps:
  • the bottom gate electrode is formed on the substrate by patterning the substrate, so that the upper surface of the substrate is recessed toward the interior thereof to form a groove; then, a bottom gate electrode is formed in the groove, The upper surface of the bottom gate electrode is at the same level as the upper surface of the substrate.
  • the substrate is patterned, and the upper surface of the substrate is recessed toward the interior thereof to form a groove, and a photoresist is coated on the substrate, through exposure, Developing forms a bottom gate electrode pattern on the substrate; then, by etching the substrate that is not protected by the photoresist, the substrate is formed into the groove having a depth.
  • the photoresist is a positive photoresist or a negative photoresist.
  • the photoresist is a negative photoresist
  • the bottom gate electrode is formed in the recess by a magnetron sputtering method or The thermal evaporation deposition method forms the bottom gate electrode, and the negative photoresist is removed such that the upper surface of the bottom gate electrode is at the same level as the upper surface of the substrate.
  • the photoresist is a positive photoresist
  • the bottom gate electrode is formed in the recess after the substrate is formed into the groove having a depth. Removing the positive photoresist, and then forming the bottom gate electrode in the groove by an inkjet printing method to make the bottom
  • the upper surface of the gate electrode is at the same level as the upper surface of the substrate.
  • the etching is dry etching or wet etching.
  • the photoresist is removed by immersing the substrate in a degumming solution.
  • the degumming solution is a solution for removing the photoresist
  • the degumming liquid which is common in the prior art can be used, for example, NMP (N-methyl-2-pyrrolidone, N-methylpyrrolidone) is used.
  • NMP N-methyl-2-pyrrolidone, N-methylpyrrolidone
  • Glue N-methyl-2-pyrrolidone
  • oxide semiconductor layer-specific Further, in the manufacturing method of the present invention, after the oxide semiconductor layer is formed over the first gate insulating layer, the oxide semiconductor layer is patterned. A patterned oxide semiconductor layer is obtained.
  • forming a top gate electrode over the second gate insulating layer is forming a second metal layer over the second gate insulating layer The second metal layer is patterned to form a patterned top gate electrode.
  • the patterning process is performed on the second metal layer by applying a photoresist on the second metal layer, and sequentially performing exposure and development to form the photoresist to form the top gate electrode. And removing the second metal layer not protected by the photoresist, the second gate insulating layer not protected by the photoresist, and removing the photoresist by etching.
  • the second metal layer protected by the photoresist and the second gate insulating layer not protected by the photoresist are removed by dry etching or wet etching.
  • the photoresist is removed by a stripping method or by plasma bombardment using oxygen.
  • forming the source contact region and the drain contact region on both sides of the oxide semiconductor layer are
  • the patterned top gate electrode is a protective layer, and the oxide semiconductor layer is plasma-treated to form the oxide semiconductor layer outside the protection range of the patterned top gate electrode to form the source contact region And the drain contact region.
  • an upper surface of the source contact region, an upper surface of the drain contact region, and the oxygen are all in the same horizontal plane.
  • the plasma treatment employs a mixture of one or both of H 2 or Ar.
  • the method further includes the steps of: forming an interconnection layer over the top gate electrode, and patterning the interconnection layer at the interconnection A contact hole is formed in the layer, the contact hole exposing the upper surface of the source contact region and the upper surface portion of the drain contact region.
  • the method further includes the steps of: forming a source and a drain respectively on the interconnect layer, the source passing through the contact hole and the source The contact regions are in contact with each other, and the drain contacts the drain contact region through the contact holes.
  • the method further includes the step of forming a planarization layer on the interconnect layer, the source, and the drain.
  • the method further includes the steps of: forming an ITO film layer on the planarization layer, and patterning the ITO film layer to form a patterned ITO film; Floor.
  • the first gate insulating layer is made of a SiOx or aluminum oxide film.
  • the second gate insulating layer is made of a SiOx or aluminum oxide film.
  • the oxide semiconductor layer is made of an amorphous IGZO film.
  • the interconnection layer is one or a combination of two of a SiOx film and a SiNx film.
  • the thin film transistor is designed as a double gate electrode structure in which a bottom gate electrode and The top gate electrode can serve as a light blocking layer, effectively reducing the influence of illumination on the stability of an oxide thin film transistor, particularly a thin film transistor using an amorphous IGZO thin film as an oxide semiconductor layer.
  • the bottom gate electrode and the top gate electrode have opposite electric fields, which can reduce the internal defect of the IGZO to the channel diffusion, and can also improve the electrical stability of the thin film transistor using the amorphous IGZO film as the oxide semiconductor layer, such as voltage bias. Test and current bias test.
  • the source contact region, the drain contact region and the oxide semiconductor layer in the present invention have a coplanar structure instead of a structure having a step difference, so that the source contact region and the drain contact region overlap with the gate respectively.
  • the smaller part can reduce the intrinsic capacitance of the thin film transistor, thereby reducing the RC delay and improving the response speed of the thin film transistor.
  • the bottom gate electrode and the substrate are also designed to have a coplanar structure, so that the first gate insulating layer and the second gate insulating layer are both planar, and there is no problem of step coverage.
  • a gate insulating layer having a stepped structure is easily broken down at an insulating layer film at a step edge thereof. Therefore, when designing a gate insulating layer having a stepped structure, it is usually necessary to increase the thickness thereof to Avoid breakdown problems.
  • the gate insulating layers are all flat, there is no breakdown problem at the step edges, so the gate insulating layer can be designed to be relatively thinner, thereby reducing the driving voltage and reducing the power consumption.
  • 1 is a schematic view showing the structure of a coplanar double gate electrode oxide thin film transistor of the embodiment.
  • 2A to 2I are process flows of a method for fabricating a coplanar double gate electrode oxide thin film transistor of the embodiment.
  • This embodiment provides a coplanar double gate electrode oxide thin film transistor, as shown in FIG. 1, comprising the following structure:
  • the substrate 1 is provided with a recess that is recessed toward the interior thereof;
  • the first gate insulating layer 31 is made of an SiOx or an aluminum oxide film as an insulating layer of the bottom gate electrode, because the bottom gate electrode and the substrate are coplanar structures. Therefore, the first gate insulating layer is a planar structure instead of a stepped structure;
  • the source contact region and the drain contact region are formed by plasma processing the oxide semiconductor layer. Since the plasma treatment of the oxide semiconductor layer can improve the conductivity of the oxide semiconductor layer, the source contact region and the drain contact region are formed;
  • a patterned source 81 and a drain 82 formed above the interconnect layer 6 and in the contact hole, wherein the source 81 is in contact with the source contact region 51 through the first contact hole 71, and the drain 82 is passed through the second contact hole 72 is in contact with the drain contact region 52.
  • a planarization layer and an ITO film layer which are sequentially formed over the interconnection layer, the source, and the drain may be included, and these structures may be conventional structures of the prior art, and Let me repeat.
  • the thin film transistor has both a double gate electrode structure and a coplanar structure.
  • the bottom gate electrode and the top gate electrode in the double gate electrode structure can be used as a light blocking layer, thereby effectively reducing the influence of illumination on the stability of the oxide thin film transistor (especially the thin film transistor using the amorphous IGZO thin film as the oxide semiconductor layer).
  • the bottom gate electrode and the top gate electrode have opposite electric fields, which can reduce the internal defects of the amorphous IGZO film to diffuse into the channel, thereby increasing The stability of a thin film transistor in which an amorphous IGZO thin film is used as an oxide semiconductor layer is strongly used.
  • the source contact region, the drain contact region, and the oxide semiconductor layer are designed as a coplanar structure instead of a structure having a step difference, which causes the source contact region and the drain.
  • the contact area and the gate overlap each other less, which can reduce the intrinsic capacitance of the thin film transistor, thereby reducing the RC delay and improving the response speed of the thin film transistor.
  • the bottom gate electrode and the substrate are designed to have a coplanar structure, so that the first gate insulating layer and the second gate insulating layer are both planar, and there is no problem of step coverage.
  • a gate insulating layer having a stepped structure is easily broken down at an insulating layer film at a step edge thereof. Therefore, when designing a gate insulating layer having a stepped structure, it is usually necessary to increase the thickness thereof to Avoid breakdown problems.
  • the gate insulating layers are all flat, there is no breakdown problem at the step edges, so the gate insulating layer can be designed to be relatively thinner, thereby reducing the driving voltage and reducing the power consumption.
  • the embodiment further provides a method for preparing the above double gate electrode oxide thin film transistor, comprising the following steps:
  • a substrate 1 is prepared, a negative photoresist is coated on the substrate, exposed and developed, and a bottom gate electrode pattern is formed on the substrate, and dry etching or wet etching is not performed.
  • the substrate protected by the negative photoresist is removed, so that the substrate 1 is formed with a groove 11 having a depth recessed toward the inside thereof, and a pattern of the bottom gate electrode is formed in the groove.
  • a first metal layer is deposited in the recess 11 of the substrate by a magnetron sputtering or a thermal evaporation process, and the first metal formed by deposition is formed due to the pattern of the bottom gate electrode formed in the recess.
  • the layer has a pattern, and the patterned first metal layer is the patterned bottom gate electrode 21; then, the substrate 1 is immersed in the NMP degumming solution to remove the negative photoresist, thereby patterning the bottom gate electrode
  • the upper surface of 21 is at the same level as the upper surface of the substrate 1, and the two form a coplanar structure.
  • a first gate insulating layer 31 is deposited on the patterned bottom gate electrode 21 and the substrate 1 based on a chemical vapor deposition method, and the first gate insulating layer is made of a SiOx or aluminum oxide film as a bottom gate electrode. Insulation layer. Since the bottom gate electrode and the substrate are in a coplanar structure, the first gate insulating layer deposited on both of them is also a planar structure instead of the conventional stepped structure.
  • amorphous is deposited over the first gate insulating layer 31 based on a physical vapor deposition method.
  • the IGZO thin film is used as the oxide semiconductor layer 4, and then the oxide semiconductor layer 4 is patterned by a photolithography process to form a patterned oxide semiconductor layer 4, which also corresponds to the bottom gate. Above the electrode 21.
  • the photolithography process refers to a process of coating a photoresist on a film layer to be patterned, and sequentially performing exposure, development, etching, and photoresist removal to finally achieve corresponding Patterning treatment of the film layer.
  • the reticle used for exposure can be a common reticle without using a relatively high cost halftone reticle.
  • the film layer refers to a conventional film layer structure of a first metal layer, an oxide semiconductor layer, an ITO film layer, or the like in a thin film transistor.
  • a second gate insulating layer 32 is deposited on the patterned oxide semiconductor layer 4 and the first gate insulating layer 31 according to a chemical vapor deposition method, and the second gate insulating layer is made of SiOx or aluminum oxide. film.
  • a second metal layer is deposited on the second gate insulating layer 32 according to a physical vapor deposition method, and the second metal layer is patterned, specifically: coating a photolithography on the second metal layer.
  • a glue (not shown), followed by exposure and development steps to form a top gate electrode pattern; then a second metal layer not protected by the photoresist and not photoresist by dry etching or wet etching
  • the protected second gate insulating layer 32 is removed; then, the photoresist is removed by a lift-off method or by plasma bombardment using oxygen. Thereby, the patterned top gate electrode 22 is obtained, and the excess portion of the second gate insulating layer is also removed.
  • the patterned top gate electrode 22 is used as a protective layer, and the patterned oxide semiconductor layer 4 outside the protection range of the top gate electrode 22 is subjected to H 2 or Ar plasma treatment to expose it to the top.
  • the electric conductivity of the oxide semiconductor layer outside the protection range of the gate electrode is increased, thereby forming the source contact region 51 and the drain contact region 52 on the right side of the oxide semiconductor layer 4, respectively.
  • an interconnect layer 6 is formed on the first gate insulating layer 31, the source contact region 51, the drain contact region 52, and the top gate electrode 22 based on a chemical vapor deposition method, and the interconnect layer is made of SiOx or An aluminum oxide film; the interconnect layer 6 is processed by a photolithography process to form a first contact hole 71 and a second contact hole 72 in the interconnect layer 6, wherein the first contact hole 71 exposes the upper surface portion of the source contact region 51, The second contact hole 72 exposes the upper surface portion of the drain contact region 52.
  • the interconnect layer may also be a SiNx film, a combination of SiOx and SiNx.
  • the formed film When the SiNx film is selected as the interconnect layer, it is not necessary to perform the above-described "top layer electrode 22 with a pattern as a protective layer, and the H2 or Ar plasma is applied to the patterned oxide semiconductor layer 4 outside the protection range of the top gate electrode 22. Processing to increase the electrical conductivity of the oxide semiconductor layer exposed outside the protection range of the top gate electrode, thereby forming the source contact region 51 and the drain contact region 52 ′ on the left side of the oxide semiconductor layer 4, respectively. step.
  • a third metal layer is deposited on the interconnect layer 6 and in the first contact hole 71 and the second contact hole 72, and the third metal layer is processed by a photolithography process to form a source 81 and a drain, respectively.
  • the source 81 is in contact with the source contact region 51 through the first contact hole 71
  • the drain 82 is in contact with the drain contact region 61 through the second contact hole 72.
  • the organic photoresist film is deposited by spin coating or printing on the interconnect layer, the source and the drain, and the organic photoresist film is planarized and post-baked. , to obtain a flattening layer.
  • the preparation method of the embodiment further includes forming an ITO film layer, and patterning the ITO film layer by a photolithography process to obtain a patterned ITO film layer.
  • the embodiment provides a method for preparing a coplanar double-gate electrode oxide thin film transistor according to the second embodiment, and the method is different from the preparation method described in the second embodiment only in that the patterned bottom gate is patterned.
  • the steps of forming the coplanar structure between the electrode and the substrate are different, specifically:
  • the substrate is removed such that the substrate forms a recess having a depth toward the interior thereof, and a pattern of the bottom gate electrode is formed in the recess; the substrate is then immersed in the degumming solution to remove the positive photoresist.
  • a patterned bottom gate electrode is formed in the groove, and by controlling the dose of the conductive ink to be dropped, the bottom gate electrode and the substrate are at the same horizontal plane to form a coplanar structure.
  • the dose of the conductive ink may be such that the bottom gate electrode and the substrate form a coplanar structure, and may be added according to actual conditions.

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Abstract

一种共平面型双栅电极氧化物薄膜晶体管，包括基板(1)、形成于基板(1)上方的底栅电极(21)；形成于底栅电极(21)上方的第一栅极绝缘层(31)；形成于第一栅极绝缘层(31)上方的氧化物半导体层(4)；形成于所述氧化物半导体层(4)两侧的源极接触区(51)和漏极接触区(52)；形成于半导体层(4)上方的第二栅极绝缘层(32)；形成于第二栅极绝缘层(32)上方的顶栅电极(22)；其中，基板(1)上表面朝向自身内部凹陷形成凹槽，底栅电极(21)形成于凹槽中，使底栅电极(21)上表面与基板(1)上表面处于同一水平面。上述薄膜晶体管同时兼具双栅电极和共平面结构的特点，可提高薄膜晶体管的稳定性、优化其响应速度、降低驱动电压等性能。

Description

共平面型双栅电极氧化物薄膜晶体管及其制备方法 技术领域
本发明涉及显示技术领域，具体是一种共平面型双栅电极氧化物薄膜晶体管及其制备方法。
背景技术
氧化物半导体的载流子迁移率是非晶硅的20-30倍，可以大大提高TFT对像素电极的充放电速率，提高像素的响应速度，实现更快的刷新率，同时更快的响应也大大提高了像素的行扫描速率，使得超高分辨率在TFT-LCD中成为可能。因此，氧化物薄膜晶体管技术正逐渐成为下一代显示技术的有力竞争者。但是该技术应用于显示面板量产时存在一重要的制约因素——其稳定性不够，因此实有必要对该技术进行深入研究，改进和优化现有的氧化物薄膜晶体管结构，使其具有更稳定的器件性能。
发明内容
为克服现有技术的不足，本发明的目的在于提供一种共平面型双栅电极氧化物薄膜晶体管及其制备方法，通过对氧化物薄膜晶体管的结构及其制备方法进行优化和改进，来提高薄膜晶体管结构的器件性能稳定性、加快薄膜晶体管的响应速度、优化工艺流程、降低生产成本。
本发明包括两个方面，第一个方面，本发明提供一种共平面型双栅电极氧化物薄膜晶体管，包括：基板；形成于所述基板上表面的底栅电极；形成于所述底栅电极上的第一栅极绝缘层；形成于所述第一栅极绝缘层上的氧化物半导体层；形成于所述氧化物半导体层两侧的源极接触区和漏极接触区；形成于所述氧化物半导体层上的第二栅极绝缘层；形成于所述第二栅极绝缘层上的顶栅电极；其中，所述基板上表面朝向自身内部凹陷形成凹槽，所述底栅电极形成于所述凹槽中，使所述底栅电极上表面与所述基板上表面处于同一水平面。
进一步地，所述源极接触区的上表面、所述漏极接触区的上表面、所述氧 化物半导体层的上表面均处于同一水平面。
【源漏接触区形成方法】进一步地，所述源极接触区和/或所述漏极接触区是对所述氧化物半导体层进行等离子处理形成的。
可选地，所述等离子处理采用气体为Ar、H2中的一种或两种的混合。
【互联层+接触孔】进一步地，所述共平面型双栅电极氧化物薄膜晶体管还包括形成于所述顶栅电极上方的互联层，且所述互联层中形成有接触孔，所述接触孔使所述源极接触区上表面、所述漏极接触区上表面部分暴露。
【源漏极】进一步地，所述共平面型双栅电极氧化物薄膜晶体管还包括形成于所述互联层上的源极和漏极，所述源极通过所述接触孔与所述源极接触区相接触，所述漏极通过所述接触孔与所述漏极接触区相接触。
【平坦化层】进一步地，所述共平面型双栅电极氧化物薄膜晶体管还包括形成于所述互联层、所述源极、所述漏极上的平坦化层。
【ITO】进一步地，所述共平面型双栅电极氧化物薄膜晶体管还包括形成于所述平坦化层上的ITO膜层。
【图案化】进一步地，所述底栅电极为图案化的底栅电极。
进一步地，所述顶栅电极为图案化的顶栅电极。
进一步地，所述氧化物半导体层为图案化的氧化物半导体层。
进一步地，所述ITO膜层为图案化的ITO膜层。
【材料】进一步地，所述第一栅极绝缘层选用SiOx或氧化铝薄膜。
进一步地，所述第二栅极绝缘层选用SiOx或氧化铝薄膜。
进一步地，所述氧化物半导体层选用非晶IGZO薄膜。
进一步地，所述互联层为SiOx薄膜、SiNx薄膜中的一种或两种的组合。
进一步地，所述平坦化层为有机光刻胶膜。
第二个方面，本发明还提供一种上述共平面型双栅电极氧化物薄膜晶体管的制备方法，包括以下步骤：
准备一基板；
在所述基板上形成底栅电极；
在所述底栅电极上方形成第一栅极绝缘层；
在所述第一栅极绝缘层上方形成氧化物半导体层；
在所述氧化物半导体层两侧分别形成所述源极接触区和漏极接触区；
在所述氧化物半导体层上方形成第二栅极绝缘层；
在所述第二栅极绝缘层上方形成顶栅电极；
其中，在所述基板上形成底栅电极是对所述基板进行图案化处理，使所述基板上表面朝向自身内部凹陷形成凹槽；接着，在所述凹槽中形成底栅电极，使所述底栅电极上表面与所述基板上表面处于同一水平面。
进一步地，在本发明所述的制备方法中，对所述基板进行图案化处理，使所述基板上表面朝向自身内部凹陷形成凹槽是在所述基板上涂布光刻胶，通过曝光、显影在所述基板上形成底栅电极图案；接着，通过刻蚀未被所述光刻胶保护的所述基板，使所述基板形成具有深度的所述凹槽。
可选地，在本发明所述的制备方法中，所述光刻胶为正性光刻胶或负性光刻胶。
可选地，在本发明所述的制备方法中，所述光刻胶为负性光刻胶，在所述凹槽中形成底栅电极是在所述凹槽中通过磁控溅射方法或者热蒸镀沉积方法形成所述底栅电极，去除所述负性光刻胶，使所述底栅电极上表面与所述基板上表面处于同一水平面。
可选地，在本发明所述的制备方法中，所述光刻胶为正性光刻胶，在所述凹槽中形成底栅电极是使所述基板形成具有深度的所述凹槽后，去除所述正性光刻胶，接着，在所述凹槽中通过喷墨打印方法形成所述底栅电极，使所述底 栅电极上表面与所述基板上表面处于同一水平面。
【刻蚀】可选地，所述刻蚀为干法刻蚀或者湿法刻蚀。
【去光刻胶】优选地，去除光刻胶是将所述基板浸泡在去胶液中实现的。
其中，所述去胶液是用于除去光刻胶的溶液，采用现有技术中常见的去胶液即可，例如采用NMP(N-methyl-2-pyrrolidone，N-甲基吡咯烷酮)作为去胶液。
【氧化物半导体层-具体】进一步地，在本发明所述的制备方法中，在所述第一栅极绝缘层上方形成氧化物半导体层后，对所述氧化物半导体层进行图案化处理，得到图案化的氧化物半导体层。
【顶栅电极-具体】进一步地，在本发明所述的制备方法中，在所述第二栅极绝缘层上方形成顶栅电极是在所述第二栅极绝缘层上方形成第二金属层，对所述第二金属层进行图案化处理，形成图案化的顶栅电极。
更进一步地，对所述第二金属层进行图案化处理是在所述第二金属层上涂布光刻胶，再依次进行曝光、显影，使所述光刻胶形成所述顶栅电极的图案，再通过刻蚀将未被所述光刻胶保护的所述第二金属层、未被所述光刻胶保护的所述第二栅极绝缘层去掉，再除去所述光刻胶。
优选地，采用干法刻蚀或湿法刻蚀将被所述光刻胶保护的所述第二金属层、未被所述光刻胶保护的所述第二栅极绝缘层去掉。
可选地，通过剥离的方法或者利用氧气进行等离子轰击的方法将所述光刻胶除去。
【源漏极接触区-具体】进一步地，在本发明所述的制备方法中，在所述氧化物半导体层两侧分别形成所述源极接触区和所述漏极接触区是以所述图案化的顶栅电极为保护层，对所述氧化物半导体层进行等离子处理，使处于所述图案化的顶栅电极保护范围之外的所述氧化物半导体层分别形成所述源极接触区和所述漏极接触区。
进一步地，所述源极接触区的上表面、所述漏极接触区的上表面、所述氧 化物半导体层的上表面均处于同一水平面。
【等离子处理-具体】进一步地，在本发明所述的制备方法中，所述等离子处理采用H2或Ar中的一种或两种的混合。
【互联层+接触孔】进一步地，在本发明所述的制备方法中，还包括以下步骤：在所述顶栅电极上方形成互联层，对所述互联层进行图案化处理，在所述互联层中形成接触孔，所述接触孔使所述所述源极接触区上表面、所述漏极接触区上表面部分暴露。
【源漏极】进一步地，在本发明所述的制备方法中，还包括以下步骤：在所述互联层上分别形成源极和漏极，所述源极通过所述接触孔与所述源极接触区相接触，所述漏极通过所述接触孔与所述漏极接触区相接触。
【平坦化层】进一步地，在本发明所述的制备方法中，还包括以下步骤：在所述互联层、所述源极、所述漏极上形成平坦化层。
【ITO】进一步地，在本发明所述的制备方法中，还包括以下步骤：在所述平坦化层上形成ITO膜层，对所述ITO膜层进行图案化处理，形成图案化的ITO膜层。
【材料】进一步地，在本发明所述的制备方法中，所述第一栅极绝缘层选用SiOx或氧化铝薄膜。
进一步地，在本发明所述的制备方法中，所述第二栅极绝缘层选用SiOx或氧化铝薄膜。
进一步地，在本发明所述的制备方法中，所述氧化物半导体层选用非晶IGZO薄膜。
进一步地，在本发明所述的制备方法中，所述互联层为SiOx薄膜、SiNx薄膜中的一种或两种的组合。
与现有技术相比，本发明的有益效果如下：
首先，在本发明中将薄膜晶体管设计为双栅电极结构，其中的底栅电极和 顶栅电极能够作为光照阻挡层，有效减少光照对于氧化物薄膜晶体管(尤其是采用非晶IGZO薄膜作为氧化物半导体层的薄膜晶体管)稳定性的影响。此外，底栅电极与顶栅电极具有相反电场，这能够减少IGZO内部缺陷向沟道扩散，也可提高采用非晶IGZO薄膜作为氧化物半导体层的薄膜晶体管的电性稳定性，如电压偏置测试和电流偏置测试。
其次，本发明中的源极接触区、漏极接触区与氧化物半导体层为共平面结构，而非具有阶梯差的结构，因此源极接触区、漏极接触区分别与栅极之间重叠的部分较少，可减少薄膜晶体管的本征电容，进而减少RC时延，提高薄膜晶体管的响应速度。
最后，本发明中还将底栅电极与基板设计为共平面结构，使得第一栅极绝缘层与第二栅极绝缘层均为平面，不存在阶梯覆盖的问题。与平面结构的栅极绝缘层相比，具有阶梯结构的栅极绝缘层其阶梯边缘处的绝缘层薄膜容易击穿，因此设计具有阶梯结构的栅极绝缘层时，通常需要增加其厚度，以避免击穿问题。而在本发明中，由于栅极绝缘层均为平面，不存在阶梯边缘处的击穿问题，因此可以将栅极绝缘层设计得相对更薄，从而降低驱动电压、降低能耗。
附图说明
图1是实施例一共平面型双栅电极氧化物薄膜晶体管的结构示意图。
图2A至图2I是实施例一共平面型双栅电极氧化物薄膜晶体管制备方法的工艺流程。
具体实施方式
实施例一
本实施例提供一种共平面型双栅电极氧化物薄膜晶体管，如图1所示，包括以下结构:
位于底部的基板1，该基板1设有朝向自身内部凹陷的凹槽；
形成于基板1的凹槽中的图案化的底栅电极21，且该底栅电极21与基板1的上表面处于同一水平面，使得底栅电极21与基板1形成共平面结构；
形成于基板1、底栅电极21上方的第一栅极绝缘层31，该第一栅极绝缘层选用SiOx或氧化铝薄膜作为底栅电极的绝缘层，由于底栅电极与基板为共平面结构，因此该第一栅极绝缘层为平面结构，而非具有阶梯的结构；
形成于第一栅极绝缘层31上方的图案化的氧化物半导体层4，该氧化物半导体层采用非晶IGZO薄膜；
分别形成于氧化物半导体层4左侧的源极接触区51和右侧的漏极接触区52，该源极接触区和漏极接触区均是对氧化物半导体层进行等离子处理后形成的，由于对氧化物半导体层进行等离子处理能够提高氧化物半导体层的导电率，因此形成了源极接触区和漏极接触区；
形成于氧化物半导体层4上方的第二栅极绝缘层32，该第二栅极绝缘层选用SiOx或氧化铝薄膜；
形成于第二栅极绝缘层32上方的图案化的顶栅电极22；
形成于第一栅极绝缘层31、源极接触区51、漏极接触区52、顶栅电极22上方的互联层6，该互联层6中形成有接触孔；其中，接触孔包括使源极接触区51上表面部分暴露的第一接触孔71、使漏极接触区52上表面部分暴露的第二接触孔72；
形成于互联层6上方以及接触孔中的图案化的源极81、漏极82，其中，源极81通过第一接触孔71与源极接触区51相接触，漏极82通过第二接触孔72与漏极接触区52相接触。
在本实施例中，除了上述结构，还可以包括依次形成于互联层、源极、漏极上方的平坦化层和ITO膜层，这些结构均采用现有技术的常规结构即可，在此不再赘述。
在本实施例的共平面型双栅电极氧化物薄膜晶体管中，薄膜晶体管兼具双栅电极结构和共平面结构。其中，双栅电极结构中的底栅电极与顶栅电极能够作为光照阻挡层，有效减少光照对于氧化物薄膜晶体管(尤其是采用非晶IGZO薄膜作为氧化物半导体层的薄膜晶体管)稳定性的影响。此外，底栅电极与顶栅电极具有相反电场，能够减少非晶IGZO薄膜内部缺陷向沟道扩散，进而增 强采用非晶IGZO薄膜作为氧化物半导体层的薄膜晶体管的稳定性。
另外，在本实施例的薄膜晶体管结构中，将源极接触区、漏极接触区与氧化物半导体层设计为共平面结构，而非具有阶梯差的结构，这使得源极接触区、漏极接触区分别与栅极之间重叠的部分较少，可减少薄膜晶体管的本征电容，进而减少RC时延，提高薄膜晶体管的响应速度。
最后，本实施例中将底栅电极与基板设计为共平面结构，使得第一栅极绝缘层与第二栅极绝缘层均为平面，不存在阶梯覆盖的问题。与平面结构的栅极绝缘层相比，具有阶梯结构的栅极绝缘层其阶梯边缘处的绝缘层薄膜容易击穿，因此设计具有阶梯结构的栅极绝缘层时，通常需要增加其厚度，以避免击穿问题。而在本发明中，由于栅极绝缘层均为平面，不存在阶梯边缘处的击穿问题，因此可以将栅极绝缘层设计得相对更薄，从而降低驱动电压、降低能耗。
本实施例还提供一种上述双栅电极氧化物薄膜晶体管的制备方法，包括以下步骤：
如图2A所示，准备一基板1，在基板上涂布负性光刻胶，并进行曝光、显影，在基板上形成底栅电极图案，采用干法刻蚀或湿法刻蚀将未被负性光刻胶保护的基板去除，使基板1形成朝向自身内部凹陷的具有深度的凹槽11，且该凹槽中形成有底栅电极的图案。
如图2B所示，通过磁控溅射或者热蒸镀工艺在所述基板的凹槽11中沉积第一金属层，由于凹槽中形成有底栅电极的图案，因此沉积形成的第一金属层具有图案，此图案化的第一金属层即为图案化的底栅电极21；接着，将基板1浸泡在NMP去胶液中以去除负性光刻胶，从而使图案化的底栅电极21上表面与基板1的上表面处于同一水平面，二者形成共平面结构。
如图2C所示，基于化学气相沉积方法在图案化的底栅电极21、基板1的上方沉积第一栅极绝缘层31，该第一栅极绝缘层选用SiOx或氧化铝薄膜作为底栅电极的绝缘层。由于底栅电极与基板为共平面结构，因此沉积在二者上方的第一栅极绝缘层也为平面结构，而非常规的阶梯结构。
如图2D所示，基于物理气相沉积方法在第一栅极绝缘层31上方沉积非晶 IGZO薄膜作为氧化物半导体层4，然后通过光刻工艺对氧化物半导体层4进行图案化处理，形成图案化的氧化物半导体层4，该图案化的氧化物半导体层4同时也对应于底栅电极21上方。
在本实施例中，光刻工艺是指如下工艺流程：在待进行图案化处理的膜层上涂布光刻胶，并依次进行曝光、显影、刻蚀、去光刻胶，最终实现对相应膜层的图案化处理。其中，曝光所采用的光罩为普通光罩即可，而无需采用成本相对更高的半色调光罩。膜层是指第一金属层、氧化物半导体层、ITO膜层等在薄膜晶体管中的常规膜层结构。
如图2E所示，基于化学气相沉积方法在图案化的氧化物半导体层4、第一栅极绝缘层31上沉积第二栅极绝缘层32，该第二栅极绝缘层选用SiOx或氧化铝薄膜。
如图2F所示，基于物理气相沉积方法在第二栅极绝缘层32上沉积形成第二金属层，对第二金属层进行图案化处理，具体为：在第二金属层上涂布光刻胶(图未示)，再依次进行曝光和显影步骤，形成顶栅电极图案；然后通过干法刻蚀或湿法刻蚀将未被光刻胶保护的第二金属层以及未被光刻胶保护的第二栅极绝缘层32去掉；接着，通过剥离的方法或者利用氧气进行等离子轰击的方法将光刻胶除去。由此，得到图案化的顶栅电极22，同时也去掉了第二栅极绝缘层的多余部分。
如图4G所示，以图案化的顶栅电极22为保护层，对于处于顶栅电极22的保护范围之外的图案化的氧化物半导体层4进行H2或Ar等离子处理，使暴露在顶栅电极保护范围之外的氧化物半导体层的电导率提高，从而形成分别位于氧化物半导体层4左侧的源极接触区51和右侧的漏极接触区52。
如图2H所示，基于化学气相沉积方法在第一栅极绝缘层31、源极接触区51、漏极接触区52、顶栅电极22的上方沉积形成互联层6，该互联层选用SiOx或氧化铝薄膜；通过光刻工艺对互联层6进行处理，使互联层6中形成第一接触孔71、第二接触孔72，其中第一接触孔71使源极接触区51上表面部分暴露，第二接触孔72使漏极接触区52上表面部分暴露。
另外，在本实施例中，互联层还可以选用SiNx薄膜、SiOx与SiNx组合 形成的薄膜。当互联层选用SiNx薄膜时，则无需进行上述“以图案化的顶栅电极22为保护层，对于处于顶栅电极22的保护范围之外的图案化的氧化物半导体层4进行H2或Ar等离子处理，使暴露在顶栅电极保护范围之外的氧化物半导体层的电导率提高，从而形成分别位于氧化物半导体层4左侧的源极接触区51和右侧的漏极接触区52”的步骤。
如图2I所示，在互联层6上方以及第一接触孔71、第二接触孔72中沉积第三金属层，通过光刻工艺对第三金属层进行处理，分别形成源极81、漏极82，其中源极81通过第一接触孔71与源极接触区51相接触，漏极82通过第二接触孔72与漏极接触区61相接触。
此外，本实施例的制备方法中，还包括在互联层、源极、漏极上通过旋涂或打印的方法沉积有机光刻胶膜，并对该有机光刻胶膜进行平坦化、后烘，得到平坦化层。
本实施例的制备方法中还包括形成ITO膜层，并通过光刻工艺对ITO膜层进行图案化处理，得到图案化的ITO膜层。
实施例二
本实施例提供一种实施例二所述的共平面型双栅电极氧化物薄膜晶体管的制备方法，该方法与实施例二中所述的制备方法的区别之处仅在于使图案化的底栅电极与基板形成共平面结构的步骤不同，具体为：
准备一基板，在基板上涂布正性光刻胶，并进行曝光、显影，在基板上形成底栅电极图案，采用干法刻蚀或湿法刻蚀将未被正性光刻胶保护的基板去除，使基板形成朝向自身内部凹陷的具有深度的凹槽，且该凹槽中形成有底栅电极的图案；接着将所述基板浸泡在去胶液中以去除正性光刻胶。
然后，通过喷墨打印的方法，在凹槽中形成图案化的底栅电极，通过控制滴入导电墨水的剂量，使得底栅电极与基板处于同一水平面，形成共平面结构。可以理解的是，在本实施例中，导电墨水的剂量只要能满足使底栅电极与基板形成共平面结构，根据实际情况添加即可。
以上仅对共平面型双栅电极氧化物薄膜晶体管的主体结构进行了说明，该 双栅电极氧化物薄膜晶体管还可以包括其它常规的功能结构，在本发明中不再一一赘述。
以上所述为本发明的具体实施方式，其目的是为了清楚说明本发明而作的举例，并非是对本发明的实施方式的限定。对于所属领域的普通技术人员来说，在上述说明的基础上还可以做出其它不同形式的变化或变动。这里无需也无法对所有的实施方式予以穷举。凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明权利要求的保护范围之内。

Claims (20)

  1. 一种共平面型双栅电极氧化物薄膜晶体管，其中，所述共平面型双栅电极氧化物薄膜晶体管包括：基板；形成于所述基板上方的底栅电极；形成于所述底栅电极上方的第一栅极绝缘层；形成于所述第一栅极绝缘层上方的氧化物半导体层；形成于所述氧化物半导体层两侧的源极接触区和漏极接触区；形成于所述半导体成上方的第二栅极绝缘层；形成于所述第二栅极绝缘层上方的顶栅电极；其中，所述基板上表面朝向自身内部凹陷形成凹槽，所述底栅电极形成于所述凹槽中，使所述底栅电极上表面与所述基板上表面处于同一水平面。
  2. 如权利要求1所述的共平面型双栅电极氧化物薄膜晶体管，其中，所述源极接触区的上表面、所述漏极接触区的上表面、所述氧化物半导体层的上表面均处于同一水平面。
  3. 如权利要求1所述的共平面型双栅电极氧化物薄膜晶体管，其中，所述源极接触区和/或所述漏极接触区是对所述氧化物半导体层进行等离子处理形成的。
  4. 如权利要求2所述的共平面型双栅电极氧化物薄膜晶体管，其中，所述源极接触区和/或所述漏极接触区是对所述氧化物半导体层进行等离子处理形成的。
  5. 一种共平面型双栅电极氧化物薄膜晶体管的制备方法，其中，包括以下步骤：准备一基板；在所述基板上形成底栅电极；在所述底栅电极上方形成第一栅极绝缘层；在所述第一栅极绝缘层上方形成氧化物半导体层；在所述氧化物半导体层两侧分别形成所述源极接触区和漏极接触区；在所述氧化物半导体层上方形成第二栅极绝缘层；在所述第二栅极绝缘层上方形成顶栅电极；其中，在所述基板上形成底栅电极是对所述基板进行图案化处理，使所述基板上表面朝向自身内部凹陷形成凹槽；在所述凹槽中形成底栅电极，使所述底栅电极上表面与所述基板上表面处于同一水平面。
  6. 如权利要求4所述的制备方法，其中，对所述基板进行图案化处理，使所述基板上表面朝向自身内部凹陷形成凹槽是在所述基板上涂布光刻胶，通过曝光、显影在所述基板上形成底栅电极图案；接着，通过刻蚀未被所述光刻胶保护的所述基板，使所述基板形成具有深度的所述凹槽。
  7. 如权利要求5所述的制备方法，其中，所述光刻胶为负性光刻胶，在所述凹槽中形成底栅电极是在所述凹槽中通过磁控溅射方法或者热蒸镀沉积方法形成所述底栅电极，去除所述负性光刻胶，使所述底栅电极上表面与所述基板上表面处于同一水平面。
  8. 如权利要求5所述的制备方法，其中，所述光刻胶为正性光刻胶，在所述凹槽中形成底栅电极是使所述基板形成具有深度的所述凹槽后，去除所述正性光刻胶，接着，在所述凹槽中通过喷墨打印方法形成所述底栅电极，使所述底栅电极上表面与所述基板上表面处于同一水平面。
  9. 如权利要求5所述的制备方法，其中，在所述第二栅极绝缘层上方形成顶栅电极是在所述第二栅极绝缘层上方形成第二金属层，对所述第二金属层进行图案化处理，形成图案化的顶栅电极。
  10. 如权利要求6所述的制备方法，其中，在所述第二栅极绝缘层上方形成顶栅电极是在所述第二栅极绝缘层上方形成第二金属层，对所述第二金属层进行图案化处理，形成图案化的顶栅电极。
  11. 如权利要求7所述的制备方法，其中，在所述第二栅极绝缘层上方形成顶栅电极是在所述第二栅极绝缘层上方形成第二金属层，对所述第二金属层进行图案化处理，形成图案化的顶栅电极。
  12. 如权利要求8所述的制备方法，其中，在所述第二栅极绝缘层上方形成顶栅电极是在所述第二栅极绝缘层上方形成第二金属层，对所述第二金属层进行图案化处理，形成图案化的顶栅电极。
  13. 如权利要求9所述的制备方法，其中，在所述氧化物半导体层两侧分别形成所述源极接触区和所述漏极接触区是以所述图案化的顶栅电极为保护层，对所述氧化物半导体层进行等离子处理，使处于所述图案化的顶栅电极 保护范围之外的所述氧化物半导体层分别形成所述源极接触区和所述漏极接触区。
  14. 如权利要求10所述的制备方法，其中，在所述氧化物半导体层两侧分别形成所述源极接触区和所述漏极接触区是以所述图案化的顶栅电极为保护层，对所述氧化物半导体层进行等离子处理，使处于所述图案化的顶栅电极保护范围之外的所述氧化物半导体层分别形成所述源极接触区和所述漏极接触区。
  15. 如权利要求11所述的制备方法，其中，在所述氧化物半导体层两侧分别形成所述源极接触区和所述漏极接触区是以所述图案化的顶栅电极为保护层，对所述氧化物半导体层进行等离子处理，使处于所述图案化的顶栅电极保护范围之外的所述氧化物半导体层分别形成所述源极接触区和所述漏极接触区。
  16. 如权利要求12所述的制备方法，其中，在所述氧化物半导体层两侧分别形成所述源极接触区和所述漏极接触区是以所述图案化的顶栅电极为保护层，对所述氧化物半导体层进行等离子处理，使处于所述图案化的顶栅电极保护范围之外的所述氧化物半导体层分别形成所述源极接触区和所述漏极接触区。
  17. 如权利要求13所述的制备方法，其中，所述源极接触区的上表面、所述漏极接触区的上表面、所述氧化物半导体层的上表面均处于同一水平面。
  18. 如权利要求14所述的制备方法，其中，所述源极接触区的上表面、所述漏极接触区的上表面、所述氧化物半导体层的上表面均处于同一水平面。
  19. 如权利要求15所述的制备方法，其中，所述源极接触区的上表面、所述漏极接触区的上表面、所述氧化物半导体层的上表面均处于同一水平面。
  20. 如权利要求16所述的制备方法，其中，所述源极接触区的上表面、所述漏极接触区的上表面、所述氧化物半导体层的上表面均处于同一水平面。
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