WO2017215025A1 - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
WO2017215025A1
WO2017215025A1 PCT/CN2016/087284 CN2016087284W WO2017215025A1 WO 2017215025 A1 WO2017215025 A1 WO 2017215025A1 CN 2016087284 W CN2016087284 W CN 2016087284W WO 2017215025 A1 WO2017215025 A1 WO 2017215025A1
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layer
semiconductor layer
substrate
semiconductor
fin structure
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PCT/CN2016/087284
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English (en)
French (fr)
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朱慧珑
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中国科学院微电子研究所
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Priority to US16/310,713 priority Critical patent/US11276769B2/en
Publication of WO2017215025A1 publication Critical patent/WO2017215025A1/zh

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    • H—ELECTRICITY
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/6681—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes

Definitions

  • the present disclosure relates to the field of semiconductors, and more particularly to a semiconductor device and a method of fabricating the same.
  • MOSFETs metal oxide semiconductor field effect transistors
  • a method of fabricating a semiconductor device comprising: forming a fin structure on a substrate; forming a support layer on the substrate on which the fin structure is formed, and patterning the support layer to a support portion extending from a surface of the substrate to a surface of the fin structure and thus physically connecting the fin structure to the substrate; removing a portion of the fin structure adjacent to the substrate to form a first semiconductor layer separate from the substrate; Forming a second semiconductor layer with the first semiconductor layer as a seed layer; removing the first semiconductor layer in at least a portion of the longitudinal extent, and placing the second semiconductor on a side of the first semiconductor layer facing away from the substrate and adjacent to the substrate side The layer is cut, and the cut second semiconductor layer serves as a fin of the semiconductor device.
  • a semiconductor device comprising: a substrate; at least two fins spaced apart from the substrate, wherein at least one pair of adjacent fins of the at least two fins are substantially Arranged parallel to the direction of the surface of the substrate, spaced apart from each other substantially parallel, and substantially mirror-symmetrical with respect to the crystal line between them; an isolation layer formed on the substrate, the isolation layer exposing the fins; And a gate stack formed on the isolation layer that intersects each of the fins.
  • the second semiconductor layer may be grown using a (thin) first semiconductor layer suspended relative to the substrate as a seed layer, and the second semiconductor layer may have high mobility.
  • a suspended thin seed layer can relax the stress in the first semiconductor layer and the second semiconductor layer, thereby helping to suppress defects in the first semiconductor layer or the second semiconductor layer.
  • the first semiconductor layer can be removed, and the second semiconductor layer can be used as a fin of the device.
  • 1-21(b) is a schematic view schematically showing a flow of manufacturing a semiconductor device in accordance with an embodiment of the present disclosure
  • 22-23 are schematic diagrams schematically showing a partial stage in a process of fabricating a semiconductor device in accordance with another embodiment of the present disclosure.
  • 24-25 are schematic diagrams schematically showing a partial stage in a process of fabricating a semiconductor device in accordance with another embodiment of the present disclosure.
  • a layer/element when referred to as being "on" another layer/element, the layer/element may be directly on the other layer/element, or there may be a central layer between them/ element.
  • the layer/element when turning the orientation, This layer/element may be located "under” the other layer/element.
  • a semiconductor device having a suspended fin structure is provided. Specifically, the fin of the device is suspended relative to the substrate.
  • “suspended” means that the fin is separated from the substrate. Note that the spacing between the fins and the substrate can be filled with other materials (eg, an isolation layer).
  • the fins may include high mobility semiconductor materials to improve device performance.
  • the "high mobility” means that the mobility with respect to silicon (Si) is high. High mobility semiconductor materials such as Ge, SiGe or III-V compound semiconductors, and the like.
  • the fin may be a second semiconductor layer formed on (eg, epitaxially) a first semiconductor layer spaced apart from the substrate on the substrate.
  • the first semiconductor layer may be fin-shaped and suspended relative to the substrate.
  • the second semiconductor layer can be formed at least partially around the outer circumference of the first semiconductor layer.
  • “partially surrounding” means that there may be a range along the longitudinal extension direction of the first semiconductor layer, within which the second semiconductor layer may completely enclose the outer surface of the first semiconductor layer. That is, within this range, the second semiconductor layer may form a closed pattern (for example, a rectangle, a polygon, etc. corresponding to the sectional shape of the first semiconductor layer) in a cross section perpendicular to the longitudinal extension direction of the first semiconductor layer. .
  • the first semiconductor layer may be covered by the second semiconductor layer in addition to the surface covered by the support portion.
  • the first semiconductor layer can be relatively thin (eg, having a thickness of about 3-20 nm) and suspended relative to the substrate.
  • stress in the first semiconductor layer and the second semiconductor layer can be relaxed during growth, and thus defects can be suppressed or prevented from occurring in the first semiconductor layer or the second semiconductor layer.
  • a transition layer may be first grown on the first semiconductor layer, and then a second semiconductor layer may be grown on the transition layer.
  • the lattice constant of the transition layer may be gradually changed (for example, by a change in its composition), for example, gradually changing from a lattice constant equal to or close to the first semiconductor layer to be equal to or close to a lattice constant of the second semiconductor layer.
  • the transition layer may be formed at least partially around the outer circumference of the first semiconductor layer, and the second semiconductor layer may be formed at least partially around the outer circumference of the transition layer.
  • the first semiconductor layer (and the transition layer, if present) may be removed leaving at least a portion of the second semiconductor layer to serve as a fin of the device.
  • a portion of the second semiconductor layer on the lateral sides (herein referred to as "left side” and "right side") of the first semiconductor layer may be left as a device. fin. Since the second semiconductor layer is seeded with the first semiconductor layer, the left side portion and the right side portion of the second semiconductor layer are respectively separated from the first semiconductor The left and right side walls of the layer (or transition layer) begin to grow, so their crystal structure can be substantially mirror symmetrical with respect to the center between them.
  • the first semiconductor layer may be physically connected to the substrate via the support and thus supported by the substrate.
  • a portion of the first semiconductor layer connected to the support portion may extend beyond a longitudinal extension of the first semiconductor layer.
  • the support portion may include a laterally extending portion extending along a surface of the substrate and a vertically extending portion extending in a direction substantially perpendicular to the surface of the substrate, wherein the vertically extending portion extends to a vertical direction of the first semiconductor layer substantially perpendicular to the surface of the substrate On the side wall.
  • the first semiconductor layer is physically connected to the substrate through the support portion and thus supported by the substrate.
  • the vertically extending portions of the support portion may extend over the vertical sidewalls on opposite sides of the first semiconductor layer to sandwich the first semiconductor layer.
  • the support portion may be provided at one or both ends of the fin-shaped first semiconductor layer or at the middle of the fin-shaped first semiconductor layer.
  • Such a semiconductor device can be produced, for example, as follows. Specifically, a fin structure may be formed on the substrate. Subsequently, when the fin structure is removed near a portion of the substrate ("lower") to obtain the first semiconductor layer, the first semiconductor layer may be suspended relative to the substrate.
  • a support portion may be formed.
  • Such a support portion can be formed as follows. Specifically, a support layer may be formed on the substrate on which the fin structure is formed, and the support layer is patterned to extend from the surface of the substrate to the surface of the fin structure and thus physically connect the fin structure to the substrate. Support section. The patterning of the support layer can be performed using a mask.
  • the mask extends over the fin structure beyond the fin structure in a direction perpendicular to the longitudinal extension direction of the fin structure (so that the mask can shield the portion of the support layer extending over the substrate surface on both sides of the fin structure) So that the portion can then be retained); and in the longitudinal extension of the fin structure, the mask covers only a portion of the longitudinal extent of the fin structure over the fin structure (so that the mask masks the longitudinal direction of the fin structure) Only a portion of the extent is extended so that the portion can then be connected to the support).
  • the mask may cover one end or both end portions of the fin structure, or cover the middle portion of the fin structure, and the obtained support portion may be correspondingly located at one end or both end portions or the middle portion of the fin structure.
  • the first semiconductor layer is similar to the substrate
  • the support is similar to the anchor of the cantilever beam, anchoring the first semiconductor layer as a cantilever to the substrate.
  • the fin structure may include a stack of a sacrificial layer and a first semiconductor layer sequentially formed on the substrate.
  • the sacrificial layer and the first semiconductor layer may be sequentially formed on the substrate, and then the first semiconductor layer and the sacrificial layer may be patterned into a fin structure.
  • the patterning step can be performed into the substrate so as to have protrusions at a position on the substrate corresponding to the fin structure. Subsequently, the sacrificial layer can be selectively removed.
  • the first semiconductor layer is suspended so that its surface is exposed, a (transition layer and) second semiconductor layer can be grown on the surface thereof.
  • the second semiconductor layer can cover all surfaces exposed by the first semiconductor layer (supported portion).
  • the first semiconductor layer (and the transition layer, if present) may be removed leaving the second semiconductor layer as the fin of the device. Since the first semiconductor layer (and the transition layer) is surrounded by the second semiconductor layer, in order to facilitate removal of the first semiconductor layer (and the transition layer), the first semiconductor layer may face away from the substrate side (herein referred to as "upper side"
  • the second semiconductor layer is opened or cut to expose the inner (transition layer and) first semiconductor layer.
  • the dimensions of the openings or slits in the second semiconductor layer are sufficient to support subsequent formation of a gate stack (including a gate dielectric layer and a gate conductor layer and an optional work function adjustment layer) therethrough.
  • the second semiconductor layer may be removed at a laterally extending portion of the upper side and the lower side (a portion extending substantially parallel to the surface of the substrate) such that the second semiconductor layer remains originally located within the at least a portion of the longitudinal extent
  • Portions of the lateral sides of the first semiconductor layer i.e., “left side” and “right side", that is, portions that extend substantially perpendicular to the surface of the substrate, may serve as fins.
  • the end of the second semiconductor layer in the longitudinal extension direction of the fin structure for example, the portion of the second semiconductor layer extending on the end face of the transition layer or the first semiconductor layer in the longitudinal extension direction may be removed) ), thereby dividing the second semiconductor layer into two portions that are opposite to each other.
  • portions of the remaining second semiconductor layer at this time extend substantially perpendicularly to the direction of the substrate surface, similar to conventional techniques.
  • the form of the middle fin is also possible to cut off the end of the second semiconductor layer in the longitudinal extension direction of the fin structure (for example, the portion of the second semiconductor layer extending on the end face of the transition layer or the first semiconductor layer in the longitudinal extension direction may be removed) ), thereby dividing the second semiconductor layer into two portions that are opposite to each other.
  • the device can be shaped on a substrate An isolation layer is formed, and a gate stack intersecting the second semiconductor layer or the fin is formed on the isolation layer.
  • the substrate 1001 may be a substrate of various forms such as, but not limited to, a bulk semiconductor material substrate such as a bulk Si substrate or the like. In the following description, a bulk Si substrate will be described as an example for convenience of explanation.
  • the substrate 1001 may be a silicon single crystal whose surface may be, for example, a (110) crystal plane, a (100) crystal plane, or a (112) crystal plane.
  • the sacrificial layer 1003 and the first semiconductor layer 1005 are sequentially formed, for example, by epitaxial growth.
  • the sacrificial layer 1003 may include a semiconductor material different from the substrate 1001 and the first semiconductor layer 1005, such as SiGe (the atomic percentage of Ge is, for example, about 5 to 20%), and the thickness is about 10 to 100 nm.
  • the first semiconductor layer 1005 may comprise a suitable semiconductor material, such as Si, having a thickness of between about 10 and 100 nm.
  • the first semiconductor layer 1005 and the sacrificial layer 1003 (and optionally the substrate 1001) thus formed may be patterned to form a fin structure.
  • this can be done as follows.
  • a hard mask layer may be formed on the first semiconductor layer 1005.
  • the hard mask layer can include an oxide (eg, silicon oxide) layer 1007 and a polycrystalline Si layer 1009.
  • the oxide layer 1007 has a thickness of about 2 to 10 nm
  • the polycrystalline Si layer 1009 has a thickness of about 50 to 120 nm.
  • the hard mask is patterned into fins using a pattern transfer technique.
  • a photoresist PR patterned (for example, by exposure, development) may be formed on the hard mask layer.
  • the photoresist PR is patterned in a strip shape extending perpendicular to the paper surface direction, and its width (dimension in the horizontal direction in the drawing) may substantially correspond to the interval between the two fin structures.
  • the polycrystalline Si layer 1009 (relative to the oxide layer 1007) is selectively etched, such as reactive ion etching (RIE), using the photoresist PR as a mask.
  • RIE reactive ion etching
  • the polycrystalline Si layer 1009 can be patterned into strips corresponding to the photoresist PR.
  • FIG. 3(a) the photoresist PR is removed, and a spacer 1011 is formed on the sidewall of the polycrystalline Si layer 1009. There are various means in the art to form side walls.
  • a layer of nitride (e.g., silicon nitride) may be substantially conformally deposited by, for example, atomic layer deposition (ALD), having a thickness of, for example, about 3 to 20 nm, and then selectively etching the deposited nitride.
  • ALD atomic layer deposition
  • the RIE (for example, in a direction substantially perpendicular to the surface of the substrate) is removed from its laterally extending portion such that the vertically extending portion remains to form the spacer 1011.
  • the sidewall 1011 covers the sidewall of the Si layer 1009.
  • Fig. 3(b) shows a plan view of the structure shown in Fig. 3(a). Note that although not shown in Figure 3(b), however, on the side walls of the upper and lower ends of the strip-shaped polycrystalline Si layer 1009, the side wall 1011 is also present, so that the side wall 1011 forms a closed pattern around the outer circumference of the strip-shaped polycrystalline Si layer 1009.
  • FIGS. 4(a) and 4(b) In order to obtain a fin-shaped mask, as shown in FIGS. 4(a) and 4(b) (FIG. 4(a) is a plan view, and 4(b) is a cross-sectional view taken along line AA' in FIG. 4(a)),
  • the polycrystalline Si layer 1009 can be selectively removed (eg, by a TMAH solution) and then patterned to form a photoresist 1013.
  • the photoresist 1013 can shield the middle portion of the sidewall 1011 and expose portions of the upper and lower sides of the sidewall 1011.
  • the spacer 1011 is selectively etched, such as RIE, by using the photoresist 1013 as a mask, so that the sidewall 1011 which is originally a closed pattern can be separated into two parts, as shown in FIG.
  • Each portion corresponds to a fin structure to be formed, which in this example is a strip extending in the vertical direction in the drawing.
  • the oxide layer 1007, the first semiconductor layer 1005, and the sacrificial layer 1003 may be selectively etched, such as RIE, by using the sidewall 1011 as a mask.
  • the pattern of the side wall 1011 is transferred to the lower layer to obtain a fin structure. Therefore, the width of the first semiconductor layer 1005 (the dimension in the horizontal direction in the drawing) is substantially the same as the width of the spacer 1011 (for example, about 3 to 20 nm).
  • the side walls of the first semiconductor layer 1005 (the left and right side walls in the drawing) may be (111) or (110) crystal faces, which are liable to reduce growth defects.
  • the substrate 1001 can be further selectively etched. Therefore, at a position corresponding to the fin structure, the substrate 1001 may have protrusions thereon. The projection of the fin structure on the substrate is located substantially in the middle of the protrusion. Due to the etching characteristics, the etched sacrificial layer 1003 and the protrusions of the substrate 1001 may have a shape that gradually becomes larger from top to bottom. Thereafter, the sidewall spacers 1011 can be selectively removed (the oxide layer 1007 can be further selectively removed).
  • a fin-shaped photoresist may be directly formed on the first semiconductor layer 1005, and the first semiconductor layer 1005, the sacrificial layer 1003, and the substrate 1001 may be selectively etched using the photoresist as a mask to form a fin. structure.
  • a fin-shaped photoresist may be directly formed on the hard mask layer, the hard mask may be patterned into a fin by a photoresist, and the first semiconductor layer 1005 may be selectively etched sequentially by using a fin-shaped hard mask.
  • the sacrificial layer 1003 and the substrate 1001 are formed to form a fin structure.
  • fin structures are shown. However, the present disclosure is not limited thereto, and for example, more or less fin structures may be formed. In addition, the layout of the fin structure can be designed differently depending on the device requirements.
  • a support portion may be formed.
  • the oxide layer 1015 and the nitride layer 1017 are deposited in a substantially conformal manner, for example, by ALD.
  • the oxide layer 1015 may have a thickness of about 1 to 10 nm
  • the nitride layer 1017 may have a thickness of about 2 to 15 nm.
  • a patterned photoresist 1019 can be formed on the structure shown in FIG.
  • the photoresist 1019 is patterned to cover the end of one side (lower side in the drawing) of the fin structure and extends in the horizontal direction in the drawing. It should be noted here that in the top view of FIG. 8, the appearance of the nitride layer 1017 with the fin structure on the substrate is not shown for convenience, and the same is true in the following plan view.
  • FIG. 9(a) is a plan view
  • Fig. 9(b) is a cross-sectional view taken along line AA' in Fig. 9(a)
  • Fig. 9 ( c) is a cross-sectional view taken along line A1A1' in Fig. 9(a)
  • the nitride layer 1017 is selectively removed by, for example, RIE (relative to the oxide layer 1015) using the photoresist 1019 as a mask.
  • RIE reactive vapor deposition
  • the nitride layer 1017 is left at the end of the fin structure side (the lower side in FIG.
  • the nitride layer 1017 physically connects the fin structure to the substrate 1001 and thus can support the fin structure (particularly after removing the sacrificial layer 1003 as described below). Thereafter, the photoresist 1019 can be removed.
  • a support layer of a laminate structure of an oxide layer and a nitride layer is formed, and the support layer is patterned into a support portion.
  • the support layer can include a variety of suitable dielectric materials.
  • the support layer may even comprise a semiconductor material or a conductive material.
  • the tip end portion of the nitride layer 1017 can also be selectively removed, for example, by RIE (relative to the oxide layer 1015). However, a portion of the nitride layer 1017 remains on the sidewalls of the first semiconductor layer 1005 to subsequently support the first semiconductor layer 1005.
  • FIGS. 11(a), 11(b) and 11(c) are plan views
  • Fig. 11(b) is a cross-sectional view taken along line AA' in Fig. 11(a)
  • Fig. 11 ( c) is shown in the cross-sectional view taken along line A1A1' in Fig. 11(a)
  • the oxide layer 1015 is removed.
  • FIGS. 11(a) and 11(c) at one end of the fin structure (lower side in FIG.
  • the oxide layer 1015 is covered by the nitride layer 1017 and can be retained. .
  • wet etching for example, wet etching, (relative to the substrate 1001 of the Si material)
  • a semiconductor layer 1005) selectively removes the sacrificial layer 1003.
  • a space 1021 is formed between the fin-shaped first semiconductor layer 1005 and the substrate 1001.
  • Figure 13 shows a perspective view of the structure shown in Figure 12.
  • the first semiconductor layer 1005 is spaced apart from the substrate 1001 by a spacer 1021, extends substantially parallel to the surface of the substrate, and is supported by the substrate 1001 via the support portion 1015/1017.
  • the extending direction of the first semiconductor layer 1005 may be parallel to the intersection of the (110) crystal plane and the (1-11) crystal plane or the (110) crystal plane and (1) -1-1) a crossing line of the crystal plane or a crossing line of the (110) crystal plane and the (-111) crystal plane
  • the side surface of the first semiconductor layer 1005 may be substantially parallel to the (111) crystal plane family; or on the surface of the substrate
  • the extending direction of the first semiconductor layer 1005 may be parallel to the intersection line of the (112) crystal plane and the (-1-11) crystal plane or the (112) crystal plane and (11-1)
  • the intersection of the crystal faces, the side faces of the first semiconductor layer 1005 may also be substantially parallel to the (111) crystal face family.
  • the extending direction of the first semiconductor layer 1005 may correspond to the ⁇ 110> direction, and in the case where the substrate surface is a (100) crystal plane, the side surface of the first semiconductor layer 1005 may be substantially parallel to the (110) crystal plane. These crystal faces are prone to reduce growth defects.
  • FIG. 13 only a single first semiconductor layer 1005 and corresponding support portions are shown for convenience, and the residual oxide layer 1015 is not shown.
  • the support portion 1015/1017 includes a laterally extending portion extending over the surface of the substrate 1001 and a vertically extending portion extending in a direction substantially perpendicular to the surface of the substrate.
  • the vertically extending portion may include a portion extending along a surface of the protrusion of the substrate 1011, a portion extending along a surface of the sacrificial layer 1003 (which has been removed), and extending along a vertical sidewall of the first semiconductor layer 1005. section.
  • the support portion 1015/1017 physically connects the first semiconductor layer 1005 to the substrate 1001 so that the first semiconductor layer 1005 can be supported.
  • the support portions 1015/1017 may extend on vertical sidewalls on opposite sides (left and right sides in the drawing) of the first semiconductor layer 1005, thereby sandwiching the first semiconductor layer to support the first semiconductor layer 1005 more stably .
  • the support portion 1015/1017 also extends on the end side wall of the first semiconductor layer 1005 facing the reader side.
  • the extension of the portion where the first semiconductor layer 1005 and the support portion 1015/1017 are connected is smaller than the longitudinal extension of the first semiconductor layer 1005.
  • the "longitudinal extension direction” means the longitudinal direction of the first semiconductor layer 1005 (the direction perpendicular to the plane of the paper in FIG.
  • the first semiconductor layer 1005 forms a structure similar to a cantilever beam with respect to the substrate 1001, and the cantilever beam passes through the branch The struts 1015/1017 are anchored to the substrate 1001.
  • the support portion includes the oxide layer 1015 in addition to the nitride layer 1017, but the present disclosure is not limited thereto.
  • the nitride layer 1017 may be formed without forming the oxide layer 1015.
  • subsequent operations can also be performed in the manner described above in connection with Figures 8-12.
  • the support portion may also be other dielectric materials or laminated structures.
  • the support portions are formed at the ends on the lower side.
  • the present disclosure is not limited thereto.
  • the support portion may be formed at the lower end portion as described above; and for the other fin structure, the support portion may be formed at other positions such as the upper side end portion as described below.
  • the mask 1019 (see FIG. 8) for patterning the support portion is not limited to the above shape.
  • the mask may extend beyond the fin structure over the fin structure in a direction perpendicular to the longitudinal extension of the fin structure. In this way, the mask can cover a portion of the nitride layer 1017 that extends over the surface of the substrate 1001 (outside the protrusion), which portion can then remain (acting as a base for the support).
  • the mask in the longitudinal extension direction of the fin structure, the mask may cover only a portion of the longitudinal extension of the fin structure above the fin structure. In this way, a configuration similar to a cantilever-anchoring structure can be formed.
  • the second semiconductor layer 1025 may be grown on the first semiconductor layer 1005.
  • the second semiconductor layer 1025 may include a high mobility material such as a Ge, SiGe or III-V compound semiconductor such as InSb, InGaSb, InAs, GaAs, InGaAs, AlSb, InP, Group III nitride, etc., and the thickness may be About 5 to 15 nm.
  • a composition thereof (for example, a percentage of Ge atom) may be graded such that, for example, a difference from a lattice constant of the first semiconductor layer 1005 (here, Si) is changed to become smaller with the first semiconductor layer.
  • the lattice constants of 1005 differ greatly in order to suppress the generation of dislocations or defects.
  • the side surface of the second semiconductor layer 1025 may be substantially parallel to the (111) crystal plane family or the (110) crystal plane family in the substrate.
  • the transition layer 1023 may be grown on the first semiconductor layer 1005, and then the second semiconductor layer 1025 may be grown on the transition layer 1023.
  • the transition layer 1023 may comprise various suitable semiconductor materials, such as Ge, SiGe or III-V compound semiconductors such as InSb, InGaSb, InAs, GaAs, InGaAs, AlSb, InP, Group III nitride, etc., having a thickness of about 1 nm - 20nm.
  • the transition layer 1023 may include the same or different material as the second semiconductor layer 1025.
  • This growth may be selective growth such that the second semiconductor layer 1025 of the transition layer 1023 is semi-conductive
  • the first semiconductor layer 1005 of the bulk material (and the substrate 1001) is grown on the surface, and the second semiconductor layer 1025 is grown on the surface of the transition layer 1023 of the semiconductor material.
  • the growth of the transition layer 1023 and the second semiconductor layer 1025 can be controlled such that it does not completely fill the gap 1021 between the first semiconductor layer 1005 and the substrate 1001. Due to the suspended configuration of the first semiconductor layer 1005, stresses in the first semiconductor layer 1005, the transition layer 1023, and the second semiconductor layer 1025 may be relaxed during growth. In this way, defects can be suppressed or prevented from occurring in the first semiconductor layer 1005, the transition layer 1023, or the second semiconductor layer 1025, which contributes to improvement in device performance (for example, reduction of off-state leakage current and improvement of on-state current).
  • the remaining surface of the first semiconductor layer 1005 is covered by the transition layer and the second semiconductor layer except for the surface covered by the support portion 1015/1017.
  • a transition layer 1023 and a second semiconductor layer 1025 may also be grown on the surface of the substrate 1001.
  • the transition layer 1023 completely encloses the outer periphery of the first semiconductor layer 1005 at the remaining longitudinal extent except for the longitudinal extent occupied by the support portion, and
  • the second semiconductor layer 1025 completely encapsulates the outer periphery of the transition layer 1023.
  • the transition layer 1023 forms a closed pattern (a rectangle in this example) in a cross section perpendicular to the longitudinal extension direction of the first semiconductor layer 1005 (ie, the cross sections shown in FIGS. 14(a) and 14(b)),
  • the second semiconductor layer 1025 forms a closed pattern (rectangular in this example).
  • the closed pattern is defined by the pattern of the first semiconductor layer 1005 at the cross section, and may be other shapes such as a polygon.
  • the second semiconductor layer 1023 can then serve as the fin of the device.
  • the transition layer 1023 and the first semiconductor layer 1005 may be removed leaving at least a portion of the second semiconductor layer 1023 (eg, the sides thereof are as shown on the left and right sides of FIG. 14(a) The side part) acts as a fin.
  • the dielectric layer 1027 may be formed on the structure shown in FIG. 14, for example, by deposition, and etched back to the dielectric layer 1027 until The second semiconductor layer 1025 is exposed.
  • the dielectric layer 1027 may be planarized, such as chemical mechanical polishing (CMP), prior to etch back. Alternatively, the planarization process may terminate the second semiconductor layer 1025 so that no further etch back is required.
  • dielectric layer 1027 can comprise an oxide (eg, silicon oxide).
  • the layer structure above the first semiconductor layer 1005 can be removed.
  • RIE can be used (it is possible to select the engraving of the transition layer 1023 and the second semiconductor layer 1025 at the same time)
  • the etch recipe etches back the transition layer 1023 and the second semiconductor layer 1025 until the first semiconductor layer 1005 is exposed.
  • a mask layer 1029 in the form of a sidewall spacer may be formed on the sidewall of such a recess.
  • the mask layer 1029 can deposit a layer of nitride (having a thickness of, for example, about 3 to 15 nm) by substantially conformal deposition, and then RIE the nitride layer to remove its laterally extending portion leaving its longitudinally extending portion. Thereby, a side wall 1029 is formed on the inner wall of the groove.
  • the sidewall spacers 1029 may cover at least a portion of the second semiconductor layer 1025 without covering the first semiconductor layer 1005 and the transition layer 1023. This formation of the mask layer 1029 is such that the sidewalls of the mask layer 1029 can be self-aligned to the sidewalls of the second semiconductor layer 1025.
  • dielectric layer 1027 can be etched back (eg, by wet etching or vapor etching).
  • the dielectric layer 1027 can be etched back to a top surface that is close to but higher than the bottom surface of the second semiconductor layer.
  • the top surface of the dielectric layer 1027 is between the bottom surface of the second dielectric layer and the bottom surface of the transition layer 1023. This is to reduce the height difference on the top surface of the dielectric layer 1027 (for example, the height difference between the top surface of the portion under the second semiconductor layer 1025 and the top surface of the remaining portion) so that the top surface can be obtained substantially later. Isolation layer of the same height.
  • the semiconductor layer (including the first semiconductor layer 1005, the transition layer 1023, and the second semiconductor layer 1025) may be selectively etched, such as RIE, using the mask layer 1029.
  • the RIE dielectric layer 1027 may be further etched back below the bottom surface of the second semiconductor layer 1025. Since the height difference on the top surface of the dielectric layer 1027 has been reduced as described above, the top surface of the dielectric layer 1027 may be substantially at the same height after further etch back (except for the portion below the second semiconductor layer 1025, the portion may Adjoining the bottom surface of the second semiconductor layer 1025).
  • the dielectric layer 1027 can serve as an isolation layer.
  • Mask layer 1029 can then be removed.
  • fins 1025 are formed on the substrate (more specifically, on the isolation layer 1027).
  • the fins 1025 extend generally perpendicular to the surface of the substrate.
  • the fins 1025 at this time in the plan view may still be in a closed shape as shown in FIG. Note that in FIG. 19, the residue of the support portion is not shown for the sake of convenience.
  • This closed shaped fin can be severed to form a separate fin.
  • the middle portion of the second semiconductor layer 1025 may be shielded by a mask (for example, photoresist) 1031, and the ends thereof (ends on the upper and lower sides in the drawing) may be exposed. Then, you can The second semiconductor layer 1025 is subjected to selective etching such as RIE. Thus, the exposed end portions of the second semiconductor layer 1025 are removed, thereby obtaining separated fins as shown in Fig.
  • the second semiconductor layer 1025 may not be cut, but still retain its closed shape as described in FIG. In this case, the source/drain regions of the device formed based on the pair of left fins are connected to each other, and the source/drain regions of the device formed based on the right pair of fins are connected to each other.
  • a gate stack intersecting the fins may be formed and a final semiconductor device (eg, a FinFET) formed.
  • a final semiconductor device eg, a FinFET
  • 21(a) and 21(b) are a plan view
  • FIG. 21(b) is a cross-sectional view taken along line AA' in FIG. 21(a)
  • the gate dielectric layer 1033 and the gate conductor layer 1035 may be sequentially formed.
  • the gate dielectric layer 1033 may include an oxide (eg, SiO 2 or GeO 2 ) having a thickness of about 0.3 to 2 nm, and the gate conductor layer 1035 may include polysilicon; or the gate dielectric layer 1033 may include a thickness of about 1 to 4 nm.
  • the high K gate dielectric such as HfO 2 or Al 2 O 3
  • the gate conductor layer 1035 may include a metal gate conductor.
  • a function adjustment layer (not shown), such as TiN, Al, Ti, TiAlC, may be formed between the gate dielectric layer 1033 and the gate conductor layer 1035, and has a thickness of about 1 to 3 nm.
  • the gate stack of the respective counterparts of the respective fins is shown in the same configuration and integrally extended for convenience of illustration, but the present disclosure is not limited thereto.
  • the devices can have different gate stack configurations (eg, the gate stack of the n-type device can be different than the gate stack of the p-type device), and the respective gate stack can be patterned according to the device layout.
  • a gate stack can be used as a mask for halo implantation and extension implantation.
  • a gate spacer can be formed on the sidewalls of the gate stack.
  • Source/drain (S/D) implantation can then be performed using the gate stack and the gate spacer as a mask.
  • the implanted ions can then be activated by annealing to form source/drain regions.
  • the semiconductor The bulk device can include at least two fins 1025 spaced apart from the substrate 1001.
  • at least one pair of adjacent fins may be arranged in a direction substantially parallel to the surface of the substrate, spaced apart from each other substantially in parallel, And is substantially mirror symmetrical with respect to the crystal structure with respect to the center line between them.
  • the pair of fins can be symmetrical about a line that is substantially perpendicular to the surface of the substrate and that passes through the middle of the corresponding protrusion on the substrate.
  • the device further includes an isolation layer 1027 and a gate stack (1033, 1035) formed on the isolation layer 1027 that intersects the fins 1025.
  • the support portion is not intentionally removed.
  • the support may also be selectively (at least partially) removed (eg, after forming the gate stack), the space resulting from its removal being subsequently filled, for example, by other dielectric layers.
  • the support portion is formed only at one end portion of the first semiconductor layer, but the present disclosure is not limited thereto, and the support portion may be formed at both end portions of the first semiconductor layer.
  • the photoresist 1019 is patterned to cover the ends of both sides of the fin structure (upper and lower sides in the drawing) and extend in the horizontal direction in the drawing. Subsequent operations can be performed in the same manner as described above. In this case, a suspension structure as shown in Fig. 23 can be obtained. Specifically, as shown in FIG. 23, the first semiconductor layer 1005 is suspended with respect to the substrate 1001, and both ends thereof are supported by the substrate 1001 through the support portion 1017.
  • the support portion is not limited to being formed at the end of the first semiconductor layer, but may be formed at any position in the longitudinal extension thereof.
  • the photoresist 1019 is patterned to cover the middle of the fin structure and extend in the horizontal direction in the drawing. Subsequent operations can be performed in the same manner as described above. In this case, a suspension structure as shown in Fig. 25 can be obtained. Specifically, as shown in FIG. 25, the first semiconductor layer 1005 is suspended with respect to the substrate 1001, and the middle portion thereof is supported by the substrate 1001 through the support portion 1017.
  • a semiconductor device can be applied to various electronic devices. For example, by integrating a plurality of such semiconductor devices and other devices (eg, other forms of transistors, etc.), an integrated circuit (IC) can be formed, and thereby an electronic device can be constructed. Accordingly, the present disclosure also provides an electronic device including the above semiconductor device.
  • the electronic device can also include a display screen that mates with the integrated circuit and a wireless transceiver that mates with the integrated circuit.
  • Such electronic devices are, for example, smart phones, tablet computers (PCs), personal digital assistants (PDAs), and the like.
  • a method of fabricating a chip system is also provided.
  • the party The method may include the above method of manufacturing a semiconductor device.
  • a variety of devices can be integrated on a chip, at least some of which are fabricated in accordance with the methods of the present disclosure.

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Abstract

一种半导体器件及其制造方法。方法包括：在衬底（1001）上形成鳍状结构；在形成有鳍状结构的衬底（1001）上形成支撑层，并将该支撑层构图为从衬底（1001）表面延伸至鳍状结构的表面并因此将鳍状结构与衬底（1001）在物理上连接的支撑部（1015/1017）；去除鳍状结构靠近衬底（1001）的一部分，以形成与衬底（1001）分离的第一半导体层（1005）；以第一半导体层（1005）为种子层，生长第二半导体层（1025）；在至少部分纵向延伸范围内，去除第一半导体层（1005），并在第一半导体层（1005）背离衬底（1001）一侧以及靠近衬底（1001）一侧将第二半导体层（1025）切断，切断的第二半导体层（1025）作为该半导体器件的鳍。

Description

半导体器件及其制造方法
相关申请的引用
本申请要求于2016年6月17日递交的题为“半导体器件及其制造方法”的中国专利申请201610438781.1的优先权，其内容一并于此用作参考。
技术领域
本公开涉及半导体领域，更具体地，涉及一种半导体器件及其制造方法。
背景技术
随着半导体器件的发展，期望以迁移率高于硅(Si)的半导体材料来制作高性能半导体器件如金属氧化物半导体场效应晶体管(MOSFET)。但是，难以形成高质量的高迁移率半导体材料。
发明内容
本公开的目的至少部分地在于提供一种具有高质量外延层的半导体器件及其制造方法。
根据本公开的一个方面，提供了一种制造半导体器件的方法，包括：在衬底上形成鳍状结构；在形成有鳍状结构的衬底上形成支撑层，并将该支撑质层构图为从衬底表面延伸至鳍状结构的表面并因此将鳍状结构与衬底在物理上连接的支撑部；去除鳍状结构靠近衬底的一部分，以形成与衬底分离的第一半导体层；以第一半导体层为种子层，生长第二半导体层；在至少部分纵向延伸范围内，去除第一半导体层，并在第一半导体层背离衬底一侧以及靠近衬底一侧将第二半导体层切断，切断的第二半导体层作为该半导体器件的鳍。
根据本公开的另一方面，提供了一种半导体器件，包括：衬底；与衬底相隔开的至少两个鳍，其中，所述至少两个鳍中至少一对相邻的鳍沿大致平行于衬底表面的方向排列，彼此间隔开大致平行延伸，且相对于它们之间的中线在晶体结构上是实质上镜像对称的；在衬底上形成的隔离层，隔离层露出各鳍；以及在隔离层上形成的与各鳍相交的栅堆叠。
根据本公开的实施例，可以利用相对于衬底悬置的(薄)第一半导体层作为种子层，来生长第二半导体层，第二半导体层可以具有高迁移率。这种悬置薄种子层可以使第一半导体层和第二半导体层中的应力弛豫，从而有助于抑制第一半导体层或第二半导体层中的缺陷。之后，可以去除第一半导体层，第二半导体层可以用作器件的鳍。
附图说明
通过以下参照附图对本公开实施例的描述，本公开的上述以及其他目的、特征和优点将更为清楚，在附图中：
图1-21(b)是示意性示出了根据本公开实施例的制造半导体器件流程的示意图；
图22-23是示意性示出了根据本公开另一实施例的制造半导体器件流程中部分阶段的示意图；
图24-25是示意性示出了根据本公开另一实施例的制造半导体器件流程中部分阶段的示意图。
具体实施方式
以下，将参照附图来描述本公开的实施例。但是应该理解，这些描述只是示例性的，而并非要限制本公开的范围。此外，在以下说明中，省略了对公知结构和技术的描述，以避免不必要地混淆本公开的概念。
在附图中示出了根据本公开实施例的各种结构示意图。这些图并非是按比例绘制的，其中为了清楚表达的目的，放大了某些细节，并且可能省略了某些细节。图中所示出的各种区域、层的形状以及它们之间的相对大小、位置关系仅是示例性的，实际中可能由于制造公差或技术限制而有所偏差，并且本领域技术人员根据实际所需可以另外设计具有不同形状、大小、相对位置的区域/层。
在本公开的上下文中，当将一层/元件称作位于另一层/元件“上”时，该层/元件可以直接位于该另一层/元件上，或者它们之间可以存在居中层/元件。另外，如果在一种朝向中一层/元件位于另一层/元件“上”，那么当调转朝向时， 该层/元件可以位于该另一层/元件“下”。
根据本公开的实施例，提供了一种具有悬置鳍结构的半导体器件。具体地，该器件的鳍相对于衬底悬置。在此，所谓“悬置”，是指鳍与衬底相分离。注意，鳍与衬底之间的间隔可以被其他材料(例如，隔离层)填充。鳍可以包括高迁移率半导体材料，以改善器件性能。在此，所谓的“高迁移率”是指相对于硅(Si)的迁移率要高。高迁移率半导体材料例如Ge、SiGe或III-V族化合物半导体等。
鳍可以是在衬底上与衬底隔开的第一半导体层上(例如，外延)形成的第二半导体层。第一半导体层可以呈鳍状，且相对于衬底悬置。于是，第二半导体层可以至少部分地环绕第一半导体层的外周形成。在此，所谓“部分地环绕”，是指沿第一半导体层的纵向延伸方向可以存在一范围，在该范围内，第二半导体层可以完全包封第一半导体层的外表面。也即，在该范围内，在与第一半导体层的纵向延伸方向垂直的截面上，第二半导体层可以形成闭合图案(例如，与第一半导体层的截面形状相对应的矩形、多边形等)。当然，第一半导体层除了被支撑部覆盖的表面之外，其余表面也可以被第二半导体层覆盖。第一半导体层可以相对较薄(例如，厚度为约3～20nm)，且相对于衬底悬置。这样，在生长过程中第一半导体层和第二半导体层中的应力可以得以弛豫，且因此可以抑制或避免在第一半导体层或第二半导体层中产生缺陷。
为了进一步降低缺陷，可以先在第一半导体层上生长一层过渡层，然后再在过渡层上生长第二半导体层。该过渡层的晶格常数可以逐渐变化(例如，通过其成分的改变)，例如从等于或接近第一半导体层的晶格常数逐渐改变为等于或接近第二半导体层的晶格常数。如上所述，过渡层可以至少部分地环绕第一半导体层的外周形成，而第二半导体层可以至少部分地环绕过渡层的外周形成。
根据本公开的实施例，第一半导体层(以及过渡层，如果存在的话)可以去除，留下第二半导体层的至少一部分用作器件的鳍。例如，可以留下第二半导体层位于第一半导体层横向两侧(在此，称作“左侧”和“右侧”)的部分，即大致垂直于衬底表面延伸的部分，充当器件的鳍。由于第二半导体层以第一半导体层为种子生长，第二半导体层的左侧部分和右侧部分分别从第一半导体 层(或者过渡层)的左侧侧壁和右侧侧壁开始生长，因此它们的晶体结构相对于它们之间的中心可以大致镜像对称。
第一半导体层可以经支撑部物理连接到衬底并因此由衬底支撑。在第一半导体层的纵向延伸方向上，第一半导体层与支撑部相连接的部分的延伸范围可以小于第一半导体层的纵向延伸长度。这样，当仅观察第一半导体层、衬底和支撑部之间的位置关系(不考虑其他层结构)时，第一半导体层类似于一种悬梁构造，支撑部类似于悬梁的锚定结构(anchor)。
支撑部可以包括沿衬底表面延伸的横向延伸部分以及沿大致垂直于衬底表面的方向延伸的竖直延伸部分，其中竖直延伸部分延伸至第一半导体层大致垂直于衬底表面的竖直侧壁上。这样，通过该支撑部，将第一半导体层物理连接到衬底上，并因此由衬底支撑。支撑部的竖直延伸部分可以在第一半导体层的相对两侧的竖直侧壁上延伸，从而夹持第一半导体层。
支撑部可以设于鳍状的第一半导体层的两侧端部之一或两端，或设于鳍状的第一半导体层的中部。
这种半导体器件例如可以如下制作。具体地，可以在衬底上形成鳍状结构。随后，当去除该鳍状结构靠近衬底的一部分(“下部”)以得到第一半导体层时，第一半导体层可以相对于衬底悬置。
为了支撑随后将悬置的第一半导体层，可以形成支撑部。这种支撑部可以如下形成。具体地，可以在形成有鳍状结构的衬底上形成支撑层，并将该支撑层构图为从衬底表面延伸至鳍状结构的表面并因此将鳍状结构与衬底在物理上连接的支撑部。支撑层的构图可以利用掩模进行。在垂直于鳍状结构纵向延伸方向的方向上，掩模在鳍状结构上方延伸超出鳍状结构的范围(这样，掩模可以遮蔽支撑层在鳍状结构两侧的衬底表面上延伸的部分，从而该部分随后可以得以保留)；而在鳍状结构的纵向延伸方向上，掩模在鳍状结构上方覆盖鳍状结构的纵向延伸长度的仅一部分(这样，掩模遮蔽鳍状结构的纵向延伸范围的仅一部分，从而该部分随后可以与支撑部相连)。掩模可以覆盖鳍状结构的一侧端部或两侧端部，或者覆盖鳍状结构的中部，得到的支撑部可以相应地位于鳍状结构的一侧端部或两侧端部或者中部。
之后，可以去除鳍状结构的下部。这样，第一半导体层相对于衬底类似于 悬梁构造，支撑部类似于悬梁的锚定结构(anchor)，将作为悬梁的第一半导体层锚定至衬底。
为了便于去除鳍状结构的下部，鳍状结构可以包括在衬底上依次形成的牺牲层和第一半导体层的叠层。例如，可以在衬底上依次形成牺牲层和第一半导体层，然后可以将第一半导体层和牺牲层构图为鳍状结构。在该构图步骤可以进行到衬底中，从而在衬底上与鳍状结构相对应的位置处可以具有突起。随后，可以选择性去除牺牲层。
由于第一半导体层悬置从而其表面露出，可以在其表面上生长(过渡层以及)第二半导体层。于是，在充分生长的情况下，第二半导体层可以覆盖第一半导体层(被支撑部)露出的所有表面。
在至少部分纵向延伸范围内，可以去除第一半导体层(以及过渡层，如果存在的话)，留下第二半导体层作为器件的鳍。由于第一半导体层(以及过渡层)被第二半导体层围绕，为便于去除第一半导体层(以及过渡层)，可以在第一半导体层背离衬底一侧(在此，称作“上侧”)将第二半导体层打开或者说切断，以露出内侧的(过渡层以及)第一半导体层。第二半导体层中的开口或者说切口的尺度足以支持随后经由其来形成栅堆叠(包括栅介质层和栅导体层以及可选的功函数调节层)。此外，还可以在靠近衬底一侧(在此，称作“下侧”)进一步将第二半导体层打开或者说切断。特别是，可以将第二半导体层在上侧以及下侧的横向延伸部分(大致平行于衬底表面延伸的部分)去除，从而在该至少部分纵向延伸范围内，第二半导体层剩下原本位于第一半导体层横向两侧(即，“左侧”和“右侧”)的部分，即大致垂直于衬底表面延伸的部分，这可以充当鳍。
此外，还可以切断第二半导体层在鳍状结构的纵向延伸方向上的端部(例如，可以将第二半导体层在过渡层或第一半导体层在纵向延伸方向上的端面上延伸的部分去除)，从而将第二半导体层分为彼此相对的两个部分。在如上所述将第二半导体层上、下两侧的横向延伸部分去除的情况下，此时剩下的第二半导体层的各部分均大致垂直于衬底表面的方向延伸，类似于常规技术中鳍的形式。
以鳍为基础，可以有多种方式来完成器件的制造。例如，可以在衬底上形 成隔离层，并在隔离层上形成与第二半导体层或者说鳍相交的栅堆叠。
本公开可以各种形式呈现，以下将描述其中一些示例。
如图1所示，提供衬底1001。该衬底1001可以是各种形式的衬底，例如但不限于体半导体材料衬底如体Si衬底等。在以下的描述中，为方便说明，以体Si衬底为例进行描述。特别是，衬底1001可以是硅单晶体，其表面可以是例如(110)晶面、(100)晶面或(112)晶面。
在衬底1001上，例如通过外延生长，依次形成牺牲层1003和第一半导体层1005。牺牲层1003可以包括与衬底1001和第一半导体层1005不同的半导体材料，如SiGe(Ge的原子百分比例如为约5～20％)，厚度为约10～100nm。第一半导体层1005可以包括合适的半导体材料，例如Si，厚度为约10～100nm。
随后，可以对如此形成的第一半导体层1005和牺牲层1003(可选地，还有衬底1001)进行构图，以形成鳍状结构。例如，这可以如下进行。
具体地，可以在第一半导体层1005上形成硬掩模层。在该示例中，硬掩膜层可以包括氧化物(例如，氧化硅)层1007和多晶Si层1009。例如，氧化物层1007的厚度为约2～10nm，多晶Si层1009的厚度为约50～120nm。在该示例中，利用图形转移技术，来将硬掩膜构图为鳍状。为此，可以在硬掩膜层上形成构图(例如，通过曝光、显影)的光刻胶PR。在此，光刻胶PR被构图沿垂直于纸面方向延伸的条状，且其宽度(图中水平方向上的维度)可以大致对应于两个鳍状结构之间的间距。
接着，如图2所示，以该光刻胶PR为掩模，对多晶Si层1009(相对于氧化层1007)进行选择性刻蚀如反应离子刻蚀(RIE)。这样，可以将多晶Si层1009构图为与光刻胶PR相对应的条状。接着，如图3(a)所示，去除光刻胶PR，并在多晶Si层1009的侧壁上形成侧墙(spacer)1011。本领域存在多种手段来形成侧墙。例如，可以通过如原子层淀积(ALD)大致共形淀积一层氮化物(例如，氮化硅)，厚度例如为约3～20nm，然后对淀积的氮化物进行选择性刻蚀如RIE(例如，沿大致垂直于衬底表面的方向进行)，去除其横向延伸部分，使得竖直延伸部分保留，以形成侧墙1011。侧墙1011覆盖Si层1009的侧壁。
图3(b)示出了图3(a)中所示结构的俯视图。注意，尽管图3(b)中未示出， 但是在条状多晶Si层1009的上下两端的侧壁上，也存在侧墙1011，从而侧墙1011绕条状多晶Si层1009的外周形成封闭图案。
为了得到鳍状的掩模，如图4(a)和4(b)(图4(a)是俯视图，4(b)是沿图4(a)中AA′线的截面图)所示，可以选择性去除多晶Si层1009(例如，通过TMAH溶液)，然后再形成构图的光刻胶1013。光刻胶1013可以遮蔽侧墙1011的中部，并露出侧墙1011上下两侧的部分。以该光刻胶1013为掩模，对侧墙1011进行选择性刻蚀如RIE，从而可以将原本为封闭图案的侧墙1011分离为两部分，如图5所示。每一部分对应于将要形成的鳍状结构，在该示例中为沿图中的竖直方向延伸的条状。
然后，如图6所示，以侧墙1011为掩模，可以依次对氧化物层1007、第一半导体层1005和牺牲层1003进行选择性刻蚀如RIE。这样，将侧墙1011的图案转移到下方的层中，得到鳍状结构。因此，第一半导体层1005的宽度(图中水平方向的维度)与侧墙1011的宽度大致相同(例如，约3～20nm)。第一半导体层1005的侧壁(图中左右两侧的侧壁)可以是(111)或(110)晶面，这些晶面易于减少生长缺陷。
在此，还可以进一步选择性刻蚀衬底1001。因此，在与鳍状结构相对应的位置处，衬底1001上可以具有突起。鳍状结构在衬底上的投影大致位于该突起的中部。由于刻蚀的特性，刻蚀后的牺牲层1003以及衬底1001的突起可以呈从上至下逐渐变大的形状。之后，可以选择性去除侧墙1011(还可以进一步选择性去除氧化物层1007)。
尽管在以上利用图形转移技术来形成鳍状结构，但是本公开不限于此。例如，可以直接在第一半导体层1005上形成鳍状的光刻胶，并以光刻胶为掩模，选择性刻蚀第一半导体层1005、牺牲层1003和衬底1001，以形成鳍状结构。或者，也可以在硬掩膜层上直接形成鳍状的光刻胶，利用光刻胶将硬掩膜构图为鳍状，并利用鳍状的硬掩膜依次选择性刻蚀第一半导体层1005、牺牲层1003和衬底1001，以形成鳍状结构。
在此，示出了两个鳍状结构。但是，本公开不限于此，例如可以形成更多或更少的鳍状结构。另外，鳍状结构的布局可以根据器件需要不同地设计。
在形成鳍状结构之后，可以形成支撑部。例如，如图7所示，可以在形成 有鳍状结构的衬底上，例如通过ALD，以大致共形的方式，淀积氧化物层1015和氮化物层1017。氧化物层1015的厚度可以为约1～10nm，氮化物层1017的厚度可以为约2～15nm。之后，如图8中的俯视图所示，可以在图7所示的结构上形成构图的光刻胶1019。该光刻胶1019被构图为覆盖鳍状结构一侧(图中下侧)的端部，并沿图中的水平方向延伸。这里需要指出的是，在图8的俯视图中，仅为方便起见，并未示出氮化物层1017随衬底上鳍状结构而起伏的形貌，以下俯视图中同样如此。
随后，如图9(a)、9(b)和9(c)(图9(a)是俯视图，图9(b)是沿图9(a)中AA′线的截面图，图9(c)是沿图9(a)中A1A1′线的截面图)所示，以光刻胶1019为掩模，例如通过RIE(相对于氧化物层1015)选择性去除氮化物层1017。这样，如图9(c)所示，氮化物层1017留在鳍状结构一侧(图9(a)中下侧)的端部，并延伸到衬底1001的表面上。这样，氮化物层1017将鳍状结构与衬底1001在物理上连接，并因此可以支撑鳍状结构(特别是在如下所述去除牺牲层1003之后)。之后，可以去除光刻胶1019。
在该实施例中，形成了氧化物层和氮化物层的叠层结构的支撑层，并将该支撑层构图为支撑部。但是，本公开不限于此。支撑层可以包括各种合适的电介质材料。在随后去除支撑部的实施例中，支撑层甚至还可以包括半导体材料或导电材料。
此外，如图10(对应于图9(c)中的截面图)所示，还可以例如通过RIE(相对于氧化物层1015)选择性去除氮化物层1017的顶端部分。但是，氮化物层1017仍有一部分留于第一半导体层1005的侧壁上，以便随后支撑第一半导体层1005。
之后，如图11(a)、11(b)和11(c)(图11(a)是俯视图，图11(b)是沿图11(a)中AA′线的截面图，图11(c)是沿图11(a)中A1A1′线的截面图)所示，可以通过例如RIE，(相对于Si材料的衬底1001和第一半导体层1005以及SiGe材料的牺牲层1003)，选择性去除氧化物层1015。如图11(a)和11(c)所示，在鳍状结构的一侧(图11(a)中下侧)端部处，氧化物层1015被氮化物层1017覆盖，并可以得以保留。然后，如图12(a)和12(b)(分别对应于图11(b)和11(c)的截面图)所示，可以通过例如湿法腐蚀，(相对于Si材料的衬底1001和第 一半导体层1005)选择性去除牺牲层1003。这样，在鳍状的第一半导体层1005和衬底1001之间形成间隔1021。
图13示出了图12所示结构的透视图。如图13所示，第一半导体层1005通过间隔1021与衬底1001隔开，大致平行于衬底表面延伸，并经支撑部1015/1017而被衬底1001支撑。例如，在衬底表面为(110)晶面时，第一半导体层1005的延伸方向可以平行于(110)晶面与(1-11)晶面的交叉线或(110)晶面与(1-1-1)晶面的交叉线或(110)晶面与(-111)晶面的交叉线，第一半导体层1005的侧面可以大致平行于(111)晶面族；或在衬底表面为(112)晶面的情况下，第一半导体层1005的延伸方向可以平行于(112)晶面与(-1-11)晶面的交叉线或(112)晶面与(11-1)晶面的交叉线，第一半导体层1005的侧面也可以大致平行于(111)晶面族。或者，第一半导体层1005的延伸方向可以对应于<110>方向，在衬底表面为(100)晶面的情况下，第一半导体层1005的侧面可以大致平行于(110)晶面。这些晶面易于减少生长缺陷。
在图13中，仅为了方便起见，仅示出了单个第一半导体层1005和相应的支撑部，且并未示出残留的氧化物层1015。
支撑部1015/1017包括在衬底1001的表面上延伸的横向延伸部分以及沿大致垂直于衬底表面的方向延伸的竖直延伸部分。在该示例中，竖直延伸部分可以包括沿衬底1011的突起的表面延伸的部分、沿牺牲层1003(已经去除)的表面延伸的部分以及沿第一半导体层1005的竖直侧壁延伸的部分。这样，支撑部1015/1017将第一半导体层1005物理连接到衬底1001，从而可以支撑第一半导体层1005。支撑部1015/1017可以在第一半导体层1005的相对两侧(图中左右两侧)的竖直侧壁上延伸，从而夹持第一半导体层，以便更为稳定地支撑第一半导体层1005。当然，在该示例中，支撑部1015/1017还在第一半导体层1005面向读者一侧的端部侧壁上延伸。在第一半导体层1005的纵向延伸方向上，第一半导体层1005与支撑部1015/1017相连接部分的延伸范围小于第一半导体层1005的纵向延伸长度。在此，所谓“纵向延伸方向”是指第一半导体层1005的长度方向(图12中垂直于纸面的方向)，与之后形成的沟道区的长度方向基本上一致，也即，从源区到漏区的方向或者反之亦然。这样，第一半导体层1005相对于衬底1001，形成类似于悬梁的构造，该悬梁通过支 撑部1015/1017锚定到衬底1001。
在以上示例中，支撑部除了氮化物层1017之外，还包括氧化物层1015，但是本公开不限于此。例如，在以上结合图7描述的操作中，可以不形成氧化物层1015，而直接形成氮化物层1017。这样，同样可以按以上结合图8-12描述的方式进行后继操作。当然，支撑部也可以是其他电介质材料或叠层结构。
此外，在以上示例中，对于两个鳍状结构，支撑部均形成于下侧的端部。但是本公开不限于此。例如，对于一个鳍状结构，支撑部可以如上所述形成于下侧端部；而对于另一鳍状结构，支撑部可以如下所述形成于其他位置例如上侧端部。
另外，用来构图支撑部的掩模1019(参见图8)不限于上述形状。一般地，在垂直于鳍状结构纵向延伸方向的方向上，掩模在鳍状结构上方可以延伸超出鳍状结构的范围。这样，掩模可以覆盖氮化物层1017在衬底1001(突起之外的)表面上延伸的部分，这部分随后可以保留(充当支撑部的底座)。另一方面，在鳍状结构的纵向延伸方向上，掩模在鳍状结构上方可以覆盖鳍状结构的纵向延伸长度的仅一部分。这样，可以形成类似悬梁-锚定结构的配置。
然后，如图14(a)和14(b)(分别对应于图12(a)和12(b)的截面图)所示，可以在第一半导体层1005上生长第二半导体层1025。在此，第二半导体层1025可以包括高迁移率材料，例如Ge、SiGe或III-V族化合物半导体如InSb、InGaSb、InAs、GaAs、InGaAs、AlSb、InP、三族氮化物等，厚度可以为约5～15nm。在化合物半导体如SiGe的情况下，其成分(例如，Ge原子百分比)可以渐变，使得例如从与第一半导体层1005(在此，Si)的晶格常数相差较少变为与第一半导体层1005的晶格常数相差较大，以便抑制位错或缺陷的生成。第二半导体层1025的侧面可以与衬底中的(111)晶面族或(110)晶面族大致平行。
此外，如上所述，可以先在第一半导体层1005上生长过渡层1023，然后再在过渡层1023上生长第二半导体层1025。过渡层1023可以包括各种合适的半导体材料，例如Ge、SiGe或III-V族化合物半导体如InSb、InGaSb、InAs、GaAs、InGaAs、AlSb、InP、三族氮化物等，厚度可以为约1nm-20nm。过渡层1023可以包括与第二半导体层1025相同或不同的材料。
这种生长可以是选择性生长，从而过渡层1023第二半导体层1025在半导 体材料的第一半导体层1005(以及衬底1001)的表面上生长，第二半导体层1025在半导体材料的过渡层1023的表面上生长。可以控制过渡层1023和第二半导体层1025的生长，使得其没有完全填满第一半导体层1005与衬底1001之间的间隔1021。由于第一半导体层1005的悬置构造，在生长过程中第一半导体层1005、过渡层1023和第二半导体层1025中的应力可以得以弛豫。这样，可以抑制或避免第一半导体层1005、过渡层1023或第二半导体层1025中产生缺陷，这有助于改善器件性能(例如，降低关态漏电流以及提升开态电流)。
在该示例中，除了被支撑部1015/1017覆盖的表面之外，第一半导体层1005的其余表面均被过渡层和第二半导体层覆盖。当然，衬底1001的表面上也可以生长有过渡层1023和第二半导体层1025。
在该示例中，沿第一半导体层的纵向延伸方向，除了支撑部所占据的纵向延伸范围之外，在其余纵向延伸范围处，过渡层1023完全包封第一半导体层1005的外周，且第二半导体层1025完全包封过渡层1023的外周。这样，在与第一半导体层1005的纵向延伸方向垂直的截面(即，图14(a)和14(b)所示的截面)上，过渡层1023形成闭合图案(该示例中为矩形)，且第二半导体层1025形成闭合图案(该示例中为矩形)。当然，该闭合图案由第一半导体层1005在该截面处的图案所定，可以为其他形状例如多边形。
第二半导体层1023随后可以充当器件的鳍。根据本公开的实施例，可以去除过渡层1023和第一半导体层1005，留下第二半导体层1023的至少一部分(例如，其侧边如图14(a)中所示左、右两侧的侧边部分)作为鳍。
为此，可以如图15(对应于图14(a)的截面图)所示，可以在图14所示的结构上例如通过淀积形成电介质层1027，并对该电介质层1027回蚀，直至露出第二半导体层1025。在回蚀之前，可以对电介质层1027进行平坦化处理例如化学机械抛光(CMP)。或者，平坦化处理可以第二半导体层1025为终点，这样无需再进一步回蚀。例如，电介质层1027可以包括氧化物(例如，氧化硅)。
然后，如图16所示，可以去除第一半导体层1005上方的层结构。例如，可以通过RIE(可以选择能够同时可使过渡层1023和第二半导体层1025的刻 蚀配方)，回蚀过渡层1023和第二半导体层1025，直至露出第一半导体层1005。这样，在电介质层1027中，由于这种回蚀，而形成了凹槽。可以在这种凹槽的侧壁上，形成侧墙形式的掩模层1029。例如，掩模层1029可以通过大致共形淀积一层氮化物层(厚度例如为约3～15nm)，然后对该氮化物层进行RIE以去除其横向延伸部分而留下其纵向延伸部分，从而在凹槽的内壁上形成侧墙1029。在此，侧墙1029可以覆盖第二半导体层1025的至少一部分，而不覆盖第一半导体层1005和过渡层1023。掩模层1029的这种形成方式使得掩模层1029的侧壁可以自对准于第二半导体层1025的侧壁。
接着，如图17所示，可以回蚀(例如，通过湿法腐蚀或者蒸气刻蚀)电介质层1027。在此，可以将电介质层1027回蚀为顶面接近但高于第二半导体层的底面。例如，电介质层1027的顶面在第二电介质层的底面与过渡层1023的底面之间。这是为了降低电介质层1027的顶面上的高度差(例如，位于第二半导体层1025下方的部分的顶面与其余部分的顶面之间的高度差)，以便随后可以获得顶面大致在同一高度的隔离层。
然后，如图18所示，可以利用掩模层1029，对半导体层(包括第一半导体层1005、过渡层1023和第二半导体层1025)进行选择性刻蚀如RIE。这样，第二半导体层1025的上下两侧被完全打开。然后，还可以进一步回蚀如RIE电介质层1027，以使其低于第二半导体层1025的底面。由于如上所述电介质层1027的顶面上的高度差已经降低，因此进一步回蚀后电介质层1027的顶面可以大致位于相同高度(除了在第二半导体层1025下方的部分之外，该部分可以与第二半导体层1025的底面相接)。该电介质层1027可以充当隔离层。然后，可以去除掩模层1029。
如图18所示，在衬底上(更具体地，在隔离层1027上)，形成了鳍1025。鳍1025大致垂直于衬底的表面延伸。
由于第二半导体层1025是绕第一半导体层形成的，因此在俯视图中此时的鳍1025仍然可以是闭合形状，如图19所示。请注意，在图19中，仅为方便起见，并未示出支撑部的残留。可以将这种闭合形状的鳍切断，以形成分离的鳍。例如，如图20所示，可以利用掩模(例如，光刻胶)1031遮蔽第二半导体层1025的中部，并露出其端部(图中上下两侧的端部)。然后，可以对第 二半导体层1025进行选择性刻蚀如RIE。这样，第二半导体层1025暴露在外的端部被去除，从而得到了分离的鳍，如图21(a)所示。对于左侧的一对鳍，它们沿着相同的第一半导体层1005的侧壁生长，因此它们彼此大致平行延伸。如上所述，由于它们是从相同的第一半导体层1005生长的，因此它们可以相对于它们之间的中线在晶体结构上成镜像对称。右侧的一对鳍同样如此。
在此需要指出的是，可以不切断第二半导体层1025，而是仍然如图20所述保留其闭合形状。这种情况下，基于左侧一对鳍形成的器件的源/漏区彼此连接，基于右侧一对鳍形成的器件的源/漏区彼此连接。
在通过上述处理形成鳍1025之后，可以形成与鳍相交的栅堆叠，并形成最终的半导体器件(例如，FinFET)。如图21(a)和21(b)(图21(a)是俯视图，图21(b)是沿图21(a)中AA′线的截面图)所示，可以在隔离层1027上形成与鳍1025相交的栅堆叠。例如，可以依次形成栅介质层1033和栅导体层1035。例如，栅介质层1033可以包括厚度为约0.3～2nm的氧化物(例如，SiO2或GeO2)，栅导体层1035可以包括多晶硅；或者，栅介质层1033可以包括厚度为约1～4nm的高K栅介质如HfO2或Al2O3，栅导体层1035可以包括金属栅导体。在高K栅介质/金属栅导体的情况下，在栅介质层1033和栅导体层1035之间还可以形成功函数调节层(未示出)，例如TiN、Al、Ti、TiAlC，厚度为约1～3nm。
在该示例中，仅为图示方便起见，将各鳍分别对应的器件的栅堆叠示出为相同配置并一体延伸，但是本公开不限于此。器件可以具有不同的栅堆叠配置(例如，n型器件的栅堆叠可以不同于p型器件的栅堆叠)，并且各自的栅堆叠可以根据器件布局而进行构图。
在形成栅堆叠之后，例如可以栅堆叠为掩模，进行晕圈(halo)注入和延伸区(extension)注入。接下来，可以在栅堆叠的侧壁上形成栅侧墙。然后，可以栅堆叠及栅侧墙为掩模，进行源/漏(S/D)注入。随后，可以通过退火，激活注入的离子，以形成源/漏区。
本领域技术人员知道多种方式来以鳍为基础制作器件，在此对于形成鳍之后的工艺不再赘述。
这样，就得到了该实施例的半导体器件。如图21(a)和21(b)所示，该半导 体器件可以包括与衬底1001相隔开的至少两个鳍1025。在这些鳍中，至少一对相邻的鳍(例如，图中左侧的一对鳍或者右侧的一对鳍)可以沿大致平行于衬底表面的方向排列，彼此间隔开大致平行延伸，且相对于它们之间的中线在晶体结构上是实质上镜像对称的。另外，该对鳍可以关于大致垂直于衬底表面且穿过衬底上相应突起中部的直线对称。此外，该器件还包括隔离层1027以及在隔离层1027上形成的与鳍1025相交的栅堆叠(1033、1035)。
在该实施例中，并未有意去除支撑部。但是，本公开不限于此。支撑部也可以被选择性(至少部分)去除(例如，在形成栅堆叠之后)，其去除而导致的空间随后例如可以被其他电介质层填充。
在以上实施例中，仅在第一半导体层的一侧端部形成了支撑部，但是本公开不限于此，也可以在第一半导体层的两侧端部均形成支撑部。例如，代替以上结合图8描述的操作，如图22所示，将光刻胶1019构图为覆盖鳍状结构两侧(图中上下两侧)的端部，并沿图中的水平方向延伸。之后的操作可以按上述相同的方式进行。这种情况下，可以得到如图23所示的悬置结构。具体地，如图23所示，第一半导体层1005相对于衬底1001悬置，且其两端通过支撑部1017被衬底1001支撑。
当然，支撑部也不限于形成在第一半导体层的端部，而是可以形成在其纵向延伸范围中的任意位置处。例如，代替以上结合图8描述的操作，如图24所示，将光刻胶1019构图为覆盖鳍状结构的中部，并沿图中的水平方向延伸。之后的操作可以按上述相同的方式进行。这种情况下，可以得到如图25所示的悬置结构。具体地，如图25所示，第一半导体层1005相对于衬底1001悬置，且其中部通过支撑部1017被衬底1001支撑。
根据本公开实施例的半导体器件可以应用于各种电子设备。例如，通过集成多个这样的半导体器件以及其他器件(例如，其他形式的晶体管等)，可以形成集成电路(IC)，并由此构建电子设备。因此，本公开还提供了一种包括上述半导体器件的电子设备。电子设备还可以包括与集成电路配合的显示屏幕以及与集成电路配合的无线收发器等部件。这种电子设备例如智能电话、平板电脑(PC)、个人数字助手(PDA)等。
根据本公开的实施例，还提供了一种芯片系统(SoC)的制造方法。该方 法可以包括上述制造半导体器件的方法。具体地，可以在芯片上集成多种器件，其中至少一些是根据本公开的方法制造的。
在以上的描述中，对于各层的构图、刻蚀等技术细节并没有做出详细的说明。但是本领域技术人员应当理解，可以通过各种技术手段，来形成所需形状的层、区域等。另外，为了形成同一结构，本领域技术人员还可以设计出与以上描述的方法并不完全相同的方法。另外，尽管在以上分别描述了各实施例，但是这并不意味着各个实施例中的措施不能有利地结合使用。
以上对本公开的实施例进行了描述。但是，这些实施例仅仅是为了说明的目的，而并非为了限制本公开的范围。本公开的范围由所附权利要求及其等价物限定。不脱离本公开的范围，本领域技术人员可以做出多种替代和修改，这些替代和修改都应落在本公开的范围之内。

Claims (26)

  1. 一种制造半导体器件的方法，包括：
    在衬底上形成鳍状结构；
    在形成有鳍状结构的衬底上形成支撑层，并将该支撑质层构图为从衬底表面延伸至鳍状结构的表面并因此将鳍状结构与衬底在物理上连接的支撑部；
    去除鳍状结构靠近衬底的一部分，以形成与衬底分离的第一半导体层；
    以第一半导体层为种子层，生长第二半导体层；
    在至少部分纵向延伸范围内，去除第一半导体层，并在第一半导体层背离衬底一侧以及靠近衬底一侧将第二半导体层切断，切断的第二半导体层作为该半导体器件的鳍。
  2. 根据权利要求1所述的方法，还包括：切断第二半导体层在鳍状结构的纵向延伸方向上的端部，从而将第二半导体层分为彼此相对的两个部分。
  3. 根据权利要求2所述的方法，其中，第二半导体层的所述两部分均沿大致垂直于衬底表面的方向延伸。
  4. 根据权利要求1所述的方法，其中，去除第一半导体层和切断第二半导体层的步骤包括：
    在衬底上形成电介质层，对该电介质层进行回蚀直至露出第二半导体层；
    对第二半导体层进行回蚀，以露出第一半导体层；
    在第二半导体层上形成掩模层，以遮蔽第二半导体层的至少一部分而露出第一半导体层；以及
    利用该掩模层，选择性刻蚀第一半导体层和第二半导体层。
  5. 根据权利要求1所述的方法，还包括：
    在第一半导体层上生长过渡层，其中，第二半导体层在该过渡层上生长，以及
    其中，去除第一半导体层和切断第二半导体层的步骤还包括：在所述至少部分纵向延伸范围内，进一步去除过渡层。
  6. 根据权利要求5所述的方法，其中，去除第一半导体层和切断第二半导体层的步骤包括：
    在衬底上形成电介质层，对该电介质层进行回蚀直至露出第二半导体层；
    对第二半导体层和过渡层进行回蚀，以露出第一半导体层；
    在第二半导体层上形成掩模层，以遮蔽第二半导体层的至少一部分而露出过渡层和第一半导体层；以及
    利用该掩模层，选择性刻蚀第一半导体层、过渡层和第二半导体层。
  7. 根据权利要求4或6所述的方法，其中，形成掩模层包括：
    在由于回蚀第二半导体层或者回蚀第二半导体层和过渡层而在电介质层中导致的凹槽的内壁上形成侧墙形式的掩模层。
  8. 根据权利要求4或6所述的方法，其中，在形成掩模层之后且在选择性刻蚀之前，该方法还包括：
    回蚀电介质层，但其顶面仍高于第二半导体层的底面。
  9. 根据权利要求8所述的方法，其中，将电介质层回蚀为其顶面低于与第二半导体层相接触的第一半导体层或过渡层的底面。
  10. 根据权利要求8所述的方法，其中，在选择性刻蚀之后，还包括：
    进一步回蚀电介质层，使其顶面低于第二半导体层的底面。
  11. 根据权利要求10所述的方法，还包括：
    在进一步回蚀后的电介质层上形成与鳍相交的栅堆叠。
  12. 根据权利要求1所述的方法，其中，鳍状结构包括在衬底上依次形成的牺牲层和第一半导体层的叠层。
  13. 根据权利要求12所述的方法，其中，去除鳍状结构靠近衬底的一部分包括：选择性去除牺牲层。
  14. 根据权利要求1所述的方法，其中，构图支撑部包括：
    形成掩模以遮蔽一部分支撑层，其中，在垂直于鳍状结构纵向延伸方向的方向上，掩模在鳍状结构上方延伸超出鳍状结构的范围；而在鳍状结构的纵向延伸方向上，掩模在鳍状结构上方覆盖鳍状结构的纵向延伸长度的仅一部分；
    选择性去除未被遮蔽的支撑层部分；以及
    去除掩模。
  15. 根据权利要求14所述的方法，其中，在去除掩模后，该方法还包括：
    选择性去除支撑部的顶端部分，以露出鳍状结构的顶面以及部分侧壁。
  16. 根据权利要求14所述的方法，其中，形成掩模包括：
    使掩模覆盖鳍状结构的一侧端部或两侧端部，或者覆盖鳍状结构的中部。
  17. 根据权利要求1所述的方法，其中，形成支撑层包括：
    以大致共形的方式，依次淀积氧化物层和氮化物层。
  18. 根据权利要求1所述的方法，其中，第一半导体层的侧面是(111)晶面或(110)晶面。
  19. 一种半导体器件，包括：
    衬底；
    与衬底相隔开的至少两个鳍，其中，所述至少两个鳍中至少一对相邻的鳍沿大致平行于衬底表面的方向排列，彼此间隔开大致平行延伸，且相对于它们之间的中线在晶体结构上是实质上镜像对称的；
    在衬底上形成的隔离层，隔离层露出各鳍；以及
    在隔离层上形成的与各鳍相交的栅堆叠。
  20. 根据权利要求19所述的半导体器件，其中，隔离层在鳍下方与鳍相接，在其余位置处顶面低于鳍的底面。
  21. 根据权利要求19所述的半导体器件，其中，鳍的侧壁是(111)晶面或(110)晶面。
  22. 根据权利要求19所述的半导体器件，其中，衬底上具有突起，所述一对相邻的鳍关于大致垂直于衬底表面且穿过该突起中部的直线对称。
  23. 根据权利要求19所述的半导体器件，其中，衬底上形成有与鳍相同材料的半导体层，且隔离层形成于该半导体层之上。
  24. 根据权利要求23所述的半导体器件，其中，衬底上形成有过渡半导体层，其中所述半导体层形成于该过渡半导体层之上。
  25. 一种电子设备，包括由如权利要求19～24中任一项所述的半导体器件形成的集成电路。
  26. 根据权利要求25所述的电子设备，还包括：与所述集成电路配合的显示器以及与所述集成电路配合的无线收发器。
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