WO2017210926A1 - Tft背板的制作方法及tft背板 - Google Patents

Tft背板的制作方法及tft背板 Download PDF

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Publication number
WO2017210926A1
WO2017210926A1 PCT/CN2016/087326 CN2016087326W WO2017210926A1 WO 2017210926 A1 WO2017210926 A1 WO 2017210926A1 CN 2016087326 W CN2016087326 W CN 2016087326W WO 2017210926 A1 WO2017210926 A1 WO 2017210926A1
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Prior art keywords
layer
gate
drain
polysilicon
source
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English (en)
French (fr)
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张晓星
周星宇
徐源竣
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US15/120,748 priority Critical patent/US20170352711A1/en
Publication of WO2017210926A1 publication Critical patent/WO2017210926A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method for fabricating a TFT backplane and a TFT backplane.
  • An OLED (Organic Light-Emitting Diode) display also known as an organic electroluminescent display, is an emerging flat panel display device because of its simple preparation process, low cost, low power consumption, and high luminance.
  • the working temperature has wide adaptability, light volume, fast response, easy to realize color display and large screen display, easy to realize integration with integrated circuit driver, easy to realize flexible display, and the like, and thus has broad application prospects.
  • OLED can be divided into two types: passive matrix OLED (PMOLED) and active matrix OLED (AMOLED), namely direct addressing and thin film transistor matrix addressing.
  • PMOLED passive matrix OLED
  • AMOLED active matrix OLED
  • the AMOLED has pixels arranged in an array, belongs to an active display type, has high luminous efficiency, and is generally used as a high-definition large-sized display device.
  • Thin Film Transistor is the main driving component in AMOLED display devices, which is directly related to the development direction of high-performance flat panel display devices.
  • the thin film transistor has various structures, and the material of the active layer of the thin film transistor for preparing the corresponding structure is also various.
  • Low temperature poly-silicon (LTPS) material is one of the preferred ones, due to the low temperature polysilicon atom. Regular arrangement, high carrier mobility, for current-driven active matrix driven organic electroluminescent display devices, low temperature polysilicon thin film transistors can better meet the drive current requirements.
  • LTPS is usually crystallized by Excimer Laser Annealing (ELA) technology, which is irradiated onto the surface of amorphous silicon by a laser pulse to dissolve and recrystallize.
  • ELA Excimer Laser Annealing
  • the ELA crystallization technique cannot effectively control the uniformity of the crystal lattice and the crystallographic direction of the crystal lattice, so the crystallization condition is uneven in the distribution of the entire substrate, resulting in a non-uniform long-range display screen and uneven brightness ( Mura) appears.
  • Oxide Semiconductor is also a good TFT active layer fabrication material, which has the characteristics of fast switching and low leakage current, but its electron mobility is slightly poor, making it slightly inferior to driving OLED.
  • An object of the present invention is to provide a method for fabricating a TFT backplane, which can improve the switching speed of the switching TFT and reduce its leakage current, and at the same time improve the electron mobility and current output uniformity of the driving TFT.
  • Another object of the present invention is to provide a TFT backplane, wherein the switching TFT can realize rapid switching and low leakage current, and the driving TFT has high electron mobility and current output uniformity, which is favorable for improving luminescence of the OLED device. Uniformity.
  • the present invention first provides a method for fabricating a TFT backplane, including the following steps:
  • Step 1 providing a substrate, forming a first gate and a second gate spaced apart on the substrate, and depositing a gate on the first gate, the second gate, and the substrate a very insulating layer, depositing an amorphous silicon film on the gate insulating layer;
  • Step 2 performing boron ion doping on the amorphous silicon film, and then performing rapid thermal annealing treatment on the amorphous silicon film to convert the amorphous silicon film into a low-temperature polysilicon film, wherein the low-temperature polysilicon film is The doping concentration of boron ions gradually decreases from top to bottom;
  • Step 3 performing patterning on the low temperature polysilicon film to obtain a polysilicon layer corresponding to the second gate;
  • Step 4 forming an oxide semiconductor layer corresponding to the upper surface of the first gate on the gate insulating layer;
  • Step 5 forming a metal layer on the oxide semiconductor layer, the polysilicon layer, and the gate insulating layer, and patterning the metal layer and the polysilicon layer by using a halftone mask process to obtain a layer a first source and a first drain on the oxide semiconductor layer and the gate insulating layer and respectively contacting the two sides of the oxide semiconductor layer, and are disposed on the polysilicon layer and the gate insulating layer and respectively a second source and a second drain in contact with both sides of the polysilicon layer, and a recess corresponding to a region between the second source and the second drain on the polysilicon layer, so that a portion of the polysilicon layer under the recess forms a channel region, and regions of the polysilicon layer on both sides of the channel region respectively form a source contact region and a drain contact region;
  • Step 6 Form a passivation layer on the first source, the first drain, the second source, the second drain, the oxide semiconductor layer, the polysilicon layer, and the gate insulating layer, in the passivation Forming a flat layer on the layer;
  • Step 7 forming a connection conductive layer and a pixel electrode on the flat layer, wherein the connection conductive layer is in contact with the first drain and the second gate via a first via hole and a third via hole, respectively Thereby connecting the first drain and the second gate, the pixel electrode being in contact with the second drain via the second via;
  • the annealing temperature of the rapid thermal annealing treatment is 600 ° C to 700 ° C, and the annealing holding time is 10 min to 30 min.
  • the step 5 includes:
  • Step 51 forming a metal layer on the oxide semiconductor layer, the polysilicon layer, and the gate insulating layer, forming a photoresist layer on the metal layer, and exposing and developing the photoresist layer by using a halftone mask. Obtaining a first photoresist segment, a second photoresist segment, and a third photoresist segment;
  • the first photoresist segment is provided with a recess corresponding to the upper portion of the oxide semiconductor layer, and the spacing region between the second photoresist segment and the third photoresist segment corresponds to the upper portion of the polysilicon layer.
  • Step 52 etching the first photoresist segment, the second photoresist segment, the third photoresist segment, the metal layer, and the polysilicon layer by using a dry etching process to obtain a first source, a first drain, and a second source and a second drain simultaneously forming a recess on the polysilicon layer, wherein a portion of the polysilicon layer below the recess forms a channel region, and the polysilicon layer is located on both sides of the channel region The regions form a source contact region and a drain contact region, respectively; after that, the remaining photoresist layer is stripped.
  • the etching process used in the dry etching process in the step 52 includes one or more of sulfur hexafluoride, carbon tetrafluoride, oxygen, and chlorine.
  • the method further includes: Step 8, forming an organic light emitting layer in the fourth via hole, thereby obtaining an OLED substrate.
  • the material of the oxide semiconductor layer includes one or more of indium gallium zinc oxide and indium zinc oxide.
  • the present invention also provides a TFT backplane, including: a substrate substrate, spaced apart first and second gates disposed on the substrate, and the first gate and the second gate And a gate insulating layer on the base substrate, an oxide semiconductor layer and a polysilicon layer respectively disposed on the gate insulating layer and corresponding to the first gate and the second gate, and the oxide layer a first source and a first drain on the semiconductor layer and the gate insulating layer and respectively contacting the two sides of the oxide semiconductor layer, and are disposed on the polysilicon layer and the gate insulating layer and respectively respectively a second source and a second drain that are in contact with each other on the two sides of the layer, and are disposed on the first source, the first drain, the second source, the second drain, the oxide semiconductor layer, the polysilicon layer, and the gate a passivation layer on the pole insulating layer, a flat layer provided on the passivation layer, a connecting conductive layer and a pixel electrode provided on the flat layer, and Connecting the conductive layer
  • the flat layer and the passivation layer are provided with a first via corresponding to the first drain and a second via corresponding to the second drain, the planarization layer, the passivation layer, and the gate a third through hole corresponding to the upper portion of the second gate is disposed on the insulating layer;
  • the connecting conductive layer is respectively in contact with the first drain and the second gate via the first via and the third via, thereby connecting the first drain and the second gate, the pixel
  • the electrode is in contact with the second drain via the second via hole
  • the pixel defining layer is provided with a fourth through hole corresponding to the pixel electrode
  • the polysilicon layer is doped with boron ions, and the doping concentration of boron ions in the polysilicon layer gradually decreases from top to bottom, and the polysilicon layer corresponds to the second source and the second drain
  • the inter-region is provided with a recess, and a portion of the polysilicon layer below the recess forms a channel region, and regions on both sides of the polysilicon layer on the polysilicon layer respectively form a source contact region and a drain contact region.
  • the organic light emitting layer disposed in the fourth via hole is further included to form an OLED substrate.
  • the material of the oxide semiconductor layer includes one or more of indium gallium zinc oxide and indium zinc oxide.
  • a buffer layer disposed between the base substrate and the first gate and the second gate is further included.
  • the invention also provides a method for fabricating a TFT backplane, comprising the following steps:
  • Step 1 providing a substrate, forming a first gate and a second gate spaced apart on the substrate, and depositing a gate on the first gate, the second gate, and the substrate a very insulating layer, depositing an amorphous silicon film on the gate insulating layer;
  • Step 2 performing boron ion doping on the amorphous silicon film, and then performing rapid thermal annealing treatment on the amorphous silicon film to convert the amorphous silicon film into a low-temperature polysilicon film, wherein the low-temperature polysilicon film is The doping concentration of boron ions gradually decreases from top to bottom;
  • Step 3 performing patterning on the low temperature polysilicon film to obtain a polysilicon layer corresponding to the second gate;
  • Step 4 forming an oxide semiconductor layer corresponding to the upper surface of the first gate on the gate insulating layer;
  • Step 5 forming a metal layer on the oxide semiconductor layer, the polysilicon layer, and the gate insulating layer, and patterning the metal layer and the polysilicon layer by using a halftone mask process to obtain a layer a first source and a first drain on the oxide semiconductor layer and the gate insulating layer and respectively contacting the two sides of the oxide semiconductor layer, and are disposed on the polysilicon layer and the gate insulating layer and respectively a second source and a second drain in contact with both sides of the polysilicon layer, and a recess corresponding to a region between the second source and the second drain on the polysilicon layer, so that a portion of the polysilicon layer below the recess forms a channel region, the polysilicon layer
  • the regions on both sides of the channel region respectively form a source contact region and a drain contact region;
  • Step 6 Form a passivation layer on the first source, the first drain, the second source, the second drain, the oxide semiconductor layer, the polysilicon layer, and the gate insulating layer, in the passivation Forming a flat layer on the layer;
  • Step 7 forming a connection conductive layer and a pixel electrode on the flat layer, wherein the connection conductive layer is in contact with the first drain and the second gate via a first via hole and a third via hole, respectively Thereby connecting the first drain and the second gate, the pixel electrode being in contact with the second drain via the second via;
  • the annealing temperature of the rapid thermal annealing treatment is 600 ° C ⁇ 700 ° C, and the annealing heat preservation time is 10 min - 30 min;
  • Step 8 Form an organic light-emitting layer in the fourth via hole to obtain an OLED substrate.
  • the present invention provides a TFT backplane manufacturing method and a TFT backplane, which are fabricated by using an oxide semiconductor to form a switching TFT, which utilizes an oxide semiconductor switch quickly and has a lower leakage current to improve the switching.
  • the switching speed of the TFT reduces the leakage current; the TFT is fabricated by using polysilicon, and the polysilicon has high electron mobility and uniformity of the crystal, thereby improving the electron mobility and current output uniformity of the driving TFT, which is beneficial to improve
  • the luminescence of OLED devices is uniform.
  • FIG. 1 is a flow chart of a method of fabricating a TFT backplane of the present invention
  • step 1 is a schematic diagram of step 1 of a method for fabricating a TFT backplane according to the present invention
  • step 2 is a schematic diagram of step 2 of a method for fabricating a TFT backplane according to the present invention
  • step 3 is a schematic diagram of step 3 of a method for fabricating a TFT backplane according to the present invention.
  • step 4 is a schematic diagram of step 4 of a method for fabricating a TFT backplane according to the present invention.
  • 6-7 are schematic diagrams showing the fifth step of the method for fabricating the TFT backplane of the present invention.
  • step 6 is a schematic diagram of step 6 of a method for fabricating a TFT backplane according to the present invention.
  • FIG. 9 is a schematic view showing the step 7 of the method for fabricating the TFT backplane of the present invention and a schematic structural view of the TFT backplane of the present invention.
  • the present invention first provides a method for fabricating a TFT backplane, including the following steps:
  • Step 1 as shown in FIG. 2, a substrate 10 is provided, and a first gate 21 and a second gate 22 are formed on the substrate 10, and the first gate 21 and the second gate are formed.
  • a gate insulating layer 30 is deposited on the second gate 22 and the base substrate 10, and an amorphous silicon film 31 is deposited on the gate insulating layer 30.
  • the base substrate 10 is a glass substrate.
  • the step 1 further includes: cleaning and baking the base substrate 10 before depositing other structural layers on the base substrate 10.
  • the step 1 further includes: depositing a buffer layer 20 on the base substrate 10 before forming the first gate electrode 21 and the second gate electrode 22 on the base substrate 10, the first The gate electrode 21 and the second gate electrode 22 are formed over the buffer layer 20 , and the gate insulating layer 30 is deposited over the first gate electrode 21 , the second gate electrode 22 , and the buffer layer 20 .
  • the buffer layer 20 includes one or a combination of two of a silicon nitride (SiN x ) layer and a silicon oxide (SiO x ) layer. Specifically, the thicknesses of the silicon nitride layer and the silicon oxide layer are respectively
  • the first gate electrode 21 and the second gate electrode 22 are a composite layer formed by two molybdenum layers and an aluminum layer between the two molybdenum layers, a single layer of molybdenum layer, or a single layer of aluminum layer.
  • the thicknesses of the first gate 21 and the second gate 22 are respectively
  • the gate insulating layer 30 includes one or a combination of two of a silicon nitride layer and a silicon oxide layer.
  • Step 2 As shown in FIG. 3, the amorphous silicon film 31 is doped with boron ions, and then the amorphous silicon film 31 is subjected to rapid thermal annealing treatment to convert the amorphous silicon film 31 into a low temperature.
  • Polysilicon film 32, the doping concentration of boron ions in the low temperature polysilicon film 32 is from top to bottom Gradually decrease.
  • the invention adopts the boron ion-induced solid phase crystallization method to prepare the low-temperature polysilicon film, and the low-temperature polysilicon film can have good uniformity compared with the conventional excimer laser annealing method, and is favorable for improving the current output uniformity of the driving TFT. To improve the uniformity of illumination of OLED devices.
  • the annealing temperature of the rapid thermal annealing treatment is 600 ° C to 700 ° C, and the annealing holding time is 10 min to 30 min.
  • Step 3 As shown in FIG. 4, the low temperature polysilicon film 32 is patterned to obtain a polysilicon layer 40 corresponding to the upper portion of the second gate 22.
  • Step 4 as shown in FIG. 5, an oxide semiconductor layer 50 corresponding to the upper portion of the first gate electrode 21 is formed on the gate insulating layer 30.
  • the material of the oxide semiconductor layer 50 includes one or more of indium gallium zinc oxide (IGZO) and indium zinc oxide (IZO).
  • IGZO indium gallium zinc oxide
  • IZO indium zinc oxide
  • Step 5 as shown in FIG. 6-7, a metal layer 51 is formed on the oxide semiconductor layer 50, the polysilicon layer 40, and the gate insulating layer 30, and the metal layer 51 is processed by a halftone mask process. And the polysilicon layer 40 is patterned to obtain a first source 71 and a first region which are disposed on the oxide semiconductor layer 50 and the gate insulating layer 30 and are respectively in contact with both sides of the oxide semiconductor layer 50.
  • a recess 41 is formed on a portion of the 40 between the second source 73 and the second drain 74 such that a portion of the polysilicon layer 40 below the recess 41 forms a channel region 42.
  • the regions on the layer 40 on either side of the channel region 42 form a source contact region 43 and a drain contact region 44, respectively.
  • the concentration of boron ions above the region is removed.
  • the high portion retains a portion having a lower boron ion concentration, the portion having a lower boron ion concentration corresponding to the P-type lightly doped region, thereby forming the channel region 42; and the polysilicon layer 40 being located at the channel region 42
  • the side region still retains a portion having a higher concentration of the upper boron ion, corresponding to the P-type heavily doped region, thereby forming the source contact region 43 and the drain contact region 44, the second source 73 and the second drain.
  • the polysilicon layer 40 and the second gate 22 constitute a P-type thin film transistor.
  • the step 5 includes:
  • Step 51 as shown in FIG. 6, a metal layer 51 is formed on the oxide semiconductor layer 50, the polysilicon layer 40, and the gate insulating layer 30, and a photoresist layer 60 is formed on the metal layer 51.
  • the photomask layer 60 is exposed and developed to obtain a first photoresist segment 61, a second photoresist segment 62, and a third photoresist segment 63;
  • the first photoresist segment 61 is provided with a recess 613 corresponding to the upper surface of the oxide semiconductor layer 50.
  • the spacing region between the second photoresist segment 62 and the third photoresist segment 63 corresponds to the polysilicon layer 40. Above.
  • Step 52 etching the first photoresist segment 61, the second photoresist segment 62, the third photoresist segment 63, the metal layer 51, and the polysilicon layer 40 by using a dry etching process.
  • a first source 71, a first drain 72, a second source 73, and a second drain 74 are obtained, and a recess 41 is formed on the polysilicon layer 40, and the polysilicon layer 40 is located below the recess 41.
  • a portion of the polysilicon layer 40 on both sides of the channel region 42 is formed with a source contact region 43 and a drain contact region 44, respectively; the remaining photoresist layer 60 is then stripped.
  • the etching gas used in the dry etching process in the step 52 includes one of sulfur hexafluoride (SF 6 ), carbon tetrafluoride (CF 4 ), oxygen (O 2 ), and chlorine (Cl 2 ). kind or more.
  • the first source 71, the first drain 72, the second source 73, and the second drain 74 are a composite layer formed by two molybdenum layers and an aluminum layer between the two molybdenum layers.
  • the thicknesses of the first source 71, the first drain 72, the second source 73, and the second drain 74 are respectively
  • the first gate 21, the oxide semiconductor layer 50, the first source 71, and the first drain 72 constitute a switching TFT
  • the second gate 22 the polysilicon layer 40
  • the second source 73 And the second drain 74 constitutes a driving TFT.
  • Step 6 as shown in FIG. 8, the first source 71, the first drain 72, the second source 73, the second drain 74, the oxide semiconductor layer 50, the polysilicon layer 40, and the gate insulating layer Forming a passivation layer 80 on the layer 30, forming a flat layer 90 on the passivation layer 80;
  • the flat layer 90, the passivation layer 80, and the gate insulating layer 30 are patterned, and a first via 91 corresponding to the first drain hole 72 is formed on the flat layer 90 and the passivation layer 80. And corresponding to the second via hole 92 above the second drain 74, forming a third via corresponding to the upper portion of the second gate 22 on the flat layer 90, the passivation layer 80, and the gate insulating layer 30. 93.
  • the passivation layer 80 includes one or a combination of two of a silicon nitride layer and a silicon oxide layer.
  • the flat layer 90 is an organic material.
  • Step 7 as shown in FIG. 9, a connection conductive layer 110 and a pixel electrode 120 are formed on the flat layer 90, and the connection conductive layer 110 is respectively connected to the first via hole 91 and the third through hole 93.
  • a drain 72 and a second gate 22 are in contact with each other to connect the first drain 72 and the second gate 22, and the pixel electrode 120 is coupled to the second drain 74 via the second via 92 contact;
  • the material connecting the conductive layer 110 and the pixel electrode 120 is a transparent conductive metal oxide, preferably indium tin oxide (ITO).
  • ITO indium tin oxide
  • the pixel defining layer 130 is an organic material.
  • the present invention further includes: Step 8, forming an organic light-emitting layer 140 in the fourth via hole 134, thereby obtaining an OLED substrate.
  • the manufacturing method of the TFT backplane is to fabricate a switching TFT by using an oxide semiconductor, and the oxide semiconductor switch is quickly and has a lower leakage current, thereby improving the switching speed of the switching TFT and reducing the leakage current thereof;
  • the driving TFT uses polysilicon to have high electron mobility and uniformity of crystal grains, and improves electron mobility and current output uniformity of the driving TFT, thereby improving the uniformity of light emission of the OLED device.
  • the present invention further provides a TFT backplane, including: a substrate substrate 10 , a first gate 21 and a first gate electrode spaced apart from each other on the substrate substrate 10 a second gate 22, a gate insulating layer 30 disposed on the first gate 21, the second gate 22, and the base substrate 10, disposed on the gate insulating layer 30 and corresponding to the first
  • the oxide semiconductor layer 50 and the polysilicon layer 40 of the gate electrode 21 and the second gate electrode 22 are disposed on the oxide semiconductor layer 50 and the gate insulating layer 30 and are respectively in contact with both sides of the oxide semiconductor layer 50.
  • passivation provided on the first source 71, the first drain 72, the second source 73, the second drain 74, the oxide semiconductor layer 50, the polysilicon layer 40, and the gate insulating layer 30 a layer 80, a flat layer 90 disposed on the passivation layer 80, a connection conductive layer 110 disposed on the flat layer 90, and a pixel electrode 120 disposed on the connection conductive layer 110
  • the flat layer 90 and the passivation layer 80 are provided with a first through hole 91 corresponding to the upper portion of the first drain 72 and a second through hole 92 corresponding to the upper portion of the second drain 74.
  • the passivation layer 80 and the gate insulating layer 30 are provided with a third through hole 93 corresponding to the upper portion of the second gate 22;
  • connection conductive layer 110 is in contact with the first drain 72 and the second gate 22 via the first via 91 and the third via 93, respectively, thereby connecting the first drain 72 and the second
  • the gate electrode 22 is in contact with the second drain electrode 74 via the second via hole 92;
  • the pixel defining layer 130 is provided with a fourth through hole 134 corresponding to the pixel electrode 120;
  • the polysilicon layer 40 is doped with boron ions, and the doping concentration of boron ions in the polysilicon layer 40 gradually decreases from top to bottom, and the polysilicon layer 40 corresponds to the second source 73 and the A recess 41 is formed in a region between the two drains 74, and the polysilicon layer 40 is located under the recess 41. Portions of the square form a channel region 42 on which regions on both sides of the channel region 42 form a source contact region 43 and a drain contact region 44, respectively.
  • the TFT backplane further includes an organic light emitting layer 140 disposed in the fourth through hole 134 to form an OLED substrate.
  • the TFT backplane further includes a buffer layer 20 disposed between the base substrate 10 and the first gate 21 and the second gate 22.
  • the base substrate 10 is a glass substrate.
  • the buffer layer 20 includes one or a combination of two of a silicon nitride layer and a silicon oxide layer. Specifically, the thicknesses of the silicon nitride layer and the silicon oxide layer are respectively
  • the first gate 21 and the second gate 22 are a composite layer formed by two molybdenum layers and an aluminum layer between the two molybdenum layers, a single layer of molybdenum layer, or a single layer of aluminum layer.
  • the thicknesses of the first gate 21 and the second gate 22 are respectively
  • the gate insulating layer 30 includes one or a combination of two of a silicon nitride layer and a silicon oxide layer.
  • the material of the oxide semiconductor layer 50 includes one or more of indium gallium zinc oxide and indium zinc oxide.
  • the first source 71, the first drain 72, the second source 73, and the second drain 74 are a composite layer formed by two molybdenum layers and an aluminum layer between the two molybdenum layers.
  • the thicknesses of the first source 71, the first drain 72, the second source 73, and the second drain 74 are respectively
  • the passivation layer 80 includes one or a combination of two of a silicon nitride layer and a silicon oxide layer.
  • the flat layer 90 is an organic material.
  • the material connecting the conductive layer 110 and the pixel electrode 120 is a transparent conductive metal oxide, preferably indium tin oxide.
  • the pixel defining layer 130 is an organic material.
  • the TFT backplane is formed by using an oxide semiconductor to form a switching TFT, and the oxide semiconductor switch is quickly and has a lower leakage current, thereby improving the switching speed of the switching TFT and reducing the leakage current thereof; by using polysilicon to fabricate the driving TFT,
  • the use of polysilicon has high electron mobility and uniformity of crystal grains, and improves the electron mobility and current output uniformity of the driving TFT, which is beneficial to improving the uniformity of illumination of the OLED device.
  • the present invention provides a TFT backplane manufacturing method and a TFT backplane, which are fabricated by using an oxide semiconductor layer to form a switching TFT, which utilizes an oxide semiconductor switch quickly and has a lower leakage current to improve the switching TFT. Switching speed and reducing its leakage current;
  • the crystalline silicon layer is used to fabricate the driving TFT, and the polysilicon has high electron mobility and uniformity of the crystal grains, and the electron mobility and current output uniformity of the driving TFT are improved, which is favorable for improving the uniformity of light emission of the OLED device.

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Abstract

本发明提供一种TFT背板的制作方法及TFT背板，通过采用氧化物半导体来制作开关TFT，利用氧化物半导体开关迅速和具有较低漏电流的优势，提高开关TFT的开关速度并降低其漏电流；通过采用多晶硅来制作驱动TFT，利用多晶硅具有较高的电子迁移率和晶粒均一的特点，提高驱动TFT的电子迁移率和电流输出均一性，有利于提高OLED器件的发光均一程度。

Description

TFT背板的制作方法及TFT背板 技术领域
本发明涉及显示技术领域，尤其涉及一种TFT背板的制作方法及TFT背板。
背景技术
OLED(Organic Light-Emitting Diode，有机发光二极管)显示器，也称为有机电致发光显示器，是一种新兴的平板显示装置，由于其具有制备工艺简单、成本低、功耗低、发光亮度高、工作温度适应范围广、体积轻薄、响应速度快，而且易于实现彩色显示和大屏幕显示、易于实现和集成电路驱动器相匹配、易于实现柔性显示等优点，因而具有广阔的应用前景。
OLED按照驱动方式可以分为无源矩阵型OLED(Passive Matrix OLED，PMOLED)和有源矩阵型OLED(Active Matrix OLED，AMOLED)两大类，即直接寻址和薄膜晶体管矩阵寻址两类。其中，AMOLED具有呈阵列式排布的像素，属于主动显示类型，发光效能高，通常用作高清晰度的大尺寸显示装置。
薄膜晶体管(Thin Film Transistor，简称TFT)是AMOLED显示装置中的主要驱动元件，直接关系到高性能平板显示装置的发展方向。薄膜晶体管具有多种结构，制备相应结构的薄膜晶体管的有源层的材料也具有多种，低温多晶硅(Low Temperature Poly-silicon，简称LTPS)材料是其中较为优选的一种，由于低温多晶硅的原子规则排列，载流子迁移率高，对于电流驱动式的有源矩阵驱动式有机电致发光显示装置而言，低温多晶硅薄膜晶体管可以更好的满足驱动电流要求。
目前，LTPS通常由准分子激光退火(Excimer Laser Annealing，ELA)技术结晶，利用激光的瞬间脉冲照射到非晶硅表面，使其溶化并重新结晶。但是ELA结晶技术对于晶格的均一性和晶格结晶方向不能做到有效控制，所以结晶状况在整个基板的分布上很不均匀，造成显示效果画面的长程不均一，有亮度不均匀的现象(mura)出现。
氧化物半导体(Oxide Semiconductor)也是较好的TFT有源层制作材料，其具有开关迅速和低漏电流的特点，但是其电子迁移率稍差，使其在驱动OLED上稍显逊色。
发明内容
本发明的目的在于提供一种TFT背板的制作方法，可提高开关TFT的开关速度并降低其漏电流，同时提高驱动TFT的电子迁移率和电流输出均一性。
本发明的目的还在于提供一种TFT背板，其开关TFT可实现开关迅速并具有较低漏电流，其驱动TFT具有较高的电子迁移率和电流输出均一性，有利于提高OLED器件的发光均一程度。
为实现上述目的，本发明首先提供一种TFT背板的制作方法，包括如下步骤：
步骤1、提供一衬底基板，在所述衬底基板上形成间隔设置的第一栅极与第二栅极，在所述第一栅极、第二栅极、及衬底基板上沉积栅极绝缘层，在所述栅极绝缘层上沉积非晶硅薄膜；
步骤2、对所述非晶硅薄膜进行硼离子掺杂，然后对所述非晶硅薄膜进行快速热退火处理，使所述非晶硅薄膜结晶转化为低温多晶硅薄膜，所述低温多晶硅薄膜中硼离子的掺杂浓度从上到下逐渐减小；
步骤3、对所述低温多晶硅薄膜进行图形化处理，得到对应于第二栅极上方的多晶硅层；
步骤4、在所述栅极绝缘层上形成对应于第一栅极上方的氧化物半导体层；
步骤5、在所述氧化物半导体层、多晶硅层、及栅极绝缘层上形成一金属层，采用一道半色调光罩制程对所述金属层、及多晶硅层进行图形化处理，得到设于所述氧化物半导体层与栅极绝缘层上且分别与所述氧化物半导体层两侧相接触的第一源极和第一漏极、以及设于所述多晶硅层与栅极绝缘层上且分别与所述多晶硅层两侧相接触的第二源极和第二漏极，同时在所述多晶硅层上对应于所述第二源极与第二漏极之间的区域形成一凹槽，使得所述多晶硅层上位于凹槽下方的部分形成沟道区，所述多晶硅层上位于沟道区两侧的区域分别形成源极接触区与漏极接触区；
步骤6、在所述第一源极、第一漏极、第二源极、第二漏极、氧化物半导体层、多晶硅层、及栅极绝缘层上形成钝化层，在所述钝化层上形成平坦层；
对所述平坦层、钝化层、及栅极绝缘层进行图形化处理，在所述平坦层与钝化层上形成对应于第一漏极上方的第一通孔、及对应于第二漏极上方的第二通孔，在所述平坦层、钝化层、及栅极绝缘层上形成对应于第二栅极上方的第三通孔；
步骤7、在所述平坦层上形成连接导电层与像素电极，所述连接导电层经由第一通孔、及第三通孔分别与所述第一漏极、及第二栅极相接触，从而连接所述第一漏极与第二栅极，所述像素电极经由第二通孔与所述第二漏极相接触；
在所述连接导电层、像素电极、及平坦层上形成像素定义层，对所述像素定义层进行图形化处理，得到对应于所述像素电极上方的第四通孔。
所述步骤2中，所述快速热退火处理的退火温度为600℃～700℃，退火保温时间为10min-30min。
所述步骤5包括：
步骤51、在所述氧化物半导体层、多晶硅层、及栅极绝缘层上形成一金属层，在所述金属层上形成光阻层，采用一半色调光罩对光阻层进行曝光显影处理，得到第一光阻段、第二光阻段、及第三光阻段；
所述第一光阻段上设有一对应于氧化物半导体层上方的一凹槽，所述第二光阻段与第三光阻段之间的间隔区域对应于多晶硅层上方。
步骤52、采用一道干蚀刻制程对所述第一光阻段、第二光阻段、第三光阻段、金属层、及多晶硅层进行蚀刻处理，得到第一源极、第一漏极、第二源极、及第二漏极，同时在所述多晶硅层上形成凹槽，所述多晶硅层上位于凹槽下方的部分形成沟道区，所述多晶硅层上位于沟道区两侧的区域分别形成源极接触区与漏极接触区；之后剥离剩余的光阻层。
所述步骤52中的干蚀刻制程采用的蚀刻气体包括六氟化硫、四氟化碳、氧气、及氯气中的一种或多种。
还包括：步骤8、在所述第四通孔内形成有机发光层，从而得到一OLED基板。
所述氧化物半导体层的材料包括铟镓锌氧化物、及氧化铟锌中的一种或多种。
本发明还提供一种TFT背板，包括：衬底基板、设于所述衬底基板上的互相间隔的第一栅极与第二栅极、设于所述第一栅极、第二栅极、及衬底基板上的栅极绝缘层、设于所述栅极绝缘层上且分别对应于第一栅极与第二栅极的氧化物半导体层与多晶硅层、设于所述氧化物半导体层与栅极绝缘层上且分别与所述氧化物半导体层两侧相接触的第一源极与第一漏极、设于所述多晶硅层与栅极绝缘层上且分别与所述多晶硅层两侧相接触的第二源极与第二漏极、设于所述第一源极、第一漏极、第二源极、第二漏极、氧化物半导体层、多晶硅层、及栅极绝缘层上的钝化层、设于所述钝化层上的平坦层、设于所述平坦层上的连接导电层与像素电极、设于所 述连接导电层、像素电极、及平坦层上的像素定义层；
所述平坦层与钝化层上设有对应于第一漏极上方的第一通孔、及对应于第二漏极上方的第二通孔，所述平坦层、钝化层、及栅极绝缘层上设有对应于第二栅极上方的第三通孔；
所述连接导电层经由第一通孔、及第三通孔分别与所述第一漏极、及第二栅极相接触，从而连接所述第一漏极与第二栅极，所述像素电极经由第二通孔与所述第二漏极相接触；
所述像素定义层上设有对应于所述像素电极上方的第四通孔；
所述多晶硅层中掺杂有硼离子，且所述多晶硅层中硼离子的掺杂浓度从上到下逐渐减小，所述多晶硅层上对应于所述第二源极与第二漏极之间的区域设有一凹槽，所述多晶硅层上位于凹槽下方的部分形成沟道区，所述多晶硅层上位于沟道区两侧的区域分别形成源极接触区与漏极接触区。
还包括设于所述第四通孔内的有机发光层，从而形成一OLED基板。
所述氧化物半导体层的材料包括铟镓锌氧化物、及氧化铟锌中的一种或多种。
还包括设于所述衬底基板与第一栅极、及第二栅极之间的缓冲层。
本发明还提供一种TFT背板的制作方法，包括如下步骤：
步骤1、提供一衬底基板，在所述衬底基板上形成间隔设置的第一栅极与第二栅极，在所述第一栅极、第二栅极、及衬底基板上沉积栅极绝缘层，在所述栅极绝缘层上沉积非晶硅薄膜；
步骤2、对所述非晶硅薄膜进行硼离子掺杂，然后对所述非晶硅薄膜进行快速热退火处理，使所述非晶硅薄膜结晶转化为低温多晶硅薄膜，所述低温多晶硅薄膜中硼离子的掺杂浓度从上到下逐渐减小；
步骤3、对所述低温多晶硅薄膜进行图形化处理，得到对应于第二栅极上方的多晶硅层；
步骤4、在所述栅极绝缘层上形成对应于第一栅极上方的氧化物半导体层；
步骤5、在所述氧化物半导体层、多晶硅层、及栅极绝缘层上形成一金属层，采用一道半色调光罩制程对所述金属层、及多晶硅层进行图形化处理，得到设于所述氧化物半导体层与栅极绝缘层上且分别与所述氧化物半导体层两侧相接触的第一源极和第一漏极、以及设于所述多晶硅层与栅极绝缘层上且分别与所述多晶硅层两侧相接触的第二源极和第二漏极，同时在所述多晶硅层上对应于所述第二源极与第二漏极之间的区域形成一凹槽，使得所述多晶硅层上位于凹槽下方的部分形成沟道区，所述多晶硅层 上位于沟道区两侧的区域分别形成源极接触区与漏极接触区；
步骤6、在所述第一源极、第一漏极、第二源极、第二漏极、氧化物半导体层、多晶硅层、及栅极绝缘层上形成钝化层，在所述钝化层上形成平坦层；
对所述平坦层、钝化层、及栅极绝缘层进行图形化处理，在所述平坦层与钝化层上形成对应于第一漏极上方的第一通孔、及对应于第二漏极上方的第二通孔，在所述平坦层、钝化层、及栅极绝缘层上形成对应于第二栅极上方的第三通孔；
步骤7、在所述平坦层上形成连接导电层与像素电极，所述连接导电层经由第一通孔、及第三通孔分别与所述第一漏极、及第二栅极相接触，从而连接所述第一漏极与第二栅极，所述像素电极经由第二通孔与所述第二漏极相接触；
在所述连接导电层、像素电极、及平坦层上形成像素定义层，对所述像素定义层进行图形化处理，得到对应于所述像素电极上方的第四通孔；
其中，所述步骤2中，所述快速热退火处理的退火温度为600℃～700℃，退火保温时间为10min-30min；
步骤8、在所述第四通孔内形成有机发光层，从而得到一OLED基板。
本发明的有益效果：本发明提供的一种TFT背板的制作方法及TFT背板，通过采用氧化物半导体来制作开关TFT，利用氧化物半导体开关迅速和具有较低漏电流的优势，提高开关TFT的开关速度并降低其漏电流；通过采用多晶硅来制作驱动TFT，利用多晶硅具有较高的电子迁移率和晶粒均一的特点，提高驱动TFT的电子迁移率和电流输出均一性，有利于提高OLED器件的发光均一程度。
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其它有益效果显而易见。
附图中，
图1为本发明的TFT背板的制作方法的流程图；
图2为本发明的TFT背板的制作方法的步骤1的示意图；
图3为本发明的TFT背板的制作方法的步骤2的示意图；
图4为本发明的TFT背板的制作方法的步骤3的示意图；
图5为本发明的TFT背板的制作方法的步骤4的示意图；
图6-7为本发明的TFT背板的制作方法的步骤5的示意图；
图8为本发明的TFT背板的制作方法的步骤6的示意图；
图9为本发明的TFT背板的制作方法的步骤7的示意图暨本发明的TFT背板的结构示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图1，本发明首先提供一种TFT背板的制作方法，包括如下步骤：
步骤1、如图2所示，提供一衬底基板10，在所述衬底基板10上形成间隔设置的第一栅极21与第二栅极22，在所述第一栅极21、第二栅极22、及衬底基板10上沉积栅极绝缘层30，在所述栅极绝缘层30上沉积非晶硅薄膜31。
具体的，所述衬底基板10为玻璃基板。
具体的，所述步骤1还包括：在所述衬底基板10上沉积其它结构层之前，对所述衬底基板10进行清洗和烘烤。
优选的，所述步骤1还包括：在所述衬底基板10上形成第一栅极21、及第二栅极22之前，在所述衬底基板10上沉积缓冲层20，所述第一栅极21、及第二栅极22形成于所述缓冲层20上方，所述栅极绝缘层30沉积于第一栅极21、第二栅极22、及缓冲层20上方。
具体的，所述缓冲层20包括氮化硅(SiNx)层、及氧化硅(SiOx)层中的一种或两种的组合。具体的，所述氮化硅层、及氧化硅层的厚度分别为
Figure PCTCN2016087326-appb-000001
具体的，所述第一栅极21、及第二栅极22为由两钼层及位于两钼层之间的一铝层形成的复合层、单层钼层、或单层铝层。具体的，所述第一栅极21、及第二栅极22的厚度分别为
Figure PCTCN2016087326-appb-000002
具体的，所述栅极绝缘层30包括氮化硅层、及氧化硅层中的一种或两种的组合。
步骤2、如图3所示，对所述非晶硅薄膜31进行硼离子掺杂，然后对所述非晶硅薄膜31进行快速热退火处理，使所述非晶硅薄膜31结晶转化为低温多晶硅薄膜32，所述低温多晶硅薄膜32中硼离子的掺杂浓度从上到 下逐渐减小。
本发明通过采用硼离子诱导固相晶化法来制备低温多晶硅薄膜，相对于传统的准分子激光退火方法，可以使低温多晶硅薄膜具有较好的均一性，有利于提高驱动TFT的电流输出均一性，提高OLED器件的发光均一程度。
具体的，所述步骤2中，所述快速热退火处理的退火温度为600℃～700℃，退火保温时间为10min-30min。
步骤3、如图4所示，对所述低温多晶硅薄膜32进行图形化处理，得到对应于第二栅极22上方的多晶硅层40。
步骤4、如图5所示，在所述栅极绝缘层30上形成对应于第一栅极21上方的氧化物半导体层50。
具体的，所述氧化物半导体层50的材料包括铟镓锌氧化物(IGZO)、及氧化铟锌(IZO)中的一种或多种。
步骤5、如图6-7所示，在所述氧化物半导体层50、多晶硅层40、及栅极绝缘层30上形成一金属层51，采用一道半色调光罩制程对所述金属层51、及多晶硅层40进行图形化处理，得到设于所述氧化物半导体层50与栅极绝缘层30上且分别与所述氧化物半导体层50两侧相接触的第一源极71和第一漏极72、以及设于所述多晶硅层40与栅极绝缘层30上且分别与所述多晶硅层40两侧相接触的第二源极73和第二漏极74，同时在所述多晶硅层40上对应于所述第二源极73与第二漏极74之间的区域形成一凹槽41，使得所述多晶硅层40上位于凹槽41下方的部分形成沟道区42，所述多晶硅层40上位于沟道区42两侧的区域分别形成源极接触区43与漏极接触区44。
具体的，所述步骤5中，通过在所述多晶硅层40上对应于所述第二源极73与第二漏极74之间的区域形成一凹槽41，去除该区域上方硼离子浓度较高的部分，保留下方硼离子浓度较低的部分，该硼离子浓度较低的部分相当于P型轻掺杂区，从而形成沟道区42；所述多晶硅层40上位于沟道区42两侧的区域依然保留有上层硼离子浓度较高的部分，相当于P型重掺杂区，从而形成源极接触区43与漏极接触区44，所述第二源极73、第二漏极74、多晶硅层40、及第二栅极22构成一P型薄膜晶体管。
具体的，所述步骤5包括：
步骤51、如图6所示，在所述氧化物半导体层50、多晶硅层40、及栅极绝缘层30上形成一金属层51，在所述金属层51上形成光阻层60，采用一半色调光罩对光阻层60进行曝光显影处理，得到第一光阻段61、第二光阻段62、及第三光阻段63；
所述第一光阻段61上设有一对应于氧化物半导体层50上方的一凹槽613，所述第二光阻段62与第三光阻段63之间的间隔区域对应于多晶硅层40上方。
步骤52、如图7所示，采用一道干蚀刻制程对所述第一光阻段61、第二光阻段62、第三光阻段63、金属层51、及多晶硅层40进行蚀刻处理，得到第一源极71、第一漏极72、第二源极73、及第二漏极74，同时在所述多晶硅层40上形成凹槽41，所述多晶硅层40上位于凹槽41下方的部分形成沟道区42，所述多晶硅层40上位于沟道区42两侧的区域分别形成源极接触区43与漏极接触区44；之后剥离剩余的光阻层60。
具体的，所述步骤52中的干蚀刻制程采用的蚀刻气体包括六氟化硫(SF6)、四氟化碳(CF4)、氧气(O2)、及氯气(Cl2)中的一种或多种。
具体的，所述第一源极71、第一漏极72、第二源极73、及第二漏极74为由两钼层及位于两钼层之间的一铝层形成的复合层、单层钼层、或单层铝层。具体的，所述第一源极71、第一漏极72、第二源极73、及第二漏极74的厚度分别为
Figure PCTCN2016087326-appb-000003
具体的，所述第一栅极21、氧化物半导体层50、第一源极71、及第一漏极72构成开关TFT，所述第二栅极22、多晶硅层40、第二源极73、及第二漏极74构成驱动TFT。
步骤6、如图8所示，在所述第一源极71、第一漏极72、第二源极73、第二漏极74、氧化物半导体层50、多晶硅层40、及栅极绝缘层30上形成钝化层80，在所述钝化层80上形成平坦层90；
对所述平坦层90、钝化层80、及栅极绝缘层30进行图形化处理，在所述平坦层90与钝化层80上形成对应于第一漏极72上方的第一通孔91、及对应于第二漏极74上方的第二通孔92，在所述平坦层90、钝化层80、及栅极绝缘层30上形成对应于第二栅极22上方的第三通孔93。
具体的，所述钝化层80包括氮化硅层、及氧化硅层中的一种或两种的组合。
具体的，所述平坦层90为有机材料。
步骤7、如图9所示，在所述平坦层90上形成连接导电层110与像素电极120，所述连接导电层110经由第一通孔91、及第三通孔93分别与所述第一漏极72、及第二栅极22相接触，从而连接所述第一漏极72与第二栅极22，所述像素电极120经由第二通孔92与所述第二漏极74相接触；
在所述连接导电层110、像素电极120、及平坦层90上形成像素定义层130，对所述像素定义层130进行图形化处理，得到对应于所述像素电极 120上方的第四通孔134。
具体的，所述连接导电层110与像素电极120的材料均为透明导电金属氧化物，优选为氧化铟锡(ITO)。
具体的，所述像素定义层130为有机材料。
具体的，本发明还包括：步骤8、在所述第四通孔134内形成有机发光层140，从而得到一OLED基板。
上述TFT背板的制作方法，通过采用氧化物半导体来制作开关TFT，利用氧化物半导体开关迅速和具有较低漏电流的优势，提高开关TFT的开关速度并降低其漏电流；通过采用多晶硅来制作驱动TFT，利用多晶硅具有较高的电子迁移率和晶粒均一的特点，提高驱动TFT的电子迁移率和电流输出均一性，有利于提高OLED器件的发光均一程度。
请参阅图9，基于上述TFT背板的制作方法，本发明还提供一种TFT背板，包括：衬底基板10、设于所述衬底基板10上互相间隔的第一栅极21与第二栅极22、设于所述第一栅极21、第二栅极22、及衬底基板10上的栅极绝缘层30、设于所述栅极绝缘层30上且分别对应于第一栅极21与第二栅极22的氧化物半导体层50与多晶硅层40、设于所述氧化物半导体层50与栅极绝缘层30上且分别与所述氧化物半导体层50两侧相接触的第一源极71与第一漏极72、设于所述多晶硅层40与栅极绝缘层30上且分别与所述多晶硅层40两侧相接触的第二源极73与第二漏极74、设于所述第一源极71、第一漏极72、第二源极73、第二漏极74、氧化物半导体层50、多晶硅层40、及栅极绝缘层30上的钝化层80、设于所述钝化层80上的平坦层90、设于所述平坦层90上的连接导电层110与像素电极120、设于所述连接导电层110、像素电极120、及平坦层90上的像素定义层130；
所述平坦层90与钝化层80上设有对应于第一漏极72上方的第一通孔91、及对应于第二漏极74上方的第二通孔92，所述平坦层90、钝化层80、及栅极绝缘层30上设有对应于第二栅极22上方的第三通孔93；
所述连接导电层110经由第一通孔91、及第三通孔93分别与所述第一漏极72、及第二栅极22相接触，从而连接所述第一漏极72与第二栅极22，所述像素电极120经由第二通孔92与所述第二漏极74相接触；
所述像素定义层130上设有对应于所述像素电极120上方的第四通孔134；
所述多晶硅层40中掺杂有硼离子，且所述多晶硅层40中硼离子的掺杂浓度从上到下逐渐减小，所述多晶硅层40上对应于所述第二源极73与第二漏极74之间的区域设有一凹槽41，所述多晶硅层40上位于凹槽41下 方的部分形成沟道区42，所述多晶硅层40上位于沟道区42两侧的区域分别形成源极接触区43与漏极接触区44。
具体的，所述TFT背板还包括设于所述第四通孔134内的有机发光层140，从而形成一OLED基板。
优选的，所述TFT背板还包括设于所述衬底基板10与第一栅极21、及第二栅极22之间的缓冲层20。
具体的，所述衬底基板10为玻璃基板。
具体的，所述缓冲层20包括氮化硅层、及氧化硅层中的一种或两种的组合。具体的，所述氮化硅层、及氧化硅层的厚度分别为
Figure PCTCN2016087326-appb-000004
优选的，所述第一栅极21、第二栅极22为由两钼层及位于两钼层之间的一铝层形成的复合层、单层钼层、或单层铝层。具体的，所述第一栅极21、第二栅极22的厚度分别为
Figure PCTCN2016087326-appb-000005
具体的，所述栅极绝缘层30包括氮化硅层、及氧化硅层中的一种或两种的组合。
具体的，所述氧化物半导体层50的材料包括铟镓锌氧化物、及氧化铟锌中的一种或多种。
具体的，所述第一源极71、第一漏极72、第二源极73、及第二漏极74为由两钼层及位于两钼层之间的一铝层形成的复合层、单层钼层、或单层铝层。具体的，所述第一源极71、第一漏极72、第二源极73、及第二漏极74的厚度分别为
Figure PCTCN2016087326-appb-000006
具体的，所述钝化层80包括氮化硅层、及氧化硅层中的一种或两种的组合。
具体的，所述平坦层90为有机材料。
具体的，所述连接导电层110与像素电极120的材料均为透明导电金属氧化物，优选为氧化铟锡。
具体的，所述像素定义层130为有机材料。
上述TFT背板，通过采用氧化物半导体来制作开关TFT，利用氧化物半导体开关迅速和具有较低漏电流的优势，提高开关TFT的开关速度并降低其漏电流；通过采用多晶硅来制作驱动TFT，利用多晶硅具有较高的电子迁移率和晶粒均一的特点，提高驱动TFT的电子迁移率和电流输出均一性，有利于提高OLED器件的发光均一程度。
综上所述，本发明提供一种TFT背板的制作方法及TFT背板，通过采用氧化物半导体层来制作开关TFT，利用氧化物半导体开关迅速和具有较低漏电流的优势，提高开关TFT的开关速度并降低其漏电流；通过采用多 晶硅层来制作驱动TFT，利用多晶硅具有较高的电子迁移率和晶粒均一的特点，提高驱动TFT的电子迁移率和电流输出均一性，有利于提高OLED器件的发光均一程度。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (14)

  1. 一种TFT背板的制作方法，包括如下步骤：
    步骤1、提供一衬底基板，在所述衬底基板上形成间隔设置的第一栅极与第二栅极，在所述第一栅极、第二栅极、及衬底基板上沉积栅极绝缘层，在所述栅极绝缘层上沉积非晶硅薄膜；
    步骤2、对所述非晶硅薄膜进行硼离子掺杂，然后对所述非晶硅薄膜进行快速热退火处理，使所述非晶硅薄膜结晶转化为低温多晶硅薄膜，所述低温多晶硅薄膜中硼离子的掺杂浓度从上到下逐渐减小；
    步骤3、对所述低温多晶硅薄膜进行图形化处理，得到对应于第二栅极上方的多晶硅层；
    步骤4、在所述栅极绝缘层上形成对应于第一栅极上方的氧化物半导体层；
    步骤5、在所述氧化物半导体层、多晶硅层、及栅极绝缘层上形成一金属层，采用一道半色调光罩制程对所述金属层、及多晶硅层进行图形化处理，得到设于所述氧化物半导体层与栅极绝缘层上且分别与所述氧化物半导体层两侧相接触的第一源极和第一漏极、以及设于所述多晶硅层与栅极绝缘层上且分别与所述多晶硅层两侧相接触的第二源极和第二漏极，同时在所述多晶硅层上对应于所述第二源极与第二漏极之间的区域形成一凹槽，使得所述多晶硅层上位于凹槽下方的部分形成沟道区，所述多晶硅层上位于沟道区两侧的区域分别形成源极接触区与漏极接触区；
    步骤6、在所述第一源极、第一漏极、第二源极、第二漏极、氧化物半导体层、多晶硅层、及栅极绝缘层上形成钝化层，在所述钝化层上形成平坦层；
    对所述平坦层、钝化层、及栅极绝缘层进行图形化处理，在所述平坦层与钝化层上形成对应于第一漏极上方的第一通孔、及对应于第二漏极上方的第二通孔，在所述平坦层、钝化层、及栅极绝缘层上形成对应于第二栅极上方的第三通孔；
    步骤7、在所述平坦层上形成连接导电层与像素电极，所述连接导电层经由第一通孔、及第三通孔分别与所述第一漏极、及第二栅极相接触，从而连接所述第一漏极与第二栅极，所述像素电极经由第二通孔与所述第二漏极相接触；
    在所述连接导电层、像素电极、及平坦层上形成像素定义层，对所述 像素定义层进行图形化处理，得到对应于所述像素电极上方的第四通孔。
  2. 如权利要求1所述的TFT背板的制作方法，其中，所述步骤2中，所述快速热退火处理的退火温度为600℃～700℃，退火保温时间为10min-30min。
  3. 如权利要求1所述的TFT背板的制作方法，其中，所述步骤5包括：
    步骤51、在所述氧化物半导体层、多晶硅层、及栅极绝缘层上形成一金属层，在所述金属层上形成光阻层，采用一半色调光罩对光阻层进行曝光显影处理，得到第一光阻段、第二光阻段、及第三光阻段；
    所述第一光阻段上设有一对应于氧化物半导体层上方的一凹槽，所述第二光阻段与第三光阻段之间的间隔区域对应于多晶硅层上方；
    步骤52、采用一道干蚀刻制程对所述第一光阻段、第二光阻段、第三光阻段、金属层、及多晶硅层进行蚀刻处理，得到第一源极、第一漏极、第二源极、及第二漏极，同时在所述多晶硅层上形成凹槽，所述多晶硅层上位于凹槽下方的部分形成沟道区，所述多晶硅层上位于沟道区两侧的区域分别形成源极接触区与漏极接触区；之后剥离剩余的光阻层。
  4. 如权利要求3所述的TFT背板的制作方法，其中，所述步骤52中的干蚀刻制程采用的蚀刻气体包括六氟化硫、四氟化碳、氧气、及氯气中的一种或多种。
  5. 如权利要求1所述的TFT背板的制作方法，还包括：步骤8、在所述第四通孔内形成有机发光层，从而得到一OLED基板。
  6. 如权利要求1所述的TFT背板的制作方法，其中，所述氧化物半导体层的材料包括铟镓锌氧化物、及氧化铟锌中的一种或多种。
  7. 一种TFT背板，包括：衬底基板、设于所述衬底基板上互相间隔的第一栅极与第二栅极、设于所述第一栅极、第二栅极、及衬底基板上的栅极绝缘层、设于所述栅极绝缘层上且分别对应于第一栅极与第二栅极的氧化物半导体层与多晶硅层、设于所述氧化物半导体层与栅极绝缘层上且分别与所述氧化物半导体层两侧相接触的第一源极与第一漏极、设于所述多晶硅层与栅极绝缘层上且分别与所述多晶硅层两侧相接触的第二源极与第二漏极、设于所述第一源极、第一漏极、第二源极、第二漏极、氧化物半导体层、多晶硅层、及栅极绝缘层上的钝化层、设于所述钝化层上的平坦层、设于所述平坦层上的连接导电层与像素电极、设于所述连接导电层、像素电极、及平坦层上的像素定义层；
    所述平坦层与钝化层上设有对应于第一漏极上方的第一通孔、及对应于第二漏极上方的第二通孔，所述平坦层、钝化层、及栅极绝缘层上设有 对应于第二栅极上方的第三通孔；
    所述连接导电层经由第一通孔、及第三通孔分别与所述第一漏极、及第二栅极相接触，从而连接所述第一漏极与第二栅极，所述像素电极经由第二通孔与所述第二漏极相接触；
    所述像素定义层上设有对应于所述像素电极上方的第四通孔；
    所述多晶硅层中掺杂有硼离子，且所述多晶硅层中硼离子的掺杂浓度从上到下逐渐减小，所述多晶硅层上对应于所述第二源极与第二漏极之间的区域设有一凹槽，所述多晶硅层上位于凹槽下方的部分形成沟道区，所述多晶硅层上位于沟道区两侧的区域分别形成源极接触区与漏极接触区。
  8. 如权利要求7所述的TFT背板，还包括设于所述第四通孔内的有机发光层，从而形成一OLED基板。
  9. 如权利要求7所述的TFT背板，其中，所述氧化物半导体层的材料包括铟镓锌氧化物、及氧化铟锌中的一种或多种。
  10. 如权利要求7所述的TFT背板，还包括设于所述衬底基板与第一栅极、及第二栅极之间的缓冲层。
  11. 一种TFT背板的制作方法，包括如下步骤：
    步骤1、提供一衬底基板，在所述衬底基板上形成间隔设置的第一栅极与第二栅极，在所述第一栅极、第二栅极、及衬底基板上沉积栅极绝缘层，在所述栅极绝缘层上沉积非晶硅薄膜；
    步骤2、对所述非晶硅薄膜进行硼离子掺杂，然后对所述非晶硅薄膜进行快速热退火处理，使所述非晶硅薄膜结晶转化为低温多晶硅薄膜，所述低温多晶硅薄膜中硼离子的掺杂浓度从上到下逐渐减小；
    步骤3、对所述低温多晶硅薄膜进行图形化处理，得到对应于第二栅极上方的多晶硅层；
    步骤4、在所述栅极绝缘层上形成对应于第一栅极上方的氧化物半导体层；
    步骤5、在所述氧化物半导体层、多晶硅层、及栅极绝缘层上形成一金属层，采用一道半色调光罩制程对所述金属层、及多晶硅层进行图形化处理，得到设于所述氧化物半导体层与栅极绝缘层上且分别与所述氧化物半导体层两侧相接触的第一源极和第一漏极、以及设于所述多晶硅层与栅极绝缘层上且分别与所述多晶硅层两侧相接触的第二源极和第二漏极，同时在所述多晶硅层上对应于所述第二源极与第二漏极之间的区域形成一凹槽，使得所述多晶硅层上位于凹槽下方的部分形成沟道区，所述多晶硅层上位于沟道区两侧的区域分别形成源极接触区与漏极接触区；
    步骤6、在所述第一源极、第一漏极、第二源极、第二漏极、氧化物半导体层、多晶硅层、及栅极绝缘层上形成钝化层，在所述钝化层上形成平坦层；
    对所述平坦层、钝化层、及栅极绝缘层进行图形化处理，在所述平坦层与钝化层上形成对应于第一漏极上方的第一通孔、及对应于第二漏极上方的第二通孔，在所述平坦层、钝化层、及栅极绝缘层上形成对应于第二栅极上方的第三通孔；
    步骤7、在所述平坦层上形成连接导电层与像素电极，所述连接导电层经由第一通孔、及第三通孔分别与所述第一漏极、及第二栅极相接触，从而连接所述第一漏极与第二栅极，所述像素电极经由第二通孔与所述第二漏极相接触；
    在所述连接导电层、像素电极、及平坦层上形成像素定义层，对所述像素定义层进行图形化处理，得到对应于所述像素电极上方的第四通孔；
    其中，所述步骤2中，所述快速热退火处理的退火温度为600℃～700℃，退火保温时间为10min-30min；
    步骤8、在所述第四通孔内形成有机发光层，从而得到一OLED基板。
  12. 如权利要求11所述的TFT背板的制作方法，其中，所述步骤5包括：
    步骤51、在所述氧化物半导体层、多晶硅层、及栅极绝缘层上形成一金属层，在所述金属层上形成光阻层，采用一半色调光罩对光阻层进行曝光显影处理，得到第一光阻段、第二光阻段、及第三光阻段；
    所述第一光阻段上设有一对应于氧化物半导体层上方的一凹槽，所述第二光阻段与第三光阻段之间的间隔区域对应于多晶硅层上方；
    步骤52、采用一道干蚀刻制程对所述第一光阻段、第二光阻段、第三光阻段、金属层、及多晶硅层进行蚀刻处理，得到第一源极、第一漏极、第二源极、及第二漏极，同时在所述多晶硅层上形成凹槽，所述多晶硅层上位于凹槽下方的部分形成沟道区，所述多晶硅层上位于沟道区两侧的区域分别形成源极接触区与漏极接触区；之后剥离剩余的光阻层。
  13. 如权利要求12所述的TFT背板的制作方法，其中，所述步骤52中的干蚀刻制程采用的蚀刻气体包括六氟化硫、四氟化碳、氧气、及氯气中的一种或多种。
  14. 如权利要求11所述的TFT背板的制作方法，其中，所述氧化物半导体层的材料包括铟镓锌氧化物、及氧化铟锌中的一种或多种。
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