WO2017206796A1 - Oled阵列基板及其制备方法、阵列基板和显示装置 - Google Patents

Oled阵列基板及其制备方法、阵列基板和显示装置 Download PDF

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Publication number
WO2017206796A1
WO2017206796A1 PCT/CN2017/085921 CN2017085921W WO2017206796A1 WO 2017206796 A1 WO2017206796 A1 WO 2017206796A1 CN 2017085921 W CN2017085921 W CN 2017085921W WO 2017206796 A1 WO2017206796 A1 WO 2017206796A1
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Prior art keywords
array substrate
conductive layer
oled
light emitting
trace
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PCT/CN2017/085921
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English (en)
French (fr)
Inventor
李永谦
徐攀
李全虎
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京东方科技集团股份有限公司
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Priority to US15/570,615 priority Critical patent/US10453909B2/en
Publication of WO2017206796A1 publication Critical patent/WO2017206796A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/10—OLEDs or polymer light-emitting diodes [PLED]
    • H10K50/11—OLEDs or polymer light-emitting diodes [PLED] characterised by the electroluminescent [EL] layers
    • H10K50/125—OLEDs or polymer light-emitting diodes [PLED] characterised by the electroluminescent [EL] layers specially adapted for multicolour light emission, e.g. for emitting white light
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
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    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/81—Anodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/82—Cathodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
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    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
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    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/351—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels comprising more than three subpixels, e.g. red-green-blue-white [RGBW]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/38—Devices specially adapted for multicolour light emission comprising colour filters or colour changing media [CCM]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/029—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel
    • G09G2320/0295—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel by monitoring each display pixel
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element

Definitions

  • Embodiments of the present invention relate to an OLED array substrate, a method for fabricating the same, an array substrate, and a display device.
  • a mainstream display mode of an OLED display is an oxide TFT (oxide thin film transistor) + WOLED (white OLED display) + COA (color filter on Array, that is, a color filter film is fabricated on the array substrate).
  • oxide TFT oxide thin film transistor
  • WOLED white OLED display
  • COA color filter on Array, that is, a color filter film is fabricated on the array substrate.
  • the driving pixels of the above mainstream display mode generally adopt the external compensation technology of 3T1C, wherein “3T1C” refers to including three thin film transistors in one pixel unit. (TFT) and one storage capacitor Cst.
  • Embodiments of the present invention provide an OLED array substrate, a method for fabricating the same, an array substrate, and a display device.
  • the embodiment of the present invention can reduce the area of an effective display area occupied by a common power supply line in the OLED array substrate.
  • an embodiment of the present invention provides an OLED array substrate, the OLED array substrate includes: a plurality of pixel units, each of the pixel units including an OLED light emitting unit, a driving transistor, and a storage capacitor; a trace; covering the An insulating layer that drives the transistor, the storage capacitor, and the trace; a conductive layer over the insulating layer, the conductive layer configured to provide a common voltage to the pixel unit. At least one of the trace, the drive transistor, and the storage capacitor overlaps the conductive layer in a direction perpendicular to the OLED array substrate.
  • the trace includes a detection compensation line connecting the pixel unit and the detection integrated circuit;
  • the conductive layer includes a first common power supply line parallel to the detection compensation line, the first common power supply line and The detection compensation lines overlap in a direction perpendicular to the OLED array substrate.
  • the trace includes a gate line;
  • the conductive layer includes a second common power supply line parallel to the gate line, and the second common power supply line and the gate line are perpendicular to the OLED array substrate The direction overlaps.
  • the second common power supply line also overlaps with a region where the driving transistor is located and a region where the storage capacitor is located in a direction perpendicular to the OLED array substrate.
  • the trace includes a data line; the conductive layer includes a third common power supply line parallel to the data line, the third common power supply line and the data line being perpendicular to the OLED array substrate The direction overlaps.
  • the trace includes a data line;
  • the OLED array substrate further includes a data line retention pattern disposed in the same layer as the data line;
  • the conductive layer passes through the first through hole and the second through hole of the insulating layer The holes are respectively connected to the source of the driving transistor and the data line retention pattern.
  • the OLED array substrate further includes a base substrate, the OLED light emitting unit includes a first electrode, a light emitting layer, and a second electrode sequentially away from the base substrate; and the third common power source is included in the conductive layer
  • the OLED array substrate further includes an interlayer insulating layer covering the conductive layer and the insulating layer; the first electrode is disposed on the interlayer insulating layer.
  • the pixel unit further includes a first transistor and a second transistor
  • the array substrate includes a plurality of traces, the plurality of traces including a data line, a gate line, and a detection compensation line; a source of the first transistor a pole electrically connected to the data line, a drain electrically connected to a gate of the driving transistor, and a gate electrically connected to the gate line; a source of the driving transistor electrically connected to the conductive layer, a drain is electrically connected to an anode of the OLED light emitting unit and a source of the second transistor; one end of the storage capacitor is electrically connected to a drain of the first transistor, and the other end is connected to a drain of the driving transistor Electrically connecting; a cathode of the OLED light emitting unit is grounded; a gate of the second transistor is electrically connected to the detection compensation line.
  • the traces are metal traces and/or the conductive layer is a metal conductive layer.
  • the array substrate includes a display area and a peripheral area located around the display area, the display area including a plurality of light-emitting areas respectively corresponding to the OLED light-emitting units of the plurality of pixel units and located in the plurality of light-emitting areas A non-light emitting region outside the region, a portion of the conductive layer overlapping at least one of the trace, the driving transistor, and the storage capacitor being at least partially outside the light emitting region.
  • an embodiment of the present invention further provides a method for preparing an OLED array substrate.
  • the preparation method includes: forming a trace; forming a plurality of pixel units, wherein the formed pixel unit comprises an OLED light emitting unit, a driving transistor, and a storage capacitor; forming an insulating layer covering the pixel unit and the trace; and Forming a conductive layer over the insulating layer overlapping at least one of the trace, the driving transistor, and the storage capacitor in a direction perpendicular to the OLED array substrate, the conductive layer being used to The pixel unit provides a common voltage.
  • the trace formed includes a data line; a data line retention pattern disposed in the same layer as the data line; an insulating layer covering the driving transistor, the storage capacitor, and the trace; and the conductive
  • the layer is connected to the source of the driving transistor and the data line retention pattern through a first via hole and a second via hole penetrating the insulating layer; and the insulating layer is further formed with a surface of the driving transistor.
  • the OLED light emitting unit includes the first electrode, the light emitting layer, and the second electrode.
  • the step of forming the first electrode and the conductive layer over the insulating layer includes: forming the conductive layer on the insulating layer, wherein the conductive layer formed includes a portion parallel to the data line a common power supply line, the third common power supply line and the data line overlap in a direction perpendicular to the OLED array substrate; forming an interlayer insulating layer covering the conductive layer, the interlayer insulation Forming a fourth via hole penetrating the third via hole; forming the first electrode on the interlayer insulating layer, wherein the first electrode passes through the fourth via hole and The third via is connected to the drain of the driving transistor.
  • the traces are metal traces and/or the conductive layer is a metal conductive layer.
  • an embodiment of the present invention further provides an array substrate, including: a plurality of pixel units, each of the pixel units including a light emitting unit and a driving transistor and a storage capacitor connected to the light emitting unit; Connected to the pixel unit; an insulating layer covering the driving transistor, the storage capacitor and the trace; and a conductive layer on the insulating layer and configured to provide to the pixel unit Common voltage.
  • the conductive layer includes a portion overlapping at least one of the trace, the drive transistor, and the storage capacitor in a direction perpendicular to the array substrate.
  • the array substrate includes a display area and a peripheral area located around the display area a domain, wherein the display region includes a plurality of light emitting regions respectively corresponding to the light emitting units included in the plurality of pixel units and a non-light emitting region outside the plurality of light emitting regions, the portion of the conductive layer Located in the non-light emitting area.
  • the embodiment of the invention further provides a display device comprising the OLED array substrate according to any one of the above, or the array substrate according to any of the above.
  • FIG. 1 is a schematic plan view of a planar architecture of an OLED array substrate according to an embodiment of the present invention
  • FIG. 2 is a second schematic diagram of a planar architecture of an OLED array substrate according to an embodiment of the present disclosure
  • FIG. 3 is a schematic diagram 3 of a planar architecture of an OLED array substrate according to an embodiment of the present invention.
  • FIG. 4 is a schematic plan view 4 of a planar architecture of an OLED array substrate according to an embodiment of the present invention.
  • FIG. 5 is a schematic diagram 5 of a planar architecture of an OLED array substrate according to an embodiment of the present disclosure
  • FIG. 6 is a schematic diagram 6 of a planar architecture of an OLED array substrate according to an embodiment of the present disclosure
  • FIG. 7 is a schematic cross-sectional view of a OLED array substrate according to an embodiment of the present invention.
  • FIG. 8 is a second schematic cross-sectional view of an OLED array substrate according to an embodiment of the present invention.
  • FIG. 9 is a schematic structural diagram of an external compensation circuit of a 3T1C driving pixel structure according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic flowchart 1 of a method for preparing an OLED array substrate according to an embodiment of the present invention
  • FIG. 11 is a schematic flowchart 2 of a method for preparing an OLED array substrate according to an embodiment of the present disclosure
  • FIG. 12 is a schematic top plan view of an array substrate according to an embodiment of the present invention.
  • the inventors of the present application have noticed that when the driving pixel of the OLED display device adopts the external compensation technology of 3T1C, the pixel aperture ratio of the OLED display device is small; and the luminous intensity of the OLED display device is reduced due to the decrease of the pixel aperture ratio. It must be increased to compensate for the effect of the reduction in pixel aperture ratio on the display of the OLED display device, thereby affecting the lifetime of the OLED display device.
  • each pattern in the OLED array substrate according to the embodiment of the present invention is very small, for the sake of clarity, the size of each structure pattern in the drawings of the embodiments of the present invention is enlarged, unless otherwise explicitly stated, and does not represent the actual size and proportion. .
  • a and B overlap in a direction perpendicular to the OLED array substrate means that A and B completely overlap in a direction perpendicular to the OLED array substrate, Or A and B partially overlap in a direction perpendicular to the OLED array substrate; in addition, a direction perpendicular to the OLED array substrate refers to a direction perpendicular to a bearing surface of the carrier substrate included in the OLED array substrate. This embodiment of the present invention does not limit this. In order to better increase the pixel aperture ratio, the former can be selected.
  • An embodiment of the present invention provides an OLED array substrate, the OLED array substrate includes: a plurality of pixel units, each of the pixel units includes an OLED light emitting unit, and a driving transistor connected to the OLED light emitting unit (eg, driving a thin film transistor (ie, driving) a TFT, and a storage capacitor; a trace, such as a metal trace, connected to the plurality of pixel units, for example, to a driving transistor of the pixel unit; an insulating layer covering the driving transistor, the storage capacitor, and the trace; above the insulating layer a conductive layer (eg, a metal conductive layer) for providing a common voltage (VDD) to the pixel cells.
  • a driving transistor connected to the OLED light emitting unit
  • a driving transistor connected to the OLED light emitting unit
  • a trace such as a metal trace
  • At least one of a trace, a driving transistor, and a storage capacitor overlaps a metal conductive layer in a direction perpendicular to the OLED array substrate.
  • the portion in which the conductive layer overlaps the trace extends in substantially the same direction as the trace extends.
  • the traces and/or conductive layers can be made of a metallic material, or can be made of, for example, a conductive metal oxide or other conductive material.
  • the driving transistor includes a gate, an active layer, a source, and a drain.
  • the conductive layer may be combined with at least one of a gate, an active layer, a source, and a drain. overlap.
  • the above trace may be, for example, a gate line, a data line, a detection compensation line connecting the pixel unit and the detection integrated circuit (Sense IC, see the detection IC in FIG. 9) (ie, Sense line, see FIG. 9
  • Sense IC see the detection IC in FIG. 9
  • the trace can be connected to the gate of the driving transistor T3; when the trace is a data line, the trace can be connected to the source or the drain of the driving transistor T3; when the trace is the detecting compensation line
  • the trace can be connected to the drain of the drive transistor T3 through another transistor (see the embodiment shown in FIG. 9).
  • the OLED array substrate includes a display area and a peripheral area outside the display area, wherein the display area is also called an AA (Active Area) area, and is generally used for realizing display, and the display area includes respectively Corresponding to a plurality of light emitting regions of the OLED light emitting unit of the plurality of pixel units and a non-light emitting region located around the light emitting region, at least a portion of the conductive layer overlapping at least one of a trace, a driving transistor, and a storage capacitor The ground is located outside the plurality of light emitting regions.
  • the peripheral area can be used to set a drive circuit or the like.
  • the plurality of pixel units and the traces are all located in the display area.
  • the conductive layer for supplying the common voltage VDD to the pixel unit is disposed above the insulating layer, and in the opaque trace in the display region, the opaque driving transistor, and the opaque storage capacitor At least one of them overlaps in a direction perpendicular to the OLED array substrate, reducing an effective display area occupied by the conductive layer corresponding to the common power supply line in the OLED array substrate (the OLED illumination unit in which all the pixel units of the display area are located)
  • the area of the region increases the aperture ratio of the display device including the OLED array substrate; since the aperture ratio is improved, it is not necessary to increase the illumination intensity of the OLED illumination unit to compensate for the effect of the reduction of the pixel aperture ratio on the display of the OLED display panel, Thereby, the service life of the OLED device in the OLED display panel is improved.
  • the above conductive layer may be a common power supply line.
  • the OLED array substrate provided by the embodiment of the present invention is specifically described in the following.
  • the above-mentioned trace includes a detection compensation line 110 connecting the pixel unit and the detection integrated circuit.
  • the detection compensation line SL may be The pixel unit is connected and connected to the detection IC; the conductive layer includes a first common power supply line 91 substantially parallel to the detection compensation line 110, and the first common power supply line 91 and the detection compensation line 110 are perpendicular to the OLED array The directions of the substrates overlap (the broken line of the detection compensation line 110 is indicated by a broken line in the figure).
  • the first common power supply line 91 is located directly above the detection compensation line 110.
  • the detection compensation line and the first common power supply line overlap in a direction perpendicular to the OLED array substrate, a certain capacitance can be formed between the detection compensation line and the first common power supply line, thereby increasing the detection compensation line.
  • the capacitance between the conductive structure and the conductive structure that overlaps with it ensures the stability of the capacitor.
  • the direction in which the compensation compensation line 110 extends is substantially parallel to the direction in which the data lines 52 extend; for example, the width of the detection compensation line 10 is greater than the width of the data lines 52.
  • FIG. 1 four pixel units are sequentially arranged, and the areas corresponding to the OLED light-emitting units included in the four sequentially arranged pixel units emit light of different colors, see R and G in FIG. 1 . , B and W, which represent red, green, blue, and white, respectively.
  • the color emitted by the area in which the light unit is located includes, but is not limited to, the embodiment shown in FIG.
  • the above-mentioned trace includes a gate line 21, and the conductive layer includes a second common power supply line 92 parallel to the gate line 21, and a second common power supply.
  • the supply line 92 overlaps the gate line 21 in a direction perpendicular to the OLED array substrate (the dotted line 21 is indicated by a broken line in the figure).
  • the second common power supply line 92 is located directly above the gate line 21.
  • the conductive layer is disposed above the insulating layer and the distance from the gate line is relatively long, the risk of electrostatic discharge (Electro-Static Discharge, ESD for short) of the gate line and the conductive layer can be reduced.
  • ESD Electro-Static Discharge
  • the second common power supply line 92 can be set wider to be in the area where the driving transistor is located, and stored.
  • the regions in which the capacitors are located overlap in a direction perpendicular to the OLED array substrate. In this way, a laterally large area is formed in the region including the gate line 21, the driving transistor, and the storage capacitor.
  • the coverage area of the conductive layer of the area is such that the width of the second common power supply line 92 is large, which reduces the voltage drop of the conductive layer (IR drop) and reduces the energy consumption of the OLED array substrate.
  • the above-mentioned trace includes a data line 52
  • the conductive layer includes a third common power supply line 93 parallel to the data line 52, and a third common power supply.
  • the supply line 93 overlaps the data line 52 in a direction perpendicular to the OLED array substrate (the dotted line indicates the data line 52 located below).
  • the third common power supply line 93 is located directly above the data line 52.
  • FIGS. 1 to 4 only separately illustrate the case where the conductive layer includes any of the first common power supply line 91, the second common power supply line 92, and the third common power supply line 93.
  • the conductive layer may include the first common power supply line and the second common power supply line, and the first common power supply line and the second common power supply line are connected to each other to form The integrated structure; or, as shown in FIG.
  • the conductive layer may include the first common power supply line, the second common power supply line, and the third common power supply line, and the first common power supply line, the second The common power supply line and the third common power supply line are connected to each other to form a unitary structure such that the area of the conductive layer is larger, thereby making the voltage drop of the conductive layer smaller.
  • the OLED array substrate further includes a data line retention pattern 53 disposed in the same layer as the data line, for example, the data line retention pattern 53 is connected to the source 50 of the driving transistor T3 (for example, a driving TFT) (for example, two The body is integrally formed and connected by a via hole penetrating the gate insulating layer 30 and the data line lead 22 (for example, the data line lead 22 is disposed in the same layer as the gate 20 of the driving transistor T3).
  • a driving TFT for example, two
  • the body is integrally formed and connected by a via hole penetrating the gate insulating layer 30 and the data line lead 22 (for example, the data line lead 22 is disposed in the same layer as the gate 20 of the driving transistor T3).
  • the data line is used to transmit a data voltage signal for the OLED lighting unit
  • the data line retention pattern 53 is used for switching, and is used to connect the data line to the data line lead 22
  • the data line lead 22 is used to connect the source driver (eg, source) The pole drive IC) and the data line retain pattern 53 to connect the source driver to the data line.
  • the conductive layer 90 is connected to the source 50 of the driving transistor T3 and the data line retention pattern 53 through the first via hole (labeled a) and the second via hole (labeled as b in the drawing) penetrating the insulating layer 60, respectively.
  • the above-described data line retention pattern 53 is generally located in a peripheral area other than the display area (labeled as AA area in the figure, indicating an Active Area).
  • the layers in FIG. 7 are sequentially: the substrate 10 ⁇ the gate 20 of the driving transistor T3 , the gate line, and the data line lead 22 disposed in the same layer as the gate ⁇ the gate insulating layer 30 ⁇ the driving transistor
  • the active layer 40 of T3 ⁇ the source 50, the drain 51, the data line of the driving transistor T3, and
  • the data line retention pattern 53 disposed in the same layer as the data line ⁇ the protective layer 61 ⁇ the color film layer 70 ⁇ the flat layer 62 ⁇ the first electrode 80 of the OLED light emitting unit and the conductive layer 90 (for example, the first electrode 80 and the conductive layer 90 are side by side Provided on the flat layer 62) ⁇ the pixel defining layer 100 ⁇ the light emitting layer 81 of the OLED light emitting unit ⁇ the second electrode 82 of the OLED light emitting unit.
  • At least one of the gate electrode 20, the active layer 40, the source electrode 50, and the drain electrode 51 included in the driving transistor T3 includes a first electrode 80 in a block shape with the OLED light emitting unit in a direction perpendicular to the substrate substrate 10. Non-overlapping parts.
  • the OLED array substrate includes a pixel defining layer 100, the opening portion 100a of the pixel defining layer 100 exposing at least a portion of the surface of the first electrode 80 of the OLED lighting unit, and the luminescent layer 81 and the second electrode 82 of the OLED lighting unit are both included A portion in the opening portion 100a.
  • the upper electrode 54 of the storage capacitor Cst may be disposed in the same layer as the source 50 and the drain 51 of the driving transistor T3, and the lower electrode 24 of the storage capacitor Cst may be disposed in the same layer as the gate 20 of the driving transistor T3.
  • both the upper electrode 54 and the lower electrode 24 of the storage capacitor Cst include portions that do not overlap with the first electrode 80 of the OLED light emitting unit in a direction perpendicular to the substrate substrate 10.
  • the layer structure illustrated in FIG. 7 above further includes a color film layer 70.
  • the color film layer 70 is perpendicular to the lining.
  • the direction of the base substrate 10 overlaps with the first electrode 80 of the OLED lighting unit.
  • the insulating layer 60 may include a protective layer (commonly referred to as a PAS layer) 61 covering the driving transistor T3 and a flat layer covering the color film layer 70 above the protective layer 61 (commonly referred to as an OC layer, Over)
  • the Coat 62 is composed of, for example, both of the first through holes and the second through holes.
  • the OLED array substrate further includes an interlayer insulating layer 120 covering the conductive layer 90 and the insulating layer 60; the first of the OLED light emitting units The electrode 80 is disposed on the interlayer insulating layer 120.
  • the interlayer insulating layer 120 is further disposed between the conductive layer 90 and the first electrode 80. In this way, the aperture ratio can be further increased by reducing the distance between the conductive layer 90 and the first electrode 80, thereby reducing both the voltage drop of the conductive layer and the further increase in the aperture ratio.
  • the pixel unit further includes a first transistor T1 and a second transistor T2, and the trace includes a data line Da, a gate line G1, and a detection compensation line G2; a source s1 of the first transistor T1 and a data line Da Electrically connected, its drain d1 is electrically connected to the gate g3 of the driving transistor T3, its gate g1 is electrically connected to the gate line G1, and the source s3 of the driving transistor T3 is electrically connected to the conductive layer (see VDD in FIG.
  • the drain d3 is electrically connected to the anode of the OLED light emitting unit (one example of the first electrode 80) and the source s2 of the second transistor T2; one end of the storage capacitor Cst is electrically connected to the drain of the first transistor T1, and the other end is
  • the drain d3 of the driving transistor T3 is electrically connected; the cathode of the OLED lighting unit (one example of the second electrode 82) is grounded; and the gate g2 of the second transistor T2 is electrically connected to the detection compensation line G2.
  • This can realize the external compensation structure of 3T1C. This structure can solve the problem that the threshold voltage (Vth) of the oxide TFT is shifted and the luminance of the light is not uniform.
  • an embodiment of the present invention further provides a method for fabricating the above OLED array substrate, the method comprising: forming a plurality of pixel units and routing, and forming the pixel unit including an OLED light emitting unit, a driving transistor, and a memory a capacitor; forming a insulating layer covering the pixel unit and the trace; the above preparation method further includes: forming at least one of a trace, a driving transistor, and a storage capacitor over the insulating layer in a direction perpendicular to the OLED array substrate An alternating conductive layer for providing a common voltage to the pixel cells.
  • the traces are metal traces and/or the conductive layer is a metal conductive layer.
  • the above preparation method includes: forming a driving transistor T3, a storage capacitor, and a trace on the base substrate 10, so that the formed trace includes a data line; forming the same as the data line a data line retention pattern 53 disposed in the layer; forming an insulating layer 60 covering the driving transistor T3, the storage capacitor and the wiring, and a third via hole c exposing the drain 51 of the driving transistor T3 is formed in the insulating layer 60;
  • a first electrode 80 is formed over 60 and a conductive layer 90 for supplying a common voltage to the pixel unit such that at least one of the conductive layer 90 and the trace, the driving transistor T3 and the storage capacitor are perpendicular to the OLED array substrate
  • the first via hole a and the second via hole b that pass through the insulating layer 60 are respectively connected to the source 50 of the driving transistor T3 and the data line retention pattern 53 and pass the first electrode 80 through the third via hole c.
  • the first electrode 80, the light emitting layer 81, and the second electrode 82 constitute an OLED light emitting unit; the OLED light emitting unit, the driving transistor, and the storage capacitor constitute a pixel unit.
  • the upper electrode 54 of the storage capacitor Cst may be disposed in the same layer as the source 50 and the drain 51 of the driving transistor T3, and the lower electrode 24 of the storage capacitor Cst may be disposed in the same layer as the gate 20 of the driving transistor T3.
  • the above-mentioned insulating layer 60 may include a protective layer (commonly referred to as a PAS layer) 61 covering the driving transistor and the protective layer 61.
  • the upper layer covering the color film layer 70 (usually abbreviated as OC layer, Over Coat) 62, the steps of the above preparation method are sequentially formed on the substrate substrate, for example, as shown in FIG.
  • the gate electrode , gate line and gate metal layer of the data line lead disposed in the same layer as the gate ⁇ gate insulating layer ⁇ active layer ⁇ etch barrier layer (here, if the material of the active layer is not susceptible to source and drain etching)
  • the preparation step of the etch barrier layer may be omitted, and the prior art may be used in the prior art.
  • the invention includes the source, the drain, the data line, and the data line disposed in the same layer as the data line.
  • the source/drain metal layer of the pattern is retained ⁇ the protective layer ⁇ the color film layer ⁇ the flat layer ⁇ the first electrode and the conductive layer of the OLED light emitting unit ⁇ the pixel defining layer ⁇ the light emitting layer of the OLED light emitting unit ⁇ the second electrode of the OLED light emitting unit.
  • the protective layer ⁇ the color film layer ⁇ the flat layer ⁇ the first electrode and the conductive layer of the OLED light emitting unit ⁇ the pixel defining layer ⁇ the light emitting layer of the OLED light emitting unit ⁇ the second electrode of the OLED light emitting unit.
  • the pixel defining layer can be fabricated by a patterning process, which can be a photolithography process including steps of exposure, development, etching, or the like, or other processes commonly used in the art to form a desired pattern.
  • the step of forming the first electrode and the conductive layer over the insulating layer comprises: forming a conductive layer on the insulating layer, the formed conductive layer comprising a third common substantially parallel to the data line a power supply line, a third common power supply line and a data line overlapping in a direction perpendicular to the OLED array substrate; as shown in FIG.
  • an interlayer insulating layer 120 covering the conductive layer 90 is formed to make an interlayer insulating layer
  • a fourth via hole (labeled as d) penetrating through the third via hole (indicated as c in the drawing) is formed in 120; the first electrode 80 is formed on the interlayer insulating layer 120, and the first electrode 80 is passed through
  • the four via holes d and the third via holes c are connected to the drain 51 of the driving transistor T3.
  • a third common power supply line is disposed above the data line. Further, the above interlayer insulating layer is provided between the conductive layer and the first electrode. In this way, the aperture ratio can be further increased by reducing the distance between the conductive layer and the first electrode, thereby reducing the voltage drop of the conductive layer and further ensuring the aperture ratio. increase.
  • the steps of the above-described preparation method are sequentially formed on the substrate substrate, for example, as shown in FIG. 11(a), including a gate electrode, a gate line, and the same layer as the gate electrode.
  • Set the gate metal layer of the data line lead ⁇ gate insulating layer ⁇ active layer ⁇ etch stop layer (here, if the material of the active layer is a material that is not easily affected by source and drain etching, the etch stop may be omitted)
  • the preparation step of the layer is not limited in the embodiment of the present invention.
  • the source/drain metal layer including the source, the drain, the data line, and the data line retention pattern disposed in the same layer as the data line ⁇ protection Layer ⁇ color film layer ⁇ flat layer ⁇ conductive layer ⁇ interlayer insulating layer ⁇ first electrode of OLED light emitting unit ⁇ pixel defining layer ⁇ light emitting layer of OLED light emitting unit ⁇ second electrode of OLED light emitting unit.
  • gate metal layer, active layer, etch barrier layer, source/drain metal layer, protective layer, color film layer, flat layer, metal conductive layer, interlayer insulation The layer, the first electrode, and the pixel defining layer can all be fabricated using a patterning process.
  • the array substrate includes: a plurality of pixel units, each of which includes a light emitting unit (see R, G, B in FIG. 12, W) and a driving transistor T3 and a storage capacitor Cst connected to the light emitting unit; a trace LW (shown by a broken line in FIG. 12) connected to the pixel unit P (for example, connected to the driving transistor T3); an insulating layer IL, The driving transistor T3, the storage capacitor Cst, and the trace LW are covered; a conductive layer CL is disposed on the insulating layer IL and configured to supply a common voltage to the pixel unit.
  • the conductive layer CL includes a portion overlapping at least one of the trace LW, the drive transistor T3, and the storage capacitor Cst in a direction perpendicular to the array substrate.
  • FIG. 12 illustrates an example in which the conductive layer CL overlaps the trace LW.
  • the array substrate includes a display area (the structure shown in FIG. 12 is located in the display area of the array substrate) and a peripheral area (not shown in FIG. 12) located at the periphery of the display area, and the display area includes a plurality of pixel units respectively included A plurality of light emitting regions of the light emitting unit (see a region where R, G, B, and W are located) and a non-light emitting region outside the plurality of light emitting regions, and the overlapping portion of the conductive layer CL is located in the non-light emitting region.
  • the trace LW may be a gate line, a data line, or a detection compensation line.
  • the trace LW when the trace LW is a gate line, the trace LW may be connected to the gate of the driving transistor T3; when the trace LW is a data line, the trace LW may be connected to the source or the drain of the driving transistor T3; the trace LW To detect the compensation line, the trace LW can be connected to the drain of the drive transistor T3 through another transistor (see Figure 9). The illustrated embodiment).
  • the light emitting unit may be an OLED (Organic Light Emitting Diode), an LED (Light Emitting Diode), or other type of active light emitting element.
  • OLED Organic Light Emitting Diode
  • LED Light Emitting Diode
  • the array substrate can be an OLED array substrate, an LED array substrate or other type of active light emitting array substrate.
  • the embodiment of the invention further provides a display device, which comprises the above OLED array substrate or array substrate.
  • the above display device may be a product or component having any display function such as an OLED display, an OLED TV, a digital photo frame, a mobile phone, a tablet computer, or the like.
  • OLED array substrate and its fabrication method, array substrate and display device embodiments can be cross-referenced.
  • a conductive layer for supplying a common voltage to the pixel unit is disposed above the insulating layer, and is opaque to the display region, the opaque driving transistor, and the opaque storage capacitor. At least one of the overlaps reduces the area of the effective display area occupied by the conductive layer corresponding to the common power supply line in the OLED display device, and improves the aperture ratio; since the aperture ratio is improved, it is not necessary to increase the illumination intensity of the illumination unit To compensate for the effect of the reduction in pixel aperture ratio on the display of the display device, thereby increasing the useful life of the display device.

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Abstract

一种OLED阵列基板及其制备方法、阵列基板和显示装置，该OLED阵列基板包括：走线；多个像素单元（P），像素单元（P）包括OLED发光单元、驱动晶体管（T3）和存储电容（Cst）；覆盖驱动晶体管（T3）、存储电容（Cst）和走线的绝缘层（60）；位于绝缘层（60）上方的导电层（90），导电层（90）用于向像素单元（P）提供公共电压。导电层（90）与走线、驱动晶体管（T3）和存储电容（Cst）中的至少一者在垂直于该OLED阵列基板的方向上交叠。本发明实施例可减少OLED阵列基板中公共电源供给线占据的有效显示区域的面积。

Description

OLED阵列基板及其制备方法、阵列基板和显示装置 技术领域
本发明实施例涉及一种OLED阵列基板及其制备方法、阵列基板和显示装置。
背景技术
目前OLED显示(Organic Light-Emitting Diode Display，有机电致发光显示)装置的一个主流显示方式为oxide TFT(oxide Thin Film Transistor，氧化物薄膜晶体管)+WOLED(白光OLED显示)+COA(color filter on array，即彩色滤色膜制作在阵列基板上)。为了解决oxide TFT的阈值电压(Vth)偏移及发光亮度不均一的问题，上述主流显示方式的驱动像素通常采用3T1C的外部补偿技术，其中“3T1C”是指一个像素单元中包括3个薄膜晶体管(TFT)以及1个存储电容Cst。
发明内容
本发明的实施例提供一种OLED阵列基板及其制备方法、阵列基板和显示装置，本发明实施例可减少OLED阵列基板中公共电源供给线占据的有效显示区域的面积。
一方面，本发明实施例提供了一种OLED阵列基板，所述OLED阵列基板包括：多个像素单元，每个所述像素单元包括OLED发光单元、驱动晶体管和存储电容；走线；覆盖所述驱动晶体管、所述存储电容和所述走线的绝缘层；位于所述绝缘层上方的导电层，所述导电层被配置为用于向所述像素单元提供公共电压。所述走线、所述驱动晶体管和所述存储电容中的至少一者与所述导电层在垂直于所述OLED阵列基板的方向上交叠。
例如，所述走线包括连接所述像素单元与检测集成电路的检测补偿线；所述导电层包括平行于所述检测补偿线的第一公共电源供给线，所述第一公共电源供给线与所述检测补偿线在垂直于所述OLED阵列基板的方向上交叠。
例如，所述走线包括栅线；所述导电层包括平行于所述栅线的第二公共电源供给线，所述第二公共电源供给线与所述栅线在垂直于所述OLED阵列基板的方向上交叠。
例如，所述第二公共电源供给线还与所述驱动晶体管所在的区域、所述存储电容所在的区域在垂直于所述OLED阵列基板的方向上交叠。
例如，所述走线包括数据线；所述导电层包括平行于所述数据线的第三公共电源供给线，所述第三公共电源供给线与所述数据线在垂直于所述OLED阵列基板的方向上交叠。
例如，所述走线包括数据线；所述OLED阵列基板还包括与所述数据线同层设置的数据线保留图案；所述导电层通过贯通所述绝缘层的第一通孔、第二通孔分别与所述驱动晶体管的源极、所述数据线保留图案相连接。
例如，所述的OLED阵列基板还包括衬底基板，所述OLED发光单元包括依次远离所述衬底基板的第一电极、发光层、第二电极；在所述导电层包括有第三公共电源供给线的情况下，所述OLED阵列基板还包括覆盖所述导电层和所述绝缘层的层间绝缘层；所述第一电极设置在所述层间绝缘层上。
例如，所述像素单元还包括第一晶体管和第二晶体管，所述阵列基板包括多个走线，所述多个走线包括数据线、栅线和检测补偿线；所述第一晶体管的源极与所述数据线电连接、其漏极与所述驱动晶体管的栅极电连接、其栅极与所述栅线电连接；所述驱动晶体管的源极与所述导电层电连接、其漏极与所述OLED发光单元的阳极和所述第二晶体管的源极电连接；所述存储电容的一端与所述第一晶体管的漏极电连接、另一端与所述驱动晶体管的漏极电连接；所述OLED发光单元的阴极接地；所述第二晶体管的栅极与所述检测补偿线电连接。
例如，所述走线为金属走线和/或所述导电层为金属导电层。
例如，所述阵列基板包括显示区域和位于所述显示区域周边的外围区域，所述显示区域包括分别对应于所述多个像素单元的OLED发光单元的多个发光区域和位于所述多个发光区域之外的非发光区域，所述导电层的与所述走线、所述驱动晶体管和所述存储电容中的至少一者交叠的部分至少部分地位于所述发光区域之外。
另一方面，本发明实施例还提供了一种OLED阵列基板的制备方法，所 述制备方法包括：形成走线；形成多个像素单元，使形成的所述像素单元包括OLED发光单元、驱动晶体管和存储电容；形成覆盖所述像素单元和所述走线的绝缘层；以及在所述绝缘层上方形成与所述走线、所述驱动晶体管和所述存储电容中的至少一者在垂直于所述OLED阵列基板的方向上交叠的导电层，所述导电层用于向所述像素单元提供公共电压。
例如，形成的所述走线包括数据线；形成与所述数据线同层设置的数据线保留图案；形成覆盖所述驱动晶体管、所述存储电容以及所述走线的绝缘层；所述导电层通过贯通所述绝缘层的第一通孔、第二通孔分别与所述驱动晶体管的源极、所述数据线保留图案相连接；所述绝缘层上还形成有露出所述驱动晶体管的漏极的第三通孔；在所述绝缘层上方形成第一电极和所述导电层；所述第一电极通过所述第三通孔与所述驱动晶体管的漏极相连接；形成覆盖所述第一电极和所述导电层的像素界定层；在所述像素界定层的开口部分形成发光层；在所述发光层上形成第二电极。在该方法中，所述OLED发光单元包括所述第一电极、所述发光层和所述第二电极。
例如，所述在所述绝缘层上方形成第一电极和导电层的步骤包括：在所述绝缘层上形成所述导电层，其中，形成的所述导电层包括平行于所述数据线的第三公共电源供给线，所述第三公共电源供给线与所述数据线在垂直于所述OLED阵列基板的方向上交叠；形成覆盖所述导电层的层间绝缘层，所述层间绝缘层上形成有与所述第三通孔贯通的第四通孔；在所述层间绝缘层上形成所述第一电极，其中，所述第一电极通过所述第四通孔和所述第三通孔与所述驱动晶体管的漏极相连接。
例如，所述走线为金属走线和/或所述导电层为金属导电层。
再一方面，本发明实施例还提供一种阵列基板，其包括：多个像素单元，每个所述像素单元包括发光单元以及与所述发光单元连接的驱动晶体管和存储电容；走线，其与所述像素单元连接；绝缘层，其覆盖所述驱动晶体管、所述存储电容和所述走线；以及导电层，其位于所述绝缘层上并且被配置为用于向所述像素单元提供公共电压。所述导电层包括与所述走线、所述驱动晶体管和所述存储电容中的至少一者在垂直于所述阵列基板的方向上交叠的部分。
例如，所述的阵列基板包括显示区域和位于所述显示区域周边的外围区 域，其中，所述显示区域包括分别对应于所述多个像素单元包括的发光单元的多个发光区域以及位于所述多个发光区域之外的非发光区域，所述导电层的所述部分位于所述非发光区域中。
再一方面，本发明实施例还提供了一种显示装置，其包括以上任一项所述的OLED阵列基板或者以上任一项所述的阵列基板。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1为本发明实施例提供的一种OLED阵列基板的平面架构示意图一；
图2为本发明实施例提供的一种OLED阵列基板的平面架构示意图二；
图3为本发明实施例提供的一种OLED阵列基板的平面架构示意图三；
图4为本发明实施例提供的一种OLED阵列基板的平面架构示意图四；
图5为本发明实施例提供的一种OLED阵列基板的平面架构示意图五；
图6为本发明实施例提供的一种OLED阵列基板的平面架构示意图六；
图7为本发明实施例提供的一种OLED阵列基板的截面架构示意图一；
图8为本发明实施例提供的一种OLED阵列基板的截面架构示意图二；
图9为本发明实施例提供的一种3T1C驱动像素结构的外部补偿电路结构示意图；
图10为本发明实施例提供的一种OLED阵列基板的制备方法流程示意图一；
图11为本发明实施例提供的一种OLED阵列基板的制备方法流程示意图二；
图12为本发明实施例提供的一种阵列基板的俯视示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描 述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在研究中，本申请的发明人注意到，OLED显示装置的驱动像素采用3T1C的外部补偿技术时，OLED显示装置的像素开口率较小；并且由于像素开口率减小，OLED显示装置的发光强度必须增大以弥补像素开口率的减小对于OLED显示装置显示的影响，从而影响了OLED显示装置的使用寿命。
由于本发明实施例所涉及的OLED阵列基板中各图案尺寸非常微小，为了清楚起见，本发明实施例附图中的各结构图案尺寸均被放大，除非另有明确说明，不代表实际尺寸与比例。
需要说明的是，在本发明实施例的描述中，“A与B在垂直于该OLED阵列基板的方向上交叠”是指：A与B在垂直于该OLED阵列基板的方向上完全重叠，或者A与B在垂直于该OLED阵列基板的方向上部分重叠；另外，垂直于该OLED阵列基板的方向是指垂直于该OLED阵列基板包括的承载基板的承载面的方向。本发明实施例对此不作限定。考虑到更好的提高像素开口率，可以选择前者。
本发明实施例提供了一种OLED阵列基板，该OLED阵列基板包括：多个像素单元，每个像素单元包括OLED发光单元、以及与该OLED发光单元连接的驱动晶体管(例如驱动薄膜晶体管(即驱动TFT)和存储电容；走线，例如金属走线，其与所述多个像素单元连接，例如与像素单元的驱动晶体管连接；覆盖驱动晶体管、存储电容和走线的绝缘层；位于绝缘层上方的导电层(例如金属导电层)，导电层用于向像素单元提供公共电压(VDD)。在 该OLED阵列基板中，走线、驱动晶体管和存储电容中的至少一者与金属导电层在垂直于该OLED阵列基板的方向上交叠。例如，在导电层与走线交叠时，导电层与走线交叠的部分的延伸方向与走线的延伸方向大致相同。
例如，走线和/或导电层可以采用金属材料制作，也可以采用例如导电金属氧化物或其它导电材料制作。
例如，驱动晶体管包括栅极、有源层、源极、漏极，在导电层与驱动晶体管交叠的情况下，导电层可以与栅极、有源层、源极和漏极中的至少一个交叠。
需要说明的是，上述的走线例如可以是栅线、数据线、连接像素单元与检测集成电路(Sense IC，参见图9中的检测IC)的检测补偿线(即Sense line，参见图9中的SL)中的至少一种走线。例如，走线为栅线时，走线可以与驱动晶体管T3的栅极连接；走线为数据线时，走线可以与驱动晶体管T3的源极或漏极连接；走线为检测补偿线时，走线可以通过另一晶体管与驱动晶体管T3的漏极连接(参见图9所示的实施例)。
另外，对于本领域技术人员来说，上述OLED阵列基板包括显示区域和位于显示区域之外的外围区域，其中，显示区域又称AA(Active Area)区，一般用于实现显示，显示区域包括分别对应于所述多个像素单元的OLED发光单元的多个发光区域以及位于发光区域周边的非发光区域，导电层的与走线、驱动晶体管和存储电容中的至少一者交叠的部分至少部分地位于该多个发光区域之外。外围区域可用于设置驱动电路等。上述多个像素单元和走线均位于显示区域内。
这样一来，由于用于向像素单元提供公共电压VDD的导电层设置在绝缘层上方，且与显示区域内不透光的走线、不透光的驱动晶体管和不透光的存储电容中的至少一者在垂直于该OLED阵列基板的方向上交叠，减少了OLED阵列基板中相当于公共电源供给线的导电层占据的有效显示区域(显示区域的全部像素单元的OLED发光单元所在的发光区域)的面积，提高了包括该OLED阵列基板的显示装置的开口率；由于开口率得以提高，不需要增加OLED发光单元的发光强度来弥补像素开口率的减小对于OLED显示面板显示的影响，从而提高了OLED显示面板中OLED器件的使用寿命。
例如，上述导电层可以是公共电源供给线。下面按照导电层的不同位置 以及走线包括的不同情况，具体说明本发明实施例提供的OLED阵列基板。
在上述任一实施例的基础上，例如，如图1所示，上述的走线包括连接像素单元与检测集成电路的检测补偿线110，例如，如图9所示，检测补偿线SL可以与像素单元连接并且与检测IC连接；上述的导电层包括大致平行于该检测补偿线110的第一公共电源供给线91，第一公共电源供给线91与检测补偿线110在垂直于所述OLED阵列基板的方向上交叠(图中以虚线示意出位于下方的检测补偿线110)。例如，第一公共电源供给线91位于检测补偿线110的正上方。
由于检测补偿线与第一公共电源供给线在垂直于所述OLED阵列基板的方向上交叠，可使得检测补偿线与第一公共电源供给线之间形成一定的电容，从而增加了检测补偿线和与其交叠的导电结构之间的电容，保证了该电容的稳定性。
例如，如图1所示，检测补偿线110的延伸方向大致平行于数据线52的延伸方向；例如，检测补偿线10的宽度大于数据线52的宽度。
需要说明的是，图1中示出了4个依次排列的像素单元，并且这4个依次排列的像素单元包括的OLED发光单元对应的区域发出不同颜色的光，参见图1中的R、G、B和W，其分别代表红色、绿色、蓝色和白色。发光单元所在区域发出的颜色包括但不限于图1所示实施例。
在上述任一实施例的基础上，例如，如图2所示，上述的走线包括栅线21，上述的导电层包括平行于栅线21的第二公共电源供给线92，第二公共电源供给线92与栅线21在垂直于所述OLED阵列基板的方向上交叠(图中以虚线示意出位于下方的栅线21)。例如，第二公共电源供给线92位于栅线21的正上方。
在该实施例中，由于导电层设置在绝缘层上方，与栅线之间的距离较远，能够减小栅线与导电层发生静电放电(Electro-Static Discharge，简称ESD)的风险。
例如，考虑到栅线所在的区域与驱动晶体管和存储电容的区域相距很近，如图3所示，可以将第二公共电源供给线92设置得再宽些以与驱动晶体管所在的区域、存储电容所在的区域在垂直于所述OLED阵列基板的方向上交叠。这样一来，在包括有栅线21、驱动晶体管以及存储电容的区域形成了横向大 面积的导电层的覆盖区域，使得第二公共电源供给线92的宽度较大，降低了导电层的电压降(IR drop)，降低了OLED阵列基板的能耗。
在上述任一实施例的基础上，例如，如图4所示，上述的走线包括数据线52，上述的导电层包括平行于数据线52的第三公共电源供给线93，第三公共电源供给线93与数据线52在垂直于所述OLED阵列基板的方向上交叠(图中以虚线示意出位于下方的数据线52)。例如，第三公共电源供给线93位于数据线52的正上方。
需要说明的是，上述图1至图4仅分别单独示意出导电层包括第一公共电源供给线91、第二公共电源供给线92、第三公共电源供给线93任一者的情况。本发明实施例对此不作限定。例如，如图5所示，上述的导电层可以包括上述的第一公共电源供给线与第二公共电源供给线，并且第一公共电源供给线与第二公共电源供给线相互之间相连以形成一体结构；或者，如图6所示，上述的导电层可以包括上述的第一公共电源供给线、第二公共电源供给线以及第三公共电源供给线，并且第一公共电源供给线、第二公共电源供给线以及第三公共电源供给线相互之间相连以形成一体结构，以使得导电层的面积更大，从而使导电层的电压降更小。
例如，如图7所示，OLED阵列基板还包括与数据线同层设置的数据线保留图案53，例如数据线保留图案53与驱动晶体管T3(例如，驱动TFT)的源极50连接(例如二者一体形成)并且通过贯穿栅绝缘层30的过孔与数据线引线22(例如，数据线引线22与驱动晶体管T3的栅极20同层设置)连接。数据线用于为OLED发光单元传输数据电压信号、数据线保留图案53起到转接作用并且用于将数据线与数据线引线22连接起来，数据线引线22用于连接源极驱动器(例如源极驱动IC)和数据线保留图案53，以将源极驱动器与数据线连接起来。导电层90通过贯通绝缘层60的第一通孔(图中标记为a)、第二通孔(图中标记为b)分别与驱动晶体管T3的源极50、数据线保留图案53相连接。上述数据线保留图案53一般位于显示区域(图中标记为AA区域，表示Active Area)之外的外围区域。
需要说明的是，图7中的各层结构依次为：衬底基板10→驱动晶体管T3的栅极20、栅线以及与栅极同层设置的数据线引线22→栅绝缘层30→驱动晶体管T3的有源层40→驱动晶体管T3的源极50、漏极51、数据线以及 与数据线同层设置的数据线保留图案53→保护层61→彩膜层70→平坦层62→OLED发光单元的第一电极80和导电层90(例如，第一电极80和导电层90并排设置在平坦层62上)→像素界定层100→OLED发光单元的发光层81→OLED发光单元的第二电极82。
例如，驱动晶体管T3包括的栅极20、有源层40、源极50和漏极51中的至少一者包括与OLED发光单元块状的第一电极80在垂直于衬底基板10的方向上不交叠的部分。
例如，OLED阵列基板包括像素界定层100，像素界定层100的开口部分100a暴露出OLED发光单元的第一电极80的至少部分表面，OLED发光单元的发光层81和第二电极82都包括位于该开口部分100a中的部分。
例如，存储电容Cst的上电极54例如可以与驱动晶体管T3的源极50和漏极51同层设置，存储电容Cst的下电极24可以与驱动晶体管T3的栅极20同层设置。例如，存储电容Cst的上电极54和下电极24都包括与OLED发光单元的第一电极80在垂直于衬底基板10的方向上不交叠的部分。
在该实施例中，由于目前主流的OLED阵列基板是集成有彩膜的COA基板，故上述图7中示意的各层结构还包括有彩膜层70，例如，彩膜层70在垂直于衬底基板10的方向上与OLED发光单元的第一电极80交叠。在此情况下，上述的绝缘层60可以包括覆盖驱动晶体管T3的保护层(通常简称为PAS层)61和位于保护层61上方的覆盖彩膜层70的平坦层(通常简称为OC层，Over Coat)62，例如由二者构成，从而上述的第一通孔、第二通孔均贯通这两层。
例如，在上述导电层包括有第三公共电源供给线的情况下，如图8所示，OLED阵列基板还包括覆盖导电层90和绝缘层60的层间绝缘层120；OLED发光单元的第一电极80设置在层间绝缘层120上。
在该实施例中，由于在数据线上方设置了与其重叠的第三公共电源供给线，为了保证OLED发光单元的第一电极80(即像素电极，例如可以由ITO材料制成)不与导电层90发生短路，本发明实施例进一步在导电层90与第一电极80之间设置了上述的层间绝缘层120。这样一来，可以通过减小导电层90与第一电极80之间的距离来进一步增加开口率，从而既能够减少导电层的电压降又能保证开口率的进一步增加。
例如，参考图9所示，像素单元还包括第一晶体管T1和第二晶体管T2，走线包括数据线Da、栅线G1和检测补偿线G2；第一晶体管T1的源极s1与数据线Da电连接、其漏极d1与驱动晶体管T3的栅极g3电连接、其栅极g1与栅线G1电连接；驱动晶体管T3的源极s3与导电层(参见图9中的VDD)电连接、其漏极d3与OLED发光单元的阳极(第一电极80的一个示例)和第二晶体管T2的源极s2电连接；存储电容Cst的一端与第一晶体管T1的漏极电连接、另一端与驱动晶体管T3的漏极d3电连接；OLED发光单元的阴极(第二电极82的一个示例)接地；第二晶体管T2的栅极g2与检测补偿线G2电连接。这样可以实现3T1C的外部补偿结构。该种结构可以解决oxide TFT的阈值电压(Vth)偏移及发光亮度不均一的问题。
例如，本发明实施例还提供了一种上述的OLED阵列基板的制备方法，该制备方法包括：形成多个像素单元和走线的步骤，且形成的像素单元包括OLED发光单元、驱动晶体管和存储电容；形成覆盖像素单元和走线的绝缘层的步骤；上述制备方法还包括：在绝缘层上方形成与走线、驱动晶体管和存储电容中的至少一者在垂直于该OLED阵列基板的方向上交叠的导电层，导电层用于向像素单元提供公共电压。
例如，走线为金属走线和/或导电层为金属导电层。
以图8所示的OLED阵列基板为例，例如，上述制备方法包括：在衬底基板10上形成驱动晶体管T3、存储电容以及走线，使形成的走线包括数据线；形成与数据线同层设置的数据线保留图案53；形成覆盖驱动晶体管T3、存储电容以及走线的绝缘层60，绝缘层60中还形成有露出驱动晶体管T3的漏极51的第三通孔c；在绝缘层60上方形成第一电极80和用于向像素单元提供公共电压的导电层90，使导电层90与走线、驱动晶体管T3和存储电容中的至少一者在垂直于该OLED阵列基板的方向上交叠并且通过贯通绝缘层60的第一通孔a、第二通孔b分别与驱动晶体管T3的源极50、数据线保留图案53相连接，并且使第一电极80通过第三通孔c与驱动晶体管T3的漏极51相连接；形成覆盖第一电极80和导电层90的像素界定层100；在像素界定层100的开口部分100a形成发光层81；在发光层81上形成第二电极82。在该实施例中，第一电极80、发光层81和第二电极82构成OLED发光单元；OLED发光单元、驱动晶体管和存储电容构成像素单元。
例如，存储电容Cst的上电极54例如可以与驱动晶体管T3的源极50和漏极51同层设置，存储电容Cst的下电极24可以与驱动晶体管T3的栅极20同层设置。
示例的，由于目前主流的OLED阵列基板是集成有彩膜的COA基板，在此情况下，上述的绝缘层60可以包括覆盖驱动晶体管的保护层(通常简称为PAS层)61和位于保护层61上方的覆盖彩膜层70的平坦层(通常简称为OC层，Over Coat)62，故上述制备方法的步骤例如如图10中(a)所示，在衬底基板上依次形成：包括栅极、栅线以及与栅极同层设置的数据线引线的栅金属层→栅绝缘层→有源层→刻蚀阻挡层(这里，若有源层的材料为不容易受到源漏极刻蚀影响的材料，也可以省略刻蚀阻挡层的制备步骤，具体可沿用现有技术，本发明实施例对此不作限定)→包括源极、漏极、数据线以及与数据线同层设置的数据线保留图案的源漏金属层→保护层→彩膜层→平坦层→OLED发光单元的第一电极和导电层→像素界定层→OLED发光单元的发光层→OLED发光单元的第二电极。在这些层结构中，例如，参见图10(b)，栅金属层、有源层、刻蚀阻挡层、源漏金属层、保护层、彩膜层、平坦层、第一电极、金属导电层以及像素界定层都可以采用构图工艺制作，构图工艺可以是包括曝光、显影、刻蚀等步骤的光刻工艺或者本领域常用的其它形成所需图案的工艺。
例如，在上述任一实施例的基础上，在绝缘层上方形成第一电极和导电层的步骤包括：在绝缘层上形成导电层，使形成的导电层包括大致平行于数据线的第三公共电源供给线，第三公共电源供给线与数据线在垂直于所述OLED阵列基板的方向上交叠；参考图8所示，形成覆盖导电层90的层间绝缘层120，使层间绝缘层120中形成有与第三通孔(图中标记为c)贯通的第四通孔(图中标记为d)；在层间绝缘层120上形成第一电极80，使第一电极80通过第四通孔d和第三通孔c与驱动晶体管T3的漏极51相连接。
由于在数据线上方设置了与其重叠的第三公共电源供给线，为了保证OLED发光单元的第一电极(即像素电极，例如可以由ITO材料制成)不与导电层发生短路，本发明实施例进一步在导电层与第一电极之间设置了上述的层间绝缘层。这样一来，可以通过减少导电层与第一电极之间的距离来进一步增加开口率，从而既能够减少导电层的电压降又能保证开口率的进一步 增加。
例如，在包括形成层间绝缘层120的情况下，上述制备方法的步骤例如如图11中(a)所示，在衬底基板上依次形成：包括栅极、栅线以及与栅极同层设置的数据线引线的栅金属层→栅绝缘层→有源层→刻蚀阻挡层(这里，若有源层的材料为不容易受到源漏极刻蚀影响的材料，也可以省略刻蚀阻挡层的制备步骤，具体可沿用现有技术，本发明实施例对此不作限定)→包括源极、漏极、数据线以及与数据线同层设置的数据线保留图案的源漏金属层→保护层→彩膜层→平坦层→导电层→层间绝缘层→OLED发光单元的第一电极→像素界定层→OLED发光单元的发光层→OLED发光单元的第二电极。在这些层结构中，例如，参见图11(b)，栅金属层、有源层、刻蚀阻挡层、源漏金属层、保护层、彩膜层、平坦层、金属导电层、层间绝缘层、第一电极以及像素界定层都可以采用构图工艺制作。
本发明的至少一个实施例还提供另一种阵列基板，如图12所示，该阵列基板包括：多个像素单元，每个像素单元包括发光单元(参见图12中的R、G、B、W)以及与发光单元连接的驱动晶体管T3和存储电容Cst；走线LW(如图12中的虚线所示)，其与像素单元P连接(例如与驱动晶体管T3连接)；绝缘层IL，其覆盖驱动晶体管T3、存储电容Cst和走线LW；导电层CL，其位于绝缘层IL上并且被配置为用于向像素单元提供公共电压。导电层CL包括与走线LW、驱动晶体管T3和存储电容Cst中的至少一者在垂直于阵列基板的方向上交叠的部分。图12以导电层CL与走线LW交叠为例进行说明。
例如，阵列基板包括显示区域(图12所示结构位于阵列基板的显示区域中)和位于显示区域周边的外围区域(图12中未示出)，显示区域包括分别对应于多个像素单元包括的发光单元的多个发光区域(参见R、G、B、W所在区域)以及位于多个发光区域之外的非发光区域，导电层CL的所述交叠部分位于非发光区域中。
例如，走线LW可以是栅线、数据线或检测补偿线。例如，走线LW为栅线时，走线LW可以与驱动晶体管T3的栅极连接；走线LW为数据线时，走线LW可以与驱动晶体管T3的源极或漏极连接；走线LW为检测补偿线时，走线LW可以通过另一晶体管与驱动晶体管T3的漏极连接(参见图9 所示的实施例)。
例如，发光单元可以是OLED(有机发光二极管)、LED(发光二极管)或者其它类型的主动发光元件。
例如，该阵列基板可以是OLED阵列基板，LED阵列基板或其它类型的主动发光阵列基板。
在上述任一实施例的基础上，本发明实施例还提供了一种显示装置，该显示装置包括上述的OLED阵列基板或阵列基板。
例如，上述显示装置可以是OLED显示器、OLED电视、数码相框、手机、平板电脑等具有任何显示功能的产品或者部件。
以上OLED阵列基板及其制作方法、阵列基板和显示装置的实施例可以互相参照。
在本发明实施例中，由于用于向像素单元提供公共电压的导电层设置在绝缘层上方，且与显示区域内不透光的走线、不透光的驱动晶体管和不透光的存储电容中的至少一者交叠，减少了OLED显示装置中相当于公共电源供给线的导电层占据的有效显示区域的面积，提高了开口率；由于开口率得以提高，不需要增加发光单元的发光强度来弥补像素开口率的减小对于显示装置的显示的影响，从而提高了显示装置的使用寿命。
以上所述仅是本发明的示范性实施方式，而非用于限制本发明的保护范围，本发明的保护范围由所附的权利要求确定。
本申请要求于2016年5月30日递交的中国专利申请第201610371658.2号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (17)

  1. 一种OLED阵列基板，包括：
    多个像素单元，其中，每个所述像素单元包括OLED发光单元、驱动晶体管和存储电容；
    走线；
    覆盖所述驱动晶体管、所述存储电容和所述走线的绝缘层；以及
    位于所述绝缘层上方的导电层，所述导电层被配置为用于向所述像素单元提供公共电压；
    其中，所述走线、所述驱动晶体管和所述存储电容中的至少一者与所述导电层在垂直于所述OLED阵列基板的方向上交叠。
  2. 根据权利要求1所述的OLED阵列基板，其中，
    所述走线包括连接所述像素单元与检测集成电路的检测补偿线；
    所述导电层包括平行于所述检测补偿线的第一公共电源供给线，所述第一公共电源供给线与所述检测补偿线在垂直于所述OLED阵列基板的方向上交叠。
  3. 根据权利要求1或2所述的OLED阵列基板，其中，
    所述走线包括栅线；
    所述导电层包括平行于所述栅线的第二公共电源供给线，所述第二公共电源供给线与所述栅线在垂直于所述OLED阵列基板的方向上交叠。
  4. 根据权利要求3所述的OLED阵列基板，其中，
    所述第二公共电源供给线还与所述驱动晶体管所在的区域、所述存储电容所在的区域在垂直于所述OLED阵列基板的方向上交叠。
  5. 根据权利要求1-4中任一项所述的OLED阵列基板，其中，
    所述走线包括数据线；
    所述导电层包括平行于所述数据线的第三公共电源供给线，所述第三公共电源供给线与所述数据线在垂直于所述OLED阵列基板的方向上交叠。
  6. 根据权利要求1至4中任一项所述的OLED阵列基板，其中，
    所述走线包括数据线；
    所述OLED阵列基板还包括与所述数据线同层设置的数据线保留图案；
    所述导电层通过贯通所述绝缘层的第一通孔、第二通孔分别与所述驱动晶体管的源极、所述数据线保留图案相连接。
  7. 根据权利要求6所述的OLED阵列基板，还包括衬底基板，其中，
    所述OLED发光单元包括依次远离所述衬底基板的第一电极、发光层、第二电极；
    在所述导电层包括有第三公共电源供给线的情况下，所述OLED阵列基板还包括覆盖所述导电层和所述绝缘层的层间绝缘层；
    所述第一电极设置在所述层间绝缘层上。
  8. 根据权利要求1所述的OLED阵列基板，其中，所述像素单元还包括第一晶体管和第二晶体管，所述阵列基板包括多个走线，所述多个走线包括数据线、栅线和检测补偿线；
    所述第一晶体管的源极与所述数据线电连接、其漏极与所述驱动晶体管的栅极电连接、其栅极与所述栅线电连接；
    所述驱动晶体管的源极与所述导电层电连接、其漏极与所述OLED发光单元的阳极和所述第二晶体管的源极电连接；
    所述存储电容的一端与所述第一晶体管的漏极电连接、另一端与所述驱动晶体管的漏极电连接；
    所述OLED发光单元的阴极接地；
    所述第二晶体管的栅极与所述检测补偿线电连接。
  9. 根据权利要求1-8中任一项所述的OLED阵列基板，其中，所述走线为金属走线和/或所述导电层为金属导电层。
  10. 根据权利要求1-9中任一项所述的OLED阵列基板，其中，所述阵列基板包括显示区域和位于所述显示区域周边的外围区域，所述显示区域包括分别对应于所述多个像素单元的OLED发光单元的多个发光区域和位于所述多个发光区域之外的非发光区域，所述导电层的与所述走线、所述驱动晶体管和所述存储电容中的至少一者交叠的部分至少部分地位于所述发光区域之外。
  11. 一种OLED阵列基板的制备方法，包括：
    形成走线；
    形成像素单元，其中，形成的每个所述像素单元包括OLED发光单元、 驱动晶体管和存储电容；
    形成覆盖所述像素单元和所述走线的绝缘层；以及
    在所述绝缘层上方形成与所述走线、所述驱动晶体管和所述存储电容中的至少一者在垂直于所述OLED阵列基板的方向上交叠的导电层，所述导电层用于向所述像素单元提供公共电压。
  12. 根据权利要求11所述的制备方法，其中，
    形成的所述走线包括数据线；
    形成与所述数据线同层设置的数据线保留图案；
    形成覆盖所述驱动晶体管、所述存储电容以及所述走线的绝缘层；所述导电层通过贯通所述绝缘层的第一通孔、第二通孔分别与所述驱动晶体管的源极、所述数据线保留图案相连接；所述绝缘层上还形成有露出所述驱动晶体管的漏极的第三通孔；
    在所述绝缘层上方形成第一电极和所述导电层；所述第一电极通过所述第三通孔与所述驱动晶体管的漏极相连接；
    形成覆盖所述第一电极和所述导电层的像素界定层；
    在所述像素界定层的开口部分形成发光层；
    在所述发光层上形成第二电极；
    其中，所述OLED发光单元包括所述第一电极、所述发光层和所述第二电极。
  13. 根据权利要求12所述的制备方法，其中，所述在所述绝缘层上方形成第一电极和导电层的步骤包括：
    在所述绝缘层上形成所述导电层，其中，形成的所述导电层包括平行于所述数据线的第三公共电源供给线，所述第三公共电源供给线与所述数据线在垂直于所述OLED阵列基板的方向上交叠；
    形成覆盖所述导电层的层间绝缘层，所述层间绝缘层上形成有与所述第三通孔贯通的第四通孔；
    在所述层间绝缘层上形成所述第一电极，其中，所述第一电极通过所述第四通孔和所述第三通孔与所述驱动晶体管的漏极相连接。
  14. 根据权利要求11-13中任一项所述的制备方法，其中，所述走线为金属走线和/或所述导电层为金属导电层。
  15. 一种阵列基板，包括：
    多个像素单元，其中，每个所述像素单元包括发光单元以及与所述发光单元连接的驱动晶体管和存储电容；
    走线，其与所述像素单元连接；
    绝缘层，其覆盖所述驱动晶体管、所述存储电容和所述走线；以及
    导电层，其位于所述绝缘层上并且被配置为用于向所述像素单元提供公共电压；
    其中，所述导电层包括与所述走线、所述驱动晶体管和所述存储电容中的至少一者在垂直于所述阵列基板的方向上交叠的部分。
  16. 根据权利要求15所述的阵列基板，包括显示区域和位于所述显示区域周边的外围区域，其中，所述显示区域包括分别对应于所述多个像素单元包括的发光单元的多个发光区域以及位于所述多个发光区域之外的非发光区域，所述导电层的所述部分位于所述非发光区域中。
  17. 一种显示装置，包括如权利要求1至10中的任一项所述的OLED阵列基板或者如权利要求15或16所述的阵列基板。
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