WO2017190567A1 - 阵列基板及其制造方法和显示装置 - Google Patents

阵列基板及其制造方法和显示装置 Download PDF

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Publication number
WO2017190567A1
WO2017190567A1 PCT/CN2017/078272 CN2017078272W WO2017190567A1 WO 2017190567 A1 WO2017190567 A1 WO 2017190567A1 CN 2017078272 W CN2017078272 W CN 2017078272W WO 2017190567 A1 WO2017190567 A1 WO 2017190567A1
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Prior art keywords
source
data line
drain
metal layer
layer
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English (en)
French (fr)
Inventor
刘正
张治超
陈曦
张小祥
刘明悬
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BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
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BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
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Priority to US15/560,374 priority Critical patent/US20180190795A1/en
Publication of WO2017190567A1 publication Critical patent/WO2017190567A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0316—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral bottom-gate TFTs comprising only a single gate
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6732—Bottom-gate only TFTs
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6745—Polycrystalline or microcrystalline silicon
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    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H10D86/443—Interconnections, e.g. scanning lines adapted for preventing breakage, peeling or short circuiting
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    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
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    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/471—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having different architectures, e.g. having both top-gate and bottom-gate TFTs
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    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
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    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays

Definitions

  • Embodiments of the present invention relate to the field of display technologies, and in particular, to an array substrate, a method of manufacturing the array substrate, and a display device including the array substrate.
  • the thin film transistor is an important switching element applied to the array substrate, and the thin film transistor can be divided into an oxide thin film transistor and a polysilicon thin film transistor depending on the material of the active layer.
  • the metal layer can be directly formed over the active layer, and then the metal layer is subjected to a wet engraving patterning process, thereby obtaining the source and the drain.
  • the oxide thin film transistor After forming the oxide thin film transistor, after forming the active layer, it is necessary to form an etch barrier layer over the active layer, and then form a source and a drain by etching.
  • the object of the embodiments of the present invention is at least to provide an array substrate, a method for manufacturing the array substrate, and a display device.
  • the array substrate has a new structure and meets the market requirements for diverse array substrate structures.
  • an array substrate is provided.
  • the array substrate is divided into a plurality of pixel units, and each of the pixel units is provided with a thin film transistor, and the thin film transistor includes An active layer, a passivation layer, a source and a drain disposed on the active layer, wherein the passivation layer is formed with a source via extending through the passivation layer, through the passivation a drain via of the layer and the source via a connected data line slot, the source is disposed in the source via to be connected to the active layer, and the drain is disposed in the drain via to be opposite to the active layer Connected, the data line is disposed in the data line slot to be electrically connected to the source disposed in a source via that is in communication with the data line slot.
  • the source, the drain, and an upper surface of the data line may be flush with an upper surface of the passivation layer.
  • the source may include a source diffusion prevention metal layer and a source core material, the source diffusion prevention metal layer being located between the outer surface of the source via and the source core;
  • the drain includes a drain diffusion-proof metal layer and a drain core, and the drain diffusion-proof metal layer is located between an outer surface of the drain via and the drain core;
  • the data line includes a data line anti-diffusion metal layer and a data line core material, and the data line anti-diffusion layer is located between an outer surface of the data line groove and the data line core material.
  • the material of the source core material, the drain core material and the data line core material may be copper, the source diffusion prevention metal layer, the drain diffusion prevention metal layer and the data line protection
  • the diffusion layers may each be made of molybdenum or a molybdenum alloy.
  • the array substrate may further include a pixel electrode disposed in each of the pixel units, the pixel electrode being formed on the passivation layer and electrically connected to the drain.
  • the array substrate may further include a plurality of source protection members and a plurality of data line protection members, each source electrode corresponding to one of the source protection members, and each of the data lines corresponds to one of the data line protection members.
  • the source protection member and the data line protection member are disposed in the same layer as the pixel electrode, and the source protection member, the data line protection member and the pixel electrode are made of the same material.
  • the active layer may be made of an oxide.
  • the array substrate may further include a gate electrode, a gate line and a gate insulating layer, the gate insulating layer being disposed between the layer where the gate is located and the active layer, and located under the active layer
  • the array substrate further includes a plurality of data line lower protection members, wherein the data line lower protection members are disposed in the same layer as the active layer, and each of the data lines corresponds to one of the data line lower protection members, and The protection element under the data line is located below the corresponding data line.
  • a method for fabricating an array substrate includes:
  • Forming a pattern of an active layer on a substrate the substrate being divided into a plurality of regions for forming a plurality of pixel units, each of the pixel units being formed with the active layer;
  • a source via, a drain via, and a data line trench on the passivation layer Forming a source via, a drain via, and a data line trench on the passivation layer, the source via and the drain via extending through the passivation layer, the source via and The drain via is located above the active layer to expose a portion of the upper surface of the active layer, and the data line slot is in communication with the corresponding source via;
  • the steps of forming a pattern of source, drain, and data lines may include:
  • the source includes a source diffusion-proof metal layer and a source core, and the source diffusion-proof metal layer is located between the outer surface of the source via and the source core;
  • the drain includes a drain diffusion-proof metal layer and a drain core, and the drain diffusion-proof metal layer is located between an outer surface of the drain via and the drain core;
  • the data line includes a data line anti-diffusion metal layer and a data line core material, and the data line anti-diffusion layer is located between an outer surface of the data line groove and the data line core material;
  • the steps of forming the metal layer include:
  • a portion of the diffusion-proof metal layer located in the source via is formed as the source diffusion-proof metal layer
  • the core metal layer a portion located in the source via hole is formed as the source core material
  • a portion of the diffusion prevention metal layer located in the drain via hole is formed as the drain diffusion prevention metal layer
  • the core material a portion of the metal layer located in the drain via is formed as the drain core
  • a portion of the diffusion preventing metal layer located in the data line trench is formed as the data line anti-diffusion metal layer
  • the core A portion of the layer metal layer located in the data line groove is formed as the data line core material.
  • the diffusion preventive metal layer may be made of molybdenum or a molybdenum alloy, and the core metal layer may be made of copper.
  • the metal layer may be ground by a chemical mechanical polishing method.
  • the metal layer may be ground using a slurry, which may include a mixture of abrasive particles and water.
  • the method can also include performing the patterning of the source, drain, and data lines:
  • each of the pixel units being provided with one of the pixel electrodes, the pixel electrodes being electrically connected to the drain, each The source corresponds to one of the source protection members, and each of the data lines corresponds to one of the data line protection members, and the source protection member covers the source, and the data line protects The piece covers the data line.
  • the active layer may be made of a metal oxide.
  • the manufacturing method may further include performing the step of forming a pattern of the active layer on the substrate:
  • Providing a substrate including:
  • the graphic including the active layer further includes a plurality of data line lower protection members, each of the data lines corresponding to one of the data line lower protection members, and the data line lower protection member is located below the corresponding data line .
  • the abrasive particles can include silica particles.
  • a display device includes an array substrate, wherein the array substrate is the above array substrate provided by the embodiments of the present invention.
  • Embodiments of the present invention provide an array substrate having a new structure, and the active layer of the array substrate is no longer limited by the manufacturing process.
  • FIG. 1 is a cross-sectional structural view of a portion of a substrate substrate including a thin film transistor taken along line A-A of FIG. 2 according to an embodiment of the present invention
  • FIG. 2 is a top plan view of a portion of an array substrate according to an embodiment of the present invention.
  • FIG. 3 is a view showing a substrate after a common electrode is formed when the array substrate is manufactured
  • FIG. 4 is a view showing a substrate after a pattern including a gate electrode is formed when the array substrate is manufactured
  • FIG. 5 is a view showing a substrate after forming a pattern including an active layer when the array substrate is manufactured
  • Figure 6 is a plan view of a portion of the active layer pattern
  • FIG. 7 is a schematic view showing formation of source vias and drain vias on a passivation layer when the array substrate is manufactured;
  • FIG. 8 is a view showing a substrate after a metal layer is formed at the time of fabricating an array substrate
  • FIG. 9 is a view showing a substrate after a polishing step in manufacturing an array substrate.
  • an array substrate is provided, the array substrate is divided into a plurality of pixel units, and each of the pixel units is provided with a thin film crystal
  • the thin film transistor includes an active layer 100, a passivation layer 200 disposed on the active layer 100, a source 310, and a drain 320.
  • the passivation layer 200 is formed with a passivation layer 200.
  • a source 310 is disposed in the source via to be connected to the active layer 100
  • a drain 320 is disposed in the drain via to be connected to the active layer 100.
  • a data line 330 is disposed in the data line slot to electrically connect with a corresponding source 310.
  • the thin film transistor portion of Fig. 1 is a cross-sectional view taken along line A-A of Fig. 2.
  • the correspondence of data lines to sources is also well known to those skilled in the art.
  • the source of the thin film transistor in the pixel unit of the same column may correspond to the same data line.
  • the embodiment of the present invention is not limited thereto, and the data line and the source may also have Other correspondences are not listed here.
  • a metal layer is directly disposed on the passivation layer 200, and the material of the metal layer can fill the source. Holes, drain vias, and data line slots.
  • the excess metal above the passivation layer is polished by grinding, leaving only the metal in the source via, the drain via, and the data line trench, wherein the metal layer remains in the source via.
  • the material is formed as a source, and a metal layer material remaining in the drain via is formed as a drain, and a metal layer material remaining in the data line trench is formed as a data line. It can be seen that when the metal layer is patterned to form the source, the drain and the data line, the mask is not required, and the cost can be saved.
  • the active layer 100 there is no particular limitation on the specific material for forming the active layer 100, and the active layer 100 or the oxide (for example, IGZO) may be used.
  • the active layer 100 is fabricated.
  • Embodiments of the present invention provide an array substrate having a new structure, and the active layer of the array substrate is no longer limited by the manufacturing process.
  • the source 310, the drain 320, and the The upper surface of the data line is flush with the upper surface of the passivation layer 200.
  • the orientation "upper” as used herein refers to the upper side in FIG.
  • the source, the drain, and the data lines are each made of a metal material.
  • a source, a drain, and a data line can be made using one material. It is also possible to form the source, drain and data lines by a metal layer structure having a "stacked structure" formed of a plurality of layers of different metal materials. Among them, a layer of metal in direct contact with the passivation layer 200 can be used to prevent diffusion of other layers of metal.
  • the source 310 includes a source diffusion-proof metal layer 311 and a source core 312, and the source diffusion-proof metal layer 311 is located outside the source core 312 and the source via. Between the surfaces. Specifically, an outer surface of the source via includes a sidewall and a bottom wall of the source via, that is, the source diffusion-proof metal layer 311 is directly in contact with an outer surface of the source via. The diffusion of the metal forming the source core 312 is prevented.
  • the drain 320 includes a drain diffusion-proof metal layer 321 and a drain core 322, and a drain diffusion-proof metal layer 321 is located between the outer surface of the drain via and the drain core 322.
  • an outer surface of the drain via includes a sidewall and a bottom wall of the drain via, that is, the drain diffusion-proof metal layer 321 is directly in contact with an outer surface of the drain via. The diffusion of the metal forming the drain core 322 is prevented.
  • the data line 330 includes a data line anti-diffusion metal layer 331 and a data line core material 332, and the data line anti-diffusion layer 331 is located between the outer surface of the data line groove and the data line core 332.
  • the outer surface of the data line slot includes a sidewall and a bottom wall of the data line slot, that is, the data line anti-diffusion layer 331 is directly in contact with the outer surface of the data line slot to prevent data from being formed.
  • the metal of the core material 332 is diffused.
  • the source core 312, the drain core 322, and the data line core 332 are made of a metal having better conductivity, and optionally, the source core 312, the drain core 322, and the data line core 332 Both are made of copper.
  • the source diffusion-proof metal layer 311, the drain diffusion-proof metal layer 321 and the data line diffusion-proof metal layer 331 can be made of a metal having poor diffusion performance, optionally, the source diffusion-proof metal layer 312 and the drain.
  • the extremely diffusion-proof metal layer 321 and the data line anti-diffusion layer 331 are each made of molybdenum or a molybdenum alloy.
  • the array substrate further includes a pixel electrode 410 disposed in each of the pixel units, the pixel electrode 410 being formed on the passivation layer 200 and electrically connected to the drain 320.
  • the source core member 312, the drain core member 322, and the data line core member 332 are each made of a material having good electrical conductivity.
  • the array substrate further includes a plurality of source protection members 420 and a plurality of data line protection members.
  • Each of the source electrodes 310 corresponds to one source protection member 420
  • each of the data lines 330 corresponds to one of the data line protection members, the source protection member 420 and the data line protection member and the pixel electrode 410. Same layer setting and the same material.
  • the source protection member 420 and the data line protection member are made of ITO (Indium Tin Oxide), and have better oxidation resistance, so that the source core member 312 and the data line core member 332 can be better protected. Since the pixel electrode 410 is covered over the drain core 322, it is not necessary to provide another protective layer on the drain core 322.
  • the pixel electrode layer 410 is also made of ITO.
  • the material for forming the active layer 100 is not particularly limited in the embodiment of the present invention, the active layer 100 is alternatively made of an oxide. Specifically, the active layer 100 may be made of IGZO.
  • the specific structure of the thin film transistor is not particularly limited.
  • the thin film transistor may have a bottom gate structure.
  • the array substrate includes a gate electrode 600, a gate line, and a gate insulating layer.
  • the layer 700 is disposed between the layer where the gate is located and the active layer, and is located under the active layer 100.
  • the array substrate further includes a plurality of data line lower protection members 110.
  • the data line lower protection members 110 are disposed in the same layer as the active layer 100, and each data line 330 corresponds to one data line.
  • the protection member 110 and the data line lower protection member 110 are located below the corresponding data line 330.
  • the purpose of setting the protective layer of the data line is to prevent the gate insulating layer under the data from being etched when etching the data line groove, thereby avoiding a short circuit between the gate line and the data line.
  • a method for fabricating an array substrate comprises:
  • a pattern including an active layer 100 is formed on a substrate, the substrate being divided into a plurality of regions for forming a plurality of pixel units, each of which is formed with an active source Layer 100;
  • a source via 310a, a drain via 320a and a data line trench are formed on the passivation layer 200.
  • the source via 310a and the drain via 320a both penetrate the passivation layer 200, and the source via 310a and the drain pass.
  • the hole 320a is located above the active layer 100 and exposes a part of the upper surface of the active layer 100 as shown in FIG. Wherein the data line slot is in communication with the corresponding source via 310a;
  • a pattern of source 310, drain 320 and data lines is formed, wherein source 310 is located in the source via and drain 320 is located in the drain via, as shown in FIG. And, the data line is located in the data line slot and is electrically connected to the corresponding source.
  • the above array substrate provided by the embodiment of the present invention can be obtained by the manufacturing method provided by the embodiment of the present invention.
  • the steps of forming a pattern including a source, a drain, and a data line include:
  • a metal layer 300 is formed, a portion of the material of the metal layer 300 filling the source vias, the drain vias, as shown in FIG. And, part of the material of the metal layer 300 is also filled in the data line groove;
  • the metal layer 300 is ground to remove a portion of the metal layer 300 on the upper surface of the passivation layer 200, and only the portions of the metal layer 300 that fill the source via, the drain via, and the data line trench are left.
  • a portion of the metal layer 300 filling the source via is formed as a source 310, and a portion of the metal layer 300 filling the drain via is formed as a drain 320, and the metal layer 300 is filled with the data line trench.
  • a portion in the formation is formed as the data line.
  • the source, the drain, and the data line can be obtained by grinding the metal layer 300, thereby reducing the use of the mask in the manufacturing method and reducing the cost of the manufacturing method.
  • the source 310 includes a source diffusion prevention metal layer 311 and a source core 312, and the source diffusion prevention metal layer 311 is located at the source core 312 and the source. Between the outer surfaces of the vias.
  • the drain 320 includes a drain diffusion-proof metal layer 321 and a drain core 322, and a drain diffusion-proof metal layer 321 is located between the outer surface of the drain via and the drain core 322.
  • the data line 330 includes a data line anti-diffusion metal layer 331 and a data line core material 332, and the data line anti-diffusion layer 331 is located between the outer surface of the data line groove and the data line core 332.
  • the step of forming the metal layer 300 includes:
  • a core metal layer 300b is formed.
  • a portion of the diffusion preventing metal layer located in the source via hole is formed as a source diffusion preventing metal layer 311, and the core metal layer is located
  • a portion of the source via is formed as a source core 312.
  • a portion of the diffusion preventing metal layer located in the drain via is formed as a drain diffusion preventing metal layer 321
  • a portion of the core metal layer located in the drain via is formed as a drain core 322 .
  • a portion of the diffusion preventing metal layer located in the data line groove is formed as a data line diffusion preventing metal layer 331, and a portion of the core material metal layer located in the data line groove is formed as a data line core material 332.
  • the diffusion resistant metal layer is made of molybdenum or a molybdenum alloy
  • the core metal layer is made of copper.
  • the metal layer is ground by a chemical mechanical polishing method.
  • Chemical mechanical polishing includes chemical grinding and mechanical grinding.
  • the grinding liquid may generally include H 2 O 2 , a grinding liquid, and an additive. Due to the different contact areas of the metallic material and the abrasive liquid in the groove positions such as the data line groove, the source and the drain, and the large metal position, the polishing rate will be different.
  • the polishing liquid used comprises a mixture of abrasive particles and water, wherein the abrasive particles may include silica particles.
  • the polishing liquid may further include an additive or the like which adjusts the fluidity of the polishing liquid.
  • the method comprises performing after chemical milling:
  • each of the pixel units being provided with one of the pixel electrodes, the pixel electrodes being electrically connected to the drain, each The source corresponds to one of the source protection members, and each of the data lines corresponds to one of the data line protection members, and the source protection member covers the source, and the data line protects The piece covers the data line.
  • the active layer is made of a metal oxide.
  • the method of fabrication includes prior to the step of forming a pattern comprising an active layer on a substrate:
  • the steps of providing a substrate include:
  • a gate insulating layer is formed.
  • the pattern including the active layer further includes a plurality of data line lower protection members 110, each of the data lines corresponding to one data line lower protection member 110, and the data line lower protection member 110 is located at the phase. Below the corresponding data line.
  • the substrate may include a glass substrate, a common electrode 500 formed on the glass substrate, a pattern including the gate 600 formed on the glass substrate, and a gate insulating layer covering the pattern including the gate 600.
  • the step of providing a substrate may include:
  • a gate insulating layer is formed over the pattern including the gate 600 and the pattern including the common electrode 500.
  • a display device is provided, where the display device includes an array substrate, wherein the array substrate is provided by an embodiment of the present invention.
  • the array substrate is provided by an embodiment of the present invention. The above array substrate.
  • the display device may be any product or component having a display function, such as a liquid crystal display panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as a liquid crystal display panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • the array substrate provided by the embodiment of the present invention is fabricated, after the source via, the drain via, and the data line trench are formed, a metal layer is directly disposed on the passivation layer, and a portion of the metal layer may be located at the source. Holes, drain vias, and data line slots. Next, the excess portion of the metal layer above the passivation layer is polished by the grinding method, and only the portion of the metal layer located in the source via, the drain via, and the data line trench is left to make the source via The metal layer material remaining in the source is formed as a source, and the metal layer material remaining in the drain via is formed as a drain, and the metal layer material remaining in the data line trench is formed as a data line. It can be seen that when the metal layer is patterned to form the source, the drain and the data line, the mask is not required, thereby saving cost and improving process efficiency.
  • the active layer may be made of a polysilicon material or may be made of an oxide (for example, IGZO). Source layer.

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Abstract

一种阵列基板，该阵列基板被划分为多个像素单元，每个该像素单元内均设置有薄膜晶体管，该薄膜晶体管包括有源层（100）、设置在该有源层上的钝化层（200）、源极（310）和漏极（320），该钝化层上形成有贯穿该钝化层的源极过孔、贯穿该钝化层的漏极过孔和与该源极过孔相连通的数据线槽，该源极设置在该源极过孔中，以与该有源层相连，该漏极设置在该漏极过孔中，以与该有源层相连，数据线（330）设置在该数据线槽中，以与相对应的该源极电连接。一种阵列基板的制造方法和一种显示装置，一种具有新结构的阵列基板，并且，该阵列基板的有源层不再受制造工艺的限制。

Description

阵列基板及其制造方法和显示装置 技术领域
本发明实施例涉及显示技术领域，具体地，涉及一种阵列基板、该阵列基板的制造方法和包括该阵列基板的显示装置。
背景技术
薄膜晶体管是应用于阵列基板中的重要开关元件，根据有源层材料的不同，可以将薄膜晶体管划分为氧化物薄膜晶体管和多晶硅薄膜晶体管。
在制作形成多晶硅薄膜晶体管时，形成了有源层之后，可以直接在有源层上方形成金属层，然后再对金属层进行湿刻构图工艺，从而可以获得源极和漏极。
在制作形成氧化物薄膜晶体管时，形成了有源层之后，需要在有源层上方形成刻蚀阻挡层，然后再通过刻蚀形成源极和漏极。
随着电子产品的多样化，对阵列基板的结构多样化也提出了要求，因此，如何提供一种具有新结构、便于制造的薄膜晶体管成为本领域亟待解决的技术问题。
发明内容
本发明实施例的目的至少在于提供一种阵列基板、该阵列基板的制造方法和显示装置，所述阵列基板具有一种新的结构，符合市场对阵列基板结构多样化的要求。
为了实现上述目的，作为本发明实施例的一个方面，提供一种阵列基板，所述阵列基板被划分为多个像素单元，每个所述像素单元内均设置有薄膜晶体管，所述薄膜晶体管包括有源层、设置在所述有源层上的钝化层、源极和漏极，其中，所述钝化层上形成有贯穿所述钝化层的源极过孔、贯穿所述钝化层的漏极过孔和与所述源极过孔相 连通的数据线槽，所述源极设置在所述源极过孔中，以与所述有源层相连，所述漏极设置在所述漏极过孔中，以与所述有源层相连，所述数据线设置在所述数据线槽中，以与设置在与该数据线槽相连通的源极过孔中的所述源极电连接。
所述源极、所述漏极和所述数据线的上表面可与所述钝化层的上表面平齐。
所述源极可包括源极防扩散金属层和源极芯材，所述源极防扩散金属层位于所述源极过孔的外表面和所述源极芯材之间；
所述漏极包括漏极防扩散金属层和漏极芯材，所述漏极防扩散金属层位于所述漏极过孔的外表面和所述漏极芯材之间；
所述数据线包括数据线防扩散金属层和数据线芯材，所述数据线防扩散层位于所述数据线槽的外表面和所述数据线芯材之间。
所述源极芯材、所述漏极芯材和所述数据线芯材的材料均可为铜，所述源极防扩散金属层、所述漏极防扩散金属层和所述数据线防扩散层可均由钼或者钼合金制成。
所述阵列基板还可包括设置在每个所述像素单元中的像素电极，所述像素电极形成在所述钝化层上，并与所述漏极电连接。
所述阵列基板还可包括多个源极保护件和多个数据线上保护件，每个源极对应一个所述源极保护件，每条所述数据线对应一个所述数据线上保护件，所述源极保护件和所述数据线上保护件与所述像素电极同层设置，并且所述源极保护件、所述数据线上保护件与所述像素电极的材料相同。
所述有源层可由氧化物制成。
所述阵列基板还可包括栅极、栅线和栅极绝缘层，所述栅极绝缘层设置在所述栅极所在的层和所述有源层之间，并位于所述有源层下方，所述阵列基板还包括多个数据线下保护件，所述数据线下保护件与所述有源层同层设置，每条所述数据线对应一个所述数据线下保护件，且所述数据线下保护件位于相对应的数据线的下方。
作为本发明实施例的另一个方面，提供一种阵列基板的制作方法，其中，所述制造方法包括：
在衬底上形成有源层的图形，所述衬底被划分为用于形成多个像素单元的多个区域，每个所述像素单元内均形成有所述有源层；
在包括有源层的图形上方形成钝化层；
在所述钝化层上形成源极过孔、漏极过孔和数据线槽，所述源极过孔和所述漏极过孔均贯穿所述钝化层，所述源极过孔和所述漏极过孔位于所述有源层上方以暴露出所述有源层的部分上表面，所述数据线槽与相对应的所述源极过孔相连通；
形成源极、漏极和数据线的图形，所述源极位于所述源极过孔中，所述漏极位于所述漏极过孔中，所述数据线位于所述数据线槽中，并与相应的所述源极电连接。
形成源极、漏极和数据线的图形的步骤可包括：
形成金属层，以使得所述金属层的部分位于所述源极过孔、所述漏极过孔和所述数据线槽中；
对所述金属层进行研磨，去除所述金属层中位于所述钝化层上表面上的部分，而仅保留所述金属层的位于所述源极过孔、所述漏极过孔和所述数据线槽中的部分，以使得所述金属层的位于所述源极过孔中的部分形成为所述源极、所述金属层的位于所述漏极过孔中的部分形成为所述漏极、所述金属层的位于所述数据线槽中的部分形成为所述数据线。
优选地，所述源极包括源极防扩散金属层和源极芯材，所述源极防扩散金属层位于所述源极过孔的外表面和所述源极芯材之间；
所述漏极包括漏极防扩散金属层和漏极芯材，所述漏极防扩散金属层位于所述漏极过孔的外表面和所述漏极芯材之间；
所述数据线包括数据线防扩散金属层和数据线芯材，所述数据线防扩散层位于所述数据线槽的外表面和所述数据线芯材之间；
形成金属层的步骤包括：
形成防扩散金属层；
形成芯材金属层，其中，
对所述金属层进行研磨的步骤之后，所述防扩散金属层位于所述源极过孔中的部分形成为所述源极防扩散金属层，所述芯材金属层 位于所述源极过孔中的部分形成为所述源极芯材，所述防扩散金属层位于所述漏极过孔中的部分形成为所述漏极防扩散金属层，所述芯材金属层位于所述漏极过孔中的部分形成为所述漏极芯材，所述防扩散金属层位于所述数据线槽中的部分形成为所述数据线防扩散金属层，所述芯层金属层位于所述数据线槽中的部分形成为所述数据线芯材。
所述防扩散金属层可由钼或者钼合金制成，所述芯层金属层可由铜制成。
在对所述金属层进行研磨的步骤中，可利用化学机械研磨法对所述金属层进行研磨。
可利用研磨液对所述金属层进行研磨，所述研磨液可包括研磨颗粒和水的混合物。
所述方法还可包括在形成源极、漏极和数据线的图形之后进行的：
形成像素电极、源极保护件、和数据线上保护件的图形的步骤，每个所述像素单元内均设置有一个所述像素电极，所述像素电极与所述漏极电连接，每个所述源极对应一个所述源极保护件，每条所述数据线对应一个所述数据线上保护件，所述源极保护件覆盖在所述源极的上方，所述数据线上保护件覆盖在所述数据线上方。
所述有源层可由金属氧化物制成。
所述制造方法还可包括在衬底上形成有源层的图形的步骤之前进行的：
提供衬底，包括：
提供玻璃基板；
在所述玻璃基板上形成栅极和栅线的图形；
形成栅极绝缘层；
所述包括有源层的图形还包括多个数据线下保护件，每条所述数据线对应一个所述数据线下保护件，且所述数据线下保护件位于相对应的数据线的下方。
所述研磨颗粒可包括二氧化硅颗粒。
作为本发明实施例的还一个方面，提供一种显示装置，所述显 示装置包括阵列基板，其中，所述阵列基板为本发明实施例所提供的上述阵列基板。
本发明实施例提供一种具有新结构的阵列基板，并且，该阵列基板的有源层不再受制造工艺的限制。
附图说明
附图是用来提供对本发明实施例的进一步理解，并且构成说明书的一部分，与下面的具体实施方式一起用于解释本发明，但并不构成对本发明的限制。在附图中：
图1是本发明实施例所提供的阵列基板的含有薄膜晶体管的一部分沿图2的线A-A截取的剖视结构图；
图2是本发明实施例所提供的阵列基板的一部分的俯视结构图；
图3是示出制造所述阵列基板时形成了公共电极后的衬底的示图；
图4是示出制造所述阵列基板时形成了包括栅极的图形之后的衬底的示图；
图5是示出制造所述阵列基板时形成了包括有源层的图形之后的衬底示图；
图6是部分有源层图形的俯视图；
图7是示出制造所述阵列基板时在钝化层上形成源极过孔和漏极过孔的示意图；
图8是示出在制造阵列基板时形成了金属层后的衬底的示图；
图9是示出在制造阵列基板时经过研磨步骤后的衬底的示图。
具体实施方式
以下结合附图对本发明的具体实施方式进行详细说明。应当理解的是，此处所描述的具体实施方式仅用于说明和解释本发明，并不用于限制本发明。
作为本发明实施例的一个方面，提供一种阵列基板，所述阵列基板被划分为多个像素单元，每个所述像素单元内均设置有薄膜晶体 管，所述薄膜晶体管包括有源层100、设置在该有源层100上的钝化层200、源极310和漏极320，其中，钝化层200上形成有贯穿该钝化层200的源极过孔、贯穿该钝化层200的漏极过孔和与所述源极过孔相连通的数据线槽。源极310设置在所述源极过孔中，以与有源层100相连，漏极320设置在所述漏极过孔中，以与有源层100相连。如图2所示，数据线330设置在所述数据线槽中，以与相对应的源极310电连接。
本领域技术人员容易理解的是，图1中的薄膜晶体管部分是沿着图2中的线A-A截取的剖视图。并且，数据线与源极的对应关系也是本领域技术人员所公知的。作为本发明实施例的一种实施方式，同一列像素单元中的薄膜晶体管的源极可以与同一条数据线相对应，当然，本发明实施例并不限于此，数据线和源极也可以具有其他对应关系，这里不在一一列举。
在制造本发明实施例所提供的阵列基板时，形成了源极过孔、漏极过孔和数据线槽之后，直接在钝化层200上设置金属层，金属层的材料可以填充源极过孔、漏极过孔和数据线槽中。接下来，利用研磨的方法将钝化层上方多余的金属打磨掉，而仅保留填充源极过孔、漏极过孔和数据线槽中的金属，其中，源极过孔中残留的金属层材料形成为源极，漏极过孔中残留的金属层材料形成为漏极，数据线槽中残留的金属层材料形成为数据线。由此可知，在对金属层进行图形化以形成源极、漏极和数据线时，无需用到掩模板，从而可以节约成本。
并且，在本发明实施例所提供的阵列基板中，对形成有源层100的具体材料并没有特殊的限制，既可以利用多晶硅材料制造有源层100，也可以用氧化物(例如，IGZO)制造有源层100。
本发明实施例提供一种具有新结构的阵列基板，并且，该阵列基板的有源层不再受制造工艺的限制。
为了便于通过利用研磨的方法形成源极、漏极和数据线从而获得所述阵列基板，作为本发明实施例的一种实施方式，如图1所示，源极310、漏极320和所述数据线的上表面与钝化层200的上表面平齐。此处所用到的方位“上”是指图1中的上方。
本领域技术人员容易理解的是，在阵列基板中，源极、漏极以及数据线均是由金属材料制成。可以利用一种材料制成源极、漏极和数据线。也可以用多层不同金属材料形成的具有“堆叠结构”的金属层结构制成源极、漏极和数据线。其中，与钝化层200直接接触的一层金属可以用于防止其他层金属扩散。
具体地，如图1和图2所示，源极310包括源极防扩散金属层311和源极芯材312，源极防扩散金属层311位于源极芯材312和源极过孔的外表面之间。具体地，所述源极过孔的外表面包括所述源极过孔的侧壁和底壁，也就是说，源极防扩散金属层311直接与所述源极过孔的外表面相接触，防止形成源极芯材312的金属扩散。
漏极320包括漏极防扩散金属层321和漏极芯材322，漏极防扩散金属层321位于所述漏极过孔的外表面和漏极芯材322之间。具体地，所述漏极过孔的外表面包括所述漏极过孔的侧壁和底壁，也就是说，漏极防扩散金属层321直接与所述漏极过孔的外表面相接触，防止形成漏极芯材322的金属扩散。
如图2所示，数据线330包括数据线防扩散金属层331和数据线芯材332，数据线防扩散层331位于所述数据线槽的外表面和数据线芯材332之间。具体地，所述数据线槽的外表面包括所述数据线槽的侧壁和底壁，也就是说，数据线防扩散层331的直接与所述数据线槽的外表面相接触，防止形成数据线芯材332的金属扩散。
通常，还会在数据线和源极等上方形成钝化保护层、取向层等其他功能层。通过根据本发明实施例的数据线槽的设置，能够减小数据线和源极之类的结构的整体厚度，从而更有利于在其上形成其他功能层。
通常，利用导电性能较好的金属制成源极芯材312、漏极芯材322和数据线芯材332，可选地，源极芯材312、漏极芯材322和数据线芯材332均由铜制成。相应地，可以利用扩散性能较差的金属制成源极防扩散金属层311、漏极防扩散金属层321和数据线防扩散金属层331，可选地，源极防扩散金属层312、漏极防扩散金属层321和数据线防扩散层331均由钼或者钼合金制成。
本领域技术人员容易理解的是，所述阵列基板还包括设置在每个所述像素单元中的像素电极410，该像素电极410形成在钝化层200上，并与漏极320电连接。
如上所述，源极芯材312、漏极芯材322和数据线芯材332均由导电性能较好的材料制成。为了防止制作过程中源极芯材312和数据线芯材322被氧化，可选地，如图1所示，所述阵列基板还包括多个源极保护件420和多个数据线上保护件，每个源极310对应一个源极保护件420，每条所述数据线330对应一个所述数据线上保护件，所述源极保护件420和所述数据线上保护件与像素电极410同层设置，且材料相同。
源极保护件420和数据线上保护件由ITO(氧化铟锡)制成，具有较好的抗氧化性能，从而可以对源极芯材312和数据线芯材332进行较好的保护。由于漏极芯材322的上方覆盖有像素电极410，因此，无需在漏极芯材322上设置其他的保护层。像素电极层410也由ITO制成。
虽然在本发明实施例中，对制成有源层100的材料并没有特殊的限制，可选地，有源层100由氧化物制成。具体地，有源层100可以由IGZO制成。
在本申请中，对薄膜晶体管的具体结构并没有特殊的限制，例如，所述薄膜晶体管可以具有底栅结构，如图中所示，所述阵列基板包括栅极600、栅线和栅极绝缘层700，所述栅极绝缘层设置在所述栅极所在的层和所述有源层之间，并位于有源层100下方。如图2所示，所述阵列基板还包括多个数据线下保护件110，所述数据线下保护件110与所述有源层100同层设置，每条数据线330对应一个数据线下保护件110，且数据线下保护件110位于相对应的数据线330的下方。设置数据线下保护层的目的在于，防止刻蚀形成数据线槽时将数据下方的栅极绝缘层刻穿，从而可以避免栅线和数据线之间产生短路。
作为本发明实施例的另一个方面，提供一种阵列基板的制作方 法，其中，所述制造方法包括：
如图5所示，在衬底上形成包括有源层100的图形，所述衬底被划分为用于形成多个像素单元的多个区域，每个所述像素单元内均形成有有源层100；
在包括有源层100的图形上方形成钝化层200，如图7所示；
在钝化层200上形成源极过孔310a、漏极过孔320a和数据线槽，源极过孔310a和漏极过孔320a均贯穿钝化层200，源极过孔310a和漏极过孔320a位于有源层100上方并将有源层100的部分上表面暴露出来，如图7所示。其中，所述数据线槽与相对应的源极过孔310a相连通；
形成源极310、漏极320和数据线的图形，其中，源极310位于所述源极过孔中，漏极320位于所述漏极过孔中，如图9所示。并且，所述数据线位于所述数据线槽中，并与相应的所述源极电连接。
利用本发明实施例所提供的制造方法可以得到本发明实施例所提供的上述阵列基板。
为了减少制造方法所用到的掩膜板的数量，并降低成本，可选地，形成包括源极、漏极和数据线的图形的步骤包括：
形成金属层300，该金属层300的部分材料填充所述源极过孔、所述漏极过孔中，如图8所示。并且，金属层300的部分材料还填充所述数据线槽中；
对金属层300进行研磨，去除金属层300中位于钝化层200上表面上的部分，而仅保留金属层300的填充源极过孔、漏极过孔和数据线槽中的部分，以使得金属层300的填充所述源极过孔中的部分形成为源极310、金属层300的填充所述漏极过孔中的部分形成为漏极320、金属层300的填充所述数据线槽中的部分形成为所述数据线。
通过对金属层300进行研磨即可获得源极、漏极和数据线，从而可以减少制作方法中掩膜板的使用，降低制造方法的成本。
如上文中所述，作为本发明的一种实施方式，源极310包括源极防扩散金属层311和源极芯材312，源极防扩散金属层311位于源极芯材312和所述源极过孔的外表面之间。
漏极320包括漏极防扩散金属层321和漏极芯材322，漏极防扩散金属层321位于所述漏极过孔的外表面和漏极芯材322之间。
数据线330包括数据线防扩散金属层331和数据线芯材332，数据线防扩散层331位于所述数据线槽的外表面和数据线芯材332之间。
相应地，形成金属层300的步骤包括：
形成防扩散金属层300a；
形成芯材金属层300b。
对所述金属层进行研磨的步骤中，如图9所示，所述防扩散金属层位于所述源极过孔中的部分形成为源极防扩散金属层311，所述芯材金属层位于所述源极过孔中的部分形成为源极芯材312。所述防扩散金属层位于所述漏极过孔中的部分形成为漏极防扩散金属层321，所述芯材金属层位于所述漏极过孔中的部分形成为漏极芯材322。所述防扩散金属层位于所述数据线槽中的部分形成为数据线防扩散金属层331，所述芯材金属层中位于所述数据线槽中的部分形成为数据线芯材332。
可选地，所述防扩散金属层由钼或者钼合金制成，所述芯层金属层由铜制成。
为了提高掩膜效率，优选地，在对所述金属层进行研磨的步骤中，利用化学机械研磨法对所述金属层进行研磨。
化学机械研磨包括化学研磨和机械研磨，如当源极和漏极的金属为Cu时，研磨液体通常可包括H2O2、研磨液和添加剂。由于在诸如数据线槽、源极和漏极的凹槽位置和大片金属位置，金属材料与研磨液体的接触面积不同，将导致研磨速率不一样。也就是说，在凹槽位置，金属材料的密度低，与研磨液体的接触面积小，导致该位置的金属研磨速率降低；而在非凹槽位置，由于大片金属暴露在研磨液体中，同时在机械研磨的作用下，其研磨速率远大于凹槽位置的研磨速率，因此可以保证凹槽位置不被研磨。同时由于PVX(SiNx)与金属具有一定的选择比，可以保证PVX不被研磨，从而形成如图所示的结构。
可选地，在对所述金属层进行研磨的步骤中，采用的研磨液包括研磨颗粒和水的混合物，其中，研磨颗粒可以包括二氧化硅颗粒。除此之外，研磨液还可以包括调节研磨液流动性的添加剂等。
可选地，所述方法包括在化学研磨之后进行的：
形成像素电极、源极保护件、和数据线上保护件的图形的步骤，每个所述像素单元内均设置有一个所述像素电极，所述像素电极与所述漏极电连接，每个所述源极对应一个所述源极保护件，每条所述数据线对应一个所述数据线上保护件，所述源极保护件覆盖在所述源极的上方，所述数据线上保护件覆盖在所述数据线上方。
可选地，所述有源层由金属氧化物制成。
容易理解的是，所述制造方法包括在衬底上形成包括有源层的图形的步骤之前进行的：
提供衬底的步骤，包括：
提供玻璃基板；
在玻璃基板上形成包括栅极600和栅线的图形；
形成栅极绝缘层。
相应地，如图6所示，包括有源层的图形还包括多个数据线下保护件110，每条所述数据线对应一个数据线下保护件110，且数据线下保护件110位于相对应的数据线的下方。
在本发明实施例中，衬底可以包括玻璃基板、形成在玻璃基板上的公共电极500、形成在玻璃基板上的包括栅极600的图形和覆盖包括栅极600的图形的栅极绝缘层。
因此，作为本发明实施例的一种实施方式，提供衬底的步骤可以包括：
在玻璃基板上形成包括公共电极500的图形，如图3所示；
在玻璃基板上形成包括栅极600的图形，如图4所示；
在包括栅极600的图形和包括公共电极500的图形上方形成栅极绝缘层。
作为本发明实施例的另一个方面，提供一种显示装置，所述显示装置包括阵列基板，其中，所述阵列基板为本发明实施例所提供的 上述阵列基板。
所述显示装置可以为：液晶显示面板、电子纸、OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
在制造本发明实施例所提供的阵列基板时，在形成了源极过孔、漏极过孔和数据线槽之后，直接在钝化层上设置金属层，金属层的部分可以位于源极过孔、漏极过孔和数据线槽中。接下来，利用研磨的方法将钝化层上方的金属层的多余部分打磨掉，而仅保留金属层位于源极过孔、漏极过孔和数据线槽中的部分，以使得源极过孔中残留的金属层材料形成为源极，漏极过孔中残留的金属层材料形成为漏极，数据线槽中残留的金属层材料形成为数据线。由此可知，在对金属层进行图形化以形成源极、漏极和数据线时，无需用到掩模板，从而可以节约成本并且提高工艺效率。
并且，在本发明实施例所提供的阵列基板中，对形成有源层的具体材料并没有特殊的限制，既可以利用多晶硅材料制造有源层，也可以用氧化物(例如，IGZO)制造有源层。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (19)

  1. 一种阵列基板，所述阵列基板被划分为多个像素单元，每个所述像素单元内均设置有薄膜晶体管，所述薄膜晶体管包括有源层、设置在所述有源层上的钝化层、源极和漏极，其中，所述钝化层上形成有贯穿所述钝化层的源极过孔、贯穿所述钝化层的漏极过孔和与所述源极过孔相连通的数据线槽，所述源极设置在所述源极过孔中，以与所述有源层相连，所述漏极设置在所述漏极过孔中，以与所述有源层相连，所述数据线设置在所述数据线槽中，以与设置在与该数据线槽相连通的源极过孔中的所述源极电连接。
  2. 根据权利要求1所述的阵列基板，其中，所述源极、所述漏极和所述数据线的上表面与所述钝化层的上表面平齐。
  3. 根据权利要求1所述的阵列基板，其中，所述源极包括源极防扩散金属层和源极芯材，所述源极防扩散金属层位于所述源极过孔的外表面和所述源极芯材之间；
    所述漏极包括漏极防扩散金属层和漏极芯材，所述漏极防扩散金属层位于所述漏极过孔的外表面和所述漏极芯材之间；
    所述数据线包括数据线防扩散金属层和数据线芯材，所述数据线防扩散层位于所述数据线槽的外表面和所述数据线芯材之间。
  4. 根据权利要求3所述的阵列基板，其中，所述源极芯材、所述漏极芯材和所述数据线芯材的材料均为铜，所述源极防扩散金属层、所述漏极防扩散金属层和所述数据线防扩散层均由钼或者钼合金制成。
  5. 根据权利要求1至4中任意一项所述的阵列基板，还包括设置在每个所述像素单元中的像素电极，所述像素电极形成在所述钝化层上，并与所述漏极电连接。
  6. 根据权利要求5所述的阵列基板，还包括多个源极保护件，每个源极对应一个所述源极保护件，所述源极保护件与所述像素电极同层设置，并且所述源极保护件与所述像素电极的材料相同。
  7. 根据权利要求1至4中任意一项所述的阵列基板，其中，所述有源层的材料为氧化物。
  8. 根据权利要求1至4中任意一项所述的阵列基板，还包括栅极和栅极绝缘层，所述栅极绝缘层设置在所述栅极所在的层和所述有源层之间，并位于所述有源层下方，所述阵列基板还包括多个数据线下保护件，所述数据线下保护件与所述有源层同层设置，每条所述数据线对应一个所述数据线下保护件，且所述数据线下保护件位于相对应的数据线的下方。
  9. 一种阵列基板的制作方法，包括：
    在衬底上形成有源层的图形，所述衬底被划分为用于形成多个像素单元的多个区域，每个所述像素单元内均形成有所述有源层；
    在包括有源层的图形上方形成钝化层；
    在所述钝化层上形成源极过孔、漏极过孔和数据线槽，所述源极过孔和所述漏极过孔均贯穿所述钝化层，所述源极过孔和所述漏极过孔位于所述有源层上方以暴露出所述有源层的部分上表面，所述数据线槽与相对应的所述源极过孔相连通；
    形成源极、漏极和数据线的图形，所述源极位于所述源极过孔中，所述漏极位于所述漏极过孔中，所述数据线位于所述数据线槽中，并与相应的所述源极电连接。
  10. 根据权利要求9所述的制造方法，其中，形成源极、漏极和数据线的图形的步骤包括：
    形成金属层，以使得所述金属层的部分位于所述源极过孔、所 述漏极过孔和所述数据线槽中；
    对所述金属层进行研磨，去除所述金属层中位于所述钝化层上表面上的部分，而保留所述金属层的位于所述源极过孔、所述漏极过孔和所述数据线槽中的部分，以使得所述金属层的位于所述源极过孔中的部分形成为所述源极，所述金属层的位于所述漏极过孔中的部分形成为所述漏极，所述金属层的位于所述数据线槽中的部分形成为所述数据线。
  11. 根据权利要求10所述的制造方法，其中，所述源极包括源极防扩散金属层和源极芯材，所述源极防扩散金属层位于所述源极过孔的外表面和所述源极芯材之间；
    所述漏极包括漏极防扩散金属层和漏极芯材，所述漏极防扩散金属层位于所述漏极过孔的外表面和所述漏极芯材之间；
    所述数据线包括数据线防扩散金属层和数据线芯材，所述数据线防扩散层位于所述数据线槽的外表面和所述数据线芯材之间；
    形成金属层的步骤包括：
    形成防扩散金属层；
    形成芯材金属层，其中，
    对所述金属层进行研磨的步骤之后，所述防扩散金属层位于所述源极过孔中的部分形成为所述源极防扩散金属层，所述芯材金属层位于所述源极过孔中的部分形成为所述源极芯材，所述防扩散金属层位于所述漏极过孔中的部分形成为所述漏极防扩散金属层，所述芯材金属层位于所述漏极过孔中的部分形成为所述漏极芯材，所述防扩散金属层位于所述数据线槽中的部分形成为所述数据线防扩散金属层，所述芯层金属层位于所述数据线槽中的部分形成为所述数据线芯材。
  12. 根据权利要求11所述的制造方法，其中，所述防扩散金属层由钼或者钼合金制成，所述芯层金属层由铜制成。
  13. 根据权利要求10所述的制造方法，其中，在对所述金属层 进行研磨的步骤中，利用化学机械研磨法对所述金属层进行研磨。
  14. 根据权利要求10所述的制造方法，其中，利用研磨液对所述金属层进行研磨，所述研磨液包括研磨颗粒和水的混合物。
  15. 根据权利要求9至14中任意一项所述的制造方法，还包括在形成源极、漏极和数据线的图形之后进行的：
    形成像素电极、源极保护件的图形的步骤，每个所述像素单元内均设置有一个所述像素电极，所述像素电极与所述漏极电连接，每个所述源极对应一个所述源极保护件，所述源极保护件覆盖在所述源极的上方。
  16. 根据权利要求9至14中任意一项所述的制造方法，其中，所述有源层由金属氧化物制成。
  17. 根据权利要求9至14中任意一项所述的制造方法，还包括在衬底上形成有源层的图形的步骤之前进行的：
    提供衬底，包括：
    提供玻璃基板；
    在所述玻璃基板上形成栅极的图形；
    形成栅极绝缘层；
    所述包括有源层的图形还包括多个数据线下保护件，每条所述数据线对应一个所述数据线下保护件，且所述数据线下保护件位于相对应的所述数据线的下方。
  18. 根据权利要求14所述的制造方法，其中，所述研磨颗粒包括二氧化硅颗粒。
  19. 一种显示装置，所述显示装置包括阵列基板，其中，所述阵列基板为权利要求1至8中任意一项所述的阵列基板。
PCT/CN2017/078272 2016-05-05 2017-03-27 阵列基板及其制造方法和显示装置 Ceased WO2017190567A1 (zh)

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CN110534659B (zh) * 2018-05-23 2022-09-27 昆明申北科技有限公司 顶发光oled的阳极结构、显示装置及其制造方法
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