WO2017185838A1 - 薄膜晶体管阵列基板及其制备方法、显示装置 - Google Patents

薄膜晶体管阵列基板及其制备方法、显示装置 Download PDF

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WO2017185838A1
WO2017185838A1 PCT/CN2017/071705 CN2017071705W WO2017185838A1 WO 2017185838 A1 WO2017185838 A1 WO 2017185838A1 CN 2017071705 W CN2017071705 W CN 2017071705W WO 2017185838 A1 WO2017185838 A1 WO 2017185838A1
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thin film
layer
film transistor
array substrate
transistor array
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PCT/CN2017/071705
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English (en)
French (fr)
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李梁梁
郭会斌
刘正
王守坤
冯玉春
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京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Priority to US15/547,643 priority Critical patent/US10340354B2/en
Publication of WO2017185838A1 publication Critical patent/WO2017185838A1/zh

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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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    • H01L27/1259—Multistep manufacturing methods
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
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    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • G—PHYSICS
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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
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    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • G02F1/13685—Top gates
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    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel

Definitions

  • Embodiments of the present invention relate to a thin film transistor array substrate, a method of fabricating the same, and a display device.
  • the oxide semiconductor thin film transistor has the advantages of high mobility, good stability, simple fabrication process, and the like, and an oxide semiconductor material represented by indium gallium zinc oxide (IGZO) in a thin film transistor liquid crystal display (TFT-LCD) and an active matrix organic Applications in the field of light-emitting diode panels (AMOLED) are very extensive.
  • IGZO indium gallium zinc oxide
  • TFT-LCD thin film transistor liquid crystal display
  • AMOLED active matrix organic Applications in the field of light-emitting diode panels
  • the structure of the oxide semiconductor thin film transistor mainly has three types: etch barrier type, back channel etch type and coplanar type.
  • the process of fabricating the back channel etched metal oxide IGZO thin film transistor is relatively simple, and the ratio is simple.
  • the etch-stop type lithography process can reduce the investment of equipment and improve the production efficiency. Therefore, the back channel etch type is a hot spot in the current research.
  • At least one embodiment of the present invention provides a method of fabricating a thin film transistor array substrate, comprising: forming a gate layer, a gate insulating layer, an oxide semiconductor layer, a source/drain electrode layer, and a transparent conductive layer on a base substrate.
  • Forming the source/drain electrode layer and forming the transparent conductive layer includes sequentially forming a transparent conductive film and a first metal film on the oxide semiconductor layer to form the transparent conductive film and the first metal a lamination of a thin film, the transparent conductive film is in contact with the oxide semiconductor layer; and a patterning process is performed on the lamination of the transparent conductive film and the first metal film to form a source, a drain, and a pixel electrode.
  • the material of the first metal thin film is a copper-based metal.
  • the copper-based metal is copper, copper-zinc alloy, copper-nickel alloy or copper-zinc-nickel alloy.
  • the material of the transparent conductive film includes at least one of ITO, IZO, GZO, and carbon nanotubes.
  • the material of the oxide semiconductor layer includes at least one of IGZO, IZO, ZnO, and GZO.
  • the method for fabricating a thin film transistor array substrate further includes: forming a protective layer film on the first metal film, the transparent conductive film, the first metal film, and the protection The layer film is subjected to a patterning process to form the pixel electrode, the source, the drain, and the protective layer.
  • the protective layer film includes at least one of ITO, IZO, IGZO, GZO, and a carbon nanotube conductive film.
  • the primary patterning process includes a photolithography process using a gray tone mask or a halftone mask.
  • the first patterning process includes: coating a photoresist on the first metal film; exposing and developing the photoresist Forming a photoresist full retention region, a photoresist semi-retention region, and a photoresist removal region; removing the transparent conductive film and the first metal film of the photoresist removal region by a first etching process Removing the photoresist of the semi-reserved region of the photoresist by an ashing process; removing the first metal film of the semi-reserved region of the photoresist by a second etching process to form the pixel electrode; stripping the A photoresist of a fully retained area of the photoresist forms the source and the drain.
  • the photoresist full-retention region corresponds to a region formed by the source and the drain
  • the photoresist semi-reserved region corresponds to a region formed by the pixel electrode
  • the photoresist removal region is the light
  • the first etching liquid used in the first etching process and the first etching liquid used in the second etching process each include hydrogen peroxide, and the concentration of the hydrogen peroxide in the first etching liquid is greater than the concentration of the hydrogen peroxide in the second etching liquid.
  • the thin film transistor is a bottom gate thin film transistor, which is sequentially formed before forming the pixel electrode, the source, and the drain.
  • the gate layer, the gate insulating layer, and the oxide semiconductor layer are sequentially formed before forming the pixel electrode, the source, and the drain.
  • the thin film transistor is a top gate thin film transistor, and the pixel electrode, the source, Forming the oxide semiconductor layer before the drain and the protective layer; forming the gate insulating sequentially after forming the pixel electrode, the source, the drain, and the oxide semiconductor layer a layer, the gate layer.
  • a method for fabricating a thin film transistor array substrate according to an embodiment of the present invention further includes forming a passivation layer to cover the pixel electrode, the source, the drain, the gate layer, and the gate An insulating layer and the oxide semiconductor layer.
  • the method for fabricating a thin film transistor array substrate according to an embodiment of the present invention further includes forming a common electrode on the passivation layer.
  • At least one embodiment of the present invention also provides a thin film transistor array substrate comprising: a substrate substrate; a gate layer, a gate insulating layer, and an oxide semiconductor layer disposed on the substrate; sequentially formed on the oxide a transparent conductive layer and a source/drain electrode layer on the semiconductor layer, and the transparent conductive layer is in contact with the oxide semiconductor layer.
  • the source/drain electrode layer includes a source and a drain; the transparent conductive layer includes a pixel electrode; and the source, the drain, and the pixel electrode are formed by one patterning process.
  • the material of the source/drain electrode layer is a copper-based metal.
  • the material of the oxide semiconductor layer includes at least one of IGZO, IZO, ZnO, and GZO.
  • the thin film transistor array substrate further includes: a protective layer disposed on the source and the drain, wherein the protective layer and the pixel The electrode, the source, and the drain are formed by one patterning process.
  • At least one embodiment of the present invention also provides a display device comprising the thin film transistor array substrate of any of the above.
  • FIG. 1 is a flow chart of a method for fabricating a thin film transistor array substrate according to an embodiment of the present invention
  • FIG. 2 is a schematic diagram of a method for fabricating a thin film transistor array substrate according to an embodiment of the present invention; a flow chart of a patterning process;
  • FIG. 3 is a process diagram of a method for fabricating a thin film transistor array substrate according to an embodiment of the present invention
  • FIG. 13 is a thin film transistor array substrate prepared by another preparation method according to an embodiment of the present invention.
  • FIG. 14 is a thin film transistor array substrate according to an embodiment of the invention.
  • the material of the source/drain electrode layer is a metal material, especially a copper-based metal material (for example, copper or copper alloy, etc.), a buffer layer needs to be added between the metal and the oxide semiconductor. Metal ions diffuse into the oxide semiconductor, which seriously affects the characteristics of the thin film transistor.
  • At least one embodiment of the present invention provides a method of fabricating a thin film transistor array substrate, a thin film transistor array substrate prepared by the preparation method, and a display device including the thin film transistor array substrate.
  • a method for fabricating a thin film transistor array substrate includes: forming a gate layer, a gate insulating layer, an oxide semiconductor layer, a source/drain electrode layer, and a transparent conductive layer on a base substrate, wherein the source/drain electrode layer and the transparent conductive layer are formed The steps include: sequentially forming a transparent layer on the oxide semiconductor layer a conductive film and a first metal film to form a laminate of a transparent conductive film and a first metal film, the transparent conductive film being in contact with the oxide semiconductor layer; and a patterning process for laminating the transparent conductive film and the first metal film A source, a drain, and a pixel electrode are formed.
  • the source/drain electrode layer and the transparent conductive layer including the pixel electrode are formed by one patterning process, and the transparent conductive layer also functions as a buffer layer for preventing metal ions from diffusing into the oxide semiconductor. effect.
  • the method reduces the number of patterning processes, shortens the production time, reduces the production cost, and in some embodiments, the method can also be used to improve process precision and aperture ratio.
  • the transparent conductive layer comprises a first portion where the pixel electrode is located and a second portion for preventing metal ions from diffusing into the oxide semiconductor. The two portions are formed in the same layer and simultaneously, and do not need alignment, thereby improving alignment precision; in the preparation process There is no need to reserve the alignment space, which can be used to increase the aperture ratio.
  • FIG. 1 is a flow chart of a method for fabricating a thin film transistor array substrate, including: forming a gate layer, a gate insulating layer, and an oxide on a substrate. a semiconductor layer, a source/drain electrode layer, and a transparent conductive layer.
  • the step of forming the source-drain electrode layer and the transparent conductive layer includes sequentially forming a transparent conductive film and a first metal film on the oxide semiconductor layer to form a laminate of the transparent conductive film and the first metal film, the transparent conductive film Contacting the oxide semiconductor layer; performing a patterning process on the stack of the transparent conductive film and the first metal film to form a source, a drain, and a pixel electrode.
  • the material of the first metal thin film is a copper (Cu) based metal.
  • the copper-based metal has the characteristics of low resistivity and good electrical conductivity, thereby improving the signal transmission rate of the source and the drain and improving the display quality.
  • the copper-based metal is copper (Cu), copper-zinc alloy (CuZn), copper-nickel alloy (CuNi) or copper-zinc-nickel alloy (CuZnNi), or other stable copper-based metal alloy.
  • the first metal thin film may have a thickness of 200 to 400 nm, and may be, for example, 200 nm, 230 nm, 250 nm, 300 nm, 350 nm, 380 nm, and 400 nm.
  • the material of the transparent conductive film is indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), gallium zinc oxide (GZO), carbon nanotubes, etc.
  • the material of the transparent conductive film can also be It is zinc oxide (ZnO), indium oxide (In 2 O 3 ), and aluminum zinc oxide (AZO).
  • the transparent conductive film may be deposited by magnetron sputtering and may have a thickness of 30 to 50 nm, for example, 30 nm, 40 nm or 50 nm.
  • the material of the oxide semiconductor layer is indium gallium zinc oxide (IGZO), indium zinc oxide. (IZO), zinc oxide (ZnO) or gallium zinc oxide (GZO).
  • IGZO indium gallium zinc oxide
  • IZO indium zinc oxide
  • ZnO zinc oxide
  • GZO gallium zinc oxide
  • the oxide semiconductor layer may be deposited by magnetron sputtering and may have a thickness of 30 to 50 nm, for example, 30 nm, 40 nm, and 50 nm.
  • the one-time patterning process includes a photolithography process using a gray tone mask or a halftone mask.
  • FIG. 2 is a flowchart of a patterning process in a method for fabricating a thin film transistor array substrate according to an embodiment of the present invention
  • the first patterning process includes the steps of: coating a photoresist on the first metal film; Exposing and developing the photoresist to form a photoresist full retention region, a photoresist semi-reserved region, and a photoresist removal region; removing the transparent conductive film of the photoresist removal region by using a first etching process a metal film; a photoresist for removing a semi-reserved region of the photoresist by an ashing process; removing a first metal film of the semi-reserved region of the photoresist by a second etching process to form a pixel electrode; and removing the photoresist
  • the photoresist in the region forms
  • the photoresist completely reserved region corresponds to a region where the source and the drain are formed
  • the photoresist semi-reserved region corresponds to a region formed by the pixel electrode
  • the photoresist removal region is a photoresist full retention region and a photoresist semi-reserved region. Outside the area.
  • the first etching liquid used in the first etching process and the second etching liquid used in the second etching process both include hydrogen peroxide, and the concentration of the hydrogen peroxide in the first etching liquid is greater than the second etching.
  • the concentration of hydrogen peroxide in the etchant may include hydrogen fluoride (HF), hydrogen peroxide (H 2 O 2 ), and deionized water (H 2 O).
  • the mass percentage of H 2 O 2 is 20%, the mass percentage of HF is 1%, and the mass percentage of deionized water is 79%; in the second etching In the liquid, the mass percentage of H 2 O 2 was 10%, the mass percentage of HF was 1%, and the mass percentage of deionized water was 89%.
  • the hydrogen fluoride/hydrogen peroxide etching solution may further include an etching liquid stabilizer having a mass percentage of 0.2% to 1%.
  • the etching solution stabilizer comprises: an alcohol having a mass percentage of 3% to 6%, such as 5% of an alcohol, and the alcohol may be a monohydric alcohol, a glycol or a polyhydric alcohol, for example, methanol, Ethanol, propanol, 1,4-butanediol, ethylene glycol, n-butanol, etc.; organic amines having a mass percentage of 10% to 15%, such as 13% of organic amines, such as the organic amines It may be one or more of a monoamine, a diamine and a polyamine, for example, methylamine, ethylamine, aniline, benzylamine, triethylenediamine, triethylamine, etc.; the mass percentage is 2%- a 5% sulfonic acid compound, such as a 5% sulfonic acid compound, such as one or more of an alkylsulfonic acid, an arylsulfonic acid, an amino
  • the mass percentage of H 2 O 2 is 20%, the mass percentage of HF is 1%, the mass percentage of deionized water is 78%, and the etching solution stabilizer The mass percentage is 1%; in the second etching solution, the mass percentage of H 2 O 2 is 10%, the mass percentage of HF is 1%, and the mass percentage of deionized water is 88. %, the etchant stabilizer has a mass percentage of 1%.
  • a protective layer film may be formed on the first metal film, and the protective layer film may protect the first metal film from being oxidized in a subsequent process, thereby ensuring electrical conductivity.
  • the signal transmission rate of the source and the drain formed by the signal is increased, thereby improving the display quality.
  • a transparent conductive film, a first metal film, and a protective layer film are successively deposited in this order, and then the transparent conductive film, the first metal film, and the protective layer film are subjected to a patterning process to form a pixel electrode, a source, and a drain.
  • This one-time patterning process can reduce two film formations and two etchings.
  • the method prevents the first metal film from being oxidized, prevents copper ions in the first metal film from diffusing to the oxide semiconductor layer, and also reduces production time, reduces production cost, and improves process precision and aperture ratio.
  • the material of the protective layer film is a conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), gallium zinc oxide (GZO), or carbon nanotubes.
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • IGZO indium gallium zinc oxide
  • GZO gallium zinc oxide
  • the protective layer film not only ensures that the first metal film is not oxidized, but also ensures a certain conductivity property, because the via structure formed by etching the first metal film needs to be electrically connected, so it is required to be in the via hole.
  • the structurally covered protective layer also has electrical conductivity.
  • FIG. 3 is a process diagram of a method for fabricating a thin film transistor array substrate according to an embodiment of the present invention.
  • a thin film transistor in the thin film transistor array substrate is used as a bottom gate thin film transistor as an example.
  • the gate layer 102, the gate insulating layer 103, and the oxide semiconductor layer 104 are sequentially formed on the base substrate 101 before forming the pixel electrode, the source, and the drain, for example, the formation process is as follows Said.
  • a gate metal layer (not shown) is deposited on the base substrate 101, a photoresist (not shown) is coated on the gate metal layer, and exposure, development, etching, and stripping of the photoresist are performed.
  • a pattern of the gate layer 102 is formed.
  • a gate insulating film is deposited on the base substrate 101 on which the gate layer 102 is formed, a photoresist (not shown) is coated on the gate insulating film, and exposed, developed, etched, and The process of stripping the photoresist or the like forms a pattern of the gate insulating layer 103.
  • An oxide semiconductor layer film is deposited on the base substrate 101 on which the gate insulating layer 103 of the gate layer 102 is formed, and a photoresist (not shown) is coated on the oxide semiconductor layer film, and exposed and developed. The process of etching and stripping the photoresist or the like forms a pattern of the oxide semiconductor layer 104.
  • the material of the gate metal layer may be a combination of copper and other metals, for example, copper/molybdenum (Cu/Mo), copper/titanium (Cu/Ti), copper/molybdenum titanium alloy (Cu/MoTi), copper/ Molybdenum-tungsten alloy (Cu/MoW), copper/molybdenum-niobium alloy (Cu/MoNb), etc.; the material of the gate metal layer may also be a chromium-based metal or a combination of chromium and other metals, for example, chromium/molybdenum (Cr/Mo) ), chromium/titanium (Cr/Ti), chromium/molybdenum titanium alloy (Cr/MoTi), and the like.
  • Cu/Mo copper/molybdenum
  • Cu/Ti copper/titanium
  • Cu/MoTi copper/molybdenum titanium alloy
  • Cu/MoW copper/mol
  • materials used as the gate insulating film include silicon nitride (SiN x , x is a natural number), silicon oxide (SiO x , x is a natural number), aluminum oxide (Al 2 O 3 ), and aluminum nitride (AlN). Or other suitable materials.
  • the coating of the photoresist may be by spin coating, knife coating or roll coating.
  • a transparent conductive film 106, a first metal thin film 107, and a protective layer film 109 are sequentially deposited on a base substrate 101 on which a gate layer 102, a gate insulating layer 103, and an oxide semiconductor layer 104 are sequentially formed. .
  • a photoresist 110 is coated on the protective layer film 109.
  • the photoresist 110 is exposed and developed to form a photoresist full retention region, a photoresist semi-retention region, and a photoresist removal region.
  • the transparent conductive film 106, the first metal film 107, and the protective layer film 109 of the photoresist removal region are removed by a first etching process.
  • the photoresist in the semi-reserved region of the photoresist is removed by an ashing process, and the thickness of the photoresist in the fully-retained region of the photoresist is also thinned.
  • the protective layer film 109 and the first metal thin film 107 of the photoresist semi-retained region are removed by a second etching process to form the pixel electrode 108.
  • the photoresist 110 in the fully-retained region of the photoresist is stripped to form a source electrode 1051, a drain electrode 1052, and a protective layer 1091.
  • the photoresist fully reserved region corresponds to a region formed by the source electrode 1051 and the drain electrode 1052
  • the photoresist semi-reserved region corresponds to a region formed by the pixel electrode 108
  • the photoresist removal region is a photoresist fully reserved region and a photoresist. An area outside the semi-reserved area.
  • the method for fabricating a thin film transistor array substrate in this embodiment further includes forming a passivation layer 111 to cover the pixel electrode 108, the source electrode 1051, the drain electrode 1052, the gate layer 102, and the gate insulating layer 103. And an oxide semiconductor layer 104.
  • the passivation layer 111 can function as a protection and insulation.
  • the material of the passivation layer 111 may be silicon nitride (SiN x , x is a natural number), silicon oxide (SiO x , x is a natural number), an acrylic resin, or the like.
  • the method for fabricating the thin film transistor array substrate in this embodiment further includes forming the common electrode 112 on the passivation layer 111.
  • the common electrode 112 may also be formed in a step of forming a gate layer, a source, and the like. During operation, applying a voltage to the common electrode 112 can form a capacitance with the pixel electrode 108 to deflect the liquid crystal molecules.
  • the thin film transistor in the thin film transistor array substrate is a top gate thin film transistor, and an oxide semiconductor layer is formed before forming a pixel electrode, a source, a drain, and a protective layer; and a pixel electrode, a source, a drain, and After the oxide semiconductor layer, a gate insulating layer and a gate layer are sequentially formed.
  • the thin film transistor in the thin film transistor array substrate is a top gate type thin film transistor.
  • An oxide semiconductor layer 104 is formed on the base substrate 101, and a pixel electrode 108, a source electrode 1051, a drain electrode 1052, a gate insulating layer 103, a gate layer 102, a passivation layer 111, and a common electrode are formed on the oxide semiconductor layer 104. 112.
  • a pixel electrode 108, a source electrode 1051, a drain electrode 1052, a gate insulating layer 103, a gate layer 102, a passivation layer 111, and a common electrode are formed on the oxide semiconductor layer 104. 112.
  • the above-mentioned bottom gate type thin film transistor array substrate which will not be described herein.
  • FIG. 14 is a thin film transistor array substrate according to an embodiment of the present invention.
  • the thin film transistor array substrate includes: a base substrate 101; a gate layer 102 disposed on the base substrate 101, a gate insulating layer 103, an oxide semiconductor layer 104, and a transparent conductive layer 113 sequentially formed on the oxide semiconductor layer 104.
  • a source-drain electrode layer, and the transparent conductive layer 113 is in contact with the oxide semiconductor layer 104; wherein the source-drain electrode layer includes a source electrode 1051 and a drain electrode 1052; the transparent conductive layer 113 includes a pixel electrode 108; a source electrode 1051 and a drain electrode 1052 And the pixel electrode 108 is formed by one patterning process.
  • the thin film transistor in the thin film transistor array substrate 101 may be a bottom gate thin film transistor or a top gate thin film transistor.
  • the material of the source/drain electrode layer is a copper-based metal.
  • Copper metal has the characteristics of low resistivity and good electrical conductivity, so that the signal transmission rate of the source and the drain can be improved, and the display quality can be improved.
  • the copper-based metal is copper (Cu), copper-zinc alloy (CuZn), and copper-nickel alloy (CuNi).
  • a copper-based metal alloy with stable properties such as copper-zinc-nickel alloy (CuZnNi).
  • the source/drain electrode layer may have a thickness of 200 to 400 nm, and may be, for example, 200 nm, 230 nm, 250 nm, 300 nm, 350 nm, 380 nm, and 400 nm.
  • the material of the oxide semiconductor layer 104 is indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), zinc oxide (ZnO), gallium zinc oxide (GZO), or the like.
  • the oxide semiconductor layer 104 may be deposited by magnetron sputtering, and may have a thickness of 30 to 50 nm, for example, 30 nm, 40 nm, and 50 nm.
  • the thin film transistor array substrate further includes: a protective layer 1091 disposed on the source electrode 1051 and the drain electrode 1052, wherein the protective layer 1091 and the pixel electrode 108, the source electrode 1051, and the drain electrode 1052
  • the three-layer stacked structure of the pixel electrode 108, the source electrode 1051, the drain electrode 1052, and the protective layer 1091 is formed by one patterning process, which can reduce two film formations and two etchings.
  • the three-layer laminated structure prevents oxidation of the first metal thin film, prevents diffusion of copper ions in the first metal thin film to the oxide semiconductor layer, and also reduces production time, reduces production cost, and improves process precision and opening. rate.
  • Embodiments of the present invention also provide a display device including the thin film transistor array substrate described above.
  • the display device can be any product or component having a display function, such as a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • embodiments of the present invention provide a thin film transistor array substrate, a method of fabricating the same, and a display device.
  • the source/drain electrode layer and the transparent conductive layer including the pixel electrode are formed by one patterning process, and the transparent conductive layer also prevents metal ions (especially copper ions) from being in the oxide semiconductor.
  • the role of diffusion Compared with the method of independently forming the buffer layer, the method reduces the number of patterning processes, shortens the production time, reduces the production cost, and improves the process precision and the aperture ratio.

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Abstract

薄膜晶体管阵列基板的制备方法，包括：在衬底基板(101)上形成栅极层(102)、栅绝缘层(103)、氧化物半导体层(104)、源漏电极层和像素电极层。其中，形成源漏电极层和形成像素电极层的步骤包括：在所述氧化物半导体层(104)上依次形成透明导电薄膜(106)和第一金属薄膜(107)，以形成所述透明导电薄膜和所述第一金属薄膜的叠层，所述透明导电薄膜(106)与所述氧化物半导体层(104)接触；对所述透明导电薄膜(106)和所述第一金属薄膜(107)的叠层进行一次构图工艺形成源极(1051)、漏极(1052)以及像素电极(108)。该方法可以节省一次构图工艺，缩短生产时间，降低生产成本。

Description

薄膜晶体管阵列基板及其制备方法、显示装置 技术领域
本发明的实施例涉及一种薄膜晶体管阵列基板及其制备方法、显示装置。
背景技术
氧化物半导体薄膜晶体管具有高迁移率、稳定性好、制作工艺简单等优点，以铟镓锌氧化物(IGZO)为代表的氧化物半导体材料在薄膜晶体管液晶显示器(TFT-LCD)和主动矩阵有机发光二极体面板(AMOLED)等领域的应用非常广泛。
目前，氧化物半导体薄膜晶体管的结构主要有刻蚀阻挡型、背沟道刻蚀型和共面型三种类型，制作背沟道刻蚀型金属氧化物IGZO的薄膜晶体管工艺流程比较简单，比刻蚀阻挡型少一次光刻工艺，可以减少设备的投资，提高生产效率，所以背沟道刻蚀型是现阶段研究的热点。
发明内容
本发明至少一实施例提供一种薄膜晶体管阵列基板的制备方法，包括：在衬底基板上形成栅极层、栅绝缘层、氧化物半导体层、源漏电极层和透明导电层。形成所述源漏电极层和形成所述透明导电层的步骤包括：在所述氧化物半导体层上依次形成透明导电薄膜和第一金属薄膜，以形成所述透明导电薄膜和所述第一金属薄膜的叠层，所述透明导电薄膜与所述氧化物半导体层接触；对所述透明导电薄膜和所述第一金属薄膜的叠层进行一次构图工艺形成源极、漏极以及像素电极。
例如，在本发明一实施例提供的薄膜晶体管阵列基板的制备方法中，所述第一金属薄膜的材料为铜基金属。
例如，在本发明一实施例提供的薄膜晶体管阵列基板的制备方法中，所述铜基金属为铜、铜锌合金、铜镍合金或铜锌镍合金。
例如，在本发明一实施例提供的薄膜晶体管阵列基板的制备方法中，所述透明导电薄膜的材料包括ITO、IZO、GZO和碳纳米管中的至少之一。
例如，在本发明一实施例提供的薄膜晶体管阵列基板的制备方法中，所述氧化物半导体层的材料包括IGZO、IZO、ZnO和GZO中的至少之一。
例如，本发明一实施例提供的薄膜晶体管阵列基板的制备方法，还包括：在所述第一金属薄膜上形成保护层薄膜，对所述透明导电薄膜、所述第一金属薄膜和所述保护层薄膜进行一次构图工艺形成所述像素电极、所述源极、所述漏极和保护层。
例如，在本发明一实施例提供的薄膜晶体管阵列基板的制备方法中，所述保护层薄膜包括ITO、IZO、IGZO、GZO和碳纳米管导电性薄膜中的至少之一。
例如，在本发明一实施例提供的薄膜晶体管阵列基板的制备方法中，所述一次构图工艺包括使用灰色调掩模或半色调掩模的光刻工艺。
例如，在本发明一实施例提供的薄膜晶体管阵列基板的制备方法中，所述一次构图工艺包括：在所述第一金属薄膜上涂覆光刻胶；对所述光刻胶进行曝光、显影，形成光刻胶全保留区域、光刻胶半保留区域和光刻胶去除区域；采用第一次刻蚀工艺去除所述光刻胶去除区域的所述透明导电薄膜和所述第一金属薄膜；采用灰化工艺去除所述光刻胶半保留区域的光刻胶；采用第二次刻蚀工艺去除所述光刻胶半保留区域的第一金属薄膜，形成所述像素电极；剥离所述光刻胶全保留区域的光刻胶，形成所述源极和所述漏极。所述光刻胶全保留区域对应所述源极和所述漏极形成的区域，所述光刻胶半保留区域对应所述像素电极形成的区域，所述光刻胶去除区域为所述光刻胶全保留区域和所述光刻胶半保留区域之外的区域。
例如，在本发明一实施例提供的薄膜晶体管阵列基板的制备方法中，在所述第一次刻蚀工艺中使用的第一刻蚀液和在所述第二次刻蚀工艺中使用的第二刻蚀液均包括双氧水，所述第一刻蚀液中双氧水的浓度大于所述第二刻蚀液中双氧水的浓度。
例如，在本发明一实施例提供的薄膜晶体管阵列基板的制备方法中，所述薄膜晶体管为底栅型薄膜晶体管，在形成所述像素电极、所述源极、所述漏极之前，依次形成所述栅极层、所述栅绝缘层和所述氧化物半导体层。
例如，在本发明一实施例提供的薄膜晶体管阵列基板的制备方法中，所述薄膜晶体管为顶栅型薄膜晶体管，在形成所述像素电极、所述源极、 所述漏极和所述保护层之前，形成所述氧化物半导体层；在形成所述像素电极、所述源极、所述漏极和所述氧化物半导体层之后，依次形成所述栅绝缘层、所述栅极层。
例如，本发明一实施例提供的薄膜晶体管阵列基板的制备方法，还包括，形成钝化层以覆盖所述像素电极、所述源极、所述漏极、所述栅极层、所述栅绝缘层和所述氧化物半导体层。
例如，本发明一实施例提供的薄膜晶体管阵列基板的制备方法，还包括，在所述钝化层上形成公共电极。
本发明至少一个实施例还提供一种薄膜晶体管阵列基板，包括：衬底基板；设置在所述衬底基板上的栅极层、栅绝缘层、氧化物半导体层；依次形成在所述氧化物半导体层上的透明导电层和源漏电极层，且所述透明导电层与所述氧化物半导体层接触。所述源漏电极层包括源极和漏极；所述透明导电层包括像素电极；所述源极、所述漏极以及所述像素电极通过一次构图工艺形成。
例如，在本发明一实施例提供的薄膜晶体管阵列基板中，所述源漏电极层的材料为铜基金属。
例如，在本发明一实施例提供的薄膜晶体管阵列基板中，所述氧化物半导体层的材料包括IGZO、IZO、ZnO和GZO中的至少之一。
例如，在本发明一实施例提供的薄膜晶体管阵列基板中，该薄膜晶体管阵列基板还包括：设置在所述源极和所述漏极上的保护层，其中，所述保护层与所述像素电极、所述源极、所述漏极通过一次构图工艺形成。
本发明至少一个实施例还提供一种显示装置，包括上述任一所述的薄膜晶体管阵列基板。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1为本发明一实施例提供的一种薄膜晶体管阵列基板的制备方法的流程图；
图2为本发明一实施例提供的一种薄膜晶体管阵列基板的制备方法中 一次构图工艺的流程图；
图3-图12为本发明一实施例提供的一种薄膜晶体管阵列基板的制备方法的过程图；
图13为本发明一实施例提供的另一种制备方法制备的薄膜晶体管阵列基板；
图14为本发明一实施例提供的薄膜晶体管阵列基板。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
对于氧化物半导体薄膜晶体管，如果源漏电极层的材料为金属材料，尤其是铜基金属材料(例如铜或铜合金等)，则在金属和氧化物半导体之间需要添加一层缓冲层，否则金属离子会向氧化物半导体中扩散，这样会严重影响薄膜晶体管的特性。
本发明至少一实施例提供一种薄膜晶体管阵列基板的制备方法以及用该制备方法制备的薄膜晶体管阵列基板、包含该薄膜晶体管阵列基板的显示装置。薄膜晶体管阵列基板的制备方法，包括：在衬底基板上形成栅极层、栅绝缘层、氧化物半导体层、源漏电极层和透明导电层，其中，形成源漏电极层和透明导电层的步骤包括：在氧化物半导体层上依次形成透 明导电薄膜和第一金属薄膜，以形成透明导电薄膜和第一金属薄膜的叠层，该透明导电薄膜与氧化物半导体层接触；对透明导电薄膜和第一金属薄膜的叠层进行一次构图工艺形成源极、漏极以及像素电极。
在该薄膜晶体管阵列基板制备的过程中，源漏电极层和包含像素电极的透明导电层通过一次构图工艺形成，同时该透明导电层还起到了防止金属离子向氧化物半导体中扩散的缓冲层的作用。相比于单独制备缓冲层的方法，该方法减少了一次构图工艺，缩短了生产时间，降低了生产成本，而且在一些实施例中，该方法还可以用于提高工艺精度和开口率。该透明导电层包括像素电极所在的第一部分和防止金属离子向氧化物半导体中扩散的第二部分，这两部分同层、同步形成，不需要对位，提高了对位精度；在制备工艺中，不需要预留对位空间，可以用于提高开口率。
本发明的实施例提供一种薄膜晶体管阵列基板的制备方法，例如，图1为薄膜晶体管阵列基板的制备方法的流程图，包括：在衬底基板上形成栅极层、栅绝缘层、氧化物半导体层、源漏电极层和透明导电层。这里，形成源漏电极层和透明导电层的步骤包括：在氧化物半导体层上依次形成透明导电薄膜和第一金属薄膜，以形成透明导电薄膜和第一金属薄膜的叠层，该透明导电薄膜与氧化物半导体层接触；对透明导电薄膜和第一金属薄膜的叠层进行一次构图工艺形成源极、漏极以及像素电极。
例如，该第一金属薄膜的材料为铜(Cu)基金属。铜基金属具有电阻率低、导电性好的特点，因而可以提高源极、漏极的信号传输速率，提高显示质量。
例如，该铜基金属为铜(Cu)、铜锌合金(CuZn)、铜镍合金(CuNi)或铜锌镍合金(CuZnNi)，或者其他性能稳定的铜基金属合金。
例如，该第一金属薄膜的厚度可以为200-400nm，例如，可以为200nm、230nm、250nm、300nm、350nm、380nm以及400nm。
例如，该透明导电薄膜的材料为氧化铟锡(ITO)、氧化铟锌(IZO)、氧化铟镓(IGO)、氧化镓锌(GZO)和碳纳米管等，该透明导电薄膜的材料还可以为氧化锌(ZnO)、氧化铟(In2O3)和氧化铝锌(AZO)等。
例如，该透明导电薄膜可以利用磁控溅射的方式沉积而成，其厚度可以为30-50nm，例如，可以为30nm、40nm或50nm。
例如，该氧化物半导体层的材料为氧化铟镓锌(IGZO)、氧化铟锌 (IZO)、氧化锌(ZnO)或氧化镓锌(GZO)等。
例如，该氧化物半导体层可以利用磁控溅射的方式沉积而成，其厚度可以为30-50nm，例如，可以为30nm、40nm以及50nm。
例如，该一次构图工艺包括使用灰色调掩模或半色调掩模的光刻工艺。例如，图2为本发明一实施例提供的一种薄膜晶体管阵列基板的制备方法中的一次构图工艺的流程图，该一次构图工艺包括以下步骤：在第一金属薄膜上涂覆光刻胶；对该光刻胶进行曝光、显影，形成光刻胶全保留区域、光刻胶半保留区域和光刻胶去除区域；采用第一次刻蚀工艺去除光刻胶去除区域的透明导电薄膜和第一金属薄膜；采用灰化工艺去除光刻胶半保留区域的光刻胶；采用第二次刻蚀工艺去除光刻胶半保留区域的第一金属薄膜，形成像素电极；剥离光刻胶全保留区域的光刻胶，形成源极和漏极。这里，光刻胶全保留区域对应源极和漏极形成的区域，光刻胶半保留区域对应像素电极形成的区域，光刻胶去除区域为光刻胶全保留区域和光刻胶半保留区域之外的区域。
例如，在第一次刻蚀工艺中使用的第一刻蚀液和在第二次刻蚀工艺中使用的第二刻蚀液均包括双氧水，第一刻蚀液中双氧水的浓度大于第二刻蚀液中双氧水的浓度。例如，该第一刻蚀液和该第二刻蚀液的成分可以包括氟化氢(HF)、双氧水(H2O2)和去离子水(H2O)。例如，在第一刻蚀液中，H2O2的质量百分含量为20％、HF的质量百分含量为1％、去离子水的质量百分含量为79％；在第二刻蚀液中，H2O2的质量百分含量为10％、HF的质量百分含量为1％、去离子水的质量百分含量为89％。
例如，为了克服由于双氧水分解而造成的刻蚀速度不稳定、刻蚀不均匀的问题，该氟化氢/双氧水刻蚀液还可以包括质量百分含量为0.2％-1％的刻蚀液稳定剂。例如，该刻蚀液稳定剂包括：质量百分含量为3％-6％的醇类，例如5％的醇类，该醇类可以为一元醇、二元醇或多元醇，例如，甲醇、乙醇、丙醇、1,4-丁二醇、乙二醇、正丁醇等；质量百分含量为10％-15％的有机胺类，例如13％的有机胺类，例如该有机胺类可以为一元胺、二元胺及多元胺中的一种或多种，例如，甲胺、乙胺、苯胺、苄胺、三乙烯二胺、三乙胺等；质量百分含量为2％-5％的磺酸基化合物，例如5％的磺酸基化合物，例如烷基磺酸、芳基磺酸、胺基磺酸中的一种或多种，例如，环己烷磺酸、胺基磺酸、环丙烷磺酸、环己胺磺酸及对甲苯磺酸等；质量 百分含量为40％-85％的水，例如77％的水，例如，去离子水。
例如，在第一刻蚀液中，H2O2的质量百分含量为20％、HF的质量百分含量为1％、去离子水的质量百分含量为78％、刻蚀液稳定剂的质量百分含量为1％；在第二刻蚀液中，H2O2的质量百分含量为10％、HF的质量百分含量为1％、去离子水的质量百分含量为88％、刻蚀液稳定剂的质量百分含量为1％。
例如，在一个示例中，在第一金属薄膜上还可以形成保护层薄膜，该保护层薄膜可以保护第一金属薄膜在后续工艺中不被氧化，从而保证其导电性能。提高由其形成的源极、漏极的信号传输速率，从而提高显示质量。
在该示例中，例如，依次连续沉积透明导电薄膜、第一金属薄膜和保护层薄膜，然后对该透明导电薄膜、第一金属薄膜和保护层薄膜进行一次构图工艺形成像素电极、源极、漏极和保护层的三层层叠结构。该一次构图工艺可以减少两次成膜和两次刻蚀。该方法防止了第一金属薄膜被氧化、防止了第一金属薄膜中的铜离子扩散至氧化物半导体层，同时还减少了生产时间，降低了生产成本，提高了工艺的精度和开口率。
例如，该保护层薄膜的材料为氧化铟锡(ITO)、氧化铟锌(IZO)、氧化铟镓锌(IGZO)、氧化镓锌(GZO)和碳纳米管等导电性材料。该保护层薄膜既要保证第一金属薄膜不被氧化，也要保证有一定的导电性性能，因为在刻蚀第一金属薄膜形成的过孔结构处需要被电性连接，所以要求在过孔结构上覆盖的保护层也具有导电性能。
例如，图3-图12为本发明一实施例提供的一种薄膜晶体管阵列基板的制备方法的过程图。例如，以该薄膜晶体管阵列基板中的薄膜晶体管为底栅型薄膜晶体管为例加以说明。
例如，如图3所示，在形成像素电极、源极、漏极之前，在衬底基板101上依次形成栅极层102、栅绝缘层103和氧化物半导体层104，例如，其形成过程如下所述。
在衬底基板101上沉积栅金属层(未示出)，在该栅金属层上涂覆一层光刻胶(未示出)，并进行曝光、显影、刻蚀和剥离光刻胶等过程形成栅极层102的图案。
然后，在形成有栅极层102的衬底基板101上沉积栅绝缘层薄膜，在该栅绝缘层薄膜上涂覆一层光刻胶(未示出)，并进行曝光、显影、刻蚀和 剥离光刻胶等过程形成栅绝缘层103的图案。
在形成有栅极层102栅绝缘层103的衬底基板101上沉积氧化物半导体层薄膜，在该氧化物半导体层薄膜上涂覆一层光刻胶(未示出)，并进行曝光、显影、刻蚀和剥离光刻胶等过程形成氧化物半导体层104的图案。
例如，该栅金属层的材料可以为铜与其他金属的组合，例如，铜/钼(Cu/Mo)、铜/钛(Cu/Ti)、铜/钼钛合金(Cu/MoTi)、铜/钼钨合金(Cu/MoW)、铜/钼铌合金(Cu/MoNb)等；该栅金属层的材料也可以为铬基金属或铬与其他金属的组合，例如，铬/钼(Cr/Mo)、铬/钛(Cr/Ti)、铬/钼钛合金(Cr/MoTi)等。
例如，被用作栅绝缘层薄膜的材料包括氮化硅(SiNx，x为自然数)、氧化硅(SiOx，x为自然数)、氧化铝(Al2O3)、氮化铝(AlN)或其他适合的材料。
例如，光刻胶的涂覆可以采用旋涂、刮涂或者辊涂的方式。
例如，如图4所示，在依次形成有栅极层102、栅绝缘层103和氧化物半导体层104的衬底基板101上依次沉积透明导电薄膜106、第一金属薄膜107和保护层薄膜109。
例如，如图5所示，在保护层薄膜109上涂覆光刻胶110。
例如，如图6所示，对该光刻胶110进行曝光、显影，形成光刻胶全保留区域、光刻胶半保留区域和光刻胶去除区域。
例如，如图7所示，采用第一次刻蚀工艺去除光刻胶去除区域的透明导电薄膜106、第一金属薄膜107和保护层薄膜109。
例如，如图8所示，采用灰化工艺去除光刻胶半保留区域的光刻胶，同时光刻胶全保留区域的光刻胶的厚度也变薄。
例如，如图9所示，采用第二次刻蚀工艺去除光刻胶半保留区域的保护层薄膜109和第一金属薄膜107，形成像素电极108。
例如，如图10所示，剥离光刻胶全保留区域的光刻胶110，形成源极1051、漏极1052和保护层1091。
例如，光刻胶全保留区域对应源极1051和漏极1052形成的区域，光刻胶半保留区域对应像素电极108形成的区域，光刻胶去除区域为光刻胶全保留区域和光刻胶半保留区域之外的区域。
例如，如图11所示，本实施例中薄膜晶体管阵列基板的制备方法，还 包括形成钝化层111以覆盖像素电极108、源极1051、漏极1052、栅极层102、栅绝缘层103和氧化物半导体层104。该钝化层111可以起到保护和绝缘的作用。例如，该钝化层111的材料可以为氮化硅(SiNx，x为自然数)、氧化硅(SiOx，x为自然数)、丙烯酸类树脂等。
例如，如图12所示，本实施例中薄膜晶体管阵列基板的制备方法，还包括在钝化层111上形成公共电极112。该公共电极112也可以在之前形成栅极层、源极等步骤中形成。在工作过程中，给公共电极112施加电压可以和像素电极108形成电容，让液晶分子偏转。在形成该公共电极的同时，还可以形成连接过孔结构处等断开的电路的连接电路等结构。
例如，该薄膜晶体管阵列基板中的薄膜晶体管为顶栅型薄膜晶体管，在形成像素电极、源极、漏极和保护层之前，形成氧化物半导体层；在形成像素电极、源极、漏极和氧化物半导体层之后，依次形成栅绝缘层、栅极层。
例如，如图13所示，该薄膜晶体管阵列基板中的薄膜晶体管为顶栅型薄膜晶体管。在衬底基板101上形成氧化物半导体层104，在氧化物半导体层104上形成像素电极108、源极1051、漏极1052、栅绝缘层103、栅极层102、钝化层111和公共电极112。各层结构的具体形成过程可参见上述底栅型薄膜晶体管阵列基板，在此不再赘述。
本发明的实施例还提供一种薄膜晶体管阵列基板，该薄膜晶体管阵列基板采用上述中的薄膜晶体管阵列基板的制备方法制备，例如，图14为本发明一实施例提供的薄膜晶体管阵列基板。该薄膜晶体管阵列基板包括：衬底基板101；设置在衬底基板101上的栅极层102、栅绝缘层103、氧化物半导体层104；依次形成在氧化物半导体层104上的透明导电层113和源漏电极层，且透明导电层113与氧化物半导体层104接触；其中，源漏电极层包括源极1051和漏极1052；透明导电层113包括像素电极108；源极1051、漏极1052以及像素电极108通过一次构图工艺形成。
例如，该薄膜晶体管阵列基板101中的薄膜晶体管可以是底栅型薄膜晶体管或顶栅型薄膜晶体管。
例如，该源漏电极层的材料为铜基金属。铜金属具有电阻率低、导电性好的特点，因而可以提高源极、漏极的信号传输速率，提高显示质量。
例如，该铜基金属为铜(Cu)、铜锌合金(CuZn)、铜镍合金(CuNi) 或铜锌镍合金(CuZnNi)等性能稳定的铜基金属合金。
例如，该源漏电极层的厚度可以为200-400nm，例如，可以为200nm、230nm、250nm、300nm、350nm、380nm以及400nm。
例如，该氧化物半导体层104的材料为氧化铟镓锌(IGZO)、氧化铟锌(IZO)、氧化锌(ZnO)或氧化镓锌(GZO)等。
例如，该氧化物半导体层104可以利用磁控溅射的方式沉积而成，其厚度可以为30-50nm，例如，可以为30nm、40nm以及50nm。
例如，如图14所示，该薄膜晶体管阵列基板还包括：设置在源极1051和漏极1052上的保护层1091，其中，该保护层1091与该像素电极108、源极1051、漏极1052通过一次构图工艺形成，即形成像素电极108、源极1051、漏极1052和保护层1091的三层层叠结构，该一次构图工艺可以减少两次成膜和两次刻蚀。该三层层叠结构防止了第一金属薄膜被氧化、防止了第一金属薄膜中的铜离子扩散至氧化物半导体层，同时还减少了生产时间，降低了生产成本，提高了工艺的精度和开口率。
本发明的实施例还提供一种显示装置，包括上述中的薄膜晶体管阵列基板。该显示装置可以为：液晶面板、电子纸、OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
综上所述，本发明的实施例提供一种薄膜晶体管阵列基板及其制备方法、显示装置。在该薄膜晶体管阵列基板制备过程中，源漏电极层和包含像素电极的透明导电层通过一次构图工艺形成，同时该透明导电层还起到了防止金属离子(尤其是铜离子)向氧化物半导体中扩散的作用。相比于独立形成缓冲层的方法，该方法减少了一次构图工艺，缩短了生产时间，降低了生产成本，提高了工艺精度和开口率。有以下几点需要说明：
(1)本发明实施例的附图只涉及到与本发明实施例涉及到的结构，其他结构可参考通常设计。
(2)为了清晰起见，在用于描述本发明的实施例的附图中，层或区域的厚度被放大或缩小，即这些附图并非按照实际的比例绘制。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
(3)在不冲突的情况下，本发明的实施例及实施例中的特征可以相 互组合以得到新的实施例。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，本发明的保护范围应以所述权利要求的保护范围为准。
本申请要求于2016年4月28日递交的中国专利申请第201610279966.2号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (19)

  1. 一种薄膜晶体管阵列基板的制备方法，包括：
    在衬底基板上形成栅极层、栅绝缘层、氧化物半导体层、源漏电极层，和透明导电层，其中，
    形成所述源漏电极层和形成所述透明导电层的步骤包括：
    在所述氧化物半导体层上依次形成透明导电薄膜和第一金属薄膜，以形成所述透明导电薄膜和所述第一金属薄膜的叠层，所述透明导电薄膜与所述氧化物半导体层接触；
    对所述透明导电薄膜和所述第一金属薄膜的叠层进行一次构图工艺形成源极、漏极以及像素电极。
  2. 根据权利要求1所述的薄膜晶体管阵列基板的制备方法，其中，所述第一金属薄膜的材料为铜基金属。
  3. 根据权利要求2所述的薄膜晶体管阵列基板的制备方法，其中，所述铜基金属为铜、铜锌合金、铜镍合金或铜锌镍合金。
  4. 根据权利要求1所述的薄膜晶体管阵列基板的制备方法，其中，所述透明导电薄膜的材料包括ITO、IZO、GZO和碳纳米管中的至少之一。
  5. 根据权利要求1所述的薄膜晶体管阵列基板的制备方法，其中，所述氧化物半导体层的材料包括IGZO、IZO、ZnO和GZO中的至少之一。
  6. 根据权利要求1-5中任一项所述的薄膜晶体管阵列基板的制备方法，还包括：
    在所述第一金属薄膜上形成保护层薄膜，对所述透明导电薄膜、所述第一金属薄膜和所述保护层薄膜进行一次构图工艺以形成所述像素电极、所述源极、所述漏极和保护层。
  7. 根据权利要求6所述的薄膜晶体管阵列基板的制备方法，其中，所述保护层薄膜包括ITO、IZO、IGZO、GZO和碳纳米管导电性薄膜中的至少之一。
  8. 根据权利要求1-7中任一项所述的薄膜晶体管阵列基板的制备方法，其中，所述一次构图工艺包括使用灰色调掩模或半色调掩模的光刻工艺。
  9. 根据权利要求8所述的薄膜晶体管阵列基板的制备方法，其中，所 述一次构图工艺包括：
    在所述第一金属薄膜上涂覆光刻胶；
    对所述光刻胶进行曝光、显影，形成光刻胶全保留区域、光刻胶半保留区域和光刻胶去除区域；
    采用第一次刻蚀工艺去除所述光刻胶去除区域的所述透明导电薄膜和所述第一金属薄膜；
    采用灰化工艺去除所述光刻胶半保留区域的光刻胶；
    采用第二次刻蚀工艺去除所述光刻胶半保留区域的第一金属薄膜，形成所述像素电极；
    剥离所述光刻胶全保留区域的光刻胶，形成所述源极和所述漏极；
    其中，所述光刻胶全保留区域对应所述源极和所述漏极形成的区域，所述光刻胶半保留区域对应所述像素电极形成的区域，所述光刻胶去除区域为所述光刻胶全保留区域和所述光刻胶半保留区域之外的区域。
  10. 根据权利要求9所述的薄膜晶体管阵列基板的制备方法，其中，
    在所述第一次刻蚀工艺中使用的第一刻蚀液和在所述第二次刻蚀工艺中使用的第二刻蚀液均包括双氧水，且所述第一刻蚀液中双氧水的浓度大于所述第二刻蚀液中双氧水的浓度。
  11. 根据权利要求8-10中任一项所述的薄膜晶体管阵列基板的制备方法，其中，所述薄膜晶体管为底栅型薄膜晶体管，在形成所述像素电极、所述源极、所述漏极之前，依次形成所述栅极层、所述栅绝缘层和所述氧化物半导体层。
  12. 根据权利要求8-10中任一项所述的薄膜晶体管阵列基板的制备方法，其中，所述薄膜晶体管为顶栅型薄膜晶体管，在形成所述像素电极、所述源极、所述漏极和所述保护层之前，形成所述氧化物半导体层；在形成所述像素电极、所述源极、所述漏极和所述氧化物半导体层之后，依次形成所述栅绝缘层、所述栅极层。
  13. 根据权利要求11或12所述的薄膜晶体管阵列基板的制备方法，还包括：
    形成钝化层以覆盖所述像素电极、所述源极、所述漏极、所述栅极层、所述栅绝缘层和所述氧化物半导体层。
  14. 根据权利要求13所述的薄膜晶体管阵列基板的制备方法，还包括：
    在所述钝化层上形成公共电极。
  15. 一种薄膜晶体管阵列基板，包括：
    衬底基板；
    设置在所述衬底基板上的栅极层、栅绝缘层、氧化物半导体层；
    依次形成在所述氧化物半导体层上的透明导电层和源漏电极层，且所述透明导电层与所述氧化物半导体层接触；
    其中，所述源漏电极层包括源极和漏极，所述透明导电层包括像素电极，所述源极、所述漏极以及所述像素电极通过一次构图工艺形成。
  16. 根据权利要求15所述的薄膜晶体管阵列基板，其中，所述源漏电极层的材料为铜基金属。
  17. 根据权利要求16所述的薄膜晶体管阵列基板，其中，所述氧化物半导体层的材料包括IGZO、IZO、ZnO和GZO中的至少之一。
  18. 根据权利要求15-17中任一项所述的薄膜晶体管阵列基板，还包括：设置在所述源极和所述漏极上的保护层，其中，所述保护层与所述像素电极、所述源极、所述漏极通过一次构图工艺形成。
  19. 一种显示装置，包括权利要求15-18中任一项所述的薄膜晶体管阵列基板。
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