WO2017185490A1 - 薄膜晶体管结构及其制作方法 - Google Patents

薄膜晶体管结构及其制作方法 Download PDF

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Publication number
WO2017185490A1
WO2017185490A1 PCT/CN2016/085489 CN2016085489W WO2017185490A1 WO 2017185490 A1 WO2017185490 A1 WO 2017185490A1 CN 2016085489 W CN2016085489 W CN 2016085489W WO 2017185490 A1 WO2017185490 A1 WO 2017185490A1
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Prior art keywords
doping
polysilicon
layer
thin film
film transistor
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French (fr)
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涂望华
殷婉婷
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to US15/303,047 priority Critical patent/US10217848B2/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6745—Polycrystalline or microcrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions

Definitions

  • Thin film transistor structure and manufacturing method thereof especially relates to low temperature poly (Low Temperature Poly Silicon, LTPS) The field of thin film transistors.
  • low temperature poly Low Temperature Poly Silicon, LTPS
  • LTPS thin film transistor Thin Film Transistor
  • the fabrication process of TFT is: setting substrate, light shield (LS), three-layer structure (SiNx, SiOx, polysilicon), channel doping (channel) Doping), N doping, gate insulating layer, gate electrode (gate insulating layer), P-type doping (P) Doping), interlayer dielectric (ILD), source and drain (source electrode, drain) Electrode), flat layer (PLN), bottom indium tin oxide (bottom indium tin oxide, BITO), passivation layer (PV), top indium tin oxide (top indium tin oxide, TITO).
  • the mask layer in the process also needs to be removed again after use, increasing the number of fabrication processes, masks, production time, and production costs.
  • the two doping of the polysilicon is performed using a mask, and how to reduce the use of the mask shows a technical problem to be solved.
  • Reference Chinese Patent Publication No. CN 200710122171 which is provided with a light shielding layer on the substrate at the TFT structure, however, the light shielding layer is made of metal, so there is still a need to increase the insulating layer between the light shielding layer and the TFT structure, which still increases the manufacturing process and masks. The number of molds, production time and production costs.
  • An object of the present invention is to provide a thin film transistor structure including a substrate, a light shielding resin, a polysilicon, a gate insulating layer, a gate, a dielectric layer, a source, and a drain.
  • the light shielding resin is disposed on the substrate.
  • the polysilicon is disposed on the light shielding resin.
  • the gate insulating layer is disposed on the substrate and the polysilicon.
  • the gate is disposed adjacent to the gate insulating layer.
  • the interlayer dielectric layer is disposed on the gate insulating layer and the gate.
  • the source and the drain are disposed on the interlayer dielectric layer. The source and the drain respectively connect the polysilicon through two vias.
  • the vias penetrate the inter-dielectric layer and a portion of the gate insulating layer.
  • the light-shielding resin comprises epoxy or polyurethane.
  • the thin film transistor structure further includes a flat layer and a transparent conductive layer, the flat layer is disposed on a portion of the source and the drain while covering the interlayer dielectric layer;
  • the transparent conductive layer is disposed on the flat layer and the drain of the other portion and the source.
  • the polysilicon includes a channel doping region and a two via doping region, the via doping region is in communication with the two via holes and doping is performed through the two via holes, The source and the drain are respectively connected to the via doping region at both ends of the channel doping region through two via holes.
  • An object of the present invention is to provide a method for fabricating a thin film transistor structure, comprising: first, disposing a substrate; then depositing a resin layer on the substrate, and forming a light-shielding resin using a first mask; Next, depositing a polysilicon layer and forming a polysilicon on the light-shielding resin using a second mask; first doping the polysilicon; depositing a gate insulating layer on the substrate and the a polysilicon layer; depositing a first metal layer and forming a gate over the gate insulating layer using a third mask; depositing a dielectric layer on the gate insulating layer and the gate Forming a second via to form the via via the intervening dielectric layer and a portion of the gate insulating layer; then depositing a second metal layer and forming a source using a fifth mask And a drain and a drain over the dielectric layer. The source and the drain respectively connect the polysilicon through the two vias.
  • doping the polysilicon includes first doping and second doping: the first doping is after forming the polysilicon and depositing the gate insulating layer The polysilicon is doped before; the second doping is doping the polysilicon through the two vias after forming the two vias.
  • the polysilicon is uniformly doped as a whole during the first doping.
  • the channel doping region of the polysilicon is doped, and the via doping region at both ends of the channel doping region is in the mask process. Protected without being doped.
  • the via doping region is in communication with the two vias and the second doping is performed through the two vias, and the via is through the second doping
  • the doping region is doped such that a channel doping region and a via doping region at both ends of the channel doping region are formed in the polysilicon.
  • the beneficial technical effect is that the light shielding and the insulating function are simultaneously provided by the light shielding resin, thereby reducing the arrangement of the insulating structure; and further, channel doping the polysilicon
  • the polysilicon channel (polysilicon and the region corresponding to the gate) is N-type or P-type, that is, the doping of the two ends is used to simplify the production process, simplify the exposure process, shorten the production time, reduce the use of the mask, and reduce the cost.
  • 1 to 18 are side views showing the structure of the thin film transistor of the present invention in various fabrication processes
  • 19 is a flow chart showing a method of fabricating the thin film transistor structure of the present invention.
  • FIG 18 is a side elevational view of a thin film transistor structure 100 of the present invention.
  • the thin film transistor structure 100 includes a substrate 110, a light shielding resin 120, a polysilicon 130, a gate insulating layer 140, a gate 150, a dielectric layer 160, a drain 171, a source 172, and a flat layer. 180 and a transparent conductive layer 190.
  • the light shielding resin 120 is disposed on the substrate 110.
  • the light shielding resin 120 includes an epoxy resin or a polyurethane.
  • the light-shielding resin 120 can be used not only for shielding light but also as an insulating layer.
  • the polysilicon 130 is disposed on the light shielding resin 120.
  • Polysilicon 130 is used to provide electrons and holes to conduct electricity.
  • the area of the polysilicon 130 and the light-shielding resin 120 are the same (the traveling direction of the vertical light).
  • the polysilicon 130 includes a channel doping region 133 and two via doping regions 131, 132, and the via doping regions 131, 132 are in communication with the two vias 170 and doping through the two vias 170, the source The pole 172 and the drain 171 are respectively connected to the via doping regions 131, 132 at both ends of the channel doping region 133 through the two via holes 170.
  • the gate insulating layer 140 is disposed on the substrate and the polysilicon 130.
  • the gate 150 is disposed adjacent to the gate insulating layer 140.
  • the light-shielding resin 120 is disposed in the region of the polysilicon 130 and the gate 150 for preventing the polysilicon 130 from generating a light leakage current.
  • the area of the light-shielding resin 120 is greater than or equal to the area of the polysilicon 130 (the traveling direction of the vertical light).
  • the first metal layer used to form the gate 150 may be molybdenum. 8 and 9, the gate 150 is formed by the third mask 203 acting on the first metal layer 155.
  • the gate insulating layer 140 has a high dielectric constant.
  • the dielectric layer 160 is disposed over the gate insulating layer 140 and the gate 150.
  • the inter-dielectric layer 160 completely covers the gate 150 and other regions.
  • the dielectric layer 160 is used to reduce the capacitance between the multiple layers of wires.
  • the inter-poly dielectric layer 160 of the flash memory is used in the form of a silicon oxide-silicon nitride-silicon oxide (ONO) stack layer or a silicon oxide-silicon nitride (ON) stack layer.
  • the via 170 penetrates the intervening dielectric layer 160 and a portion of the gate insulating layer 140.
  • the via holes 170 are formed in the gate insulating layer 140 and the interlayer dielectric layer 160. Since the two vias 170 are deposited with the same material as the drain 171 and the source 172, the source 171 and the drain 172 are connected to both ends of the polysilicon 130 through the two vias 170, respectively.
  • drain 171 and the source 172 are disposed over the dielectric layer 160.
  • the locations of drain 171 and source 172 can vary.
  • the second metal layer used to form the drain 171 and the source 172 may be molybdenum/aluminum/molybdenum.
  • the planarization layer 180 is disposed over a portion of the drain 171 and the source 172 while covering the intervening dielectric layer 160. In the preferred embodiment, the planarization layer 180 completely covers the source 172, however, only partially covers the drain 171.
  • the transparent conductive layer 190 is disposed on the flat layer 180 and the drain 171 and the source 172 of the other portion. In the preferred embodiment, the transparent conductive layer 190 directly covers the drain 171 that is not covered by the planarization layer 180.
  • the transparent conductive layer 190 may be indium tin oxide.
  • Doping the polysilicon 130 includes a first doping and a second doping.
  • the first doping is doping the polysilicon 130 after forming the polysilicon 130 and before depositing the gate insulating layer 140.
  • the second doping is performed by doping the two via doping regions 131, 132 in the polysilicon 130 through the two vias 170 after forming the two vias 170.
  • FIG. 19 is a flow chart showing a method of fabricating the thin film transistor structure 100 of the present embodiment. Production methods include:
  • Step S01 As shown in FIG. 1, the substrate 110 is disposed, and the substrate 110 may be a glass substrate or a transparent plastic substrate.
  • Step S02 As shown in FIG. 2, a resin layer 125 is deposited on the substrate 110. As shown in FIG. 3, the resin layer 125 is exposed and developed using the first mask 201 to etch the light-shielding resin 120.
  • Step S03 As shown in FIG. 4, a polysilicon layer 135 is deposited. As shown in FIG. 5, the polysilicon layer 135 is exposed and developed using the second mask 202 to etch only the polysilicon 130 over the light-shielding resin 120.
  • Step S04 As shown in FIG. 6-1, the polysilicon 130 is first doped using a first doping mask 208. In the preferred embodiment, the polysilicon 130 is uniformly doped as a whole.
  • the polysilicon 130 is first doped using a second doping mask 209.
  • the channel doping region 133 of the polysilicon 130 is doped, and the via doping regions 131, 132 at both ends of the channel doping region are protected from being doped during the mask process. .
  • Step S05 As shown in FIG. 7, a gate insulating layer 140 is deposited over the substrate 110 and the polysilicon 130.
  • the gate insulating layer 140 may be SiOx or SiNx or a mixture thereof.
  • Step S06 As shown in FIG. 8, the first metal layer 155 is deposited by chemical vapor deposition or vacuum evaporation. As shown in FIG. 9, the first metal layer 155 is exposed and developed using a third mask 203 to etch the gate 150 over the gate insulating layer 140.
  • the first metal layer 155 is generally made of a material such as molybdenum (Mo), aluminum (Al), and an aluminum alloy, titanium (Ti), copper (Cu), or tungsten (W).
  • Step S07 As shown in FIG. 10, the inter-dielectric layer 160 is deposited over the gate insulating layer 140 and the gate 150.
  • Step S08 as shown in FIG. 11, the intermediate dielectric layer 160 and the gate insulating layer 140 are exposed and developed using a fourth mask 204 to etch the vias 170 between the dielectric layer 160 and a portion of the gate. Insulation layer 140.
  • Step S09 As shown in FIG. 12, the polysilicon 130 is doped a second time through the two vias 170.
  • the via doping regions 131, 132 are in communication with the two vias 170 and complete the second doping through the two vias 170, and the via doping regions 131, 132 through the second doping Doping, a channel doping region 133 and via doping regions 131, 132 at both ends of the channel doping region are formed in the polysilicon 130.
  • Step S10 As shown in FIG. 13, the second metal layer 175 is deposited by chemical vapor deposition or vacuum evaporation. As shown in FIG. 14, the second metal layer 175 is exposed and developed using a fifth mask 205 to etch the drain 171 and the source 172 over the dielectric layer 160. Because the second metal layer 175 fills the two vias 170, the drain 171 and the source 172 are connected to the polysilicon 130 through the two vias 170, respectively.
  • Step S11 As shown in FIG. 15, a flat layer 180 is deposited. As shown in FIG. 16, the sixth mask 206 is used for exposure development to etch the planar layer 180 such that the planar layer 180 covers only a portion of the drain 171 and the source 172 while covering the dielectric layer. 160.
  • Step S12 As shown in FIG. 17, a transparent conductive layer 190 is deposited over the flat layer 180 and another portion of the drain 171 and the source 172.
  • Step S13 As shown in FIG. 18, the transparent conductive layer 190 may expose and develop the transparent conductive layer 190 by using the seventh mask 207 to etch a gap above the drain electrode 171.

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  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)

Abstract

一种薄膜晶体管结构（100），其包括一基板（110）、一遮光树脂（120）、一多晶硅（130）、一栅极绝缘层（140）、一栅极（150）、一间介电层（160）以及一源极（172）以及一漏极（171）。其中遮光树脂（120）同时具有遮光以及绝缘的功能，通过两端过孔掺杂，因此能简化生产工艺、简化曝光工艺、缩短生产时间、减少掩膜使用以及降低成本等技术效果。

Description

薄膜晶体管结构及其制作方法 技术领域
一种薄膜晶体管结构及其制作方法，尤涉及低温多晶硅(Low Temperature Poly Silicon, LTPS)薄膜晶体管的领域。
 背景技术
习知技术中，LTPS的薄膜晶体管(Thin Film Transistor, TFT)的制作流程为：设置基板、遮光层(light shield, LS)、三层结构(SiNx, SiOx, 多晶硅)、通道掺杂(channel doping)、N型掺杂(N doping)、栅极绝缘层以及栅极(gate electrode, gate insulating layer)、P型掺杂(P Doping)、间绝缘层(interlayer dielectric, ILD)、源极及漏极(source electrode, drain electrode)、平坦层(planar, PLN)、底层氧化铟锡(bottom indium tin oxide, BITO)、钝化层(passivation layer, PV)、顶层氧化铟锡(top indium tin oxide, TITO)。过程中的遮光层在使用后也需要再次移除，增加了制作工艺、掩模的数量、生产时间以及生产成本。
现有技术中，对所述多晶硅的两次掺杂都是使用掩模进行的，如何减少掩模的使用示一个需要解决的技术问题。
参考中国专利公开号 CN 200710122171，其在基板上于TFT结构处设置遮光层，然而所述遮光层是由金属制成，因此所述遮光层与所述TFT结构之间仍旧需要增加绝缘层，仍旧增加了制作工艺、掩模的数量、生产时间以及生产成本。
故，有必要提供一种薄膜晶体管结构及其制作方法，以解决上述问题。
 技术问题
本发明的一目的在于提供一种薄膜晶体管结构，其包括一基板、一遮光树脂、一多晶硅、一栅极绝缘层、一栅极、一间介电层以及一源极以及一漏极。
 技术解决方案
所述遮光树脂，设置于所述基板之上。所述多晶硅，设置于所述遮光树脂之上。所述栅极绝缘层,设置于所述基板以及所述多晶硅之上。所述栅极,紧靠所述栅极绝缘层设置。所述间介电层，设置于所述栅极绝缘层以及所述栅极之上。所述源极以及所述漏极，设置于所述间介电层之上。所述源极以及所述漏极分别通过二过孔连接所述多晶硅。
在一优选实施例中，所述过孔贯通所述间介电层以及部份的所述栅极绝缘层。
在一优选实施例中，所述遮光树脂包括环氧树脂或聚氨脂。
在一优选实施例中，所述薄膜晶体管结构还包括一平坦层和一透明导电层，平坦层设置于一部分的所述源极以及所述漏极之上，同时覆盖所述间介电层；所述透明导电层设置于所述平坦层以及另一部分的所述漏极以及所述源极之上。
在一优选实施例中，所述多晶硅包括通道掺杂区和二过孔掺杂区，所述过孔掺杂区与所述二过孔连通并通过所述二过孔完成掺杂，所述源极以及所述漏极分别通过二过孔与位于所述通道掺杂区的两端的所述过孔掺杂区连接。
本发明的一目的在于提供一种薄膜晶体管结构的制作方法，其包括：首先，设置一基板；接着，沉积一树脂层于所述基板之上，并使用一第一掩膜形成一遮光树脂；接着，沉积一多晶硅层，并使用一第二掩膜仅形成一多晶硅于所述遮光树脂之上；对所述多晶硅进行第一次掺杂；沉积一栅极绝缘层于所述基板以及所述多晶硅之上；沉积一第一金属层，并使用一第三掩膜形成一栅极于所述栅极绝缘层之上；沉积一间介电层于所述栅极绝缘层以及所述栅极之上；使用一第四掩膜形成二过孔于所述间介电层以及部份的所述栅极绝缘层；接着，沉积一第二金属层，并使用一第五掩膜形成一源极以及一漏极于所述间介电层之上。所述源极以及所述漏极分别通过所述二过孔连接所述多晶硅。
在一优选实施例中，对所述多晶硅进行掺杂包括第一次掺杂和第二次掺杂：所述第一次掺杂是在形成所述多晶硅后且在沉积所述栅极绝缘层之前对所述多晶硅掺杂；所述第二次掺杂是在形成所述二过孔后通过所述二过孔对所述多晶硅掺杂。
在一优选实施例中，在所述第一次掺杂过程中，所述多晶硅整体被均匀掺杂。
在一优选实施例中，在所述第一次掺杂过程中，所述多晶硅的通道掺杂区被掺杂，而位于所述通道掺杂区两端的过孔掺杂区在光罩制程中受到保护而未被掺杂。
在一优选实施例中，所述过孔掺杂区与所述二过孔连通并通过所述二过孔完成所述第二次掺杂，通过所述第二次掺杂对所述过孔掺杂区掺杂，使所述多晶硅中形成了通道掺杂区和位于所述通道掺杂区两端的过孔掺杂区。
 有益效果
因此通过本发明的技术方案，产生的有益技术效果在于，藉由所述遮光树脂同时具有遮光以及绝缘的功能，减少了一层绝缘结构的设置；此外，对所述多晶硅进行通道掺杂使所述多晶硅通道（多晶硅与与栅极对应的区域）成为N型或P型，即，通过两端过孔掺杂进而简化生产工艺、简化曝光工艺、缩短生产时间、减少掩膜使用以及降低成本等技术效果。
 附图说明
图1-图18绘示本发明的薄膜晶体管结构的在各个制作工艺的侧视图；
图19绘示本发明的薄膜晶体管结构的制作方法的流程图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
参考图18，图18是本发明的薄膜晶体管结构100的侧视图。薄膜晶体管结构100包括一基板110、一遮光树脂120、一多晶硅130、一栅极绝缘层140、一栅极150、一间介电层160、一漏极171、一源极172、一平坦层180以及一透明导电层190。
遮光树脂120设置于基板110之上。详细地，遮光树脂120包括环氧树脂或聚氨脂。遮光树脂120不仅可以用于遮蔽光线，还可以作为绝缘层。
多晶硅130设置于遮光树脂120之上。多晶硅130是用于提供电子以及空穴来导电。详细地，多晶硅130与遮光树脂120的面积大小相同(垂直光线的行进方向)。所述多晶硅130包括通道掺杂区133和二过孔掺杂区131,132，所述过孔掺杂区131,132与所述二过孔170连通并通过所述二过孔170完成掺杂，所述源极172以及所述漏极171分别通过二过孔170与位于所述通道掺杂区133的两端的所述过孔掺杂区131,132连接。
栅极绝缘层140设置于基板以及多晶硅130之上。栅极150紧靠栅极绝缘层140设置。详细地，遮光树脂120设置于多晶硅130以及栅极150的区域，用于避免多晶硅130产生光漏电流。换句话说，遮光树脂120的面积大于或等于多晶硅130的面积(垂直光线的行进方向)。用于形成栅极150的第一金属层可以是钼。结合图8和图9，栅极150是利用第三掩膜203对第一金属层155作用所形成。栅极绝缘层140具有高介电系数。
间介电层160设置于栅极绝缘层140以及栅极150之上。详细地，间介电层160完整的覆盖了栅极150以及其他区域。间介电层160是用于降低多层导线间之电容值。一般而言，会以氧化硅-氮化硅-氧化硅(ONO)堆栈层或氧化硅-氮化硅(ON)堆栈层的形式来作为闪存的多晶硅间介电层160。
过孔170贯通间介电层160以及部份的栅极绝缘层140。详细地，因为在栅极绝缘层140以及间介电层160中形成了二过孔170。因为二过孔170与漏极171以及源极172沉积了相同的材料，源极171以及漏极172分别通过二过孔170连接多晶硅130的两端。
在本优选实施例中，漏极171以及源极172设置于间介电层160之上。然而，在不同的优选实施例中，漏极171以及源极172的位置可以改变。用于形成漏极171以及源极172的第二金属层可以是钼/铝/钼。
平坦层180设置于一部分的漏极171以及源极172之上，同时覆盖间介电层160。在本优选实施例中，平坦层180完整地覆盖源极172，然而，仅部分地覆盖漏极171。
透明导电层190设置于平坦层180以及另一部分的漏极171以及源极172之上。在本优选实施例中，透明导电层190直接覆盖了未被平坦层180所覆盖的漏极171。透明导电层190可以是氧化铟锡。
对所述多晶硅130进行掺杂包括第一次掺杂和第二次掺杂。所述第一次掺杂是在形成所述多晶硅130后且在沉积所述栅极绝缘层140之前对所述多晶硅130掺杂。所述第二次掺杂是在形成所述二过孔170后通过所述二过孔170对所述多晶硅130内的二过孔掺杂区131,132掺杂。
请参阅图1-图19，图1-图18绘示本发明的薄膜晶体管结构的在各个制作工艺的侧视图。图19绘示制作本实施例的薄膜晶体管结构100的方法流程图。制作方法包括：
步骤S01：如图1所示，设置基板110，基板110可以为玻璃基材或透明塑料基材。
步骤S02：如图2所示，沉积树脂层125于基板110之上。如图3所示，使用第一掩膜201对树脂层125进行曝光显影，以蚀刻出遮光树脂120
步骤S03：如图4所示，沉积多晶硅层135。如图5所示，使用第二掩膜202对多晶硅层135进行曝光显影，以仅蚀刻出多晶硅130于遮光树脂120之上。
步骤S04：如图6-1所示，使用一第一掺杂掩膜208对多晶硅130进行第一次掺杂。在本较佳实施例中，所述多晶硅130整体被均匀掺杂。
在另一较佳实施例中，如图6-2所示，使用一第二掺杂掩膜209对多晶硅130进行第一次掺杂。在本较佳实施例中，所述多晶硅130的通道掺杂区133被掺杂，而位于所述通道掺杂区两端的过孔掺杂区131,132在光罩制程中受到保护而未被掺杂。
步骤S05：如图7所示，沉积栅极绝缘层140于基板110以及多晶硅130之上。栅极绝缘层140可以是SiOx或SiNx或是其混合物。
步骤S06：如图8所示，以化学气相沉积或是真空蒸镀等方法沉积第一金属层155。如图9所示，使用第三掩膜203对第一金属层155进行曝光显影，以蚀刻出栅极150于栅极绝缘层140之上。第一金属层155一般采用钼(Mo)、铝(Al)以及铝合金、钛(Ti)、铜(Cu)或钨(W)等材料制作。
步骤S07：如图10所示，沉积间介电层160于栅极绝缘层140以及栅极150之上。
步骤S08：如图11所示，使用第四掩膜204对间介电层160以及栅极绝缘层140进行曝光显影，以蚀刻出二过孔170于间介电层160以及部份的栅极绝缘层140。
步骤S09：如图12所示，通过二过孔170对多晶硅130进行第二次掺杂。所述过孔掺杂区131,132与所述二过孔170连通并通过所述二过孔170完成所述第二次掺杂，通过所述第二次掺杂对所述过孔掺杂区131,132掺杂，使所述多晶硅130中形成了通道掺杂区133和位于所述通道掺杂区两端的过孔掺杂区131,132。
步骤S10：如图13所示，以化学气相沉积或是真空蒸镀等方法沉积第二金属层175。如图14所示，使用第五掩膜205对第二金属层175进行曝光显影，以蚀刻出漏极171以及源极172于间介电层160之上。因为第二金属层175填满了二过孔170，漏极171以及源极172分别通过二过孔170连接多晶硅130。
步骤S11：如图15所示，沉积平坦层180。如图16所示，使用第六掩膜206进行曝光显影，以蚀刻所述平坦层180，令平坦层180仅覆盖于于一部分的漏极171以及源极172之上，同时覆盖间介电层160。
步骤S12：如图17所示，沉积透明导电层190于平坦层180以及另一部分的漏极171以及源极172之上。
步骤S13：如图18所示，透明导电层190可以利用第七掩膜207对透明导电层190进行曝光显影，以蚀刻出在漏极171之上的一个缺口。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (15)

  1. 一种薄膜晶体管结构，包括：
    一基板；
    一遮光树脂，设置于所述基板之上；
    一多晶硅，设置于所述遮光树脂之上；
    一栅极绝缘层,设置于所述基板以及所述多晶硅之上；
    一栅极,紧靠所述栅极绝缘层设置；
    一间介电层，设置于所述栅极绝缘层以及所述栅极之上；以及
    一源极以及一漏极，设置于所述间介电层之上；
    其中所述源极以及所述漏极分别通过二过孔连接所述多晶硅，所述多晶硅包括通道掺杂区和二过孔掺杂区，所述过孔掺杂区与所述二过孔连通并通过所述二过孔完成掺杂，所述源极以及所述漏极分别通过二过孔与位于所述通道掺杂区的两端的所述过孔掺杂区连接。
  2. 根据权利要求1的薄膜晶体管结构，其中所述过孔贯通所述间介电层以及部份的所述栅极绝缘层。
  3. 根据权利要求1的薄膜晶体管结构，其中所述遮光树脂包括环氧树脂或聚氨脂。
  4. 根据权利要求1的薄膜晶体管结构，其中所述薄膜晶体管结构还包括一平坦层和一透明导电层，平坦层设置于一部分的所述漏极以及所述源极之上，同时覆盖所述间介电层；所述透明导电层设置于所述平坦层以及另一部分的所述漏极以及所述源极之上。
  5. 一种薄膜晶体管结构，包括：
    一基板；
    一遮光树脂，设置于所述基板之上；
    一多晶硅，设置于所述遮光树脂之上；
    一栅极绝缘层,设置于所述基板以及所述多晶硅之上；
    一栅极,紧靠所述栅极绝缘层设置；
    一间介电层，设置于所述栅极绝缘层以及所述栅极之上；以及
    一源极以及一漏极，设置于所述间介电层之上；
    其中，所述源极以及所述漏极分别通过二过孔连接所述多晶硅。
  6. 根据权利要求5的薄膜晶体管结构，其中所述过孔贯通所述间介电层以及部份的所述栅极绝缘层。
  7. 根据权利要求5的薄膜晶体管结构，其中所述遮光树脂包括环氧树脂或聚氨脂。
  8. 根据权利要求5的薄膜晶体管结构，其中所述薄膜晶体管结构还包括一平坦层和一透明导电层，平坦层设置于一部分的所述漏极以及所述源极之上，同时覆盖所述间介电层；所述透明导电层设置于所述平坦层以及另一部分的所述漏极以及所述源极之上。
  9. 根据权利要求5的薄膜晶体管结构，其中所述多晶硅包括通道掺杂区和二过孔掺杂区，所述过孔掺杂区与所述二过孔连通并通过所述二过孔完成掺杂，所述源极以及所述漏极分别通过二过孔与位于所述通道掺杂区的两端的所述过孔掺杂区连接。
  10. 一种薄膜晶体管结构的制作方法，其中包括：
    设置一基板；
    沉积一树脂层于所述基板之上，并使用一第一掩膜形成一遮光树脂；
    沉积一多晶硅层，并使用一第二掩膜仅形成一多晶硅于所述遮光树脂之上；
    对所述多晶硅进行第一次掺杂；
    沉积一栅极绝缘层于所述基板以及所述多晶硅之上；
    沉积一第一金属层，并使用一第三掩膜形成一栅极于所述栅极绝缘层之上；
    沉积一间介电层于所述栅极绝缘层以及所述栅极之上；
    使用一第四掩膜形成二过孔于所述间介电层以及部份的所述栅极绝缘层；以及
    沉积一第二金属层，并使用一第五掩膜形成一源极以及一漏极于所述间介电层之上；
    其中所述源极以及所述漏极分别通过所述二过孔连接所述多晶硅。
  11. 根据权利要求10的薄膜晶体管结构的制作方法，其中对所述多晶硅进行掺杂包括第一次掺杂和第二次掺杂：
    所述第一次掺杂是在形成所述多晶硅后且在沉积所述栅极绝缘层之前对所述多晶硅层掺杂；
    所述第二次掺杂是在形成所述二过孔后通过所述二过孔对所述多晶硅掺杂。
  12. 根据权利要求11的薄膜晶体管结构的制作方法，其中在所述第一次掺杂过程中，所述多晶硅整体被均匀掺杂。
  13. 根据权利要求11的薄膜晶体管结构的制作方法，其中在所述第一次掺杂过程中，所述多晶硅的通道掺杂区被掺杂，而位于所述通道掺杂区两端的过孔掺杂区在光罩制程中受到保护而未被掺杂。
  14. 根据权利要求12薄膜晶体管结构的制作方法，其中所述过孔掺杂区与所述二过孔连通并通过所述二过孔完成所述第二次掺杂，通过所述第二次掺杂对所述过孔掺杂区掺杂，使所述多晶硅中形成了通道掺杂区和位于所述通道掺杂区两端的过孔掺杂区。
  15. 根据权利要求13所述的薄膜晶体管结构的制作方法，其中所述过孔掺杂区与所述二过孔连通并通过所述二过孔完成所述第二次掺杂，通过所述第二次掺杂对所述过孔掺杂区掺杂，使所述多晶硅中形成了通道掺杂区和位于所述通道掺杂区两端的过孔掺杂区。
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