WO2017181449A1 - 薄膜晶体管、薄膜晶体管的制备方法及cmos器件 - Google Patents

薄膜晶体管、薄膜晶体管的制备方法及cmos器件 Download PDF

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WO2017181449A1
WO2017181449A1 PCT/CN2016/081458 CN2016081458W WO2017181449A1 WO 2017181449 A1 WO2017181449 A1 WO 2017181449A1 CN 2016081458 W CN2016081458 W CN 2016081458W WO 2017181449 A1 WO2017181449 A1 WO 2017181449A1
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doped region
hole
low temperature
layer
heavily doped
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French (fr)
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邓金全
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6731—Top-gate only TFTs
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0314—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral top-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H10D30/6715—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6745—Polycrystalline or microcrystalline silicon
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/213—Channel regions of field-effect devices
    • H10D62/221—Channel regions of field-effect devices of FETs
    • H10D62/235—Channel regions of field-effect devices of FETs of IGFETs
    • H10D62/299—Channel regions of field-effect devices of FETs of IGFETs having lateral doping variations
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H10D30/6715—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions
    • H10D30/6721—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions having lightly-doped extensions consisting of multiple lightly doped zones or having non-homogeneous dopant distributions, e.g. graded LDD

Definitions

  • the present invention relates to the field of display, and in particular, to a thin film transistor, a method of fabricating a thin film transistor, and a CMOS device.
  • a display device such as a liquid crystal display (LCD) is a commonly used electronic device that is favored by users because of its low power consumption, small size, and light weight.
  • LCD liquid crystal display
  • LTPS low temperature Ploy-silicon
  • CMOS devices fabricated from low temperature polysilicon can be applied to make liquid crystal displays have higher resolution and lower power consumption. Therefore, low temperature polysilicon has been widely used and studied. Higher carrier mobility is prone to hot carrier effects, resulting in threshold voltage (Vth) drift, Kink effect, etc.
  • low temperature polysilicon thin film transistors used in low temperature polysilicon.
  • ion implantation is generally used to form shallow doped transition regions, such as LDD (Light Doped Drain) and GOLDD (Gate On LDD).
  • the formation of the shallow doped transition region is typically formed by a mask process or by a gate self-alignment process (Gate Self Alignment).
  • GATE Self Alignment The disadvantages of these methods are that there are many mask processes required, and the formed low-temperature polysilicon thin film transistor is prone to doping deviation or offset between the gate and the LDD region, resulting in poor device characteristics of the low-temperature polysilicon thin film transistor.
  • the invention provides a thin film transistor, the thin film transistor comprising:
  • a low temperature polysilicon layer disposed adjacent to a surface of the substrate
  • the first lightly doped region and the second lightly doped region are disposed in the same layer as the low temperature polysilicon layer, and are disposed at opposite ends of the low temperature polysilicon layer, the first lightly doped region and the second The lightly doped region has the same doping concentration with respect to the symmetric portion of the low temperature polysilicon layer;
  • the first heavily doped region and the second heavily doped region are disposed in the same layer as the low temperature polysilicon layer, and the first heavily doped region is disposed at an end of the first lightly doped region away from the low temperature polysilicon layer
  • the second heavily doped region is disposed at an end of the second lightly doped region away from the low temperature polysilicon layer, and the first heavily doped region and the second heavily doped region are related to the low temperature polysilicon
  • the doping concentration of the layer symmetrical portion is the same, and the doping types of the first lightly doped region, the second lightly doped region, the first heavily doped region, and the second heavily doped region are the same ;
  • a first insulating layer covering the first lightly doped region, the second lightly doped region, the first heavily doped region, and the second heavily doped region, and the first insulating layer is away from The distance from the surface of the substrate to the first lightly doped region, the second lightly doped region, the first heavily doped region, and the second heavily doped region away from the surface of the substrate is equal ;
  • the gate includes a first surface, a second surface, and a third surface, the first surface being disposed on a surface of the first insulating layer away from the substrate, the second surface and the second surface
  • the third surfaces are oppositely disposed and the second surface intersects the first surface, the second surface being disposed adjacent to the first lightly doped region than the third surface, the third surface being The first surfaces intersect, a distance between a plane in which the second surface is located and a plane in which the surface of the first lightly doped region is in contact with the low temperature polysilicon layer is equal to a plane in which the third surface is located and The distance between the plane in which the second lightly doped region is in contact with the surface of the low temperature polysilicon layer.
  • the plane where the second surface is located is located at a plane where the end face of the first lightly doped region in contact with the low temperature polysilicon layer is located, and the first lightly doped region is in contact with the first heavily doped region
  • the plane where the third surface is located is located at a plane where the end face of the second lightly doped region in contact with the low temperature polysilicon layer is located, and the second lightly doped region and the first The plane where the end faces of the double-doped regions are in contact are located.
  • the first insulating layer defines a first through hole and a second through hole, the first through hole corresponds to the first heavily doped region, and the second through hole corresponds to the second heavily doped region
  • the thin film transistor further includes:
  • the second insulating layer covering the gate, the second insulating layer is provided with a third through hole and a fourth through hole, and the third through hole is in communication with the first through hole, the fourth through hole Communicating with the second through hole;
  • a source and a drain are disposed on the second insulating layer, and the source is connected to the first heavily doped region through the first through hole and the third through hole, the drain The pole is connected to the second heavily doped region through the second through hole and the fourth through hole;
  • the thin film transistor further includes: a flat layer and a pixel electrode covering the source and the drain, wherein the flat layer is provided with a fifth through hole, and the fifth through hole corresponds to the drain
  • the pixel electrode is disposed on the flat layer and connected to the drain through the fifth through hole.
  • the doping types of the first lightly doped region, the second lightly doped region, the first heavily doped region, and the second heavily doped region are the same as N-type ion doping or the same Doped with P-type ions.
  • the invention also provides a method for preparing a thin film transistor, the method for preparing the thin film transistor comprises:
  • Patterning the first photoresist layer to expose both ends of the first metal layer, and the patterned first photoresist layer is a first photoresist pattern to cure the first photoresist pattern, wherein the first A photoresist pattern includes a first portion disposed at a middle portion of the first metal layer, and a second portion disposed at a surface of the first portion away from the first metal layer, The first part and the second part form a "convex" word;
  • the second photoresist pattern includes a first sub-portion disposed on the gate and a second sub-portion disposed at the first sub-portion away from the gate a surface of the pole and a width of the second sub-portion being smaller than a width of the first sub-portion, the first sub-portion and the second
  • the sub-portion forms a "convex" word, and the width of the second sub-portion is equal to the width of the gate;
  • the low temperature polysilicon pattern is ion doped with the second photoresist pattern and the first insulating layer as a mask, and the low temperature polysilicon pattern corresponding to the gate forms a low temperature polysilicon layer, corresponding only to the first sub-portion And the low temperature polysilicon pattern corresponding to the second sub-portion forms a first lightly doped region and a second lightly doped region, and the first lightly doped region is away from the end of the low temperature polysilicon layer to form a first heavily doped region. a second lightly doped region is formed away from one end of the low temperature polysilicon layer to form a second heavily doped region;
  • the second photoresist pattern is stripped.
  • the method for preparing the thin film transistor further includes:
  • a planar layer is deposited on the source and the drain.
  • the ion doping is N-type ion doping or P-type ion doping.
  • the low temperature polysilicon pattern is ion doped with the second photoresist pattern and the first insulating layer as a mask, corresponding to the first portion, the second portion, and the first photoresist
  • the patterned doped ions have equal ion concentrations and the same doping time.
  • the present invention also provides a CMOS device comprising the thin film transistor of any of the foregoing embodiments.
  • the low temperature polysilicon pattern is ion doped with the second photoresist pattern and the first insulating layer as a mask, and the second photoresist pattern and the The thickness of the first insulating layer itself is such as to achieve a difference in ion concentration of each portion of the low temperature polysilicon pattern that is finally doped.
  • the low temperature polysilicon pattern corresponding to the gate forms a low temperature polysilicon layer
  • only the low temperature polysilicon pattern corresponding to the first sub portion and not corresponding to the second sub portion forms the first lightly doped region and the second lightly doped region Forming the first lightly doped region away from one end of the low temperature polysilicon layer to form a first
  • the heavily doped region, the second lightly doped region is away from one end of the low temperature polysilicon layer to form a second heavily doped region.
  • the mask process is not required in this step, which simplifies the manufacturing process of the thin film transistor.
  • FIG. 1 is a schematic cross-sectional view showing a thin film transistor according to a preferred embodiment of the present invention.
  • FIG. 2 is a circuit diagram of a CMOS device in accordance with a preferred embodiment of the present invention.
  • FIG 3 is a schematic cross-sectional view of a CMOS according to a preferred embodiment of the present invention.
  • FIG. 4 is a flow chart of a method of fabricating a thin film transistor according to a preferred embodiment of the present invention.
  • 5 to 12 are schematic structural views corresponding to respective steps of a method for fabricating a thin film transistor of the present invention.
  • FIG. 1 is a cross-sectional structural diagram of a thin film transistor according to a preferred embodiment of the present invention.
  • the thin film transistor 10 includes a substrate 110, a low temperature polysilicon layer 120, a first lightly doped region 130a, a second lightly doped region 130b, a first heavily doped region 140a, a second heavily doped region 140b, and a first insulating layer. 150 and gate 160.
  • the low temperature polysilicon layer 120, the first lightly doped region 130a, the second lightly doped region 130b, the first heavily doped region 140a, the second heavily doped region 140b, the first An insulating layer 150 and the gate 160 are disposed adjacent to the substrate 110.
  • the first lightly doped region 130a and the second lightly doped region 130b are disposed in the same layer as the low temperature polysilicon layer 120, and are disposed at opposite ends of the low temperature polysilicon layer 120, the first lightly doped
  • the doping concentration of the symmetrical portion of the low temperature polysilicon layer 130 is the same for the impurity region 130a and the second lightly doped region 130b.
  • the first heavily doped region 140a and the second heavily doped region 140b are disposed in the same layer as the low temperature polysilicon layer 120, and the first heavily doped The impurity region 140a is disposed at an end of the first lightly doped region 130a away from the low temperature polysilicon layer 120, and the second heavily doped region 140b is disposed at the second lightly doped region 130b away from the low temperature polysilicon layer At one end of 120, the doping concentration of the first heavily doped region 140a and the second heavily doped region 140b with respect to the symmetrical portion of the low temperature polysilicon layer 120 is the same.
  • the doping types of the first lightly doped region 130a, the second lightly doped region 130b, the first heavily doped region 140a, and the second heavily doped region 140b are the same.
  • the first insulating layer 150 covers the first lightly doped region 130a, the second lightly doped region 130b, the first heavily doped region 140a, and the second heavily doped region 140b, and The first insulating layer 150 is away from the surface of the substrate 110 to the first lightly doped region 130a, the second lightly doped region 130b, the first heavily doped region 140a, and the second heavily doped.
  • the distance of the miscellaneous regions 140b away from the surface of the substrate 110 is equal.
  • the first insulating layer 150 is away from the surface of the substrate 110 to the surface of the first lightly doped region 130a away from the substrate 110, and the second lightly doped region 130b is away from the substrate 110.
  • the surface, the first heavily doped region 140a is away from the surface of the substrate 110, and the second heavily doped region 140b is equidistant from the surface of the substrate 110.
  • the gate 160 includes a first surface 161, a second surface 162, and a third surface 163.
  • the first surface 161 is disposed on a surface of the first insulating layer 150 away from the substrate 110, the second surface 162 is disposed opposite to the third surface 163, and the second surface 162 is compared to the second surface 162
  • the third surface 163 is disposed adjacent to the first lightly doped region 130a, the third surface 163 intersects the first surface 161, and the plane where the second surface 162 is located and the first lightly doped
  • the distance between the plane in which the surface of the region 130a is in contact with the low temperature polysilicon layer 120 is equal to the plane in which the third surface 163 is located and the surface in which the second lightly doped region 130b is in contact with the low temperature polysilicon layer 120. The distance between the planes.
  • a distance between a plane in which the second surface 162 is located and a plane in which the surface of the first lightly doped region 130a and the low temperature polysilicon layer 120 are located is equal to a plane in which the third surface 163 is located and the first
  • the first plane, the distance between the plane in which the second surface 162 is located and the first plane is a first distance.
  • the material of the substrate 110 includes any one or more of electrical insulating materials such as quartz, mica, alumina or transparent plastic.
  • the substrate 110 is an insulating layer substrate capable of reducing high frequency loss of the substrate 110.
  • the low temperature polysilicon layer 120, the first lightly doped region 130a, the second lightly doped region 130b, the first heavily doped region 140a, the second heavily doped region 140b, the first An insulating layer 150 and the gate 160 are disposed on the same side of the substrate 110. It can be understood that the low temperature polysilicon layer 120, the first lightly doped region 130a, the second lightly doped region 130b, the first heavily doped region 140a, and the second heavily doped region 140b
  • the first insulating layer 150 and the gate 160 may be disposed directly or indirectly on the same side of the substrate 110.
  • the low temperature polysilicon layer 120, the first lightly doped region 130a, the second lightly doped region 130b, the first heavily doped region 140a, and the second heavily doped region are described.
  • the region 140b, the first insulating layer 150 and the gate electrode 160 are disposed on the same side of the substrate 110 through a buffer layer.
  • the buffer layer can reduce damage to the substrate 110 during the preparation of the thin film transistor 10.
  • a plane in which the third surface 163 is located is located in a plane where the end surface of the second lightly doped region 130b is in contact with the low temperature polysilicon layer 120, and the second lightly doped region 130b and the second heavily doped region The plane between the end faces where the regions 140b are in contact is located.
  • the first insulating layer 150 defines a first through hole 151 and a second through hole 152.
  • the first through hole 151 corresponds to the first heavily doped region 140a
  • the second through hole 151 corresponds to the second heavily doped region 140b.
  • the thin film transistor 10 further includes a second insulating layer 170, a source 180a, and a drain 180b.
  • the second insulating layer 170 covers the gate 160, and the second insulating layer 170 defines a third through hole 171 and a fourth through hole 172.
  • the third through hole 171 is in communication with the first through hole 151
  • the fourth through hole 172 is in communication with the second through hole 152 .
  • the source 180a and the drain 180b are spaced apart from each other on the second insulating layer 170, and the source 180a passes through the first through hole 151 and the third through hole 171 and the first
  • the heavily doped regions 140a are connected, and the drains 180b are connected to the second heavily doped regions 140b through the second through holes 152.
  • the thin film transistor 10 further includes a flat layer 190 and a pixel electrode 180c.
  • the flat layer 190 covers the source 180a and the drain 180b.
  • the flat layer 190 is provided with a fifth through hole 191, and the fifth through hole 191 is disposed corresponding to the drain 180b.
  • the pixel electrode 180c is disposed on the flat layer 190 and connected to the drain electrode 180b through the fifth through hole 191.
  • the doping types of the first lightly doped region 130a, the second lightly doped region 130b, the first heavily doped region 140a, and the second heavily doped region 140b are the same as N-type ion doping. Or the same as P-type ion doping.
  • the N-type ion doped ions may be, but are not limited to, phosphorus (P) ions, arsenic (AS) ions, and the like.
  • the P-type ion doped ions may be, but are not limited to, boron (B) ions or the like.
  • the doping concentration of the first heavily doped region 140b is greater than the doping concentration of the first lightly doped region 130a.
  • the doping concentration of the second heavily doped region 140b is greater than the doping concentration of the second lightly doped region 130b.
  • the doping concentration of the first heavily doped region 140a in the present embodiment is greater than the doping concentration of the first lightly doped region 130a, and the doping concentration of the second heavily doped region 140b is greater than the first
  • the doping concentration of a lightly doped region 130b can reduce the contact resistance between the source 180a and the low temperature polysilicon layer 120, and reduce the contact resistance between the drain 180b and the low temperature polysilicon layer 120. Further, the leakage current of the thin film transistor 10 can be reduced.
  • the first insulating layer 150 includes, but is not limited to, silicon nitride (SiNx), silicon oxide (SiOx) materials, and the like.
  • the material of the gate 160 includes, but is not limited to, one or more of metal materials such as Al, Mo, Cu, Ag, Cr, Ti, AlNi, MoTi.
  • the gate 160 has a thickness of 1500 to 6000 angstroms.
  • the second insulating layer 170 includes, but is not limited to, silicon nitride (SiNx), silicon oxide (SiOx) materials, and the like.
  • the materials of the source 180a and the drain 180b include, but are not limited to, one or more of metal materials such as Al, Mo, Cu, Ag, Cr, Ti, AlNi, MoTi.
  • the pixel electrode 180c may include, but is not limited to, one or more of the following materials: a ZnO-based transparent oxide semiconductor material, a SnO 2 -based transparent oxide semiconductor material, an In 2 O 3 -based transparent oxide semiconductor material, or the like.
  • the transparent oxide semiconductor film layer may be Indium Gallium Zinc Oxide (IGZO).
  • the first lightly doped region 130a and the second lightly doped region 130b in the thin film transistor 10 of the present invention are The low temperature polysilicon layer 120 is disposed in the same layer, and the first lightly doped region 130a and the second lightly doped region 130b are opposite to the low temperature polysilicon layer at opposite ends of the low temperature polysilicon layer 120.
  • the doping concentration of the 120 symmetric portion is equal; the first heavily doped region 140a and the second heavily doped region 140b are disposed in the same layer as the low temperature polysilicon layer 120, and the first heavily doped region 140a is disposed
  • the second heavily doped region 140b is disposed at an end of the first lightly doped region 130a away from the low temperature polysilicon layer 120, and the second heavily doped region 140b is disposed at an end of the second lightly doped region 130a away from the low temperature polysilicon layer 120.
  • the first heavily doped region 140a and the second heavily doped region 140b have the same doping concentration with respect to the symmetrical portion of the low temperature polysilicon layer 120; the gate 160 includes a first surface 161, a second surface 162, and a third Surface 163.
  • the first surface 161 is disposed on a surface of the first insulating layer 150 away from the substrate 110, the second surface 162 is disposed opposite to the third surface 163, and the second surface 162 is compared to the second surface 162
  • the third surface 163 is disposed adjacent to the first lightly doped region 130a, the third surface 163 intersects the first surface 161, and the plane where the second surface 162 is located and the first lightly doped
  • the distance between the plane in which the surface of the region 130a is in contact with the low temperature polysilicon layer 120 is equal to the plane in which the third surface 163 is located and the surface in which the second lightly doped region 130b is in contact with the low temperature polysilicon layer 120.
  • the distance between the planes is such that the threshold voltage of the thin film transistor 10 is relatively stable, so that the electrical performance of the thin film transistor 10 is improved.
  • the present invention also provides a CMOS (Complementary Metal Oxide Semiconductor) device 1, please refer to FIG. 2 and FIG. 3 together.
  • 2 is a schematic circuit diagram of a CMOS device according to a preferred embodiment of the present invention
  • FIG. 3 is a cross-sectional structural view of a CMOS according to a preferred embodiment of the present invention.
  • the CMOS device 1 includes a first thin film transistor Q1 and a second thin film transistor Q2, wherein when the first thin film transistor Q1 is an N-type thin film transistor, the second thin film transistor Q2 is a P-type thin film transistor. When the first thin film transistor Q1 is a P-type thin film transistor, the second thin film transistor Q2 is an N-type thin film transistor.
  • a gate of the first thin film transistor Q1 is electrically connected to a gate of the second thin film transistor Q2, and a drain of the first thin film transistor Q1 is connected to a source of the second thin film transistor.
  • the first thin film transistor Q1 in the CMOS device of the present embodiment may be the thin film transistor 10 described above, or the second thin film transistor Q2 of the CMOS device is the thin film transistor 10 described above, and details are not described herein again.
  • FIG. 4 is a diagram of a thin film transistor according to a preferred embodiment of the present invention. Flow chart of the method. The method of preparing the thin film transistor includes, but is not limited to, the following steps.
  • a substrate 110 is provided.
  • the material of the substrate 110 includes any one or more of electrical insulating materials such as quartz, mica, alumina or transparent plastic.
  • the substrate 110 is an insulating layer substrate capable of reducing high frequency loss of the substrate 110.
  • a low temperature polysilicon material layer on the surface of the substrate 110 and patterning the low temperature polysilicon material layer to form a low temperature polysilicon pattern 211.
  • an amorphous silicon material layer may be formed on the surface of the substrate 110, and then the amorphous silicon material layer may be subjected to excimer laser annealing or other methods to make The amorphous silicon in the amorphous silicon material layer becomes polycrystalline silicon.
  • first photoresist layer 24 patterning the first photoresist layer 24 to expose both ends of the first metal layer 23, and the patterned first photoresist layer 24 is a first photoresist pattern 241 to cure the first photoresist pattern 241, wherein the first photoresist pattern comprises a first portion 242 and a second portion 243, the first portion 242 is disposed at a middle portion of the first metal layer 23, and the second portion 243 is disposed at the first portion
  • the second portion 242 and the second portion 243 form a "convex" word away from the surface of the first metal layer 23. Please refer to Figure 7 together.
  • the second photoresist pattern 243a includes a first sub-portion 2431 and a second sub-portion 2432, the first sub-portion 2431 being disposed on the gate 160, the second sub-portion 2432 is disposed at a surface of the first sub-portion 2431 away from the gate 160 and a width of the second sub-portion 2432 is smaller than a width of the first sub-portion 2431, the first sub-portion 2431 and the first The two sub-portions 2432 form a "convex" word and the width of the second sub-portion 2432 is equal to the width of the gate 160. Please refer to Figure 9 together.
  • the tempering polysilicon pattern 211 is ion-doped, and the low-temperature polysilicon pattern 211 corresponding to the gate 160 forms a low-temperature polysilicon layer 120, and only the low-temperature polysilicon pattern 211 corresponding to the first sub-portion 2431 and not corresponding to the second sub-portion 2432 is formed.
  • the first lightly doped region 130a and the second lightly doped region 130b, the first lightly doped region 130a is away from the end of the low temperature polysilicon layer 211 to form a first heavily doped region 140a
  • the second lightly doped region The region 130b is away from one end of the low temperature polysilicon layer 120 to form a second heavily doped region 140b. Please refer to Figure 10 together.
  • the low-temperature polysilicon pattern 211 is ion-doped by using the second photoresist pattern 243a and the first insulating layer 150 as a mask, and the second photoresist pattern is utilized. 243a and the thickness of the first insulating layer 150 itself to achieve a difference in ion concentration of each portion of the low temperature polysilicon pattern 211 that is finally doped.
  • the low temperature polysilicon pattern 211 corresponding to the gate 160 forms the low temperature polysilicon layer 120, and only the low temperature polysilicon pattern 211 corresponding to the first sub-portion 2431 and not corresponding to the second sub-portion 2432 forms the first lightly doped region 130a
  • the second lightly doped region 130b the first lightly doped region 130a is away from the end of the low temperature polysilicon layer 211 to form a first heavily doped region 140a
  • the second lightly doped region 130b is away from the low temperature polysilicon
  • One end of the layer 120 forms a second heavily doped region 140b.
  • the mask process is not required in this step, which simplifies the manufacturing process of the thin film transistor.
  • the method for preparing the thin film transistor further includes the following steps.
  • a through hole is formed in the second insulating layer 170 and the first insulating layer 150 corresponding to the first heavily doped region 140a and the second heavily doped region 140b to be in the first insulating layer Forming a first through hole 151 corresponding to the first heavily doped region 140a and a second through hole 152 corresponding to the second heavily doped region 140b, and forming a space on the second insulating layer 170
  • a third through hole 171 communicating with the first through hole 151 and a fourth through hole 172 communicating with the second through hole 152 are described.
  • a flat layer 190 is deposited on the source 180a and the drain 180b.
  • the method for preparing the thin film transistor further includes the following steps.
  • step S113 a fifth through hole 191 is defined in the flat layer 190 corresponding to the drain 180b.
  • Step S114 depositing a transparent conductive layer on the flat layer 190, and patterning the transparent conductive layer to form a pixel electrode 180c connected to the drain 180b through the fifth through hole 191. Please refer to FIG. 12 from step S109 to step S114.

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  • Thin Film Transistor (AREA)

Abstract

一种薄膜晶体管、薄膜晶体管的制备方法及CMOS器件。薄膜晶体管(10)包括：基板(110)及设置在基板(110)同侧的低温多晶硅层(120)，与低温多晶硅层(120)同层且设置在低温多晶硅层(120)相对两端的第一及第二轻掺杂区(130a、130b)，与低温多晶硅层(120)同层设置的第一、第二重掺杂区(140a、140b)，第一重掺杂区(140a)设置在第一轻掺杂区(130a)远离低温多晶硅层(120)的一端，第二重掺杂区(140b)设置在第二轻掺杂区(130b)远离低温多晶硅层(120)的一端，第一绝缘层(150)，覆盖第一、第二轻掺杂区(130a、130b)、第一、第二重掺杂区(140a、140b)，栅极(160)包括第一表面(161)、第二表面(162)及第三表面(163)，第一表面(161)设置在第一绝缘层(150)上，第二、第三表面(162、163)相对设置且均与第一表面(161)相交，第二表面(162)相较于第三表面(163)邻近第一轻掺杂区(130a)设置，第二表面(162)与第一轻掺杂区(130a)与低温多晶硅层(120)接触的表面之间的距离等于第三表面(163)与第二轻掺杂区(130b)与低温多晶硅层(120)接触的表面之间的距离。

Description

薄膜晶体管、薄膜晶体管的制备方法及CMOS器件
本发明要求2016年4月18日递交的发明名称为“薄膜晶体管、薄膜晶体管的制备方法及CMOS器件”的申请号201610242557.5的在先申请优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明涉及显示领域，尤其涉及一种薄膜晶体管、薄膜晶体管的制备方法及CMOS器件。
背景技术
显示设备，比如液晶显示器(Liquid Crystal Display,LCD)是一种常用的电子设备，由于其具有功耗低、体积小、重量轻等特点，因此备受用户的青睐。随着平面显示技术的发展，具有高分辨率、低能耗的液晶显示器的需求被提出。非晶硅的电子迁移率较低，而低温多晶硅(Low Temperature Ploy-silicon，LTPS)可以在低温下制作，且拥有比非晶硅更高的载流子迁移率。其次，低温多晶硅制作的CMOS器件可应用于使液晶显示器具有更高的分辨率和低能耗。因此，低温多晶硅得到了广泛地应用和研究。较高的载流子迁移率容易产生热载流子效应，导致低温多晶硅所应用的低温多晶硅薄膜晶体管的阈值电压(Vth)漂移，Kink效应等。为了避免热载流子效应一般采用离子注入形成浅掺杂过渡区，如LDD(Light Doped Drain)和GOLDD(Gate On LDD)等。浅掺杂过渡区的形成一般通过光罩(mask)工艺或者通过栅极自对准工艺(Gate Self Alignment)掺杂形成。这些方法的缺点是需要的光罩工序较多，且形成的低温多晶硅薄膜晶体管容易出现掺杂偏差或者栅极与LDD区域偏移，从而导致低温多晶硅薄膜晶体管的器件特性不良。
发明内容
本发明提供一种薄膜晶体管，所述薄膜晶体管包括：
基板；
低温多晶硅层，邻近所述基板的表面设置；
第一轻掺杂区及第二轻掺杂区，与所述低温多晶硅层同层设置，且设置在所述低温多晶硅层相对的两端，所述第一轻掺杂区及所述第二轻掺杂区关于所述低温多晶硅层对称部分的掺杂浓度相同；
第一重掺杂区及第二重掺杂区，与所述低温多晶硅层同层设置，所述第一重掺杂区设置在所述第一轻掺杂区远离所述低温多晶硅层的一端，所述第二重掺杂区设置在所述第二轻掺杂区远离所述低温多晶硅层的一端，所述第一重掺杂区与所述第二重掺杂区关于所述低温多晶硅层对称部分的掺杂浓度相同，且所述第一轻掺杂区、所述第二轻掺杂区、所述第一重掺杂区、所述第二重掺杂区的掺杂类型相同；
第一绝缘层，覆盖所述第一轻掺杂区、所述第二轻掺杂区、所述第一重掺杂区及所述第二重掺杂区，且所述第一绝缘层远离所述基板的表面到所述第一轻掺杂区、所述第二轻掺杂区、所述第一重掺杂区及所述第二重掺杂区远离所述基板的表面的距离相等；
栅极，所述栅极包括第一表面、第二表面及第三表面，所述第一表面设置在所述第一绝缘层远离所述基板的表面上，所述第二表面与所述第三表面相对设置且所述第二表面与所述第一表面相交，所述第二表面相较于所述第三表面邻近所述第一轻掺杂区设置，所述第三表面与所述第一表面相交，所述第二表面所在的平面与所述第一轻掺杂区与所述低温多晶硅层接触的表面所在的平面之间的距离等于所述第三表面所在的平面与所述第二轻掺杂区与所述低温多晶硅层接触的表面所在的平面之间的距离。
其中，所述第二表面所在的平面位于所述第一轻掺杂区与所述低温多晶硅层接触的端面所在的平面以及所述第一轻掺杂区与所述第一重掺杂区接触的端面所在的平面之间，所述第三表面所在的平面位于所述第二轻掺杂区与所述低温多晶硅层接触的端面所在的平面以及所述第二轻掺杂区与所述第二重掺杂区接触的端面所在的平面之间。
其中，所述第一绝缘层开设有第一贯孔及第二贯孔，所述第一贯孔对应所述第一重掺杂区，所述第二贯孔对应所述第二重掺杂区，所述薄膜晶体管还包括:
第二绝缘层，覆盖所述栅极，所述第二绝缘层开设有第三贯孔及第四贯孔，所述第三贯孔与所述第一贯孔连通，所述第四贯孔与所述第二贯孔连通；
源极和漏极，间隔设置在所述第二绝缘层上，且所述源极通过所述第一贯孔及所述第三贯孔与所述第一重掺杂区相连，所述漏极通过所述第二贯孔及所述第四贯孔与所述第二重掺杂区相连；
其中，所述薄膜晶体管还包括:平坦层及像素电极，覆盖所述源极和所述漏极，且所述平坦层开设有第五贯孔，所述第五贯孔对应所述漏极设置，所述像素电极设置在所述平坦层上且通过所述第五贯孔连接所述漏极。
其中，所述第一轻掺杂区、所述第二轻掺杂区、所述第一重掺杂区及所述第二重掺杂区的掺杂类型同为N型离子掺杂或者同为P型离子掺杂。
本发明还提供了一种薄膜晶体管的制备方法，所述薄膜晶体管的制备方法包括：
提供基板；
在所述基板的表面形成低温多晶硅材料层并图案化所述低温多晶硅材料层，以形成低温多晶硅图案；
在所述低温多晶硅图案远离所述基板的表面依次设置第一绝缘层、第一金属层及第一光阻层；
图案化所述第一光阻层，以露出第一金属层的两端，图案化后的第一光阻层为第一光阻图案，固化所述第一光阻图案，其中，所述第一光阻图案包括第一部分及第二部分，所述第一部分设置在所述第一金属层的中部，所述第二部分设置在所述第一部分远离所述第一金属层的表面，所述第一部分及所述第二部分形成“凸”字；
图案化所述第一金属层，仅保留同时被所述第一部分及所述第二部分覆盖的第一金属层，保留下来的所述第一金属层形成薄膜晶体管的栅极；
对所述第一部分未被所述第二部分覆盖的部分进行部分灰化以及对所述第二部分进行全部灰化，对所述第一部分进行部分灰化后的图案为第二光阻图案，所述第二光阻图案包括第一子部分及第二子部分，所述第一子部分设置在所述栅极上，所述第二子部分设置在所述第一子部分远离所述栅极的表面且所述第二子部分的宽度小于所述第一子部分的宽度，所述第一子部分及所述第二 子部分形成“凸”字，且所述第二子部分的宽度等于所述栅极的宽度；
以所述第二光阻图案及所述第一绝缘层为掩膜对所述低温多晶硅图案进行离子掺杂，所述栅极对应的低温多晶硅图案形成低温多晶硅层，仅与第一子部分对应且未所述第二子部分对应的低温多晶硅图案形成第一轻掺杂区及第二轻掺杂区，所述第一轻掺杂区远离所述低温多晶硅层的一端形成第一重掺杂区，所述第二轻掺杂区远离所述低温多晶硅层的一端形成第二重掺杂区；
剥离所述第二光阻图案。
其中，所述薄膜晶体管的制备方法还包括：
在所述栅极及所述第一绝缘层上沉积第二绝缘层；
在所述第二绝缘层及所述第一绝缘层对应所述第一重掺杂区及所述第二重掺杂区开设贯孔，以在所述第一绝缘层上形成对应所述第一重掺杂区的第一贯孔及对应所述第二重掺杂区的第二贯孔，以及在所述第二绝缘层上形成与所述第一贯孔连通的第三贯孔以及与所述第二贯孔连通的第四贯孔；
在所述第二绝缘层上沉积第二金属层，对所述第二金属层进行图案化，以形成通过所述第一贯孔及所述第三贯孔与所述第一重掺杂区连接的源极，以及通过所述第二贯孔及所述第四贯孔与所述第二重掺杂区连接的漏极；
在所述源极和所述漏极上沉积平坦层。
其中，所述离子掺杂为N型离子掺杂或者为P型离子掺杂。
其中，以所述第二光阻图案及所述第一绝缘层为掩膜对所述低温多晶硅图案进行离子掺杂时，对应所述第一部分、所述第二部分及所述第一光阻图案的掺杂的离子浓度相等，掺杂时间相同。
本发明还提供了一种CMOS器件，所述CMOS器件包括前述任意一实施方式所述的薄膜晶体管。
本发明的薄膜晶体管的制备方法中以所述第二光阻图案及所述第一绝缘层为掩膜，对所述低温多晶硅图案进行离子掺杂，利用所述第二光阻图案及所述第一绝缘层自身的厚度，来实现最终掺杂到所述低温多晶硅图案的各部分离子浓度的不同。即，所述栅极对应的低温多晶硅图案形成低温多晶硅层，仅与第一子部分对应且未所述第二子部分对应的低温多晶硅图案形成第一轻掺杂区及第二轻掺杂区，所述第一轻掺杂区远离所述低温多晶硅层的一端形成第一 重掺杂区，所述第二轻掺杂区远离所述低温多晶硅层的一端形成第二重掺杂区。此步骤中不需要光罩工艺，从而简化了薄膜晶体管的制程工序。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明一较佳实施方式的薄膜晶体管的剖面结构示意图。
图2为本发明的一较佳实施方式的CMOS器件的电路示意图。
图3为本发明一较佳实施方式的CMOS的剖面结构示意图。
图4为本发明一较佳实施方式的薄膜晶体管的制备方法的流程图。
图5至图12为本发明薄膜晶体管的制备方法各步骤对应的结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参阅图1，图1为本发明一较佳实施方式的薄膜晶体管的剖面结构示意图。所述薄膜晶体管10包括基板110、低温多晶硅层120、第一轻掺杂区130a、第二轻掺杂区130b、第一重掺杂区140a、第二重掺杂区140b、第一绝缘层150及栅极160。所述低温多晶硅层120、所述第一轻掺杂区130a、所述第二轻掺杂区130b、所述第一重掺杂区140a、所述第二重掺杂区140b、所述第一绝缘层150及所述栅极160邻近所述基板110设置。所述第一轻掺杂区130a及所述第二轻掺杂区130b与所述低温多晶硅层120同层设置，且设置在所述低温多晶硅层120相对的两端，所述第一轻掺杂区130a及所述第二轻掺杂区130b关于所述低温多晶硅层130对称部分的掺杂浓度相同。所述第一重掺杂区140a及所述第二重掺杂区140b与所述低温多晶硅层120同层设置，所述第一重掺 杂区140a设置在所述第一轻掺杂区130a远离所述低温多晶硅层120的一端，所述第二重掺杂区140b设置在所述第二轻掺杂区130b远离所述低温多晶硅层120的一端，所述第一重掺杂区140a与所述第二重掺杂区140b关于所述低温多晶硅层120对称部分的掺杂浓度相同。且所述第一轻掺杂区130a、所述第二轻掺杂区130b、所述第一重掺杂区140a及所述第二重掺杂区140b的掺杂类型相同。所述第一绝缘层150覆盖所述第一轻掺杂区130a、所述第二轻掺杂区130b、所述第一重掺杂区140a及所述第二重掺杂区140b，且所述第一绝缘层150远离所述基板110的表面到所述第一轻掺杂区130a、所述第二轻掺杂区130b、所述第一重掺杂区140a及所述第二重掺杂区140b远离所述基板110的表面的距离相等。换句话说，所述第一绝缘层150远离所述基板110的表面到所述第一轻掺杂区130a远离所述基板110的表面、所述第二轻掺杂区130b远离所述基板110的表面、所述第一重掺杂区140a远离所述基板110的表面及所述第二重掺杂区140b远离所述基板110的表面的距离相等。所述栅极160包括第一表面161、第二表面162、第三表面163。所述第一表面161设置在所述第一绝缘层150远离所述基板110的表面上，所述第二表面162与所述第三表面163相对设置，且所述第二表面162相较于所述第三表面163邻近所述第一轻掺杂区130a设置，所述第三表面163与所述第一表面161相交，所述第二表面162所在的平面与所述第一轻掺杂区130a与所述低温多晶硅层120接触的表面所在的平面之间的距离等于所述第三表面163所在的平面与所述第二轻掺杂区130b与所述低温多晶硅层120接触的表面所在的平面之间的距离。
所述第二表面162所在的平面与所述第一轻掺杂区130a与所述低温多晶硅层120接触的表面所在的平面之间的距离等于所述第三表面163所在的平面与所述第二轻掺杂区130b与所述低温多晶硅层120接触的表面所在的平面之间的距离，换句话说，所述第一轻掺杂区130a与所述低温多晶硅层120接触的表面所在的平面为第一平面，所述第二表面162所在的平面与所述第一平面之间的距离为第一距离。所述第二轻掺杂区130b与所述低温多晶硅层120接触的表面所在的平面为第二平面，所述第三表面163所在的平面与所述第二平面之间的距离为第二距离，所述第二距离等于所述第一距离。
所述基板110的材料包括石英、云母、氧化铝或者透明塑料等电绝缘材料中的任意一种或者多种。所述基板110为绝缘层衬底能够减小所述基板110的高频损耗。
所述低温多晶硅层120、所述第一轻掺杂区130a、所述第二轻掺杂区130b、所述第一重掺杂区140a、所述第二重掺杂区140b、所述第一绝缘层150及所述栅极160设置在所述基板110的同侧。可以理解地，所述低温多晶硅层120、所述第一轻掺杂区130a、所述第二轻掺杂区130b、所述第一重掺杂区140a、所述第二重掺杂区140b、所述第一绝缘层150及所述栅极160可以直接或者间接设置在所述基板110的同侧。在另一实施方式中，述低温多晶硅层120、所述第一轻掺杂区130a、所述第二轻掺杂区130b、所述第一重掺杂区140a、所述第二重掺杂区140b、所述第一绝缘层150及所述栅极160通过一缓冲层设置在所述基板110的同侧。所述缓冲层可以减小在所述薄膜晶体管10的制备过程中对所述基板110的损伤。
所述第二表面162所在的平面位于所述第一轻掺杂区130a与所述低温多晶硅层120接触的端面所在的平面以及所述第一轻掺杂区130a与所述第一重掺杂区140a接触的端面所在的平面之间。所述第三表面163所在的平面位于所述第二轻掺杂区130b与所述低温多晶硅层120接触的端面所在的平面以及所述第二轻掺杂区130b与所述第二重掺杂区140b接触的端面所在的平面之间。
所述第一绝缘层150开设有第一贯孔151及第二贯孔152。所述第一贯孔151对应所述第一重掺杂区140a，所述第二贯孔151对应所述第二重掺杂区140b。所述薄膜晶体管10还包括第二绝缘层170、源极180a及漏极180b。所述第二绝缘层170覆盖所述栅极160，所述第二绝缘层170开设有第三贯孔171及第四贯孔172。所述第三贯孔171与所述第一贯孔151连通，所述第四贯孔172与所述第二贯孔152连通。所述源极180a和所述漏极180b间隔设置在所述第二绝缘层170上，且所述源极180a通过所述第一贯孔151和所述第三贯孔171与所述第一重掺杂区140a相连，所述漏极180b通过所述第二贯孔152与所述第二重掺杂区140b相连。
所述薄膜晶体管10还包括平坦层190及像素电极180c。所述平坦层190覆盖所述源极180a和所述漏极180b，所述平坦层190开设有第五贯孔191，所述第五贯孔191对应所述漏极180b设置。所述像素电极180c设置在所述平坦层190上且通过所述第五贯孔191连接所述漏极180b。
所述第一轻掺杂区130a、所述第二轻掺杂区130b、所述第一重掺杂区140a及所述第二重掺杂区140b的掺杂类型同为N型离子掺杂或者同为P型离子掺杂。所述N型离子掺杂的离子可以为但不仅限于为磷(P)离子、砷(AS)离子等。所述P型离子掺杂的离子可以为但不仅限于为硼(B)离子等。
所述第一重掺杂区140b的掺杂浓度大于所述第一轻掺杂区130a的掺杂浓度。所述第二重掺杂区140b的掺杂浓度大于所述第二轻掺杂区130b的掺杂浓度。本实施方式中的所述第一重掺杂区140a的掺杂浓度大于所述第一轻掺杂区130a的掺杂浓度，所述第二重掺杂区140b的掺杂浓度大于所述第一轻掺杂区130b的掺杂浓度既能够降低所述源极180a与所述低温多晶硅层120之间的接触电阻，降低所述漏极180b与所述低温多晶硅层120之间的接触电阻，又能够减小所述薄膜晶体管10的泄露电流。
所述第一绝缘层150包括但不仅限于氮化硅(SiNx)、氧化硅(SiOx)材料等。
所述栅极160的材料包括但不仅限于Al，Mo，Cu，Ag、Cr、Ti、AlNi、MoTi等金属材料材料中的一种或者多种。所述栅极160的厚度为1500～6000埃。
所述第二绝缘层170包括但不仅限于氮化硅(SiNx)、氧化硅(SiOx)材料等。
所述源极180a和所述漏极180b的材料包括但不仅限于Al，Mo，Cu，Ag、Cr、Ti、AlNi、MoTi等金属材料材料中的一种或者多种。
所述像素电极180c可以包括但不仅限于以下材料中的一种或者多种：ZnO基透明氧化物半导体材料，SnO2基透明氧化物半导体材料，In2O3基透明氧化物半导体材料等。举例而言，所述透明氧化物半导体膜层可以为铟镓锌氧化物(Indium Gallium Zinc Oxide，IGZO)。
本发明的薄膜晶体管10中的第一轻掺杂区130a及第二轻掺杂区130b与 所述低温多晶硅层120同层设置，且所述在所述低温多晶硅层120相对的两端，所述第一轻掺杂区130a及所述第二轻掺杂区130b关于所述低温多晶硅层120对称部分的掺杂浓度相等；所述第一重掺杂区140a及所述第二重掺杂区140b与所述低温多晶硅层120同层设置，且所述第一重掺杂区140a设置在第一轻掺杂区130a远离所述低温多晶硅层120的一端，所述第二重掺杂区140b设置在所述第二轻掺杂区130a远离所述低温多晶硅层120的一端，所述第一重掺杂区140a与所述第二重掺杂区140b关于所述低温多晶硅层120对称部分的掺杂浓度相同；所述栅极160包括第一表面161、第二表面162、第三表面163。所述第一表面161设置在所述第一绝缘层150远离所述基板110的表面上，所述第二表面162与所述第三表面163相对设置，且所述第二表面162相较于所述第三表面163邻近所述第一轻掺杂区130a设置，所述第三表面163与所述第一表面161相交，所述第二表面162所在的平面与所述第一轻掺杂区130a与所述低温多晶硅层120接触的表面所在的平面之间的距离等于所述第三表面163所在的平面与所述第二轻掺杂区130b与所述低温多晶硅层120接触的表面所在的平面之间的距离，从而使得所述薄膜晶体管10的阈值电压较为稳定，使得所述薄膜晶体管10的电学性能得到提高。
本发明还提供了一种CMOS(Complementary Metal Oxide Semiconductor，互补金属氧化物半导体)器件1，请一并参阅图2和图3。图2为本发明的一较佳实施方式的CMOS器件的电路示意图；图3为本发明一较佳实施方式的CMOS的剖面结构示意图。所述CMOS器件1包括第一薄膜晶体管Q1和第二薄膜晶体管Q2，其中，当所述第一薄膜晶体管Q1为N型薄膜晶体管时，所述第二薄膜晶体管Q2为P型薄膜晶体管，当所述第一薄膜晶体管Q1为P型薄膜晶体管时，所述第二薄膜晶体管Q2为N型薄膜晶体管。所述第一薄膜晶体管Q1的栅极电连接所述第二薄膜晶体管Q2的栅极，所述第一薄膜晶体管Q1的漏极连接所述第二薄膜晶体管的源极。本实施方式中的CMOS器件中的第一薄膜晶体管Q1可以为前述介绍的薄膜晶体管10，或者所述CMOS器件中的第二薄膜晶体管Q2为前述介绍的薄膜晶体管10，在此不再赘述。
下面结合图1及对薄膜晶体管10的描述，对本发明薄膜晶体管的制备方法进行介绍。请参阅图4，图4为本发明一较佳实施方式的薄膜晶体管的制备 方法的流程图。所述薄膜晶体管的制备方法包括但不仅限于以下步骤。
S101，提供基板110。所述基板110的材料包括石英、云母、氧化铝或者透明塑料等电绝缘材料中的任意一种或者多种。所述基板110为绝缘层衬底能够减小所述基板110的高频损耗。
S102，在所述基板110的表面形成低温多晶硅材料层并图案化所述低温多晶硅材料层，以形成低温多晶硅图案211。请一并参阅图5，在其他实施方式中，也可以在所述基板110的表面形成非晶硅材料层，再将所述非晶硅材料层进行准分子激光退火或者其他方法处理，以使所述非晶硅材料层中的非晶硅变为多晶硅。
S103，在所述低温多晶硅图案211远离所述基板110的表面依次设置第一绝缘层150、第一金属层23及第一光阻层24。请一并参阅图6。
S104，图案化所述第一光阻层24，以露出第一金属层23的两端，图案化后的第一光阻层24为第一光阻图案241，固化所述第一光阻图案241，其中，所述第一光阻图案包括第一部分242及第二部分243，所述第一部分242设置在所述第一金属层23的中部，所述第二部分243设置在所述第一部分242远离所述第一金属层23的表面，所述第一部分242及所述第二部分243形成“凸”字。请一并参阅图7。
S105，图案化所述第一金属层23，仅保留同时被所述第一部分242及所述第二部分243覆盖的第一金属层23，保留下来的所述第一金属层23形成薄膜晶体管10的栅极160。请一并参阅图8。
S106，对所述第一部分242未被所述第二部分243覆盖的部分进行部分灰化以及对所述第二部分243进行全部灰化，对所述第一部分242进行部分灰化后的图案为第二光阻图案243a，所述第二光阻图案243a包括第一子部分2431及第二子部分2432，所述第一子部分2431设置在所述栅极160上，所述第二子部分2432设置在所述第一子部分2431远离所述栅极160的表面且所述第二子部分2432的宽度小于所述第一子部分2431的宽度，所述第一子部分2431及所述第二子部分2432形成“凸”字，且所述第二子部分2432的宽度等于所述栅极160的宽度。请一并参阅图9。
S107，以所述第二光阻图案243a及所述第一绝缘层150为掩膜对所述低 温多晶硅图案211进行离子掺杂，所述栅极160对应的低温多晶硅图案211形成低温多晶硅层120，仅与第一子部分2431对应且未所述第二子部分2432对应的低温多晶硅图案211形成第一轻掺杂区130a及第二轻掺杂区130b，所述第一轻掺杂区130a远离所述低温多晶硅层211的一端形成第一重掺杂区140a，所述第二轻掺杂区130b远离所述低温多晶硅层120的一端形成第二重掺杂区140b。请一并参阅图10。
S108，剥离所述第二光阻图案243a。请一并参阅图11。
本发明的薄膜晶体管的制备方法中以所述第二光阻图案243a及所述第一绝缘层150为掩膜，对所述低温多晶硅图案211进行离子掺杂，利用所述第二光阻图案243a及所述第一绝缘层150自身的厚度，来实现最终掺杂到所述低温多晶硅图案211的各部分离子浓度的不同。即，所述栅极160对应的低温多晶硅图案211形成低温多晶硅层120，仅与第一子部分2431对应且未所述第二子部分2432对应的低温多晶硅图案211形成第一轻掺杂区130a及第二轻掺杂区130b，所述第一轻掺杂区130a远离所述低温多晶硅层211的一端形成第一重掺杂区140a，所述第二轻掺杂区130b远离所述低温多晶硅层120的一端形成第二重掺杂区140b。此步骤中不需要光罩工艺，从而简化了薄膜晶体管的制程工序。
所述薄膜晶体管的制备方法还包括如下步骤。
S109，在所述栅极160及所述第一绝缘层150上沉积第二绝缘层170。
S110，在所述第二绝缘层170及所述第一绝缘层150对应所述第一重掺杂区140a及所述第二重掺杂区140b开设贯孔，以在所述第一绝缘层150上形成对应所述第一重掺杂区140a的第一贯孔151及对应所述第二重掺杂区140b的第二贯孔152，以及在所述第二绝缘层170上形成与所述第一贯孔151连通的第三贯孔171以及与所述第二贯孔152连通的第四贯孔172。
S111，在所述第二绝缘层170上沉积第二金属层，对所述第二金属层进行图案化，以形成通过所述第一贯孔151及所述第三贯孔171与所述第一重掺杂区140a连接的源极180a，以及通过所述第二贯孔152及所述第四贯孔172与所述第二重掺杂区140b连接的漏极180b。
S112，在所述源极180a和所述漏极180b上沉积平坦层190。
所述薄膜晶体管的制备方法还包括如下步骤。
步骤S113，在所述平坦层190上对应所述漏极180b开设第五贯孔191。
步骤S114，在所述平坦层190上沉积透明导电层，并对所述透明导电层进行图案化，以形成通过所述第五贯孔191连接所述漏极180b的像素电极180c。步骤S109～步骤S114请参阅图12。
以上所揭露的仅为本发明一种较佳实施例而已，当然不能以此来限定本发明之权利范围，本领域普通技术人员可以理解实现上述实施例的全部或部分流程，并依本发明权利要求所作的等同变化，仍属于发明所涵盖的范围。

Claims (14)

  1. 一种薄膜晶体管，其中，所述薄膜晶体管包括：
    基板；
    低温多晶硅层，邻近所述基板的表面设置；
    第一轻掺杂区及第二轻掺杂区，与所述低温多晶硅层同层设置，且设置在所述低温多晶硅层相对的两端，所述第一轻掺杂区及所述第二轻掺杂区关于所述低温多晶硅层对称部分的掺杂浓度相同；
    第一重掺杂区及第二重掺杂区，与所述低温多晶硅层同层设置，所述第一重掺杂区设置在所述第一轻掺杂区远离所述低温多晶硅层的一端，所述第二重掺杂区设置在所述第二轻掺杂区远离所述低温多晶硅层的一端，所述第一重掺杂区与所述第二重掺杂区关于所述低温多晶硅层对称部分的掺杂浓度相同，且所述第一轻掺杂区、所述第二轻掺杂区、所述第一重掺杂区、所述第二重掺杂区的掺杂类型相同；
    第一绝缘层，覆盖所述第一轻掺杂区、所述第二轻掺杂区、所述第一重掺杂区及所述第二重掺杂区，且所述第一绝缘层远离所述基板的表面到所述第一轻掺杂区、所述第二轻掺杂区、所述第一重掺杂区及所述第二重掺杂区远离所述基板的表面的距离相等；
    栅极，所述栅极包括第一表面、第二表面及第三表面，所述第一表面设置在所述第一绝缘层远离所述基板的表面上，所述第二表面与所述第三表面相对设置且所述第二表面与所述第一表面相交，所述第二表面相较于所述第三表面邻近所述第一轻掺杂区设置，所述第三表面与所述第一表面相交，所述第二表面所在的平面与所述第一轻掺杂区与所述低温多晶硅层接触的表面所在的平面之间的距离等于所述第三表面所在的平面与所述第二轻掺杂区与所述低温多晶硅层接触的表面所在的平面之间的距离。
  2. 如权利要求1所述的薄膜晶体管，其中，所述第二表面所在的平面位于所述第一轻掺杂区与所述低温多晶硅层接触的端面所在的平面以及所述第一轻掺杂区与所述第一重掺杂区接触的端面所在的平面之间，所述第三表面所在 的平面位于所述第二轻掺杂区与所述低温多晶硅层接触的端面所在的平面以及所述第二轻掺杂区与所述第二重掺杂区接触的端面所在的平面之间。
  3. 如权利要求1所述的薄膜晶体管，其中，所述第一绝缘层开设有第一贯孔及第二贯孔，所述第一贯孔对应所述第一重掺杂区，所述第二贯孔对应所述第二重掺杂区，所述薄膜晶体管还包括：
    第二绝缘层，覆盖所述栅极，所述第二绝缘层开设有第三贯孔及第四贯孔，所述第三贯孔与所述第一贯孔连通，所述第四贯孔与所述第二贯孔连通；
    源极和漏极，间隔设置在所述第二绝缘层上，且所述源极通过所述第一贯孔及所述第三贯孔与所述第一重掺杂区相连，所述漏极通过所述第二贯孔及所述第四贯孔与所述第二重掺杂区相连。
  4. 如权利要求3所述的薄膜晶体管，其中，所述薄膜晶体管还包括：平坦层及像素电极，覆盖所述源极和所述漏极，且所述平坦层开设有第五贯孔，所述第五贯孔对应所述漏极设置，所述像素电极设置在所述平坦层上且通过所述第五贯孔连接所述漏极。
  5. 如权利要求1所述的薄膜晶体管，其中，所述第一轻掺杂区、所述第二轻掺杂区、所述第一重掺杂区及所述第二重掺杂区的掺杂类型同为N型离子掺杂或者同为P型离子掺杂。
  6. 一种薄膜晶体管的制备方法，其中，所述薄膜晶体管的制备方法包括：
    提供基板；
    在所述基板的表面形成低温多晶硅材料层并图案化所述低温多晶硅材料层，以形成低温多晶硅图案；
    在所述低温多晶硅图案远离所述基板的表面依次设置第一绝缘层、第一金属层及第一光阻层；
    图案化所述第一光阻层，以露出第一金属层的两端，图案化后的第一光阻层为第一光阻图案，固化所述第一光阻图案，其中，所述第一光阻图案包括第 一部分及第二部分，所述第一部分设置在所述第一金属层的中部，所述第二部分设置在所述第一部分远离所述第一金属层的表面，所述第一部分及所述第二部分形成“凸”字；
    图案化所述第一金属层，仅保留同时被所述第一部分及所述第二部分覆盖的第一金属层，保留下来的所述第一金属层形成薄膜晶体管的栅极；
    对所述第一部分未被所述第二部分覆盖的部分进行部分灰化以及对所述第二部分进行全部灰化，对所述第一部分进行部分灰化后的图案为第二光阻图案，所述第二光阻图案包括第一子部分及第二子部分，所述第一子部分设置在所述栅极上，所述第二子部分设置在所述第一子部分远离所述栅极的表面且所述第二子部分的宽度小于所述第一子部分的宽度，所述第一子部分及所述第二子部分形成“凸”字，且所述第二子部分的宽度等于所述栅极的宽度；
    以所述第二光阻图案及所述第一绝缘层为掩膜对所述低温多晶硅图案进行离子掺杂，所述栅极对应的低温多晶硅图案形成低温多晶硅层，仅与第一子部分对应且未所述第二子部分对应的低温多晶硅图案形成第一轻掺杂区及第二轻掺杂区，所述第一轻掺杂区远离所述低温多晶硅层的一端形成第一重掺杂区，所述第二轻掺杂区远离所述低温多晶硅层的一端形成第二重掺杂区；
    剥离所述第二光阻图案。
  7. 如权利要求6所述的薄膜晶体管的制备方法，其中，所述薄膜晶体管的制备方法还包括：
    在所述栅极及所述第一绝缘层上沉积第二绝缘层；
    在所述第二绝缘层及所述第一绝缘层对应所述第一重掺杂区及所述第二重掺杂区开设贯孔，以在所述第一绝缘层上形成对应所述第一重掺杂区的第一贯孔及对应所述第二重掺杂区的第二贯孔，以及在所述第二绝缘层上形成与所述第一贯孔连通的第三贯孔以及与所述第二贯孔连通的第四贯孔；
    在所述第二绝缘层上沉积第二金属层，对所述第二金属层进行图案化，以形成通过所述第一贯孔及所述第三贯孔与所述第一重掺杂区连接的源极，以及通过所述第二贯孔及所述第四贯孔与所述第二重掺杂区连接的漏极；
    在所述源极和所述漏极上沉积平坦层。
  8. 如权利要求6所述的薄膜晶体管的制备方法，其中，所述离子掺杂为N型离子掺杂或者为P型离子掺杂。
  9. 如权利要求6所述的薄膜晶体管的制备方法，其中，以所述第二光阻图案及所述第一绝缘层为掩膜对所述低温多晶硅图案进行离子掺杂时，对应所述第一部分、所述第二部分及所述第一光阻图案的掺杂的离子浓度相等，掺杂时间相同。
  10. 一种CMOS器件，其中，所述CMOS器件包括薄膜晶体管，所述薄膜晶体管包括：
    基板；
    低温多晶硅层，邻近所述基板的表面设置；
    第一轻掺杂区及第二轻掺杂区，与所述低温多晶硅层同层设置，且设置在所述低温多晶硅层相对的两端，所述第一轻掺杂区及所述第二轻掺杂区关于所述低温多晶硅层对称部分的掺杂浓度相同；
    第一重掺杂区及第二重掺杂区，与所述低温多晶硅层同层设置，所述第一重掺杂区设置在所述第一轻掺杂区远离所述低温多晶硅层的一端，所述第二重掺杂区设置在所述第二轻掺杂区远离所述低温多晶硅层的一端，所述第一重掺杂区与所述第二重掺杂区关于所述低温多晶硅层对称部分的掺杂浓度相同，且所述第一轻掺杂区、所述第二轻掺杂区、所述第一重掺杂区、所述第二重掺杂区的掺杂类型相同；
    第一绝缘层，覆盖所述第一轻掺杂区、所述第二轻掺杂区、所述第一重掺杂区及所述第二重掺杂区，且所述第一绝缘层远离所述基板的表面到所述第一轻掺杂区、所述第二轻掺杂区、所述第一重掺杂区及所述第二重掺杂区远离所述基板的表面的距离相等；
    栅极，所述栅极包括第一表面、第二表面及第三表面，所述第一表面设置在所述第一绝缘层远离所述基板的表面上，所述第二表面与所述第三表面相对设置且所述第二表面与所述第一表面相交，所述第二表面相较于所述第三表面 邻近所述第一轻掺杂区设置，所述第三表面与所述第一表面相交，所述第二表面所在的平面与所述第一轻掺杂区与所述低温多晶硅层接触的表面所在的平面之间的距离等于所述第三表面所在的平面与所述第二轻掺杂区与所述低温多晶硅层接触的表面所在的平面之间的距离。
  11. 如权利要求10所述的CMOS器件，其中，所述第二表面所在的平面位于所述第一轻掺杂区与所述低温多晶硅层接触的端面所在的平面以及所述第一轻掺杂区与所述第一重掺杂区接触的端面所在的平面之间，所述第三表面所在的平面位于所述第二轻掺杂区与所述低温多晶硅层接触的端面所在的平面以及所述第二轻掺杂区与所述第二重掺杂区接触的端面所在的平面之间
  12. 如权利要求10所述的CMOS器件，其中，所述第一绝缘层开设有第一贯孔及第二贯孔，所述第一贯孔对应所述第一重掺杂区，所述第二贯孔对应所述第二重掺杂区，所述薄膜晶体管还包括：
    第二绝缘层，覆盖所述栅极，所述第二绝缘层开设有第三贯孔及第四贯孔，所述第三贯孔与所述第一贯孔连通，所述第四贯孔与所述第二贯孔连通；
    源极和漏极，间隔设置在所述第二绝缘层上，且所述源极通过所述第一贯孔及所述第三贯孔与所述第一重掺杂区相连，所述漏极通过所述第二贯孔及所述第四贯孔与所述第二重掺杂区相连。
  13. 如权利要求12所述的CMOS器件，其中，所述薄膜晶体管还包括：平坦层及像素电极，覆盖所述源极和所述漏极，且所述平坦层开设有第五贯孔，所述第五贯孔对应所述漏极设置，所述像素电极设置在所述平坦层上且通过所述第五贯孔连接所述漏极。
  14. 如权利要求10所述的CMOS器件，其中，所述第一轻掺杂区、所述第二轻掺杂区、所述第一重掺杂区及所述第二重掺杂区的掺杂类型同为N型离子掺杂或者同为P型离子掺杂。
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